Multi-channel clock signal output circuit

Abstract

The embodiment of the invention discloses a multi-channel clock signal output circuit, which is characterized in that a phase-locked loop is arranged in the multi-channel clock signal output circuit, and a signal output module outputs a sampling signal at the moment when a feedback clock signal reaches a half signal period to the phase-locked loop; the phase difference of sampling signals output by two adjacent signal output modules is locked at a preset angle through a phase-locked loop, and a control signal is output to each signal output module according to the locked phase difference, so that the phase difference of clock signals output by the two adjacent signal output modules is kept at the preset angle. Therefore, conduction moments of different switching circuits are controlled, simultaneous conduction of adjacent switching circuits is avoided, the current value of ripple current is reduced, and the technical problem that the ripple current is too large due to the fact that multiple output channels are integrated on a bare chip in the prior art is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuits, and in particular to a multi-channel clock signal output circuit. Background Art

[0002] At present, in order to meet the power supply requirements of multiple power sources, a single converter is generally used to achieve the output of multiple power sources. There are generally two design methods for achieving the output of multiple power sources in the prior art. One is to package and integrate multiple independent bare chips (die) together to form multiple output channels, and the other method is to integrate multiple output channels on the bare chip. The bare chip integrated multiple output channel method has obvious advantages in terms of area and efficiency.

[0003] However, for the method of integrating multiple output channels on a bare chip, if the phases of the multiple output channels are not controlled during operation, the currents of multiple output channels are easily superimposed, resulting in excessive input ripple current, thereby affecting the stability and reliability of the circuit. Summary of the invention

[0004] The embodiment of the present invention provides a method for solving the technical problem of excessive ripple current in the prior art method of integrating multiple output channels on a bare chip.

[0005] An embodiment of the present invention provides a multi-channel clock signal output circuit, comprising a phase-locked loop and at least two signal output modules;

[0006] The first output end of the signal output module is used to connect with the switch circuit, and is used to output the clock signal to the switch circuit. The second output end of the signal output module is connected with the input port of the phase-locked loop, and is used to output the sampling signal to the phase-locked loop, and the sampling signal is used to detect the moment when the clock signal reaches half a signal cycle; the input end of the signal output module is connected with the output port of the phase-locked loop, and is used to receive the control signal output by the phase-locked loop, and generate the clock signal according to the control signal;

[0007] The phase-locked loop is used to lock the phase difference of the sampling signals output by two adjacent signal output modules at a preset angle, and output the control signal to each of the signal output modules according to the locked phase difference, so as to keep the phase difference of the clock signals output by the two adjacent signal output modules at the preset angle, wherein the preset angle is 360° / n, and n is the number of the signal output modules.

[0008] Wherein, the signal output module includes a first signal output module and a second signal output module;

[0009] The first output end of the first signal output module is used to be connected to the first switch circuit, and is used to output a first clock signal to the first switch circuit. The second output end of the first signal output module is connected to the first input end of the phase-locked loop, and is used to output a first sampling signal to the phase-locked loop, and the first sampling signal is used to detect the moment when the first clock signal reaches half a signal cycle; the input end of the first signal output module is connected to the first output end of the phase-locked loop, and is used to receive a first control signal output by the phase-locked loop, and generate the first clock signal according to the first control signal;

[0010] The first output end of the second signal output module is used to connect with the second switch circuit, and is used to output the second clock signal to the second switch circuit. The second output end of the second signal output module is connected with the second input end of the phase-locked loop, and is used to output the second sampling signal to the phase-locked loop. The second sampling signal is used to detect the moment when the second clock signal reaches half a signal cycle. The input end of the second signal output module is connected with the second output end of the phase-locked loop, and is used to receive the second control signal output by the phase-locked loop, and generate the second clock signal according to the second control signal. The duration of the signal cycle of the first clock signal is the same as the duration of the signal cycle of the second clock signal.

[0011] The phase-locked loop is used to lock the phase difference between the first sampling signal and the second sampling signal at 180°, and output the first control signal and the second control signal according to the locked phase difference to keep the phase difference between the first clock signal and the second clock signal at 180°.

[0012] Wherein, the first signal output module includes a first charging and discharging unit and a first signal output unit;

[0013] The first input end of the first charge and discharge unit is connected to the first output end of the phase-locked loop, and is used to charge with a constant current according to the first control signal received; the first output end and the second output end of the first charge and discharge unit are respectively connected to the first input end and the second input end of the first signal output unit, and are used to output a corresponding first voltage signal to the first signal output unit according to the charge amount; the second input end of the first charge and discharge unit is connected to the first output end of the first signal output unit, and is used to receive the first clock signal and discharge according to the first clock signal;

[0014] The first output end of the first signal output unit is also used to connect to the first switching circuit, for generating the first clock signal according to the first voltage signal, and transmitting the first clock signal to the first switching circuit and the first charging and discharging unit; the second output end of the first signal output unit is connected to the first input end of the phase-locked loop, for generating the first sampling signal according to the first voltage signal, and transmitting the first sampling signal to the phase-locked loop, and the first sampling signal is used to feedback the moment when the charging amount reaches half of the maximum charging amount.

[0015] Among them, the first charging and discharging unit includes a first controlled current source, a first capacitor and a first MOS transistor, the controlled end of the first controlled current source is connected to the first output end of the phase-locked loop, the output end of the first controlled current source is connected to the first end of the first capacitor and the first input end and the second input end of the first signal output unit, and is used to charge the first capacitor with a constant current when receiving the first control signal; the second end of the first capacitor is connected to the drain of the first MOS transistor, the source of the first MOS transistor is grounded, the gate of the first MOS transistor is connected to the first output end of the first signal output unit, and the first MOS transistor is used to be turned on and off according to the first clock signal.

[0016] Wherein, the first MOS transistor is an N-channel MOS transistor.

[0017] Among them, the first signal output unit is specifically used to detect whether the charge amount of the first capacitor reaches the maximum charge amount, and generate a first clock signal according to whether the charge amount of the first capacitor reaches the maximum charge amount; and is used to detect whether the charge amount of the first capacitor reaches half of the maximum charge amount, and generate a first sampling signal according to whether the charge amount of the first capacitor reaches half of the maximum charge amount.

[0018] Wherein, the first signal output unit includes a first comparator and a second comparator, the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are connected to the first terminal of the first capacitor, the inverting input terminal of the first comparator is used to input a first reference voltage signal, and the voltage value of the first reference voltage signal is a voltage signal corresponding to the first capacitor reaching the maximum charge amount; the output terminal of the first comparator is connected to the first switch circuit and the gate of the first MOS tube;

[0019] The non-inverting input terminal of the second comparator is used to input a second reference voltage signal, and the voltage value of the second reference voltage signal is a voltage signal corresponding to the first capacitor reaching half of the maximum charge amount; the output terminal of the second comparator is connected to the first input terminal of the phase-locked loop.

[0020] Wherein, the second signal output module includes a second charging and discharging unit and a second signal output unit;

[0021] The first input end of the second charge and discharge unit is connected to the second output end of the phase-locked loop, and is used to charge with a constant current according to the second control signal received; the first output end and the second output end of the second charge and discharge unit are respectively connected to the first input end and the second input end of the second signal output unit, and are used to output a corresponding second voltage signal to the second signal output unit according to the charging amount; the second input end of the second charge and discharge unit is connected to the first output end of the second signal output unit, and is used to receive the second clock signal and discharge according to the second clock signal;

[0022] The first output end of the second signal output unit is also used to connect to the second switching circuit, for generating the second clock signal according to the second voltage signal, and transmitting the second clock signal to the second switching circuit and the second charging and discharging unit; the second output end of the second signal output unit is connected to the second input end of the phase-locked loop, for generating the second sampling signal according to the second voltage signal, and transmitting the second sampling signal to the phase-locked loop, and the second sampling signal is used to feedback the moment when the charging amount reaches half of the maximum charging amount.

[0023] Among them, the second charging and discharging unit includes a second controlled current source, a second capacitor and a second MOS tube, the controlled end of the second controlled current source is connected to the second output end of the phase-locked loop, the output end of the second controlled current source is connected to the first end of the second capacitor and the first input end and the second input end of the second signal output unit, and is used to charge the second capacitor with a constant current when receiving the second control signal; the second end of the second capacitor is connected to the drain of the second MOS tube, the source of the second MOS tube is grounded, the gate of the second MOS tube is connected to the first output end of the second signal output unit, and the second MOS tube is used to be turned on and off according to the second clock signal.

[0024] Among them, the second signal output unit is specifically used to detect whether the charge amount of the second capacitor reaches the maximum charge amount, and generate a second clock signal according to whether the charge amount of the second capacitor reaches the maximum charge amount; and is used to detect whether the charge amount of the second capacitor reaches half of the maximum charge amount, and generate a second sampling signal according to whether the charge amount of the second capacitor reaches half of the maximum charge amount.

[0025] Wherein, the second signal output unit includes a third comparator, a fourth comparator and an inverter, the non-inverting input terminal of the third comparator and the inverting input terminal of the fourth comparator are connected to the first terminal of the second capacitor, the inverting input terminal of the third comparator is used to input a third reference voltage signal, and the voltage value of the third reference voltage signal is a voltage signal corresponding to the second capacitor reaching the maximum charge amount; the output terminal of the third comparator is connected to the second switch circuit and the gate of the second MOS tube;

[0026] The non-inverting input terminal of the fourth comparator is used to input a fourth reference voltage signal, and the voltage value of the fourth reference voltage signal is a voltage signal corresponding to the second capacitor reaching half of the maximum charge amount; the output terminal of the fourth comparator is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the second input terminal of the phase-locked loop.

[0027] An embodiment of the present invention discloses a multi-channel clock signal output circuit. The embodiment of the present invention sets a phase-locked loop in the multi-channel clock signal output circuit. The signal output module outputs a sampling signal to the phase-locked loop when the feedback clock signal reaches half a signal cycle. The phase-locked loop locks the phase difference of the sampling signals output by two adjacent signal output modules at a preset angle, and outputs a control signal to each signal output module according to the locked phase difference, so as to keep the phase difference of the clock signals output by the two adjacent signal output modules at the preset angle, thereby controlling the turn-on time of different switch circuits, avoiding the adjacent switch circuits from being turned on at the same time, thereby reducing the current value of the ripple current, and solving the technical problem of excessive ripple current in the prior art method of integrating multiple output channels on a bare chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic structural diagram of a multi-channel clock signal output circuit provided by an embodiment of the present invention.

[0029] Figure 2 A schematic diagram of the structure of another multi-channel clock signal output circuit provided by an embodiment of the present invention.

[0030] Figure 3 A schematic diagram of the structure of another multi-channel clock signal output circuit provided by an embodiment of the present invention.

[0031] Figure 4 A circuit schematic diagram of a multi-channel clock signal output circuit provided by an embodiment of the present invention.

[0032] Figure 5 This is a timing diagram of the first sampling signal and the second sampling signal provided by an embodiment of the present invention.

[0033] Reference numerals:

[0034] Phase-locked loop 10, signal output module 20, first signal output module 21, second signal output module 22, first charge and discharge unit 211, first signal output unit 212, first charge and discharge unit 221, first signal output unit 222, first controlled current source CCCS1, first capacitor C1, first MOS tube Q1, first comparator U1, second comparator U2, second controlled current source CCCS2, second capacitor C2, second MOS tube Q2, third comparator U3, fourth comparator U4, inverter U5. DETAILED DESCRIPTION

[0035] The following description and accompanying drawings fully illustrate the specific embodiments of the present application so that those skilled in the art can practice them. The examples represent possible variations only. Unless explicitly required, separate components and functions are optional, and the order of operation can vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. The scope of the embodiments of the present application includes the entire scope of the claims, and all available equivalents of the claims. In this article, each embodiment may be represented individually or generally by the term "invention", which is only for convenience, and if more than one invention is disclosed in fact, it is not intended to automatically limit the scope of the application to any single invention or inventive concept. In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. The various embodiments are described in a progressive manner herein, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. As for the structures, products, etc. disclosed in the embodiments, since they correspond to the parts disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0036] In order to meet the needs of multi-power supply, each power supply end was powered by an independent switching power supply in the early days. Although this approach can make the output of each switching power supply accurate and stable, it will make the power supply system have many components and the size of the power supply system is often larger. At the same time, when the operating frequencies of the switching tubes of each independent switching power supply are different, beat frequency interference will occur, affecting the stability and accuracy of the output of the switching power supply. Based on this, the need to use a single converter to achieve multi-channel power output has arisen.

[0037] At present, there are generally two design methods for realizing the output of multiple power supplies in the prior art. One is to package and integrate multiple independent bare chips (die) together to form multiple power output channels in the form of chip by chip. However, since each bare chip is a relatively independent bare chip (i.e., different substrates), the crosstalk between signals when the multiple power output channels are output is minimized. However, since they are all relatively independent bare chips, there are common parts between the power output channels, so the chip area is relatively large, the current consumption is large and the efficiency is low. At the same time, due to the limitation of the chip area, the output channels that can be integrated are limited, and generally two outputs are common. Another method is to integrate multiple power output channels on the bare chip. The method of integrating multiple power output channels on the bare chip has obvious advantages in terms of area and efficiency, but it is easy to generate large ripple current. Taking two-way output as an example, if the two power output channels work together and the phase is not controlled, the input current of the two power output channels will be superimposed, resulting in excessive ripple current. If the power switch tubes of the two power output channels are turned on and off at the same time, this will cause surge input current in the power supply, affecting the reliability and stability of the circuit. In addition, the larger the ripple current, the larger the bypass capacitor is required, which increases the difficulty of peripheral circuit design and the circuit cost.

[0038] Based on this, in order to solve the above technical problems, an embodiment of the present invention provides a multi-channel clock signal output circuit, such as Figure 1 As shown, Figure 1 A schematic diagram of the structure of a multi-channel clock signal output circuit provided in an embodiment of the present invention. The multi-channel clock signal output circuit provided in an embodiment of the present invention comprises a phase-locked loop 10 and at least two signal output modules 20;

[0039] The first output end of the signal output module 20 is used to connect to the switching circuit, and is used to output a clock signal to the switching circuit. The second output end of the signal output module 20 is connected to the input port of the phase-locked loop 10, and is used to output a sampling signal to the phase-locked loop 10. The sampling signal is used to detect the moment when the clock signal reaches half a signal cycle; the input end of the signal output module 20 is connected to the output port of the phase-locked loop 10, and is used to receive the control signal output by the phase-locked loop 10, and generate a clock signal according to the control signal.

[0040] The multi-channel clock signal output circuit of the embodiment of the present invention includes at least two signal output modules 20, wherein the first output end of the signal output module 20 is used to connect to the switch circuit, wherein the switch circuit is a circuit that realizes the on / off and change of current and voltage by controlling the switch state of the power switch tube, thereby realizing the operation and control of the circuit. The first output end of the signal output module 20 is used to output a clock signal to the switch circuit. It can be understood that the on / off of the power switch tube (such as MOSFET or IGBT) in the switch circuit is realized by controlling its gate (or base) voltage, and the clock signal is a periodic signal, and its frequency and phase determine the switching frequency and timing of the power switch tube, so the output voltage or current can be adjusted by controlling the on / off of the power switch tube in the switch circuit by the clock signal.

[0041] In addition, the second output end of the signal output module 20 is connected to the input port of the phase-locked loop 10, and the second output end of the signal output module 20 is used to output a sampling signal to the phase-locked loop 10, wherein the sampling signal is used to detect the moment when the clock signal output by the signal output module 20 reaches half a signal cycle. In one embodiment, the moment when the clock signal reaches half a signal cycle can be determined by the level change in the sampling signal. For example, when the sampling signal changes from a high level to a low level, it can be confirmed that the moment when the level changes is the moment when the clock signal reaches half a signal cycle. In addition, the input end of the signal output module 20 is connected to the output port of the phase-locked loop 10, and the input end of the signal output module 20 is used to receive the control signal output by the phase-locked loop 10, and determine the time when the clock signal starts to be generated according to the control signal, that is, the moment when the control signal is received is the moment when the cycle of the clock signal starts. In addition, it can be understood that the duration of the signal cycle of the clock signal output by each signal output module 20 in this embodiment is the same.

[0042] The phase-locked loop 10 is used to lock the phase difference of the sampling signals output by two adjacent signal output modules 20 at a preset angle, and output a control signal to each signal output module 20 according to the locked phase difference, so as to keep the phase difference of the clock signals output by two adjacent signal output modules 20 at a preset angle, wherein the preset angle is 360° / n, and n is the number of signal output modules 20.

[0043] In this embodiment, the phase-locked loop 10 is used to lock the phase difference of the sampling signals output by two adjacent signal output modules 20 at a preset angle, wherein the preset angle is 360° / n, and n is the number of the signal output modules 20. Specifically, in this embodiment, the moment when the clock signal output by each signal output module 20 reaches half a signal cycle can be determined according to the sampling signal output by each signal output module 20, and the phase difference at the moment when the clock signal output by the adjacent signal output modules 20 reaches half a signal cycle can be locked at a preset angle. Afterwards, the phase-locked loop 10 can output a control signal to each signal output module 20 according to the locked phase difference, so as to keep the phase difference of the clock signals output by the two adjacent signal output modules 20 at a preset angle, wherein the two adjacent signal output modules 20 refer to the signal output modules 20 adjacent to each other at the position integrated on the circuit board, that is, the phase difference of the control signals of the two adjacent signal output modules 20 is a preset angle. Since the signal output module 20 starts to generate a clock signal when receiving the control signal, it is possible to keep the phase difference of the clock signals output by the two adjacent signal output modules 20 at a preset angle. When the phase difference of the clock signals output by two adjacent signal output modules 20 is maintained at a preset angle, since the clock signal controls the conduction of the power switch tube, the conduction time of the power switch tubes connected to the two adjacent signal output modules 20 will be staggered alternately, and the current value of the input ripple current can be reduced in this way. It should also be noted that in this embodiment, the phase-locked loop 10 is started only when the signal output modules 20 are all working in the PWM mode, and the required static current is extremely small, which is suitable for low power consumption occasions.

[0044] As described above, the embodiment of the present invention sets a phase-locked loop in the multi-channel clock signal output circuit, and the signal output module outputs a sampling signal to the phase-locked loop when the feedback clock signal reaches half a signal cycle. The phase-locked loop locks the phase difference of the sampling signals output by two adjacent signal output modules at a preset angle, and outputs a control signal to each signal output module according to the locked phase difference, so as to keep the phase difference of the clock signals output by the two adjacent signal output modules at the preset angle, thereby controlling the turn-on time of different switch circuits, avoiding the adjacent switch circuits from being turned on at the same time, thereby reducing the current value of the ripple current, and solving the technical problem of excessive ripple current in the prior art method of integrating multiple output channels on a bare chip.

[0045] Based on the above embodiments, Figure 2 As shown, Figure 2 A schematic diagram of another multi-channel clock signal output circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the signal output module 20 of the multi-channel clock signal output circuit provided in the embodiment of the present invention includes a first signal output module 21 and a second signal output module 22 .

[0046] The first output end of the first signal output module 21 is used to be connected to the first switching circuit, and is used to output a first clock signal to the first switching circuit. The second output end of the first signal output module 21 is connected to the first input end of the phase-locked loop 10, and is used to output a first sampling signal to the phase-locked loop 10. The first sampling signal is used to detect the moment when the first clock signal reaches half a signal cycle; the input end of the first signal output module 21 is connected to the first output end of the phase-locked loop 10, and is used to receive a first control signal output by the phase-locked loop 10, and generate a first clock signal according to the first control signal.

[0047] The multi-channel clock signal output circuit of an embodiment of the present invention includes a first signal output module 21, wherein the first output end of the first signal output module 21 is used to connect to the first switching circuit, and the first output end of the first signal output module 21 is used to output a first clock signal to the first switching circuit, and the output voltage or current is adjusted by controlling the conduction and shutdown of the main power switch tube in the switching power supply through the first clock signal.

[0048] In addition, the second output end of the first signal output module 21 is connected to the first input end of the phase-locked loop 10, and the second output end of the first signal output module 21 is used to output a first sampling signal to the phase-locked loop 10, wherein the first sampling signal is used to detect the moment when the first clock signal reaches half a signal cycle. In one embodiment, the moment when the first clock signal reaches half a signal cycle can be determined by the level change in the first sampling signal. For example, when the first sampling signal changes from a high level to a low level, it can be confirmed that the moment of the level change is the moment when the first clock signal reaches half a signal cycle. In addition, the input end of the first signal output module 21 is connected to the first output end of the phase-locked loop 10, and the input end of the first signal output module 21 is used to receive the first control signal output by the phase-locked loop 10, and determine the time when the first clock signal starts to be generated according to the first control signal, that is, the moment when the first control signal is received is the moment when the cycle of the first clock signal starts.

[0049] The first output end of the second signal output module 22 is used to be connected to the second switching circuit, and is used to output a second clock signal to the second switching circuit. The second output end of the second signal output module 22 is connected to the second input end of the phase-locked loop 10, and is used to output a second sampling signal to the phase-locked loop 10. The second sampling signal is used to detect the moment when the second clock signal reaches half a signal cycle; the input end of the second signal output module 22 is connected to the second output end of the phase-locked loop 10, and is used to receive a second control signal output by the phase-locked loop 10, and generate a second clock signal according to the second control signal. The duration of the signal cycle of the first clock signal is the same as the duration of the signal cycle of the second clock signal.

[0050] The multi-channel clock signal output circuit of the embodiment of the present invention further includes a second signal output module 22. The working principle of the second signal output module 22 is similar to that of the first signal output module 21. For details, reference may be made to the working principle of the first signal output module 21, which will not be described in detail in this embodiment. It should be noted that, in this embodiment, the duration of the signal cycle of the first clock signal is the same as the duration of the signal cycle of the second clock signal.

[0051] The phase-locked loop 10 is used to lock the phase difference between the first sampling signal and the second sampling signal at 180°, and output the first control signal and the second control signal in sequence according to the locked phase difference, so as to keep the phase difference between the first clock signal and the second clock signal at 180°.

[0052] In this embodiment, the phase-locked loop 10 is used to lock the phase difference between the first sampling signal and the second sampling signal at 180°. Specifically, in this embodiment, the moment when the first clock signal reaches half a signal cycle can be determined according to the first sampling signal, and the moment when the second clock signal reaches half a signal cycle can be determined according to the second sampling signal, and the phase difference of the moment when the two clock signals reach half a signal cycle is locked at 180°. Afterwards, the phase-locked loop 10 can output the first control signal and the second control signal according to the locked phase difference, that is, the phase difference between the output first control signal and the second control signal is also 180°. Since the first signal output module 21 and the second signal output module 22 start to generate clock signals when receiving the first control signal and the second control signal respectively, it is possible to achieve the phase difference between the first clock signal and the second clock signal being maintained at 180°. When the phase difference between the first clock signal and the second clock signal is maintained at 180°, the signal periods of the first clock signal and the second clock signal differ by half a cycle. Since the clock signal controls the conduction of the power switch tube, that is, the conduction time of the power switch tubes of the first switch circuit and the second switch circuit differs by half a cycle. If at this time, the time when the first clock signal controls the first switch circuit to be turned on and the time when the second clock signal controls the second switch circuit to be turned on are exactly half a cycle, the power switch tube of the first switch circuit will be turned on and the power switch tube of the second switch circuit will be turned off. When the power switch tube of the first switch circuit is turned off, the power switch tube of the second switch circuit will be turned on. This is reflected in the inductor current waveforms of the two switch circuits, with the peak of the inductor current of the first switch circuit and the trough of the inductor current of the second switch circuit corresponding to each other. In this way, the input ripple current can be minimized.

[0053] As described above, in the embodiment of the present invention, a phase-locked loop is set in the multi-channel clock signal output circuit, and the first signal output module and the second signal output module will respectively output and feedback to the phase-locked loop a first sampling signal at the moment when the first clock signal reaches half a signal period and a second sampling signal at the moment when the second clock signal reaches half a signal period, and the phase difference between the first sampling signal and the second sampling signal is locked at 180° through the phase-locked loop, and the first control signal and the second control signal are output according to the locked phase difference, so that the phase difference between the first clock signal and the second clock signal can be maintained at 180°, thereby alternately controlling the turn-on time of the first switch circuit and the second switch circuit, avoiding the first switch circuit and the second switch circuit from being turned on at the same time, reducing the current value of the ripple current, and solving the technical problem of excessive ripple current in the prior art of integrating multiple output channels on a bare chip.

[0054] On the basis of the above embodiment, the first signal output module 21 includes a first charging and discharging unit 211 and a first signal output unit 212 .

[0055] The first input end of the first charge and discharge unit 211 is connected to the first output end of the phase-locked loop 10, and is used to charge with a constant current according to the received first control signal; the first output end and the second output end of the first charge and discharge unit 211 are respectively connected to the first input end and the second input end of the first signal output unit 212, and are used to output a corresponding first voltage signal to the first signal output unit 212 according to the charging amount; the second input end of the first charge and discharge unit 211 is connected to the first output end of the first signal output unit 212, and is used to receive a first clock signal and discharge according to the first clock signal.

[0056] In one embodiment, if Figure 3 As shown, Figure 3 A schematic diagram of the structure of another multi-channel clock signal output circuit provided by an embodiment of the present invention, Figure 3In the embodiment, the first signal output module 21 includes a first charge and discharge unit 211, and the first charge and discharge unit 211 is used to charge with a constant current according to the first clock signal received, that is, to adjust the time to start charging according to the first control signal received, and to start charging with a constant current when the first control signal is received. Specifically, the first output terminal and the second output terminal of the first charge and discharge unit 211 are respectively connected to the first input terminal and the second input terminal of the first signal output unit 212, and are used to output a corresponding first voltage signal to the first signal output unit 212 according to the charge amount. The first voltage signals output by the first output terminal and the second output terminal of the first charge and discharge unit 211 are the same. It can be understood that when the charge amount is higher, the voltage value of the first voltage signal output by the first output terminal and the second output terminal of the first charge and discharge unit 211 is higher. In addition, the second input end of the first charge and discharge unit 211 is connected to the first output end of the first signal output unit 212, and is used to receive the first clock signal and discharge according to the first clock signal. Exemplarily, the first charge and discharge unit 211 can determine the moment when the charge amount reaches the maximum charge amount according to the change of the level in the first clock signal, and discharge when the charge amount reaches the maximum charge amount, so as to recharge after discharging.

[0057] The first output end of the first signal output unit 212 is also used to connect to the first switching circuit, for generating a first clock signal according to the first voltage signal, and transmitting the first clock signal to the first switching circuit and the first charging and discharging unit 211; the second output end of the first signal output unit 212 is connected to the first input end of the phase-locked loop 10, for generating a first sampling signal according to the first voltage signal, and transmitting the first sampling signal to the phase-locked loop 10, and the first sampling signal is used to feedback the moment when the charging amount reaches half of the maximum charging amount.

[0058] In addition, the first signal output module 21 also includes a first signal output unit 212, and the first signal output unit 212 is used to output a first clock signal and a first sampling signal. Specifically, the first output end of the first signal output unit 212 is also used to connect to the first switch circuit, and is used to generate a first clock signal according to the first voltage signal, and transmit the first clock signal to the first switch circuit and the first charge and discharge unit 211. It can be understood that since the first charge and discharge unit 211 will discharge according to the received first clock signal, repeated charging is achieved, so that the first voltage signal changes periodically, and the first clock signal is generated according to the first voltage signal, that is, the first clock signal also changes periodically according to the change of the first voltage signal. In addition, the second output end of the first signal output unit 212 is connected to the first input end of the phase-locked loop 10, and the first signal output unit 212 is also used to generate a first sampling signal according to the first voltage signal, and transmit the first sampling signal to the phase-locked loop 10, and the first sampling signal is used to feedback the moment when the charging amount reaches half of the maximum charging amount. Exemplarily, a comparator may be provided in the first signal output unit 212 , and the comparator is used to compare the first voltage signal with the first voltage signal corresponding to when the charge amount reaches half of the maximum charge amount to generate the first sampling signal.

[0059] On the basis of the above embodiment, the first charge and discharge unit 211 includes a first controlled current source CCCS1, a first capacitor C1 and a first MOS transistor Q1. The controlled end of the first controlled current source CCCS1 is connected to the first output end of the phase-locked loop 10, and the output end of the first controlled current source CCCS1 is connected to the first end of the first capacitor C1 and the first input end and the second input end of the first signal output unit 212, so as to charge the first capacitor C1 with a constant current when receiving the first control signal; the second end of the first capacitor C1 is connected to the drain of the first MOS transistor Q1, the source of the first MOS transistor Q1 is grounded, the gate of the first MOS transistor Q1 is connected to the first output end of the first signal output unit 212, and the first MOS transistor Q1 is used to be turned on and off according to the first clock signal.

[0060] In one embodiment, if Figure 4 , Figure 4A circuit schematic diagram of another multi-channel clock signal output circuit provided by an embodiment of the present invention, wherein the first charge and discharge unit 211 includes a first controlled current source CCCS1, a first capacitor C1, and a first MOS transistor Q1, wherein the controlled end of the first controlled current source CCCS1 is connected to the first output end of the phase-locked loop 10, and the output end of the first controlled current source CCCS1 is connected to the first end of the first capacitor C1 and the first input end and the second input end of the first signal output unit 212, and the first controlled current source CCCS1 is used to start charging the first capacitor C1 with a constant current when receiving the first control signal, that is, the first control signal is used to adjust the moment when the first controlled current source CCCS1 outputs the current. In addition, the second end of the first capacitor C1 is connected to the drain of the first MOS transistor Q1, the source of the first MOS transistor Q1 is connected to the ground, the gate of the first MOS transistor Q1 is connected to the first output end of the first signal output unit 212, and the first MOS transistor Q1 is used to be turned on and off according to the first clock signal. Exemplarily, when the first capacitor C1 is fully charged, the first clock signal outputs a high-level signal, at which time the first MOS transistor Q1 is turned on, and the first capacitor C1 is grounded and begins to discharge. In one embodiment, the first MOS transistor Q1 is an N-channel MOS transistor. In this embodiment, since the current output by the first controlled current source CCCS1 is constant, the voltage of the first capacitor C1 rises linearly with time in one signal cycle, and the time for the voltage of the first capacitor C1 to rise from 0V to 100% is twice the time for the voltage of the capacitor to rise from 0 to 50%, and the time from 0V to 100% is one signal cycle.

[0061] Based on the above embodiment, the first signal output unit 212 is specifically used to detect whether the charge amount of the first capacitor C1 reaches the maximum charge amount, and generate a first clock signal according to whether the charge amount of the first capacitor C1 reaches the maximum charge amount; and is used to detect whether the charge amount of the first capacitor C1 reaches half of the maximum charge amount, and generate a first sampling signal according to whether the charge amount of the first capacitor C1 reaches half of the maximum charge amount.

[0062] In this embodiment, the first signal output unit 212 is specifically used to detect whether the charge of the first capacitor C1 reaches the maximum charge, and to generate a first clock signal according to whether the charge of the first capacitor C1 reaches the maximum charge. Exemplarily, the first signal output unit 212 includes a comparator, which is used to compare the first voltage signal and the voltage signal corresponding to whether the charge of the first capacitor C1 reaches the maximum charge, and to generate a first clock signal according to the comparison result. In addition, the first signal output unit 212 is also used to detect whether the charge of the first capacitor C1 reaches half of the maximum charge, and to generate a first sampling signal according to whether the charge of the first capacitor C1 reaches half of the maximum charge. Similarly, the first sampling signal can also be generated by a comparator.

[0063] On the basis of the above embodiment, the first signal output unit 212 includes a first comparator U1 and a second comparator U2, the non-inverting input terminal of the first comparator U1 and the inverting input terminal of the second comparator U2 are connected to the first end of the first capacitor C1, the inverting input terminal of the first comparator U1 is used to input a first reference voltage signal, and the voltage value of the first reference voltage signal is a voltage signal corresponding to the maximum charge amount of the first capacitor C1; the output terminal of the first comparator U1 is connected to the first switch circuit and the gate of the first MOS tube Q1.

[0064] In one embodiment, if Figure 4 As shown, the first signal output unit 212 includes a first comparator U1 and a second comparator U2, and the in-phase input terminal of the first comparator U1 and the inverting input terminal of the second comparator U2 are connected to the first terminal of the first capacitor C1 for inputting a first voltage signal. The inverting input terminal of the first comparator U1 is used to input a first reference voltage signal, and the voltage value of the first reference voltage signal is a voltage signal corresponding to the maximum charge amount of the first capacitor C1. The first reference voltage signal can be obtained by pre-detecting the voltage signal corresponding to the maximum charge amount of the first capacitor C1. The output terminal of the first comparator U1 is connected to the first switch circuit and the gate of the first MOS tube Q1. That is, in this embodiment, when the first capacitor C1 is charged to a first voltage value greater than the first reference voltage signal, the first clock signal output by the first comparator U1 will be converted from a low level signal to a high level signal, the first MOS tube Q1 is turned on, and the first capacitor C1 is discharged.

[0065] The non-inverting input terminal of the second comparator U2 is used to input a second reference voltage signal, the voltage value of which is a voltage signal corresponding to half of the maximum charge amount of the first capacitor C1 ; the output terminal of the second comparator U2 is connected to the first input terminal of the phase-locked loop 10 .

[0066] In addition, the in-phase input terminal of the second comparator U2 is used to input the second reference voltage signal, the voltage value of the second reference voltage signal is the voltage signal corresponding to the first capacitor C1 reaching half of the maximum charge amount, and the second reference voltage signal can also be measured in advance. That is, when the first voltage value is not less than the second reference voltage signal, the first sampling signal will be converted from a high level to a low level, until the first capacitor C1 starts to discharge and the first voltage signal is less than the second reference voltage signal, then the first sampling signal is converted from a low level to a high level. In addition, since the second comparator U2 outputs the first sampling signal to the phase-locked loop 10, the rising edge signal of the first sampling signal can be locked by the phase-locked loop 10 to achieve subsequent phase difference locking.

[0067] On the basis of the above embodiment, the second signal output module 22 includes a second charging and discharging unit 221 and a second signal output unit 222;

[0068] The first input end of the second charge and discharge unit 221 is connected to the second output end of the phase-locked loop 10, and is used to charge with a constant current according to the second control signal received; the first output end and the second output end of the second charge and discharge unit 221 are respectively connected to the first input end and the second input end of the second signal output unit 222, and are used to output a corresponding second voltage signal to the second signal output unit 222 according to the charging amount; the second input end of the second charge and discharge unit 221 is connected to the first output end of the second signal output unit 222, and is used to receive the second clock signal and discharge according to the second clock signal;

[0069] The first output end of the second signal output unit 222 is also used to connect to the second switching circuit, for generating a second clock signal according to the second voltage signal, and transmitting the second clock signal to the second switching circuit and the second charging and discharging unit 221; the second output end of the second signal output unit 222 is connected to the second input end of the phase-locked loop 10, for generating a second sampling signal according to the second voltage signal, and transmitting the second sampling signal to the phase-locked loop 10, and the second sampling signal is used to feedback the moment when the charging amount reaches half of the maximum charging amount.

[0070] On the basis of the above embodiment, the second charge and discharge unit 221 includes a second controlled current source CCCS2, a second capacitor C2 and a second MOS transistor Q2, the controlled end of the second controlled current source CCCS2 is connected to the second output end of the phase-locked loop 10, the output end of the second controlled current source CCCS2 is connected to the first end of the second capacitor C2 and the first input end and the second input end of the second signal output unit 222, and is used to charge the second capacitor C2 with a constant current when receiving the second control signal; the second end of the second capacitor C2 is connected to the drain of the second MOS transistor Q2, the source of the second MOS transistor Q2 is grounded, the gate of the second MOS transistor Q2 is connected to the first output end of the second signal output unit 222, and the second MOS transistor Q2 is used to be turned on and off according to the second clock signal.

[0071] Based on the above embodiment, the second signal output unit 222 is specifically used to detect whether the charge amount of the second capacitor C2 reaches the maximum charge amount, and generate a second clock signal according to whether the charge amount of the second capacitor C2 reaches the maximum charge amount; and is used to detect whether the charge amount of the second capacitor C2 reaches half of the maximum charge amount, and generate a second sampling signal according to whether the charge amount of the second capacitor C2 reaches half of the maximum charge amount.

[0072] On the basis of the above embodiment, the second signal output unit 222 includes a third comparator U3, a fourth comparator U4 and an inverter U5, the non-inverting input terminal of the third comparator U3 and the inverting input terminal of the fourth comparator U4 are connected to the first end of the second capacitor C2, the inverting input terminal of the third comparator U3 is used to input a third reference voltage signal, and the voltage value of the third reference voltage signal is a voltage signal corresponding to the maximum charge amount of the second capacitor C2; the output terminal of the third comparator U3 is connected to the second switch circuit and the gate of the second MOS tube Q2;

[0073] The non-inverting input terminal of the fourth comparator U4 is used to input a fourth reference voltage signal, and the voltage value of the fourth reference voltage signal is a voltage signal corresponding to half of the maximum charge amount of the first capacitor C1; the output terminal of the fourth comparator U4 is connected to the input terminal of the inverter U5, and the output terminal of the inverter U5 is connected to the second input terminal of the phase-locked loop 10.

[0074] Similarly, the circuit structure of the second signal output unit 222 in this embodiment is similar to the circuit structure of the second signal output unit 222, and the specifications (i.e., capacitance values) of the first capacitor C1 and the second capacitor C2 are the same, and the only difference is that the second signal output unit 222 further includes an inverter U5. Figure 4 As shown, the output end of the fourth comparator U4 is connected to the input end of the inverter U5, and the output end of the inverter U5 is connected to the second input end of the phase-locked loop 10. The inverter U5 is used to invert the signal output by the fourth comparator U4 to obtain a second sampling signal, and then output the second sampling signal to the phase-locked loop 10. In one embodiment, as Figure 5 As shown, Figure 5 The timing diagram of the first sampling signal and the second sampling signal provided by the embodiment of the present invention, wherein Verf is the voltage signal corresponding to the charge amount of the first capacitor C1 and the second capacitor C2 when the charge amount reaches the maximum charge amount, Vcap1 is the first voltage signal, CLK1-PFD is the first sampling signal, Vcap2 is the second voltage signal, CLK2-PFD is the voltage signal output by the second comparator U2, CLK2-PFDb is the second sampling signal, Figure 5 It can be seen that if the phase-locked loop 10 phase-locks the rising edge of the first sampling signal CLK1_PFD and the rising edge of the second sampling signal CLK2_PFDb, then when the first clock signal ends a signal cycle, the second clock signal executes half a signal cycle, that is, the phase difference between the first clock signal and the second clock signal is half a signal cycle.

[0075] As described above, the embodiment of the present invention sets a phase-locked loop in the multi-channel clock signal output circuit, and the signal output module outputs a sampling signal to the phase-locked loop when the feedback clock signal reaches half a signal cycle. The phase difference of the sampling signals output by two adjacent signal output modules is locked at a preset angle through the phase-locked loop, and a control signal is output to each signal output module according to the locked phase difference to keep the phase difference of the clock signals output by the two adjacent signal output modules at the preset angle, thereby controlling the turn-on time of different switch circuits and avoiding the adjacent switch circuits from being turned on at the same time, thereby reducing the current value of the ripple current, and solving the technical problem of excessive ripple current in the prior art method of integrating multiple output channels on a bare chip.

[0076] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the embodiments of the present invention are not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the embodiments of the present invention. Therefore, although the embodiments of the present invention are described in more detail through the above embodiments, the embodiments of the present invention are not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the embodiments of the present invention, and the scope of the embodiments of the present invention is determined by the scope of the appended claims.

Claims

1. A multi-channel clock signal output circuit, characterized in that: It includes a phase-locked loop and at least two signal output modules; The first output end of the signal output module is used to connect with the switch circuit, and is used to output the clock signal to the switch circuit. The second output end of the signal output module is connected with the input port of the phase-locked loop, and is used to output the sampling signal to the phase-locked loop, and the sampling signal is used to detect the moment when the clock signal reaches half a signal cycle; the input end of the signal output module is connected with the output port of the phase-locked loop, and is used to receive the control signal output by the phase-locked loop, and generate the clock signal according to the control signal; The phase-locked loop is used to lock the phase difference of the sampling signals output by two adjacent signal output modules at a preset angle, and output the control signal to each of the signal output modules according to the locked phase difference, so as to keep the phase difference of the clock signals output by the two adjacent signal output modules at the preset angle, wherein the preset angle is 360° / n, and n is the number of the signal output modules.

2. The multi-channel clock signal output circuit according to claim 1, characterized in that: The signal output module includes a first signal output module and a second signal output module; The first output end of the first signal output module is used to be connected to the first switch circuit, and is used to output a first clock signal to the first switch circuit. The second output end of the first signal output module is connected to the first input end of the phase-locked loop, and is used to output a first sampling signal to the phase-locked loop, and the first sampling signal is used to detect the moment when the first clock signal reaches half a signal cycle; the input end of the first signal output module is connected to the first output end of the phase-locked loop, and is used to receive a first control signal output by the phase-locked loop, and generate the first clock signal according to the first control signal; The first output end of the second signal output module is used to connect with the second switch circuit, and is used to output the second clock signal to the second switch circuit. The second output end of the second signal output module is connected with the second input end of the phase-locked loop, and is used to output the second sampling signal to the phase-locked loop. The second sampling signal is used to detect the moment when the second clock signal reaches half a signal cycle. The input end of the second signal output module is connected with the second output end of the phase-locked loop, and is used to receive the second control signal output by the phase-locked loop, and generate the second clock signal according to the second control signal. The duration of the signal cycle of the first clock signal is the same as the duration of the signal cycle of the second clock signal. The phase-locked loop is used to lock the phase difference between the first sampling signal and the second sampling signal at 180°, and output the first control signal and the second control signal according to the locked phase difference to keep the phase difference between the first clock signal and the second clock signal at 180°.

3. The multi-channel clock signal output circuit according to claim 2, characterized in that: The first signal output module includes a first charging and discharging unit and a first signal output unit; The first input end of the first charge and discharge unit is connected to the first output end of the phase-locked loop, and is used to charge with a constant current according to the first control signal received; the first output end and the second output end of the first charge and discharge unit are respectively connected to the first input end and the second input end of the first signal output unit, and are used to output a corresponding first voltage signal to the first signal output unit according to the charging amount; The second input end of the first charge and discharge unit is connected to the first output end of the first signal output unit, and is used to receive the first clock signal and discharge according to the first clock signal; The first output end of the first signal output unit is also used to connect to the first switching circuit, for generating the first clock signal according to the first voltage signal, and transmitting the first clock signal to the first switching circuit and the first charging and discharging unit; the second output end of the first signal output unit is connected to the first input end of the phase-locked loop, for generating the first sampling signal according to the first voltage signal, and transmitting the first sampling signal to the phase-locked loop, and the first sampling signal is used to feedback the moment when the charging amount reaches half of the maximum charging amount.

4. The multi-channel clock signal output circuit according to claim 3, characterized in that: The first charge and discharge unit includes a first controlled current source, a first capacitor and a first MOS transistor, wherein the controlled end of the first controlled current source is connected to the first output end of the phase-locked loop, the output end of the first controlled current source is connected to the first end of the first capacitor and the first input end and the second input end of the first signal output unit, and is used to charge the first capacitor with a constant current when the first control signal is received; the second end of the first capacitor is connected to the drain of the first MOS transistor, the source of the first MOS transistor is grounded, the gate of the first MOS transistor is connected to the first output end of the first signal output unit, and the first MOS transistor is used to be turned on and off according to the first clock signal.

5. The multi-channel clock signal output circuit according to claim 4, characterized in that: The first MOS transistor is an N-channel MOS transistor.

6. The multi-channel clock signal output circuit according to claim 4, characterized in that: The first signal output unit is specifically used to detect whether the charge amount of the first capacitor reaches the maximum charge amount, and generate a first clock signal according to whether the charge amount of the first capacitor reaches the maximum charge amount; and to detect whether the charge amount of the first capacitor reaches half of the maximum charge amount, and generate a first sampling signal according to whether the charge amount of the first capacitor reaches half of the maximum charge amount.

7. The multi-channel clock signal output circuit according to claim 6, characterized in that: The first signal output unit includes a first comparator and a second comparator, the non-inverting input terminal of the first comparator and the inverting input terminal of the second comparator are connected to the first end of the first capacitor, the inverting input terminal of the first comparator is used to input a first reference voltage signal, and the voltage value of the first reference voltage signal is a voltage signal corresponding to the first capacitor reaching the maximum charge amount; The output end of the first comparator is connected to the first switch circuit and the gate of the first MOS tube; The non-inverting input terminal of the second comparator is used to input a second reference voltage signal, and the voltage value of the second reference voltage signal is a voltage signal corresponding to the first capacitor reaching half of the maximum charge amount; the output terminal of the second comparator is connected to the first input terminal of the phase-locked loop.

8. The multi-channel clock signal output circuit according to claim 2, characterized in that: The second signal output module includes a second charging and discharging unit and a second signal output unit; The first input terminal of the second charge and discharge unit is connected to the second output terminal of the phase-locked loop, and is used for charging with a constant current according to the second control signal received; The first output terminal and the second output terminal of the second charge-discharge unit are respectively connected to the first input terminal and the second input terminal of the second signal output unit, and are used to output a corresponding second voltage signal to the second signal output unit according to the charge amount; the second input terminal of the second charge-discharge unit is connected to the first output terminal of the second signal output unit, and is used to receive the second clock signal and discharge according to the second clock signal; The first output end of the second signal output unit is also used to connect to the second switch circuit, to generate the second clock signal according to the second voltage signal, and to transmit the second clock signal to the second switch circuit and the second charge and discharge unit; The second output end of the second signal output unit is connected to the second input end of the phase-locked loop, and is used to generate the second sampling signal according to the second voltage signal, and transmit the second sampling signal to the phase-locked loop, and the second sampling signal is used to feedback the moment when the charging amount reaches half of the maximum charging amount.

9. The multi-channel clock signal output circuit according to claim 8, characterized in that: The second charge and discharge unit includes a second controlled current source, a second capacitor and a second MOS tube, the controlled end of the second controlled current source is connected to the second output end of the phase-locked loop, the output end of the second controlled current source is connected to the first end of the second capacitor and the first input end and the second input end of the second signal output unit, and is used to charge the second capacitor with a constant current when receiving the second control signal; the second end of the second capacitor is connected to the drain of the second MOS tube, the source of the second MOS tube is grounded, the gate of the second MOS tube is connected to the first output end of the second signal output unit, and the second MOS tube is used to be turned on and off according to the second clock signal.

10. The multi-channel clock signal output circuit according to claim 9, characterized in that: The second signal output unit is specifically used to detect whether the charge amount of the second capacitor reaches the maximum charge amount, and generate a second clock signal according to whether the charge amount of the second capacitor reaches the maximum charge amount; and to detect whether the charge amount of the second capacitor reaches half of the maximum charge amount, and generate a second sampling signal according to whether the charge amount of the second capacitor reaches half of the maximum charge amount.

11. The multi-channel clock signal output circuit according to claim 10, characterized in that: The second signal output unit includes a third comparator, a fourth comparator and an inverter, wherein the non-inverting input terminal of the third comparator and the inverting input terminal of the fourth comparator are connected to the first terminal of the second capacitor, and the inverting input terminal of the third comparator is used to input a third reference voltage signal, wherein the voltage value of the third reference voltage signal is a voltage signal corresponding to the second capacitor reaching the maximum charge amount; the output terminal of the third comparator is connected to the second switch circuit and the gate of the second MOS tube; The non-inverting input terminal of the fourth comparator is used to input a fourth reference voltage signal, and the voltage value of the fourth reference voltage signal is a voltage signal corresponding to the second capacitor reaching half of the maximum charge amount; the output terminal of the fourth comparator is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the second input terminal of the phase-locked loop.

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