Sub-sampling phase-locked loop based on dead zone generation module and control method thereof

Abstract

The invention provides a sub-sampling phase-locked loop based on a dead zone generation module and a control method thereof.The sub-sampling phase-locked loop comprises a sub-sampling loop, a frequency locking loop, a loop filter and a voltage-controlled oscillator, and the sub-sampling loop is used for sampling an oscillation signal output by the voltage-controlled oscillator according to a received reference clock signal; a first current signal is output to the loop filter; the frequency locking loop is used for outputting a second current signal to the loop filter according to the received reference clock signal and the first frequency division signal and generating a dead zone control signal; the dead zone control signal is used for adjusting the first current signal or the second current signal; the loop filter is used for receiving the first current signal and the second current signal and outputting an oscillation control signal to the voltage-controlled oscillator; the voltage-controlled oscillator is used for generating an oscillation signal according to the oscillation control signal. The sub-sampling phase-locked loop can generate a plurality of dead zone ranges by using the frequency locking loop, so that the locking time of the sub-sampling phase-locked loop is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of phase-locked loops, and in particular to a sub-sampling phase-locked loop based on a dead zone generation module and a control method thereof. Background Art

[0002] A phase-locked loop is a negative feedback control system that uses the voltage generated by phase synchronization to regulate a voltage-controlled oscillator to generate a target frequency. Phase-locked loops can be used in technical scenarios such as recovering system-on-chip signals, modulating frequencies, and generating clock signals. In the process of using a phase-locked loop to generate a clock signal, the phase noise of the clock signal is too large due to the frequency divider in the phase-locked loop, which in turn reduces the performance of the phase-locked loop.

[0003] By using the sub-sampling phase detector in the sub-sampling phase-locked loop to perform low-frequency sampling on the voltage-controlled oscillator, the phase noise of the clock signal output by the voltage-controlled oscillator can be reduced. However, since the sub-sampling phase detector cannot obtain the frequency information of the clock signal, the sub-sampling phase-locked loop needs to use an auxiliary circuit to lock the phase of the clock signal. Among them, the auxiliary circuit can be a frequency-locked loop with a dead zone phase detector. In order to open the frequency-locked loop, a certain amount of time is required to accumulate the phase error of the clock signal. When the phase error rises to a value greater than the dead zone threshold, the frequency-locked loop is turned on and the phase of the clock signal is adjusted until the phase error drops to a value less than the dead zone threshold, and the frequency-locked loop is disconnected.

[0004] Since the dead zone threshold of the frequency locked loop cannot be adjusted according to the frequency of the clock signal, when the phase error of the clock signal is small, it takes a long time to accumulate the phase error before the frequency locked loop can be turned on, which leads to a longer locking time of the sub-sampling phase-locked loop. Summary of the invention

[0005] The present application provides a sub-sampling phase-locked loop based on a dead zone generation module and a control method thereof, which can utilize a frequency locked loop to generate multiple dead zone ranges, automatically adjust the charge and discharge currents of a charge pump and a sub-sampling charge pump, and reduce the locking time of the sub-sampling phase-locked loop.

[0006] In a first aspect, the present application provides a sub-sampling phase-locked loop based on a dead zone generation module, comprising: a sub-sampling loop, configured to: sample an oscillation signal output by a voltage-controlled oscillator according to a received reference clock signal, and output a first current signal to a loop filter;

[0007] A frequency locked loop, configured to: output a second current signal to the loop filter and generate a dead zone control signal according to a received reference clock signal and a first frequency division signal; the dead zone control signal is used to adjust the first current signal or the second current signal, and the first frequency division signal is obtained by dividing the oscillation signal;

[0008] A loop filter, configured to: receive the first current signal and the second current signal, and output an oscillation control signal to the voltage-controlled oscillator, wherein the oscillation control signal is used to adjust an output frequency of the voltage-controlled oscillator;

[0009] The voltage-controlled oscillator is configured to generate the oscillation signal according to the oscillation control signal.

[0010] Optionally, the sub-sampling loop includes: a sub-sampling phase detector configured to: sample the oscillation signal according to the received reference clock signal, and output a voltage difference signal to a sub-sampling charge pump;

[0011] a sub-sampling charge pump configured to: generate the first current signal according to the received voltage difference signal, adjust the first current signal according to the received dead zone control signal, and output the adjusted first current signal to the loop filter;

[0012] The pulse generator is configured to generate a pulse signal according to the received reference clock signal, and output the pulse signal to the sub-sampling charge pump, wherein the pulse signal is used to control the conduction or disconnection of the first current signal.

[0013] Optionally, the frequency locked loop includes: a frequency detector and a phase detector configured to: sample the first frequency-divided signal according to the received reference clock signal, and output a charging signal and a discharging signal to the dead zone generation module;

[0014] A frequency divider is configured to: perform frequency division on the received oscillation signal to obtain a first frequency division signal and a second frequency division signal, and output the first frequency division signal to the frequency detector and phase detector, and output the first frequency division signal and the second frequency division signal to the dead zone generation module; the frequency of the first frequency division signal is less than the frequency of the second frequency division signal;

[0015] a dead zone generating module, configured to: output the dead zone control signal to the charge pump to adjust the second current signal, or output the dead zone control signal to the sub-sampling charge pump to adjust the first current signal according to the received reference clock signal, the first frequency-divided signal, the second frequency-divided signal, the charging signal and the discharging signal;

[0016] The charge pump is configured to generate the second current signal according to the received dead zone control signal, and output the second current signal to the loop filter.

[0017] Optionally, the frequency divider is also configured to: perform frequency division on the received oscillation signal to obtain a third frequency division signal and a fourth frequency division signal, and output the third frequency division signal and the fourth frequency division signal to the dead zone generation module; the frequency of the third frequency division signal is less than the frequency of the fourth frequency division signal, and the frequency of the third frequency division signal is greater than the frequency of the second frequency division signal.

[0018] Optionally, the dead zone generation module includes a first dead zone module, and the first dead zone module includes: a first inverter configured to: perform phase inversion on the received second frequency-divided signal, and output a first frequency-divided inverted signal to a first trigger;

[0019] A second inverter is configured to: perform phase inversion on the received second frequency-divided signal, and output a second frequency-divided inverted signal to a second flip-flop;

[0020] a first trigger, configured to: perform sampling on the received charging signal according to the first frequency-divided inverted signal, and output a first sampled charging signal to a third trigger;

[0021] a second trigger, configured to: perform sampling on the received discharge signal according to the second frequency-divided inverted signal, and output a first sampled discharge signal to a fourth trigger;

[0022] a third trigger, configured to: sample the first sampled charging signal according to the received first frequency-divided signal, and output a second sampled charging signal to the first OR gate;

[0023] a fourth trigger, configured to: sample the first sampled discharge signal according to the received reference clock signal, and output a second sampled discharge signal to the first OR gate;

[0024] The first OR gate is configured to perform an OR operation on the received second sampled charging signal and the second sampled discharging signal, and output a first dead zone control signal to the charge pump.

[0025] Optionally, the dead zone generating module includes a second dead zone module, and the second dead zone module includes: a third inverter configured to: perform phase inversion on the received third frequency-divided signal, and output the third frequency-divided inverted signal to the fifth trigger;

[0026] a fourth inverter configured to: perform phase inversion on the received third frequency-divided signal, and output a fourth frequency-divided inverted signal to a sixth flip-flop;

[0027] a fifth trigger, configured to: perform sampling on the received charging signal according to the third frequency-divided inverted signal, and output a third sampled charging signal to the seventh trigger;

[0028] a sixth trigger, configured to: perform sampling on the received discharge signal according to the fourth frequency-divided inverted signal, and output a third sampled discharge signal to an eighth trigger;

[0029] a seventh trigger, configured to: sample the third sampled charging signal according to the received first frequency-divided signal, and output a fourth sampled charging signal to the second OR gate and the charge pump;

[0030] an eighth trigger, configured to: sample the third sampled discharge signal according to the received reference clock signal, and output a fourth sampled discharge signal to the second OR gate and the charge pump;

[0031] The second OR gate is configured to perform an OR operation on the received fourth sampled charging signal and the fourth sampled discharging signal, and output a second dead zone control signal to the charge pump.

[0032] Optionally, the dead zone generation module includes a third dead zone module, and the third dead zone module includes: a fifth inverter configured to: perform phase inversion on the received fourth frequency-divided signal and output a fifth frequency-divided inverted signal to a ninth flip-flop;

[0033] a sixth inverter configured to: perform phase inversion on the received fourth frequency-divided signal, and output a sixth frequency-divided inverted signal to a tenth flip-flop;

[0034] a ninth trigger, configured to: perform sampling on the received charging signal according to the fifth frequency-divided inverted signal, and output a fifth sampled charging signal to the eleventh trigger;

[0035] a tenth flip-flop, configured to: perform sampling on the received discharge signal according to the sixth frequency-divided inverted signal, and output a fifth sampled discharge signal to a twelfth flip-flop;

[0036] an eleventh trigger, configured to: sample the fifth sampled charging signal according to the received first frequency-divided signal, and output a sixth sampled charging signal to a third OR gate;

[0037] a twelfth trigger, configured to: sample the fifth sampled discharge signal according to the received reference clock signal, and output a sixth sampled discharge signal to a third OR gate;

[0038] The third OR gate is configured to perform an OR operation on the received sixth sampling charge signal and the sixth sampling discharge signal, and output a third dead zone control signal to the sub-sampling charge pump.

[0039] Optionally, the charge pump includes a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a sixth current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch;

[0040] The first current source, the second current source and the third current source are connected in parallel to the first node, and the fourth current source, the fifth current source and the sixth current source are connected in parallel to the second node;

[0041] The first switch is provided between the second current source and the first node, and the second switch is provided between the third current source and the first node;

[0042] The third switch and the fourth switch are sequentially arranged between the first node and the second node, and the third switch and the fourth switch are connected to the third node;

[0043] The fifth switch is provided between the fifth current source and the second node, and the sixth switch is provided between the sixth current source and the second node.

[0044] Optionally, the sub-sampling charge pump includes a seventh switch, and the sub-sampling charge pump is configured to: control the on or off of the seventh switch according to the received third dead zone control signal;

[0045] The charge pump is further configured to: control the on or off of the first switch according to the first dead zone control signal received; control the on or off of the second switch according to the second dead zone control signal received; control the on or off of the third switch according to the fourth sampled charging signal received; control the on or off of the fourth switch according to the fourth sampled discharging signal received; control the on or off of the fifth switch according to the first dead zone control signal received; control the on or off of the sixth switch according to the second dead zone control signal received

[0046] In a second aspect, the present application further provides a sub-sampling phase-locked loop control method based on a dead zone generation module, the control method being applied to a sub-sampling phase-locked loop based on a dead zone generation module as in the above-mentioned embodiment, wherein the sub-sampling phase-locked loop control method based on a dead zone generation module comprises: sampling an oscillation signal output by a voltage-controlled oscillator according to a received reference clock signal, and outputting a first current signal to a loop filter;

[0047] Outputting a second current signal to the loop filter and generating a dead zone control signal according to the received reference clock signal and the first frequency division signal; the dead zone control signal is used to adjust the first current signal or the second current signal, and the first frequency division signal is obtained by dividing the oscillation signal;

[0048] receiving the first current signal and the second current signal, and outputting an oscillation control signal to the voltage-controlled oscillator, wherein the oscillation control signal is used to adjust an output frequency of the voltage-controlled oscillator;

[0049] The oscillation signal is generated according to the oscillation control signal.

[0050] It can be seen from the above technical solution that the present application provides a sub-sampling phase-locked loop based on a dead zone generation module and a control method thereof, including a sub-sampling loop, a frequency-locked loop, a loop filter and a voltage-controlled oscillator, wherein the sub-sampling loop is used to sample the oscillation signal output by the voltage-controlled oscillator according to the received reference clock signal, and output a first current signal to the loop filter; the frequency-locked loop is used to output a second current signal to the loop filter according to the received reference clock signal and the first frequency-divided signal, and generate a dead zone control signal; the dead zone control signal is used to adjust the first current signal or the second current signal; the loop filter is used to receive the first current signal and the second current signal, and output an oscillation control signal to the voltage-controlled oscillator; the voltage-controlled oscillator is used to generate an oscillation signal according to the oscillation control signal. The above-mentioned sub-sampling phase-locked loop can generate multiple dead zone ranges using the frequency-locked loop, thereby reducing the locking time of the sub-sampling phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] Figure 1 A schematic diagram of a sub-sampling phase-locked loop circuit based on a dead zone generation module according to an embodiment of the present application;

[0053] Figure 2 This is a circuit diagram of a first dead zone module according to an embodiment of the present application;

[0054] Figure 3 This is a circuit diagram of a second dead zone module according to an embodiment of the present application;

[0055] Figure 4 This is a circuit diagram of a third dead zone module according to an embodiment of the present application;

[0056] Figure 5 A schematic diagram of a first condition of a dead zone control signal according to an embodiment of the present application;

[0057] Figure 6 A schematic diagram of a second condition of a dead zone control signal according to an embodiment of the present application;

[0058] Figure 7A circuit diagram of a charge pump according to an embodiment of the present application;

[0059] Figure 8 A circuit diagram of a sub-sampling charge pump according to an embodiment of the present application;

[0060] Fig. 9 Schematic diagram of the steps of a sub-sampling phase-locked loop control method based on a dead zone generation module according to an embodiment of the present application. DETAILED DESCRIPTION

[0061] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0062] A phase-locked loop is a negative feedback control system that uses the voltage generated by phase synchronization to regulate a voltage-controlled oscillator to generate a target frequency. Phase-locked loops can be used in technical scenarios such as recovering signals of on-chip systems, modulating frequencies, and generating clock signals. In digital systems that generate clock signals, larger clock jitter will increase the signal settling time and affect the operating frequency of the digital system. Since clock jitter represents the instability of the sampling voltage and affects the signal-to-noise ratio of the digital-to-analog hybrid converter, it is necessary to improve the performance of the phase-locked loop to reduce the phase noise of the digital system.

[0063] In the traditional phase-locked loop structure, the presence of the frequency divider in the feedback loop causes the noise of the reference clock to be amplified in the loop, which in turn limits the noise performance of the traditional phase-locked loop. The fractional phase-locked loop uses a higher reference frequency and a larger loop bandwidth during the design process, and the output frequency is a fractional multiple of the reference frequency to reduce the locking time of the phase-locked loop. However, the fractional phase-locked loop will introduce fractional spurious and quantization noise, which will reduce the performance of the phase-locked loop.

[0064] By using the sub-sampling phase detector in the sub-sampling phase-locked loop to perform low-frequency sampling on the voltage-controlled oscillator, the phase noise of the clock signal output by the voltage-controlled oscillator can be reduced. However, since the sub-sampling phase detector cannot obtain the frequency information of the clock signal, the sub-sampling phase-locked loop needs to use an auxiliary circuit to lock the phase of the clock signal. Among them, the auxiliary circuit can be a frequency-locked loop with a dead-zone phase detector. Since the frequency-locked loop needs to switch the working state of the loop according to the phase error and the frequency error, the sub-sampling phase-locked loop will have high power consumption and low working efficiency.

[0065] In the above auxiliary circuit, in order to open the frequency lock loop, a certain amount of time is required to accumulate the phase error of the clock signal. When the phase error rises to a value greater than the dead zone threshold, the frequency lock loop is turned on and the phase of the clock signal is adjusted until the phase error drops to a value less than the dead zone threshold, and the frequency lock loop is disconnected. Since the dead zone threshold of the frequency lock loop cannot be adjusted according to the frequency of the clock signal, when the phase error of the clock signal is small, a longer time is required to accumulate the phase error before the frequency lock loop can be opened, which results in a longer locking time of the sub-sampling phase-locked loop.

[0066] In order to reduce the locking time of a sub-sampling phase-locked loop, some embodiments of the present application provide a sub-sampling phase-locked loop based on a dead zone generation module. Figure 1 The sub-sampling phase-locked loop circuit diagram based on the dead zone generation module of the embodiment of the present application is shown below. Figure 1 The sub-sampling phase-locked loop based on the dead zone generation module of this embodiment is described in detail.

[0067] Some embodiments of the present application provide a sub-sampling phase-locked loop based on a dead zone generation module, comprising: a sub-sampling loop, a frequency locked loop, a loop filter, and a voltage controlled oscillator. The sub-sampling loop is configured to receive a reference clock signal f ref The oscillation signal f output by the voltage controlled oscillator out The frequency locked loop is configured to sample the reference clock signal f ref and the first frequency-divided signal f div , output the second current signal to the loop filter, and generate a dead zone control signal; the dead zone control signal is used to adjust the first current signal or the second current signal, the first frequency division signal f div By the oscillation signal f out The loop filter is configured to receive the first current signal and the second current signal, and output an oscillation control signal to the voltage-controlled oscillator, the oscillation control signal is used to adjust the output frequency of the voltage-controlled oscillator; the voltage-controlled oscillator is configured to generate an oscillation signal f according to the oscillation control signal out .

[0068] It should be noted that the oscillation signal f output by the voltage-controlled oscillator out The frequency of the voltage-controlled oscillator changes continuously with the change of the input voltage. By adjusting the oscillation control signal at the input end, the capacitance of the voltage-controlled capacitor inside the voltage-controlled oscillator is changed, thereby controlling the oscillation signal f out The loop filter filters the first current signal and the second current signal, and outputs an oscillation control signal to the voltage-controlled oscillator. The filtered signal adjusts the oscillation signal f out frequency, while improving the stability of the sub-sampling phase-locked loop system.

[0069] In some embodiments, the sub-sampling loop includes: a sub-sampling phase detector, a sub-sampling charge pump and a pulse generator. The sub-sampling phase detector is a phase detector for phase detection. The sub-sampling phase detector is configured to receive a reference clock signal f ref For the oscillation signal f out The sub-sampling phase detector samples the oscillation signal f output by the voltage-controlled oscillator directly. out , converting the phase difference into a voltage difference signal output.

[0070] For example, when the oscillation signal f out With the reference clock signal f ref When the phase is aligned, the sampled voltage value will be close to the DC level of the voltage-controlled oscillator output. out With the reference clock signal f ref When there is a phase error, the sampled voltage will deviate from the DC level. Based on this, the phase difference is obtained by measuring the deviation between the sampled voltage and the DC level.

[0071] The sub-sampling charge pump converts the voltage difference signal output by the sub-sampling phase detector into an output current. The sub-sampling charge pump is configured to generate a first current signal according to the received voltage difference signal, adjust the first current signal according to the received dead zone control signal, and output the adjusted first current signal to the loop filter. The sub-sampling charge pump generates the first current signal by converting the received voltage difference signal into a current signal. In addition, the sub-sampling charge pump also receives a dead zone control signal and adjusts the first current signal by changing the number of current sources operating in the sub-sampling charge pump.

[0072] The pulse generator is used to generate a pulse signal with a specific width. The pulse generator is configured to, according to the received reference clock signal f ref A pulse signal is generated and output to a sub-sampling charge pump. The pulse signal controls the conduction or disconnection of the first current signal by controlling the on and off time of the sub-sampling charge pump.

[0073] The above sub-sampling loop uses the sub-sampling phase detector to detect the oscillation signal f output by the voltage-controlled oscillator. out Direct sampling is performed to input the voltage difference signal, the dead zone control signal and the pulse signal into a sub-sampling charge pump, and the first current signal is input into the loop filter through the sub-sampling charge pump, which can simplify the loop structure, reduce noise, and achieve higher phase synchronization accuracy and lower phase error.

[0074] In some embodiments, a frequency locked loop is used to lock the reference clock signal f ref With the first frequency-divided signal f divThe phase difference is converted into a second current signal to control the output frequency of the voltage controlled oscillator. The frequency locked loop includes: a frequency detector, a frequency divider, a dead zone generation module and a charge pump.

[0075] The phase frequency detector is configured to receive a reference clock signal f ref For the first frequency-divided signal f div The frequency detector compares the reference clock signal f ref and the first frequency-divided signal f div The phase difference between the two signals is used to detect the frequency difference and phase difference between the two signals.

[0076] For example, when the reference clock signal f ref The phase of the first frequency division signal f div When the frequency detector outputs the charging signal UP, it is a high-level rectangular pulse, and the pulse width is the same as the reference clock signal f ref , the first frequency division signal f div The high-level rectangular pulse corresponds to the phase difference between the reference clock signal f ref When the rising edge arrives, the first frequency division signal f div At the same time, the discharge signal DN output by the frequency detector is always at a low level.

[0077] Exemplarily, when the first frequency-divided signal f div The phase leads the reference clock signal f ref When the frequency detector outputs the discharge signal DN, it is a high-level rectangular pulse, and the pulse width is the same as the reference clock signal f ref , the first frequency division signal f div The high-level rectangular pulse in the first frequency-divided signal f div The rising edge starts at the reference clock signal f ref At the same time, the charging signal UP output by the frequency detector is always at a low level.

[0078] For example, when the reference clock signal f ref With the first frequency-divided signal f div When the phases of the charging signal UP and the discharging signal DN are the same, both the charging signal UP and the discharging signal DN are always at a low level.

[0079] A frequency divider is an electronic component that divides the frequency of an input signal to reduce the signal frequency. The frequency divider is configured to receive an oscillating signal f out Perform frequency division to obtain a first frequency division signal f div and the second frequency division signal f1, and outputs the first frequency division signal f1 to the frequency and phase detector div, and output the first frequency division signal f to the dead zone generation module div and the second frequency-divided signal f1. div The frequency of is less than the frequency of the second frequency-divided signal f1.

[0080] In some embodiments, the frequency divider is further configured to receive the oscillating signal f out Frequency division is performed to obtain a third frequency division signal f2 and a fourth frequency division signal f3, and the third frequency division signal f2 and the fourth frequency division signal f3 are output to the dead zone generation module. The frequency of the third frequency division signal f2 is less than the frequency of the fourth frequency division signal f3, and the frequency of the third frequency division signal f2 is greater than the frequency of the second frequency division signal f1.

[0081] The dead zone generation module is used to monitor and compare the input signal. When the input signal is within the preset dead zone range, the dead zone generation module does not generate output; when the input signal exceeds the preset dead zone range, the dead zone generation module generates corresponding output according to the preset rules. The dead zone generation module is configured to receive the reference clock signal f ref , the first frequency division signal f div , the second frequency-divided signal f1, the charging signal UP and the discharging signal DN, output a dead zone control signal to the charge pump to adjust the second current signal, or output a dead zone control signal to the sub-sampling charge pump to adjust the first current signal.

[0082] In some embodiments, the dead zone generation module includes a first dead zone module, a second dead zone module and a third dead zone module, and the first dead zone module, the second dead zone module and the third dead zone module are used to generate dead zone ranges of different widths according to different input frequencies. The dead zone generation module includes a preset number of inverters, triggers, or gates.

[0083] It should be noted that an inverter is an electronic component that inverts the level of an input signal and outputs it. For example, when the input signal is at a high level, the output signal is at a low level. When the input signal is at a low level, the output signal is at a high level.

[0084] A trigger is a basic timing element used to store and transmit data under the control of a clock signal. The trigger includes a data input port D, a clock input port CLK, and an output port Q. The data input port D is used to receive an external input data signal. Under the trigger of the clock signal, the data of the data input port D will be transmitted to the output port Q. The clock input port CLK is used to receive a clock signal, which is used to characterize the time when the trigger samples the data of the data input port D. The output port Q is used to output the data stored in the trigger.

[0085] The OR gate is used to perform a logical OR operation on two or more input signals. For example, when there are one or more high-level signals in the input signals, the OR gate outputs a high-level signal. When there is no high-level signal in the input signals, the OR gate outputs a low-level signal.

[0086] In some embodiments, Figure 2 As shown, the first dead zone module includes: a first inverter INV1, a second inverter INV2, a first trigger DFF1, a second trigger DFF2, a third trigger DFF3, a fourth trigger DFF4 and a first OR gate OR_1. The first inverter INV1 is configured to perform phase inversion on the received second frequency-divided signal f1 and output a first frequency-divided inverted signal to the first trigger DFF1. The second inverter INV2 is configured to perform phase inversion on the received second frequency-divided signal f1 and output a second frequency-divided inverted signal to the second trigger DFF2.

[0087] The data input port D of the first flip-flop DFF1 is used to receive the charging signal UP, the clock input port CLK is used to receive the first frequency-divided inverted signal, and the output port Q is used to output the first sampled charging signal UP_1. The first flip-flop DFF1 is configured to sample the received charging signal UP according to the first frequency-divided inverted signal and output the first sampled charging signal UP_1 to the third flip-flop DFF3.

[0088] The data input port D of the second flip-flop DFF2 is used to receive the discharge signal DN, the clock input port CLK is used to receive the second frequency-divided inverted signal, and the output port Q is used to output the first sampled discharge signal DN_1. The second flip-flop DFF2 is configured to sample the received discharge signal DN according to the second frequency-divided inverted signal and output the first sampled discharge signal DN_1 to the fourth flip-flop DFF4.

[0089] The data input port D of the third flip-flop DFF3 is used to receive the first sampling charging signal UP_1, and the clock input port CLK is used to receive the first frequency-divided signal f div The output port Q is used to output the second sampling charging signal UP_2. The third trigger DFF3 is configured to receive the first frequency division signal f div The first sampled charging signal UP_1 is sampled, and the second sampled charging signal UP_2 is output to the first OR gate OR_1.

[0090] The data input port D of the fourth flip-flop DFF4 is used to receive the first sampling discharge signal DN_1, and the clock input port CLK is used to receive the reference clock signal f ref The output port Q is used to output the second sampling discharge signal DN_2. The fourth flip-flop DFF4 is configured to receive the reference clock signal f refThe first sampling discharge signal DN_1 is sampled, and the second sampling discharge signal DN_2 is output to the first OR gate OR_1.

[0091] The first OR gate OR_1 is configured to perform an OR operation on the received second sampled charging signal UP_2 and the second sampled discharging signal DN_2 and output a first dead zone control signal DZ_EN_1 to the charge pump.

[0092] Exemplarily, when the rising edge of the first frequency-divided inverted signal arrives, the first trigger DFF1 samples the charging signal UP according to the first frequency-divided inverted signal, and outputs the first sampled charging signal UP_1 to the third trigger DFF3; the second trigger DFF2 samples the discharge signal DN according to the second frequency-divided inverted signal, and outputs the first sampled discharge signal DN_1 to the fourth trigger DFF4. ref The phase of the first frequency division signal f div When the phase of the third flip-flop DFF3 is div When the rising edge of comes, according to the first frequency division signal f div The first sampling charging signal UP_1 is sampled, and the second sampling charging signal UP_2 is output to the first OR gate OR_1; the fourth flip-flop DFF4 samples the first sampling charging signal UP_1 and outputs the second sampling charging signal UP_2 to the first OR gate OR_1; ref The first sampling discharge signal DN_1 is sampled, and the second sampling discharge signal DN_2 is output to the first OR gate OR_1.

[0093] In some embodiments, Figure 3 As shown, the second dead zone module includes: a third inverter INV3, a fourth inverter INV4, a fifth trigger DFF5, a sixth trigger DFF6, a seventh trigger DFF7, an eighth trigger DFF8 and a second OR gate OR_2. The third inverter INV3 is configured to perform phase inversion on the received third frequency-divided signal f2 and output the third frequency-divided inverted signal to the fifth trigger DFF5. The fourth inverter INV4 is configured to perform phase inversion on the received third frequency-divided signal f2 and output the fourth frequency-divided inverted signal to the sixth trigger DFF6.

[0094] The data input port D of the fifth flip-flop DFF5 is used to receive the charging signal UP, the clock input port CLK is used to receive the third frequency-divided inverted signal, and the output port Q is used to output the third sampled charging signal UP_3. The fifth flip-flop DFF5 is configured to sample the received charging signal UP according to the third frequency-divided inverted signal and output the third sampled charging signal UP_3 to the seventh flip-flop DFF7.

[0095] The data input port D of the sixth flip-flop DFF6 is used to receive the discharge signal DN, the clock input port CLK is used to receive the fourth frequency-divided inverted signal, and the output port Q is used to output the third sampled discharge signal DN_3. The sixth flip-flop DFF6 is configured to sample the received discharge signal DN according to the fourth frequency-divided inverted signal and output the third sampled discharge signal DN_3 to the eighth flip-flop DFF8.

[0096] The data input port D of the seventh flip-flop DFF7 is used to receive the third sampling charging signal UP_3, and the clock input port CLK is used to receive the first frequency division signal f div The output port Q is used to output the fourth sampling charging signal UP_4. The seventh trigger DFF7 is configured to receive the first frequency division signal f div The third sampled charging signal UP_3 is sampled, and a fourth sampled charging signal UP_4 is output to the second OR gate OR_2 and the charge pump.

[0097] The data input port D of the eighth flip-flop DFF8 is used to receive the third sampling discharge signal DN_3, and the clock input port CLK is used to receive the reference clock signal f ref The output port Q is used to output the fourth sampling discharge signal DN_4. The eighth flip-flop DFF8 is configured to receive the reference clock signal f ref The third sampling discharge signal DN_3 is sampled, and a fourth sampling discharge signal DN_4 is output to the second OR gate OR_2 and the charge pump.

[0098] The second OR gate OR_2 is configured to perform an OR operation on the received fourth sampling charge signal UP_4 and the fourth sampling discharge signal DN_4 and output the second dead zone control signal DZ_EN_2 to the charge pump.

[0099] In some embodiments, Figure 4 As shown, the third dead zone module includes: a fifth inverter INV5, a sixth inverter INV6, a ninth flip-flop DFF9, a tenth flip-flop DFF10, an eleventh flip-flop DFF11, a twelfth flip-flop DFF12 and a third OR gate OR_3. The fifth inverter INV5 is configured to perform phase inversion on the received fourth frequency-divided signal f3 and output the fifth frequency-divided inverted signal to the ninth flip-flop DFF9. The sixth inverter INV6 is configured to perform phase inversion on the received fourth frequency-divided signal f3 and output the sixth frequency-divided inverted signal to the tenth flip-flop DFF10.

[0100] The data input port D of the ninth flip-flop DFF9 is used to receive the charging signal UP, the clock input port CLK is used to receive the fifth frequency-divided inverted signal, and the output port Q is used to output the fifth sampled charging signal UP_5. The ninth flip-flop DFF9 is configured to sample the received charging signal UP according to the fifth frequency-divided inverted signal and output the fifth sampled charging signal UP_5 to the eleventh flip-flop DFF11.

[0101] The data input port D of the tenth flip-flop DFF10 is used to receive the discharge signal DN, the clock input port CLK is used to receive the sixth frequency-divided inverted signal, and the output port Q is used to output the fifth sampled discharge signal DN_5. The tenth flip-flop DFF10 is configured to sample the received discharge signal DN according to the sixth frequency-divided inverted signal and output the fifth sampled discharge signal DN_5 to the twelfth flip-flop DFF12.

[0102] The data input port D of the eleventh flip-flop DFF11 is used to receive the fifth sampling charging signal UP_5, and the clock input port CLK is used to receive the first frequency-divided signal f div The output port Q is used to output the sixth sampling charging signal UP_6. The eleventh flip-flop DFF11 is configured to receive the first frequency-divided signal f div The fifth sampled charging signal UP_5 is sampled, and a sixth sampled charging signal UP_6 is output to the third OR gate OR_3 .

[0103] The data input port D of the twelfth flip-flop DFF12 is used to receive the fifth sampling discharge signal DN_5, and the clock input port CLK is used to receive the reference clock signal f ref The output port Q is used to output the sixth sampling discharge signal DN_6. The twelfth flip-flop DFF12 is configured to receive the reference clock signal f ref The fifth sampling discharge signal DN_5 is sampled, and a sixth sampling discharge signal DN_6 is output to the third OR gate OR_3.

[0104] The third OR gate OR_3 is configured to perform an OR operation on the received sixth sampling charge signal UP_6 and the sixth sampling discharge signal DN_6 and output a third dead zone control signal DZ_EN_3 to the sub-sampling charge pump.

[0105] In some embodiments, the voltage controlled oscillator outputs a high frequency oscillation signal f out , the frequency divider outputs the oscillation signal f of the voltage controlled oscillator out To divide the reference clock signal f ref There is a phase difference between the divided signal output by the divider and the reference clock signal f refThere is a time difference between the rising edge of the frequency division signal and the rising edge of the frequency division signal. When the time difference increases and exceeds the first preset dead zone range, the third dead zone module outputs a high-level third dead zone control signal DZ_EN_3 to increase the charge and discharge current of the sub-sampling charge pump and shorten the time for the sub-sampling loop to accumulate phase errors. When the time difference increases and exceeds the second preset dead zone range, the frequency locked loop is turned on, and the second dead zone module will output the second dead zone control signal DZ_EN_2, the fourth sampling charge signal UP_4 and the fourth sampling discharge signal DN_4, all of which are high levels, to increase the charge and discharge current of the charge pump and control the charge and discharge time of the charge pump. When the time difference continues to increase and exceeds the third preset dead zone range, the first dead zone module outputs a high-level first dead zone control signal DZ_EN_1 to continue to increase the charge and discharge current of the charge pump.

[0106] When the time difference decreases to within the third preset dead zone range, the first dead zone module outputs a low-level first dead zone control signal DZ_EN_1 to reduce the charge and discharge current of the charge pump. When the time difference continues to decrease to within the second preset dead zone range, the frequency locked loop is closed, and the second dead zone module outputs a low-level second dead zone control signal DZ_EN_2, a fourth sampling charge signal UP_4, and a fourth sampling discharge signal DN_4 to further reduce the charge and discharge current of the charge pump and reduce the power consumption of the charge pump. When the time difference continues to decrease to within the first preset dead zone range, the third dead zone module outputs a low-level third dead zone control signal DZ_EN_3 to reduce the charge and discharge current of the sub-sampling charge pump.

[0107] The embodiment of the present application utilizes a dead zone generation module to generate different dead zone control signals based on different phase differences, thereby adjusting the charge and discharge currents of the charge pump and the sub-sampling charge pump. ref The phase of the first frequency division signal f div The phase of the reference clock signal f ref The rising edge of the first frequency division signal f div There is a time difference Δt between the rising edges of the frequency divider. When the time difference is greater than half of the period of the frequency divider signal output by the frequency divider, the dead zone generation module is triggered and the dead zone control signal is high level. Figure 5 When the time difference is less than or equal to half of the period of the frequency-divided signal output by the frequency divider, the dead zone generation module is not triggered, and the dead zone control signal is at a low level. Figure 5 (b) in .

[0108] Exemplarily, the first frequency-divided signal f div The phase leads the reference clock signal f ref The phase of the reference clock signal f ref The rising edge of the first frequency division signal f divThere is a time difference Δt between the rising edges of the frequency divider. When the time difference is greater than half of the period of the frequency divider signal output by the frequency divider, the dead zone generation module is triggered and the dead zone control signal is high level. Figure 6 When the time difference is less than or equal to half of the period of the frequency-divided signal output by the frequency divider, the dead zone generation module is not triggered, and the dead zone control signal is at a low level. Figure 6 (b) in .

[0109] In some embodiments, the charge pump generates the second current signal by converting the received dead zone control signal into a current signal. The charge pump is configured to generate the second current signal according to the received dead zone control signal and output the second current signal to the loop filter.

[0110] In some embodiments, Figure 7 As shown, the charge pump includes a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a sixth current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch. The first current source, the second current source and the third current source are connected in parallel to the first node, and the fourth current source, the fifth current source and the sixth current source are connected in parallel to the second node. A first switch is provided between the second current source and the first node, and a second switch is provided between the third current source and the first node. A third switch and a fourth switch are provided between the first node and the second node in sequence, and the third switch and the fourth switch are connected to the third node. A fifth switch is provided between the fifth current source and the second node, and a sixth switch is provided between the sixth current source and the second node.

[0111] The charge pump controls the on or off of the switch according to the dead zone signal. The charge pump is configured to control the on or off of the first switch according to the received first dead zone control signal DZ_EN_1. Control the on or off of the second switch according to the received second dead zone control signal DZ_EN_2. Control the on or off of the third switch according to the received fourth sampling charge signal UP_4. Control the on or off of the fourth switch according to the received fourth sampling discharge signal DN_4. Control the on or off of the fifth switch according to the received first dead zone control signal DZ_EN_1. Control the on or off of the sixth switch according to the received second dead zone control signal DZ_EN_2.

[0112] Exemplarily, when the first dead zone control signal DZ_EN_1 and the fourth sampling charging signal UP_4 are both at high levels, the first switch and the third switch are in an on state, and the first current source and the second current source supply power to the charge pump to generate a second current signal.

[0113] Exemplarily, when the second dead zone control signal DZ_EN_2 and the fourth sampling discharge signal DN_4 are both at high levels, the fourth switch and the sixth switch are in the on state, and the fourth current source and the sixth current source supply power to the charge pump to generate the second current signal.

[0114] In some embodiments, Figure 8 As shown, the sub-sampling charge pump includes a seventh switch, and the sub-sampling charge pump is configured to control the conduction or disconnection of the seventh switch according to the received third dead zone control signal DZ_EN_3. Exemplarily, when the third dead zone control signal DZ_EN_3 is at a high level, the seventh switch is in a conducting state. When the third dead zone control signal DZ_EN_3 is at a low level, the seventh switch is in a disconnected state.

[0115] According to the sub-sampling phase-locked loop based on the dead zone generation module described in the above embodiments, some embodiments of the present application also provide a sub-sampling phase-locked loop control method based on the dead zone generation module, which is applied to the sub-sampling phase-locked loop based on the dead zone generation module described in the above embodiments. Fig. 9 FIG. 1 is a schematic diagram of the steps of the sub-sampling phase-locked loop control method based on the dead zone generation module according to an embodiment of the present application, referring to FIG. Fig. 9 The sub-sampling phase-locked loop control method based on the dead zone generation module of the embodiment of the present application includes the following steps.

[0116] Step S901: sampling an oscillation signal output by a voltage-controlled oscillator according to a received reference clock signal, and outputting a first current signal to a loop filter.

[0117] Step S902: output a second current signal to the loop filter according to the received reference clock signal and the first frequency-divided signal, and generate a dead zone control signal; the dead zone control signal is used to adjust the first current signal or the second current signal, and the first frequency-divided signal is obtained by dividing the oscillation signal.

[0118] Step S903 , receiving the first current signal and the second current signal, and outputting an oscillation control signal to the voltage-controlled oscillator, where the oscillation control signal is used to adjust the output frequency of the voltage-controlled oscillator.

[0119] Step S904: Generate an oscillation signal according to the oscillation control signal.

[0120] It can be seen from the above technical solutions that the present application provides a sub-sampling phase-locked loop based on a dead zone generation module and a control method thereof. The sub-sampling phase-locked loop based on the dead zone generation module includes: a sub-sampling loop, a frequency-locked loop, a loop filter and a voltage-controlled oscillator, wherein the sub-sampling loop is configured to sample the oscillation signal output by the voltage-controlled oscillator according to the received reference clock signal, and output a first current signal to the loop filter. The frequency-locked loop is configured to output a second current signal to the loop filter according to the received reference clock signal and the first frequency-divided signal, and to generate a dead zone control signal; the dead zone control signal is used to adjust the first current signal or the second current signal, and the first frequency-divided signal is obtained by dividing the oscillation signal. The loop filter is configured to receive the first current signal and the second current signal, and output an oscillation control signal to the voltage-controlled oscillator, and the oscillation control signal is used to adjust the output frequency of the voltage-controlled oscillator; the voltage-controlled oscillator is configured to generate an oscillation signal according to the oscillation control signal. The above-mentioned sub-sampling phase-locked loop can generate multiple dead zone ranges using the frequency-locked loop, thereby reducing the locking time of the sub-sampling phase-locked loop.

[0121] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A sub-sampling phase-locked loop based on a dead zone generation module, characterized in that: include: A sub-sampling loop is configured to: sample an oscillation signal output by a voltage-controlled oscillator according to a received reference clock signal, and output a first current signal to a loop filter; A frequency locked loop, configured to: output a second current signal to the loop filter and generate a dead zone control signal according to a received reference clock signal and a first frequency division signal; the dead zone control signal is used to adjust the first current signal or the second current signal, and the first frequency division signal is obtained by dividing the oscillation signal; A loop filter, configured to: receive the first current signal and the second current signal, and output an oscillation control signal to the voltage-controlled oscillator, wherein the oscillation control signal is used to adjust an output frequency of the voltage-controlled oscillator; The voltage-controlled oscillator is configured to generate the oscillation signal according to the oscillation control signal.

2. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 1, characterized in that: The sub-sampling loop comprises: A sub-sampling phase detector is configured to: sample the oscillation signal according to the received reference clock signal, and output a voltage difference signal to a sub-sampling charge pump; a sub-sampling charge pump configured to: generate the first current signal according to the received voltage difference signal, adjust the first current signal according to the received dead zone control signal, and output the adjusted first current signal to the loop filter; The pulse generator is configured to generate a pulse signal according to the received reference clock signal, and output the pulse signal to the sub-sampling charge pump, wherein the pulse signal is used to control the conduction or disconnection of the first current signal.

3. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 2, characterized in that: The frequency locked loop comprises: a frequency detector and a phase detector, configured to: sample the first frequency-divided signal according to the received reference clock signal, and output a charging signal and a discharging signal to the dead zone generation module; A frequency divider is configured to: perform frequency division on the received oscillation signal to obtain a first frequency division signal and a second frequency division signal, and output the first frequency division signal to the frequency detector and phase detector, and output the first frequency division signal and the second frequency division signal to the dead zone generation module; the frequency of the first frequency division signal is less than the frequency of the second frequency division signal; a dead zone generating module, configured to: output the dead zone control signal to the charge pump to adjust the second current signal, or output the dead zone control signal to the sub-sampling charge pump to adjust the first current signal according to the received reference clock signal, the first frequency-divided signal, the second frequency-divided signal, the charging signal and the discharging signal; The charge pump is configured to generate the second current signal according to the received dead zone control signal, and output the second current signal to the loop filter.

4. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 3, characterized in that: The frequency divider is also configured as: The received oscillation signal is frequency-divided to obtain a third frequency-divided signal and a fourth frequency-divided signal, and the third frequency-divided signal and the fourth frequency-divided signal are output to the dead zone generation module; the frequency of the third frequency-divided signal is less than the frequency of the fourth frequency-divided signal, and the frequency of the third frequency-divided signal is greater than the frequency of the second frequency-divided signal.

5. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 4, characterized in that: The dead zone generating module comprises a first dead zone module, and the first dead zone module comprises: A first inverter is configured to: perform phase inversion on the received second frequency-divided signal, and output a first frequency-divided inverted signal to a first flip-flop; A second inverter is configured to: perform phase inversion on the received second frequency-divided signal, and output a second frequency-divided inverted signal to a second flip-flop; a first trigger, configured to: perform sampling on the received charging signal according to the first frequency-divided inverted signal, and output a first sampled charging signal to a third trigger; a second trigger, configured to: perform sampling on the received discharge signal according to the second frequency-divided inverted signal, and output a first sampled discharge signal to a fourth trigger; a third trigger, configured to: sample the first sampled charging signal according to the received first frequency-divided signal, and output a second sampled charging signal to the first OR gate; a fourth trigger, configured to: sample the first sampled discharge signal according to the received reference clock signal, and output a second sampled discharge signal to the first OR gate; The first OR gate is configured to perform an OR operation on the received second sampled charging signal and the second sampled discharging signal, and output a first dead zone control signal to the charge pump.

6. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 5, characterized in that: The dead zone generating module includes a second dead zone module, and the second dead zone module includes: A third inverter is configured to: perform phase inversion on the received third frequency-divided signal, and output the third frequency-divided inverted signal to the fifth flip-flop; a fourth inverter configured to: perform phase inversion on the received third frequency-divided signal, and output a fourth frequency-divided inverted signal to a sixth flip-flop; a fifth trigger, configured to: perform sampling on the received charging signal according to the third frequency-divided inverted signal, and output a third sampled charging signal to the seventh trigger; a sixth trigger, configured to: perform sampling on the received discharge signal according to the fourth frequency-divided inverted signal, and output a third sampled discharge signal to an eighth trigger; a seventh trigger, configured to: sample the third sampled charging signal according to the received first frequency-divided signal, and output a fourth sampled charging signal to the second OR gate and the charge pump; an eighth trigger, configured to: sample the third sampled discharge signal according to the received reference clock signal, and output a fourth sampled discharge signal to the second OR gate and the charge pump; The second OR gate is configured to perform an OR operation on the received fourth sampled charging signal and the fourth sampled discharging signal, and output a second dead zone control signal to the charge pump.

7. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 6, characterized in that: The dead zone generating module includes a third dead zone module, and the third dead zone module includes: a fifth inverter configured to: perform phase inversion on the received fourth frequency-divided signal, and output a fifth frequency-divided inverted signal to a ninth flip-flop; a sixth inverter configured to: perform phase inversion on the received fourth frequency-divided signal, and output a sixth frequency-divided inverted signal to a tenth flip-flop; a ninth trigger, configured to: perform sampling on the received charging signal according to the fifth frequency-divided inverted signal, and output a fifth sampled charging signal to the eleventh trigger; a tenth flip-flop, configured to: perform sampling on the received discharge signal according to the sixth frequency-divided inverted signal, and output a fifth sampled discharge signal to a twelfth flip-flop; an eleventh trigger, configured to: sample the fifth sampled charging signal according to the received first frequency-divided signal, and output a sixth sampled charging signal to a third OR gate; a twelfth trigger, configured to: sample the fifth sampled discharge signal according to the received reference clock signal, and output a sixth sampled discharge signal to a third OR gate; The third OR gate is configured to perform an OR operation on the received sixth sampling charge signal and the sixth sampling discharge signal, and output a third dead zone control signal to the sub-sampling charge pump.

8. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 7, characterized in that: The charge pump comprises a first current source, a second current source, a third current source, a fourth current source, a fifth current source, a sixth current source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; The first current source, the second current source and the third current source are connected in parallel to the first node, and the fourth current source, the fifth current source and the sixth current source are connected in parallel to the second node; The first switch is provided between the second current source and the first node, and the second switch is provided between the third current source and the first node; The third switch and the fourth switch are sequentially arranged between the first node and the second node, and the third switch and the fourth switch are connected to the third node; The fifth switch is provided between the fifth current source and the second node, and the sixth switch is provided between the sixth current source and the second node.

9. The sub-sampling phase-locked loop based on the dead zone generation module according to claim 8, characterized in that: The sub-sampling charge pump includes a seventh switch, and the sub-sampling charge pump is configured to: control the conduction or disconnection of the seventh switch according to the received third dead zone control signal; The charge pump is also configured to: control the on or off of the first switch according to the first dead zone control signal received; control the on or off of the second switch according to the second dead zone control signal received; control the on or off of the third switch according to the fourth sampled charging signal received; control the on or off of the fourth switch according to the fourth sampled discharging signal received; control the on or off of the fifth switch according to the first dead zone control signal received; and control the on or off of the sixth switch according to the second dead zone control signal received.

10. A sub-sampling phase-locked loop control method based on a dead zone generation module, characterized in that: Applied to the sub-sampling phase-locked loop based on the dead zone generation module according to any one of claims 1 to 9, the method comprising: sampling an oscillation signal output by a voltage-controlled oscillator according to a received reference clock signal, and outputting a first current signal to a loop filter; Outputting a second current signal to the loop filter and generating a dead zone control signal according to the received reference clock signal and the first frequency division signal; the dead zone control signal is used to adjust the first current signal or the second current signal, and the first frequency division signal is obtained by dividing the oscillation signal; receiving the first current signal and the second current signal, and outputting an oscillation control signal to the voltage-controlled oscillator, wherein the oscillation control signal is used to adjust an output frequency of the voltage-controlled oscillator; The oscillation signal is generated according to the oscillation control signal.

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