Dual-ADC data acquisition and processing device and method

Abstract

The invention provides a dual-ADC data acquisition and processing device and method, and relates to the technical field of data acquisition devices and methods, the dual-ADC data acquisition and processing device comprises an acquisition device body, and the acquisition device body comprises an amplification circuit, a data acquisition module and an FPGA signal processing module; the number of the amplification circuits is two, and the two amplification circuits have different amplification factors. The data acquisition module comprises two ADC chips, the two ADC chips have different measuring ranges, and the two ADC chips are respectively connected with the two amplification circuits; and the FPGA signal processing module is connected with the two ADC chips and is used for generating an ADC sampling synchronous clock. After an analog signal is amplified at different multiplying powers through the two amplification circuits, a large signal is measured through one large-range ADC chip, and a small signal is measured through one small-range ADC chip, so that the large signal and the small signal can be acquired at the same time; and the acquisition requirement of superposing small signals on large signals in an actual application scene can be well met.

Description

Technical Field

[0001] The present application relates to the technical field of data acquisition devices and methods, and in particular to a dual ADC data acquisition and processing device and method. Background Art

[0002] The main function of the data acquisition device is to convert analog signals into digital signals to facilitate data analysis and processing at the back end. Dynamic range is an important technical indicator for measuring the performance of data acquisition devices. Traditional data acquisition devices use a single ADC and a single amplifier circuit to sample analog signals. The dynamic range of the device is determined by the effective number of bits of a single ADC. For example, the dynamic range of a 24-bit ADC is about 120dB. Improving the dynamic range of data acquisition devices is a goal that the industry has always pursued.

[0003] For a data acquisition device with a single ADC architecture, using multiple acquisition devices with different acquisition ranges to acquire the same analog signal can increase the dynamic range of the device. For example, the invention application with publication number CN 102297703A discloses a data acquisition device, which uses multiple AD analog-to-digital converters to synchronously sample each measurement signal, and uses an amplifier with different but fixed amplification factors in front of each AD analog-to-digital converter to amplify, thereby simultaneously obtaining digital signals measured under multiple ranges. The controller receives the digital amplified signal of each amplifier after analog-to-digital conversion by the analog-to-digital converter, and selects the output of one of the multiple amplification paths as the final output signal according to the size of the measurement signal and the input voltage range of the corresponding analog-to-digital converter.

[0004] However, since the above-mentioned data acquisition device can only select the digital amplified signal output by one of the multiple amplifiers and converted by the corresponding analog-to-digital converter as the output signal, and the dynamic measurement range of a single analog-to-digital converter is very limited, for application scenarios where a small signal is superimposed on a large signal, it is impossible to collect large signals and small signals at the same time, and cannot meet the actual application needs well. Summary of the invention

[0005] The purpose of the present application is to provide a dual ADC data acquisition and processing device and method, which is used to solve the problem that the data acquisition equipment in the related art cannot simultaneously collect large signals and small signals for application scenarios where a small signal is superimposed on a large signal, and cannot meet the actual application needs well.

[0006] In the first aspect, the present application provides a dual ADC data acquisition and processing device that adopts the following technical solution:

[0007] A dual ADC data acquisition and processing device, comprising:

[0008] The acquisition device body includes an amplification circuit, a data acquisition module and an FPGA signal processing module;

[0009] The amplifier circuit is provided with two paths, and the two paths have different amplification factors and are used to amplify the analog signal at different factors.

[0010] The data acquisition module includes two ADC chips, the two ADC chips have different ranges, the two ADC chips are respectively connected to the two amplifying circuits, and are used to convert the analog signals amplified by the amplifying circuits into digital signals;

[0011] The FPGA signal processing module is connected to the two ADC chips and is used to generate an ADC sampling synchronization clock, and simultaneously performs real-time splicing and restoration processing on the digital signals output by the two ADC chips at the same time.

[0012] Optionally, the acquisition device body further includes a signal conditioning circuit, which is connected to the two amplifying circuits, and is used to amplify and filter the analog signal input to the amplifying circuit.

[0013] Optionally, it also includes a box body and a sealing mechanism. The acquisition device body also includes a shell. The amplifying circuit, data acquisition module and FPGA signal processing module are arranged in the shell. The shell is provided with an acquisition interface. The shell is placed in the box body. The box body is provided with a through groove for avoiding the acquisition interface. The sealing mechanism is arranged on the box body and is used to open and close the through groove.

[0014] Optionally, the sealing mechanism includes two end covers, a first elastic member and two sealing plates, the two end covers can be opened and closed at the through groove of the box body, the first elastic member is arranged on the box body and acts on the end covers, the first elastic member is used to push the two end covers to close, the end covers are provided with wire holes, and the two sealing plates are respectively slidably arranged on the two end covers and are used to open and close and seal the wire holes.

[0015] Optionally, the sealing mechanism also includes a second elastic member, the end cover is provided with a guide groove that passes through the wire hole, the sealing plate is slidably arranged in the guide groove, the second elastic member is arranged on the end cover and acts on the sealing plate, and the second elastic member is used to push the sealing plates on the two end covers to move towards each other.

[0016] Optionally, the blocking mechanism also includes a locking assembly, which includes a wedge block and a third elastic member, the box body is provided with a slide groove and a connecting hole that passes through the slide groove, the end cover is provided with a locking tongue that can be plugged into the connecting hole, and the locking tongue is provided with a locking groove, the wedge block is slidably arranged in the slide groove and can be engaged with the locking groove, the third elastic member is arranged on the box body and acts on the wedge block, and the third elastic member is used to push the wedge block to move toward the locking groove.

[0017] Optionally, it also includes an airbag, an outer frame, an air intake mechanism and a high-pressure gas cylinder, the outer frame is arranged on the outside of the box body and connected to the box body through an elastic column, the airbag is arranged between the box body and the outer frame, and the two ends of the airbag extend outward toward the two ends of the box body. The high-pressure gas cylinder is arranged on the outer frame and connected to the inside of the airbag through the air intake mechanism. When the air pressure inside the airbag is lower than a set value, the air intake mechanism connects the high-pressure gas cylinder and the airbag.

[0018] Optionally, the air intake mechanism includes an air bin, an air valve, a piston and a fourth elastic member. The air bin is arranged on the outer frame and is connected to the interior of the airbag. The air bin is connected to the high-pressure gas cylinder through a tube body. A first air hole is provided at the end of the tube body. The air valve is rotatably arranged in the tube body. The air valve is provided with a second air hole that can overlap or stagger with the first air hole. The air bin is provided with a cylinder body that is connected to the inside and outside of the air bin. The piston is slidably arranged in the cylinder body and is connected to the air valve. When the piston slides, it can drive the air valve to rotate. The fourth elastic member is provided on the air bin and acts on the piston.

[0019] Optionally, the air intake mechanism also includes a rotating shaft, a worm and a transmission rack, a first gear is provided on the air valve, the rotating shaft is rotatably arranged in the air bin, a worm wheel and a second gear meshing with the first gear are provided on the rotating shaft, the worm is rotatably arranged in the air bin and meshes with the worm wheel, a third gear is provided on the worm, and the transmission rack is fixed to the piston and meshes with the third gear.

[0020] In a second aspect, a dual ADC data acquisition and processing method provided by the present application adopts the following technical solution:

[0021] A dual ADC data acquisition and processing method is based on the dual ADC data acquisition and processing device, and comprises the following steps:

[0022] Step 1: amplify and filter the input analog signal through a signal conditioning circuit;

[0023] Step 2, amplifying the conditioned analog signal at different magnifications through two amplifier circuits;

[0024] Step 3, the signals after being amplified at different magnifications are respectively transmitted to two ADC chips, which are controlled by the synchronous sampling clock generated by the FPGA signal processing module. The ADC chip converts the analog signal into a digital signal after holding, quantizing and encoding the signal, and transmits it to the FPGA signal processing module;

[0025] Step 4: Use the FPGA signal processing module to perform real-time splicing and restoration processing on the digital signals output by the two ADC chips at the same time, thereby expanding the dynamic range of each frame of data.

[0026] In summary, the present application includes at least one of the following beneficial technical effects: the analog signal conditioned by the signal conditioning circuit is amplified at different magnifications by two-way amplification circuits, and the signals amplified at different magnifications are respectively transmitted to two ADC chips, and the ADC chips convert the analog signals into digital signals after signal processing such as retention, quantization and encoding, and the digital signals output by the two ADC chips at the same time are spliced ​​and restored in real time through the FPGA signal processing module. Since the two ADC chips have different ranges, after the analog signal is amplified at different magnifications by the two-way amplification circuits, the large signal is measured by one of the large-range ADC chips, and the small signal is measured by a small-range ADC chip, so that large signals and small signals can be collected at the same time, which can better meet the collection requirements of superimposing small signals on large signals in actual application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a structural block diagram of a dual ADC data acquisition and processing device in an embodiment of the present application;

[0028] Figure 2 This is a structural diagram of a dual ADC data acquisition and processing device in an embodiment of the present application;

[0029] Figure 3 It is a cross-sectional view of the dual ADC data acquisition and processing device from a first perspective in an embodiment of the present application;

[0030] Figure 4 for Figure 3 A partial enlarged schematic diagram of part D in the middle;

[0031] Figure 5 This is a front view of a dual ADC data acquisition and processing device in an embodiment of the present application;

[0032] Figure 6 for Figure 5 A partial enlarged schematic diagram of part A;

[0033] Figure 7 It is a cross-sectional view of the dual ADC data acquisition and processing device from a second viewing angle in an embodiment of the present application;

[0034] Figure 8 It is a cross-sectional view of the dual ADC data acquisition and processing device from a third viewing angle in an embodiment of the present application;

[0035] Fig. 9 for Figure 8 A partial enlarged schematic diagram of part B;

[0036] Fig.10 It is a cross-sectional view of the dual ADC data acquisition and processing device from a fourth viewing angle in an embodiment of the present application;

[0037] Fig.11 for Fig.10 A partial enlarged schematic diagram of part C in the middle.

[0038] Description of reference numerals:

[0039] 10. Collection device body; 11. Signal conditioning circuit; 12. Amplification circuit; 13. ADC chip; 14. FPGA signal processing module; 15. Housing; 16. Collection interface;

[0040] 20, box body; 21, through slot; 22, box cover; 23, guide rail; 24, stopper; 25, convex seat; 251, slide slot; 252, connecting hole;

[0041] 30. Blocking mechanism; 31. End cover; 311. Wire hole; 312. Sliding column; 313. First limit block; 314. Splitting and closing rack; 315. Guide groove; 316. Lock tongue; 3161. Lock groove;

[0042] 32. first spring; 33. sealing plate; 331. column; 332. second limit block;

[0043] 34. Intermediate gear; 35. Second spring; 36. Wedge block; 361. Rod body; 362. Third limit block; 37. Third spring;

[0044] 40. airbag; 41. avoidance groove; 42. air nozzle; 50. outer frame;

[0045] 60. air intake mechanism; 61. air chamber; 611. through hole;

[0046] 62, air valve; 621, second air hole; 622, first gear;

[0047] 63. piston; 64. fourth spring; 65. tube body; 651. first air hole;

[0048] 66, cylinder; 67, rotating shaft; 671, worm gear; 672, second gear;

[0049] 68, worm; 681, third gear; 69, transmission rack; 691, bracket;

[0050] 70. High-pressure gas cylinder; 80. Rubber column. DETAILED DESCRIPTION

[0051] The following is combined with Figure 1 -Attached Fig.11 , further details of this application are given.

[0052] Example 1

[0053] This embodiment discloses a dual ADC data acquisition and processing device.

[0054] Reference Figure 1 A dual ADC data acquisition and processing device and method, comprising an acquisition device body 10, the acquisition device body 10 comprising a signal conditioning circuit 11, an amplifier circuit 12, a data acquisition module and an FPGA signal processing module 14. The amplifier circuit 12 is provided with two paths, the two amplifier circuits 12 have different amplification factors, and are used to amplify the analog signal at different magnifications. The signal conditioning circuit 11 is connected to the two amplifier circuits 12, and the signal conditioning circuit 11 is used to amplify and filter the analog signal input to the amplifier circuit 12. The data acquisition module comprises two ADC chips 13, the two ADC chips 13 have different ranges, the two ADC chips 13 are respectively connected to the two amplifier circuits 12, and are used to convert the analog signal amplified by the amplifier circuit 12 into a digital signal. The FPGA signal processing module 14 is connected to the two ADC chips 13, and is used to generate an ADC sampling synchronization clock, and at the same time, the digital signals output by the two ADC chips 13 at the same time are spliced ​​and restored in real time.

[0055] This embodiment also discloses a dual ADC data acquisition and processing method.

[0056] A dual ADC data acquisition and processing method is based on a dual ADC data acquisition and processing device and includes the following steps:

[0057] Step 1: amplify and filter the input analog signal through the signal conditioning circuit 11;

[0058] Step 2, amplifying the conditioned analog signal at different magnifications through two-way amplifier circuits 12;

[0059] Step 3, the signals after being amplified at different magnifications are respectively transmitted to two ADC chips 13, which are controlled by the synchronous sampling clock generated by the FPGA signal processing module 14. The ADC chip 13 converts the analog signal into a digital signal through signal processing such as retention, quantization and encoding, and transmits the converted digital signal to the FPGA signal processing module 14 through the LVDS interface inside the ADC chip 13;

[0060] Step 4: The digital signals output by the two ADC chips 13 at the same time are spliced ​​and restored in real time through the FPGA signal processing module 14 to expand the dynamic range of each frame of data.

[0061] The following is a detailed description of the mechanism of expanding the dynamic range of the data acquisition system by the dual ADC data acquisition processing method of this embodiment. Assume that the effective number of bits of the ADC chip 13 is N (N can be 12, 16, 24, 32, etc.), the signal amplification channels of the two amplifier circuits 12 are respectively recorded as CH1 and CH2, the amplification factors of the two channels are respectively K1 and K2, and the reference power supplies of the two ADC chips 13 are both V ref After signal amplification, the theoretical signal acquisition range of CH1 channel is [V ref / K1,V ref / (2N×K1)], the theoretical signal acquisition range of CH2 channel is [V ref / K2,V ref / (2N×K2)], the theoretical acquisition range of the two-channel signal has a certain overlap area, and the theoretical acquisition range after the CH1 channel and CH2 channel data are combined is [V ref / K1,V ref / (2N×K2)], through data splicing, the theoretical data acquisition range of the dual ADC data acquisition and processing device is larger than that of the single CH1 channel [V ref / (2N×K1), V ref / (2N×K2)] interval, thereby expanding the dynamic range of the dual ADC data acquisition and processing device.

[0062] When the dual ADC data acquisition and processing device of this embodiment is working, the synchronous pulse signal generated by the FPGA signal processing module 14 synchronously triggers the ADC chip 13 to sample. The obtained digital signal needs to be calibrated first to eliminate various errors. The calibrated data is then spliced. The principle of splicing is to use CH1 channel as the main channel. If the weak signal cannot be covered by CH1 channel, CH2 channel is used as the main channel. Assume K1 = 10, K2 = 1000, V ref =1V, N = 24, the theoretical signal acquisition range of CH1 channel is [1×10 -1 V, 6×10 -9V], the theoretical signal acquisition range of the CH2 channel is [1×10 -3 V, 6×10 -11 V], when splicing data, you can choose to retain the effective decimal places, intercept the effective data of CH1 channel and CH2 channel for splicing, for example, the effective decimal point of CH1 channel data is retained to the 8th decimal place, and the effective decimal point of CH2 channel data is retained to the 11th decimal place. When splicing data, the 9th to 11th decimal places of CH2 channel data are spliced ​​after the CH1 channel data. The effective decimal place of the new data obtained after splicing is 11 digits, which includes both the larger data collected by the CH1 channel and the small signal data collected by the CH2 channel, thereby expanding the dynamic range of the dual ADC data acquisition and processing device at any sampling time.

[0063] Example 2

[0064] This embodiment discloses a dual ADC data acquisition and processing device.

[0065] Reference Figures 2 to 4 The dual ADC data acquisition and processing device of this embodiment is different from that of the first embodiment in that it further includes a box 20 and a blocking mechanism 30. The acquisition device body 10 also includes a housing 15. The signal conditioning circuit 11, the amplifying circuit 12, the data acquisition module and the FPGA signal processing module 14 are arranged in the housing 15. The housing 20 is an open structure at one end, and a box cover 22 is detachably installed at the open end of the housing 20. The housing 15 is provided with an acquisition interface 16, which is used to connect with a sensor for analog signal acquisition. The housing 15 is placed in the housing 20, and the housing 20 is provided with a through slot 21 for avoiding the acquisition interface 16. The blocking mechanism 30 is arranged on the housing 20 and is used to open and close the through slot 21.

[0066] Since the acquisition device body 10 often needs to be used in harsh environments such as outdoor dusty environments, dust in the air easily enters the acquisition interface 16, which may easily lead to excessive dust accumulation in the acquisition interface 16 over time, affecting the connection between the analog signal acquisition sensor and the acquisition device body 10. Therefore, when the dual ADC data acquisition and processing device of this embodiment is used, the acquisition device body 10 is placed in the box 20, and the through slot 21 is openably and closably blocked by the blocking mechanism 30, thereby reducing dust from entering the acquisition interface 16.

[0067] Reference Figures 3 to 6In an optional embodiment, the blocking mechanism 30 may adopt the following structure: the blocking mechanism 30 includes two end covers 31, a first elastic member, two sealing plates 33, an intermediate gear 34, a second elastic member and a locking assembly, a guide rail 23 is provided on the box body 20, the end cover 31 is slidably arranged on the guide rail 23, the two end covers 31 can be opened and closed at the through groove 21 of the box body 20, the intermediate gear 34 is rotatably arranged on the box body 20, and the two end covers 31 are respectively provided with a splitting and combining rack 314, which are respectively meshed with the intermediate gear 34.

[0068] The first elastic member is arranged on the box body 20 and acts on the end cover 31. The first elastic member is used to push the two end covers 31 to close. The first elastic member can adopt a first spring 32. More specifically, a stopper 24 is provided on the box body 20, and a slide column 312 is provided on the end cover 31. The slide column 312 slides through the stopper 24. The slide column 312 is provided with a first limit block 313 that can abut against the stopper 24 and is used to limit the sliding stroke of the end cover 31 on the guide rail 23. The first spring 32 is sleeved on the outside of the slide column 312, and the two ends of the first spring 32 abut against the end cover 31 and the stopper 24 respectively.

[0069] The end cover 31 is provided with a wire hole 311 , and two sealing plates 33 are slidably disposed on the two end covers 31 , respectively. More specifically, the end cover 31 is provided with a guide groove 315 that passes through the wire hole 311 , and the sealing plate 33 is slidably disposed in the guide groove 315 .

[0070] The two sealing plates 33 are used to open and close the wire holes 311. The second elastic member is provided on the end cover 31 and acts on the sealing plate 33. The second elastic member is used to push the sealing plates 33 on the two end covers 31 to move towards each other. More specifically, a column 331 is provided on the sealing plate 33. The column 331 is slidably penetrated through the end cover 31. The column 331 is provided with a second limit block 332 that can abut against the end cover 31 and is used to limit the sliding stroke of the sealing plate 33 in the guide groove 315. The second elastic member is a second spring 35. The second spring 35 is sleeved on the outside of the column 331. The two ends of the second spring 35 respectively abut against the inner end surfaces of the sealing plate 33 and the guide groove 315 of the end cover 31.

[0071] The locking assembly includes a wedge block 36 and a third elastic member. A boss 25 is provided on the box body 20. A slide groove 251 and a connecting hole 252 that passes through the slide groove 251 are provided on the boss 25. A locking tongue 316 that can be plugged into the connecting hole 252 is provided on the end cover 31. A locking groove 3161 is provided on the locking tongue 316. The wedge block 36 is slidably arranged in the slide groove 251 and can be engaged with the locking groove 3161.

[0072] The third elastic member is arranged on the boss 25 of the box body 20 and acts on the wedge block 36. The third elastic member is used to push the wedge block 36 to move toward the locking groove 3161. More specifically, the wedge block 36 is provided with a rod body 361, and the rod body 361 is slidably penetrated through the boss 25. The third elastic member is a third spring 37, and the third spring 37 is sleeved on the outside of the rod body 361. The two ends of the third spring 37 are respectively abutted against the wedge block 36 and the inner end surface of the slide groove 251. The rod body 361 is provided with a third limit block 362 which can abut against the boss 25 and is used to limit the sliding stroke of the wedge block 36 in the slide groove 251.

[0073] The implementation principle of a dual ADC data acquisition and processing device of the present embodiment is as follows: when the dual ADC data acquisition and processing device of the present embodiment is in use, the acquisition device body 10 is placed in the box body 20, and when the connector of the analog signal acquisition sensor is not connected to the acquisition interface 16, the two end covers 31 are sealed in the through groove 21, and the two sealing plates 33 are sealed in the wire hole 311, so as to isolate the acquisition interface 16 from the outside world, protect the acquisition interface 16, and prevent external dust from entering the acquisition interface 16.

[0074] When the connector of the analog signal acquisition sensor needs to be connected to the acquisition interface 16, the two end covers 31 are first moved back to back until the locking tongue 316 is inserted into the connection hole 252 and the wedge block 36 is engaged with the locking groove 3161, and the end cover 31 is locked to maintain the open state. Then the connector of the analog signal acquisition sensor is connected to the acquisition interface 16, and the wedge block 36 is pulled by the third limit block 362 to separate it from the locking groove 3161. Then the two end covers 31 are closed under the elastic force of the first spring 32 to block the through groove 21. At this time, the wire of the analog signal acquisition sensor is placed in the wire hole 311, and the sealing plate 33 slides and shrinks into the guide groove 315.

[0075] Example 3

[0076] This embodiment discloses a dual ADC data acquisition and processing device.

[0077] Reference Figures 7 to 9The dual ADC data acquisition and processing device of this embodiment is different from that of the first embodiment in that it further includes an airbag 40, an outer frame 50, an air intake mechanism 60 and a high-pressure gas cylinder 70. The outer frame 50 is arranged outside the box 20 and connected to the box 20 through an elastic column. The elastic column can be a rubber column 80. The airbag 40 is provided with an avoidance groove 41 for avoiding the rubber column 80. The airbag 40 is arranged between the box 20 and the outer frame 50. Both ends of the airbag 40 extend outward toward both ends of the box 20. When the dual ADC data acquisition and processing device of this embodiment is in use, after the acquisition device body 10 is placed in the box 20, the airbag 40 can provide a certain protective effect on it. When it falls from a higher position, the airbag 40 can provide a certain buffering effect to reduce the damage to the acquisition device body 10.

[0078] The high-pressure gas cylinder 70 is arranged on the outer frame 50 and is connected to the inside of the airbag 40 through the air intake mechanism 60. When the air pressure inside the airbag 40 is lower than the set value, the air intake mechanism 60 connects the high-pressure gas cylinder 70 and the airbag 40, thereby inflating the airbag 40 through the high-pressure gas cylinder 70, so that the air pressure inside the airbag 40 is always maintained at a certain pressure, so as to reduce the influence of slow leakage of the airbag 40 that may occur during long-term use on the cushioning effect.

[0079] Reference Figures 8 to 11 In an optional embodiment, the air intake mechanism 60 may adopt the following structure: the air intake mechanism 60 includes an air bin 61, an air valve 62, a piston 63, a fourth elastic member, a rotating shaft 67, a worm 68 and a transmission rack 69. The air bin 61 is arranged on the outer frame 50 and is connected to the interior of the airbag 40 through the air nozzle 42. The air bin 61 is connected to the high-pressure gas cylinder 70 through the tube body 65. The end of the tube body 65 is provided with a first air hole 651. The air valve 62 is rotatably arranged in the tube body 65. The air valve 62 is provided with a second air hole 621 that can overlap or stagger with the first air hole 651.

[0080] The gas chamber 61 is provided with a cylinder 66 communicating with the inside and outside of the gas chamber 61, and the piston 63 is slidably disposed in the cylinder 66 and connected to the gas valve 62. When the piston 63 slides, the gas valve 62 can be driven to rotate. More specifically, the gas valve 62 is provided with a first gear 622, and a rotating shaft 67 is rotatably disposed in the gas chamber 61. The rotating shaft 67 is provided with a worm gear 671 and a second gear 672 meshing with the first gear 622. The worm 68 is rotatably disposed in the gas chamber 61 and meshed with the worm gear 671. The worm 68 is provided with a third gear 681. The transmission rack 69 is fixedly connected to the piston 63 through a bracket 691 and meshed with the third gear 681.

[0081] The fourth elastic member is arranged on the gas chamber 61 and acts on the piston 63. The fourth elastic member can adopt a fourth spring 64. More specifically, a through hole 611 connected to the cylinder 66 is provided on the side wall of the gas chamber 61, and both ends of the fourth spring 64 are respectively abutted against the side wall of the gas chamber 61 and the piston 63.

[0082] The implementation principle of the dual ADC data acquisition and processing device of this embodiment is as follows: when the air pressure inside the airbag 40 and the air chamber 61 is at a relatively high pressure, the fourth spring 64 is in a compressed state, the first air hole 651 is staggered with the second air hole 621, and the high-pressure gas cylinder 70 cannot inflate the airbag 40. When the airbag 40 leaks slowly during long-term use, causing the air pressure inside the air chamber 61 to decrease, the piston 63 is pushed to slide under the elastic force of the fourth spring 64, and then the third gear 681 is driven to rotate through the transmission rack 69, and then the worm wheel 671 is driven to rotate through the worm 68, and then the air valve 62 is driven to rotate through the second gear 672 and the first gear 622, so that the first air hole 651 coincides with the second air hole 621, and the high-pressure gas cylinder 70 is connected to the air chamber 61, so that the airbag 40 is inflated through the high-pressure gas cylinder 70. When the air pressure inside the air chamber 61 rises, the piston 63 is pushed to slide against the elastic force of the fourth spring 64 , so that the first air hole 651 is offset from the second air hole 621 again.

[0083] The embodiments of this specific implementation are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. The same components are represented by the same figure marks. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A dual ADC data acquisition and processing device, characterized in that: include: A data acquisition device body (10), the data acquisition device body (10) comprising an amplification circuit (12), a data acquisition module and an FPGA signal processing module (14); The amplifier circuit (12) is provided with two paths, and the two paths of the amplifier circuit (12) have different amplification factors and are used to amplify the analog signal at different factors; The data acquisition module comprises two ADC chips (13), the two ADC chips (13) have different measurement ranges, the two ADC chips (13) are respectively connected to two amplifying circuits (12), and are used to convert analog signals amplified by the amplifying circuits (12) into digital signals; The FPGA signal processing module (14) is connected to the two ADC chips (13) and is used to generate an ADC sampling synchronization clock and simultaneously perform real-time splicing and restoration processing on the digital signals output by the two ADC chips (13) at the same time.

2. A dual ADC data acquisition and processing device according to claim 1, characterized in that: The acquisition device body (10) further comprises a signal conditioning circuit (11), wherein the signal conditioning circuit (11) is connected to two amplifying circuits (12), and the signal conditioning circuit (11) is used to amplify and filter the analog signal input to the amplifying circuit (12).

3. A dual ADC data acquisition and processing device according to claim 1, characterized in that: The device also comprises a box (20) and a blocking mechanism (30). The acquisition device body (10) further comprises a shell (15). The amplifying circuit (12), the data acquisition module and the FPGA signal processing module (14) are arranged in the shell (15). The shell (15) is provided with an acquisition interface (16). The shell (15) is placed in the box (20). The box (20) is provided with a through slot (21) for avoiding the acquisition interface (16). The blocking mechanism (30) is arranged on the box (20) and is used to openably and closably block the through slot (21).

4. A dual ADC data acquisition and processing device according to claim 3, characterized in that: The blocking mechanism (30) comprises two end covers (31), a first elastic member and two sealing plates (33); the two end covers (31) are openably and closably arranged at the through slot (21) of the box body (20); the first elastic member is arranged on the box body (20) and acts on the end covers (31); the first elastic member is used to push the two end covers (31) to close; the end covers (31) are provided with wire holes (311); the two sealing plates (33) are respectively slidably arranged on the two end covers (31) and are used to openably and closably block the wire holes (311).

5. A dual ADC data acquisition and processing device according to claim 4, characterized in that: The blocking mechanism (30) further comprises a second elastic member, the end cover (31) is provided with a guide groove (315) which penetrates the wire hole (311), the sealing plate (33) is slidably arranged in the guide groove (315), the second elastic member is arranged on the end cover (31) and acts on the sealing plate (33), and the second elastic member is used to push the sealing plates (33) on the two end covers (31) to move towards each other.

6. A dual ADC data acquisition and processing device according to claim 4, characterized in that: The blocking mechanism (30) further comprises a locking assembly, wherein the locking assembly comprises a wedge block (36) and a third elastic member, the box body (20) is provided with a slide groove (251) and a connecting hole (252) which penetrates the slide groove (251), the end cover (31) is provided with a locking tongue (316) which can be plugged into the connecting hole (252), the locking tongue (316) is provided with a locking groove (3161), the wedge block (36) is slidably arranged in the slide groove (251) and can be engaged with the locking groove (3161), the third elastic member is arranged on the box body (20) and acts on the wedge block (36), and the third elastic member is used to push the wedge block (36) to move toward the locking groove (3161).

7. A dual ADC data acquisition and processing device according to claim 3, characterized in that: The invention also comprises an air bag (40), an outer frame (50), an air intake mechanism (60) and a high-pressure gas cylinder (70); the outer frame (50) is arranged on the outside of the box body (20) and is connected to the box body (20) through an elastic column; the air bag (40) is arranged between the box body (20) and the outer frame (50); two ends of the air bag (40) extend outward toward two ends of the box body (20); the high-pressure gas cylinder (70) is arranged on the outer frame (50) and is connected to the inside of the air bag (40) through the air intake mechanism (60); when the air pressure inside the air bag (40) is less than a set value, the air intake mechanism (60) connects the high-pressure gas cylinder (70) and the air bag (40).

8. A dual ADC data acquisition and processing device according to claim 7, characterized in that: The air intake mechanism (60) comprises an air chamber (61), an air valve (62), a piston (63) and a fourth elastic member. The air chamber (61) is arranged on the outer frame (50) and is communicated with the interior of the air bag (40). The air chamber (61) is communicated with the high-pressure gas cylinder (70) through a tube body (65). The end of the tube body (65) is provided with a first air hole (651). The air valve (62) is rotatably arranged in the tube body (65). A second air hole (621) is provided which can overlap or be offset with the first air hole (651); a cylinder (66) which is in communication with the inside and outside of the air warehouse (61) is provided on the air warehouse (61); the piston (63) is slidably arranged in the cylinder (66) and is connected to the air valve (62); when the piston (63) slides, the air valve (62) can be driven to rotate; the fourth elastic member is provided on the air warehouse (61) and acts on the piston (63).

9. A dual ADC data acquisition and processing device according to claim 8, characterized in that: The air intake mechanism (60) further comprises a rotating shaft (67), a worm gear (68) and a transmission rack (69); a first gear (622) is provided on the air valve (62); the rotating shaft (67) is rotatably arranged in the air chamber (61); a worm wheel (671) and a second gear (672) meshing with the first gear (622) are provided on the rotating shaft (67); the worm gear (68) is rotatably arranged in the air chamber (61) and meshing with the worm wheel (671); a third gear (681) is provided on the worm gear (68); and the transmission rack (69) is fixedly connected to the piston (63) and meshing with the third gear (681).

10. A dual ADC data acquisition and processing method, characterized in that: A dual ADC data acquisition and processing device based on claim 2, comprising the following steps: Step 1: amplifying and filtering the input analog signal through the signal conditioning circuit (11); Step 2, amplifying the conditioned analog signal at different magnifications through two amplifier circuits (12); Step 3, the signals amplified at different magnifications are respectively transmitted to two ADC chips (13), the two ADC chips (13) are controlled by a synchronous sampling clock generated by an FPGA signal processing module (14), and the ADC chip (13) converts the analog signal into a digital signal after holding, quantizing and encoding the signal, and transmits the digital signal to the FPGA signal processing module (14); Step 4: The digital signals outputted by the two ADC chips (13) at the same time are spliced ​​and restored in real time through the FPGA signal processing module (14), thereby expanding the dynamic range of each frame of data.

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