Multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing

Abstract

The present application relates to a multi-channel direct digital conversion sensing interface circuit based on current-domain frequency division multiplexing. The interface circuit comprises a frequency modulator module, a first-stage integrator, a second-stage proportional integrator, a successive approximation quantizer, a dynamic weighted averaging unit, and a current digital-to-analog converter. The direct digital conversion architecture of this interface circuit eliminates the need for dedicated physiological signal amplification circuits and directly converts the collected signals into digital signals for processing, thereby exhibiting significant advantages in terms of area and power consumption. Furthermore, the interface circuit combines the advantages of frequency division multiplexing technology and a direct digital conversion architecture, providing an efficient and innovative solution for multi-channel physiological signal acquisition systems.

Description

Technical Field

[0001] The present application relates to the field of analog integrated circuit technology, and in particular to a multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing. Background Art

[0002] Nowadays, people want to keep up to date with the latest health data, which has driven the popularity of wearable devices such as smart bracelets and smart watches. These devices integrate multiple sensors and can monitor heart rate, blood pressure, sleep, and other data in real time. They can also easily view and share information through seamless connection with mobile phones and other devices. Advances in semiconductor technology have enabled the integration of biosignal acquisition and processing systems on small chips, providing technical support for low-power, small-sized wearable devices. Bioelectric signal acquisition systems mainly include analog front-ends, analog-to-digital converters, digital signal processing, wireless transmission, and power management modules. Among them, the analog front-end and analog-to-digital converters are key interfaces that determine the overall performance of the system. As demand grows, ultra-low-power multi-channel sensor interface circuits are becoming a future development trend.

[0003] In multi-channel design, the traditional "one-to-one" architecture is more common, but as the number of channels increases, power consumption and area increase sharply. Therefore, the "many-to-one" multiplexing circuit has gradually attracted attention. Common multiplexing structures such as Figure 1 As shown in the figure, (a) is voltage-domain time-division multiplexing (TDDM), (b) is current-domain time-division multiplexing (TDDM), (c) is voltage-domain frequency-division multiplexing (FDDM), and (d) is current-domain frequency-division multiplexing (CDDM). TDDM uses N independent amplifiers and a multiplexer to select the signal inputs of different channels into a shared analog-to-digital converter for processing. While this facilitates integration, as the number of channels N increases, the size of the multiplexer increases by N², and the driver power consumption also increases accordingly. TDDM uses a variable-gain transconductance amplifier to drive low-impedance loads, alleviating the effects of load capacitance. However, as N increases, the time period allocated to each channel decreases, resulting in incomplete or distorted signal processing and the inability to sample multiple channels simultaneously. In contrast, frequency-division multiplexing modulates the signal of each channel to a different frequency to achieve parallel signal processing. However, as N increases, the maximum carrier frequency must be increased to avoid noise folding and signal interference, increasing bandwidth requirements and extending the amplifier's -3 dB bandwidth. TDDM typically uses a closed-loop instrumentation amplifier, whose feedback factor is inversely proportional to N², causing power consumption to increase with N². Current-domain frequency-division multiplexing replaces closed-loop instrumentation amplifiers with open-loop transconductance units, significantly reducing the power consumption associated with feedback current. Total system power consumption scales linearly with the number of channels, while the average power consumption per channel remains relatively stable. This innovative design effectively addresses the power consumption bottleneck associated with multi-channel multiplexing and provides a new solution for high-channel-count, low-power applications. However, achieving high dynamic range is challenging with traditional analog front-end and cascaded analog-to-digital converter architectures. Summary of the Invention

[0004] Based on this, it is necessary to provide a multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing to address the above technical problems.

[0005] A multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing, the multi-channel direct digital conversion sensing interface circuit comprising:

[0006] The frequency modulator module is used to modulate N-channel low-frequency input signals into N non-overlapping high-frequency bands to generate N-channel high-frequency band signals; N is an integer greater than 0; the high-frequency band signals are voltage domain signals.

[0007] The first-stage integrator is used to convert the received N-channel high-frequency band signal into a current domain signal, add the signals, subtract the addition result from the feedback current output by the current digital-to-analog converter, and then perform integration processing to obtain a first integration result.

[0008] The second-stage proportional integrator is used to perform integration and feedforward superposition processing on the first integration result to obtain a second integration result.

[0009] The successive approximation quantizer is used to sample the second integration result and generate a corresponding binary digital code.

[0010] The dynamic weighted averaging unit is used to convert the binary digital code into a thermometer code and process the thermometer code through a round-robin control strategy to obtain a thermometer code after dynamic weighted averaging.

[0011] The current digital-to-analog converter is used to generate a corresponding feedback current according to the thermometer code after dynamic weighted averaging, and feed the feedback current back to the first-stage integrator.

[0012] In one embodiment, the frequency modulator module includes N frequency modulation units, each frequency modulation unit is used to modulate a low-frequency channel input signal through a square wave carrier, and the spectrum of each low-frequency channel input signal is up-converted to a preset range of N different high-frequency fundamental carrier frequencies and odd harmonic frequencies.

[0013] In one embodiment, the first-stage integrator includes: N transconductance units, two common-mode resistors, an operational amplifier, and two integrating capacitors.

[0014] The positive ends of all transconductance units are connected to the first end of the first common-mode resistor, the second end of the first common-mode resistor is connected to the first end of the second common-mode resistor, the negative ends of all transconductance units are connected to the second end of the second common-mode resistor, the first end of the first common-mode resistor is connected to the positive input terminal of the operational amplifier, the second end of the second common-mode resistor is connected to the negative input terminal of the operational amplifier, the positive end of the operational amplifier is connected to one end of the first integrating capacitor, the other end of the first integrating capacitor is connected to the negative output terminal of the operational amplifier, the negative end of the operational amplifier is connected to one end of the second integrating capacitor, and the other end of the second integrating capacitor is connected to the positive output terminal of the operational amplifier.

[0015] The transconductance unit is used to convert the high-frequency band signal generated by the frequency modulator module into a current signal, and perform current superposition at the output node to achieve linear conversion from voltage to current.

[0016] In one embodiment, the second-stage proportional integrator includes two integrating resistors, two proportional resistors, a first operational amplifier, and two first integrating capacitors.

[0017] One end of the first integrating resistor is connected to the first output end of the first-stage integrator, the other end of the first integrating resistor is connected to the positive input end of the first operational amplifier, one end of the first proportional resistor is connected to the positive input end of the first operational amplifier, the other end of the first proportional resistor is connected to one end of the first first integrating capacitor, and the other end of the first first integrating capacitor is connected to the negative output end of the first operational amplifier; one end of the second integrating resistor is connected to the second output end of the first-stage integrator, the other end of the second integrating resistor is connected to the negative input end of the first operational amplifier, one end of the second proportional resistor is connected to the negative input end of the first operational amplifier, the other end of the second proportional resistor is connected to one end of the second first integrating capacitor, and the other end of the second first integrating capacitor is connected to the positive output end of the first operational amplifier.

[0018] In one embodiment, the successive approximation quantizer is a three-bit quantizer controlled by asynchronous logic, which is used to sample the second integration result output by the second-stage proportional integrator, convert it into a three-bit binary digital code through successive approximation logic, and output the binary digital code.

[0019] In one embodiment, the dynamic weighted averaging unit includes a binary code to thermometer code unit, a pointer register, and a barrel shifter.

[0020] The binary code to thermometer code unit is used to convert the binary digital code into a thermometer code.

[0021] A pointer register is used to record the first unused unit current unit each time through a pointer as a starting point for the next selection;

[0022] The barrel shifter is used for shifting the thermometer code according to the starting point recorded by the pointer register and outputting the shifted code to the current digital-to-analog converter.

[0023] In one embodiment, a current digital-to-analog converter includes a register, a low cross-point control circuit, and a digital-to-analog converter unit.

[0024] The register and the low cross point control circuit form a switch driving circuit, which is connected to the digital-to-analog converter unit; the digital-to-analog converter unit outputs a feedback current to the first-stage integrator.

[0025] In one embodiment, the digital-to-analog converter unit adopts a bipolar architecture.

[0026] The multi-channel direct digital conversion sensing interface circuit based on current-domain frequency division multiplexing (CDM) includes a frequency modulator module, a first-stage integrator, a second-stage proportional integrator, a successive approximation quantizer, a dynamic weighted averaging unit, and a current digital-to-analog converter. This interface circuit's direct digital conversion architecture eliminates dedicated physiological signal amplification circuits and directly converts the collected signals into digital signals for processing, demonstrating significant advantages in terms of area and power consumption. Furthermore, this interface circuit combines the advantages of frequency division multiplexing technology and a direct digital conversion architecture, providing an efficient and innovative solution for multi-channel physiological signal acquisition systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the existing multi-channel multiplexing circuit structure, where (a) is a schematic diagram of the voltage domain time division multiplexing circuit structure, (b) is a schematic diagram of the current domain time division multiplexing circuit structure, (c) is a schematic diagram of the voltage domain frequency division multiplexing circuit structure, and (d) is a schematic diagram of the current domain frequency division multiplexing circuit structure;

[0028] Figure 2 A schematic diagram of a multi-channel direct digital conversion sensing interface circuit structure based on current domain frequency division multiplexing in one embodiment;

[0029] Figure 3 2 is a schematic structural diagram of a first-stage integrator in another embodiment;

[0030] Figure 4 2 is a schematic structural diagram of a second-stage proportional integrator in another embodiment;

[0031] Figure 5 Schematic diagram of the structure of a dynamic weighted averaging unit in another embodiment;

[0032] Figure 6 FIG. 4 is a structural diagram of a current digital-to-analog converter in another embodiment. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0034] In one embodiment, Figure 2 As shown, a multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing is provided, and the multi-channel direct digital conversion sensing interface circuit includes:

[0035] The frequency modulator module 1 is used to modulate N-channel low-frequency input signals into N non-overlapping high-frequency bands to generate N-channel high-frequency band signals; N is an integer greater than 0; the high-frequency band signals are voltage domain signals.

[0036] Specifically, the N-channel low-frequency input signal is composed of N channels of high-frequency carriers (f ch1 、f ch2、 …、f chN ) is moved to high frequency, high frequency carrier (f ch1 、f ch2 ,…,f chN ) are equally spaced, and f ch1 The higher harmonics are far away from f chN Among them, f ch1 、f ch2 、f chN They are the frequencies of the first, second and Nth high-frequency carriers respectively.

[0037] The first-stage integrator 2 is used to convert the received N-channel high-frequency band signal into a current domain signal, add it, subtract the addition result from the feedback current output by the current digital-to-analog converter, and then perform integration processing to obtain a first integration result.

[0038] Specifically, the first-stage integrator 2 converts the voltage domain signal into a current domain signal through the coordinated work of N transconductance units, two common-mode resistors, an operational amplifier, and an integrating capacitor, and performs addition and integration processing.

[0039] The second-stage proportional integrator 3 is used to perform integration and feedforward superposition processing on the first integration result to obtain a second integration result.

[0040] Specifically, the second-stage proportional integrator 3 performs further integration and feedforward superposition processing on the output signal of the first-stage integrator 2 to optimize signal quality.

[0041] The successive approximation quantizer 4 is used to sample the second integration result and generate a corresponding binary digital code.

[0042] Specifically, the successive approximation quantizer 4 is a three-bit quantizer controlled by asynchronous logic, which can convert the output result of the second-stage proportional integrator 3 into a three-bit binary digital code for output.

[0043] The dynamic weighted averaging unit 5 is used to convert the binary digital code into a thermometer code, and process the thermometer code through a round-robin control strategy to obtain a thermometer code after dynamic weighted averaging.

[0044] Specifically, the dynamic weighted averaging unit 5 receives these three-bit binary digital codes, converts them into seven-bit thermometer codes, and further processes them through a round-robin control strategy to control the digital-to-analog converter to reduce noise and distortion.

[0045] The current digital-to-analog converter 6 is used to generate a corresponding feedback current according to the thermometer code after dynamic weighted averaging, and feed the feedback current back to the first-stage integrator 2 .

[0046] Specifically, the current digital-to-analog converter 6 generates corresponding currents according to the thermometer code generated by the dynamic weighted average unit, and feeds these currents back to the output node of the transconductance unit in the first-stage integrator to form a closed-loop control.

[0047] The multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing combines the advantages of frequency division multiplexing technology and direct digital conversion architecture, and proposes a Gm-C based continuous-time Delta-Sigma modulator composed of a first-stage integrator 2, a second-stage proportional integrator 3, a successive approximation quantizer 4, a dynamic weighted average unit 5 and a current digital-to-analog converter 6 as the core module, providing an efficient and innovative solution for multi-channel physiological signal acquisition systems.

[0048] The multi-channel direct digital conversion sensing interface circuit based on current-domain frequency division multiplexing (CDM) includes a frequency modulator module, a first-stage integrator, a second-stage proportional integrator, a successive approximation quantizer, a dynamic weighted averaging unit, and a current digital-to-analog converter. This interface circuit's direct digital conversion architecture eliminates dedicated physiological signal amplification circuits and directly converts the collected signals into digital signals for processing, resulting in significant advantages in area and power consumption. Furthermore, this interface circuit combines the advantages of frequency division multiplexing technology and a direct digital conversion architecture, providing an efficient and innovative solution for multi-channel physiological signal acquisition systems.

[0049] In one embodiment, the frequency modulator module 1 includes N frequency modulation units, each frequency modulation unit is used to modulate a low-frequency channel input signal through a square wave carrier, and the spectrum of each low-frequency channel input signal is up-converted to a preset range of N different high-frequency fundamental carrier frequencies and odd harmonic frequencies.

[0050] Specifically, the input signals of the N channels in the frequency modulator module 1 are modulated by square wave carriers. The spectrum of the low-frequency input signal of the N channels is up-converted to N different high-frequency fundamental carrier frequencies (f ch1 、f ch2 …f chN ) and odd harmonic frequencies. To ensure effective separation of the signal and harmonic components, the frequency of each channel needs to be carefully selected. In addition, a guard band needs to be added. To prevent interference from adjacent channels. In an N-channel frequency division multiplexing system, to ensure that the frequency domain of the modulated signal does not contain high-frequency interference, it is necessary to ensure that the high-order harmonic components are far away from the frequency of each channel. At the same time, to avoid signal overlap between adjacent channels, the channel spacing Need to be consistent.

[0051] In one embodiment, the circuit structure of the first stage integrator is as follows: Figure 3 As shown, the first-stage integrator 2 includes: N transconductance units 21 , two common-mode resistors 22 , an operational amplifier 23 and two integrating capacitors 24 .

[0052] The positive ends of all transconductance units 21 are connected to the first end of the first common-mode resistor 22, the second end of the first common-mode resistor 22 is connected to the first end of the second common-mode resistor 22, the negative ends of all transconductance units 21 are connected to the second end of the second common-mode resistor 22, the first end of the first common-mode resistor 22 is connected to the positive input end of the operational amplifier 23, the second end of the second common-mode resistor 22 is connected to the negative input end of the operational amplifier 23, the positive end of the operational amplifier 23 is connected to one end of the first integrating capacitor 24, the other end of the first integrating capacitor 24 is connected to the negative output end of the operational amplifier 23, the negative end of the operational amplifier 23 is connected to one end of the second integrating capacitor 24, and the other end of the second integrating capacitor 24 is connected to the positive output end of the operational amplifier 23.

[0053] The transconductance unit 21 is used to convert the high-frequency band signal generated by the frequency modulator module 1 into a current signal, and perform current superposition at the output node to achieve linear conversion from voltage to current.

[0054] Specifically, such as Figure 3As shown, the first-stage integrator 2 is composed of N transconductance units 21, two common-mode resistors 22, an operational amplifier 23 and an integrating capacitor 24. The transconductance unit 21 converts the input voltage signal modulated to a high frequency into a current signal and performs current superposition at the output node. In order to achieve efficient linear conversion from voltage to current, the transconductance unit 21 has a wide linear input range. In order to stabilize the common-mode voltage, the positive and negative output terminals of the transconductance unit 21 are each connected to a common-mode resistor 22 to the common-mode level. At the same time, the introduction of the operational amplifier 23 improves the driving capability of the system and ensures the stable performance of the subsequent cascade circuit. Integration is achieved by the integrating capacitor 24.

[0055] The transconductance unit 21 converts the N-channel high-frequency band signal from the voltage domain to the current domain and superimposes the current at the output node. Two common-mode resistors 22 are connected to the positive and negative output terminals, respectively, and to the common-mode voltage level to stabilize the common-mode voltage. The current and signal are integrated by the integrating capacitor 24, while the operational amplifier 23 ensures the stability of the output common-mode voltage.

[0056] Compared to voltage-domain frequency-division multiplexing (VDFDM), current-domain frequency-division multiplexing (CDFDM) significantly reduces power consumption by replacing closed-loop instrumentation amplifiers with open-loop transconductance units. While total system power consumption increases linearly with the number of channels, the average power consumption per channel remains relatively stable. Furthermore, the direct digital conversion architecture eliminates dedicated physiological signal amplification circuitry and directly converts the collected signals into digital signals for processing, resulting in significant advantages in terms of area and power consumption.

[0057] In one embodiment, the circuit structure of the second-stage proportional integrator is as follows: Figure 4 As shown, the second-stage proportional integrator 3 includes two integrating resistors 31 , two proportional resistors 32 , a first operational amplifier 33 and two first integrating capacitors 34 .

[0058] One end of the first integrating resistor 31 is connected to the first output end of the first-stage integrator 2, the other end of the first integrating resistor 31 is connected to the positive input end of the first operational amplifier 33, one end of the first proportional resistor 32 is connected to the positive input end of the first operational amplifier 33, the other end of the first proportional resistor 32 is connected to one end of the first first integrating capacitor 34, and the other end of the first first integrating capacitor 34 is connected to the negative output end of the first operational amplifier 33; one end of the second integrating resistor 31 is connected to the second output end of the first-stage integrator 2, the other end of the second integrating resistor 31 is connected to the negative input end of the first operational amplifier 33, one end of the second proportional resistor 32 is connected to the negative input end of the first operational amplifier 33, the other end of the second proportional resistor 32 is connected to one end of the second first integrating capacitor 34, and the other end of the second first integrating capacitor 34 is connected to the positive output end of the first operational amplifier 33.

[0059] Specifically, such as Figure 4 As shown. The second-stage proportional integrator 3 includes: an integrating resistor 31, a proportional resistor 32, a first operational amplifier 33, and a first integrating capacitor 34 connected across the first operational amplifier 33. There are two signal paths in the second-stage proportional integrator 3: an integral path and a proportional path. The proportional path is realized by connecting the integrating capacitor 34 and the proportional resistor 32 in series. The unity gain bandwidth and DC gain of the first operational amplifier 33 affect the overall performance. The ratio of the proportional resistor 32 to the integrating resistor 31 determines the forward proportional coefficient (feedforward coefficient), while the integrating resistor 31 and the first integrating capacitor 34 jointly determine the integral coefficient. The first operational amplifier 33 also ensures the stability of the input and output common modes. In order to reduce the variation of the proportional coefficient, the mismatch between the proportional resistor 32 and the integrating resistor 31 needs to be minimized, which can be achieved by selecting resistors of the same process and type.

[0060] In one embodiment, the successive approximation quantizer is a three-bit quantizer controlled by asynchronous logic, which is used to sample the second integration result output by the second-stage proportional integrator, convert it into a three-bit binary digital code through successive approximation logic, and output the binary digital code.

[0061] In one embodiment, the circuit structure of the dynamic weighted averaging unit is as follows: Figure 5 As shown, the dynamic weighted averaging unit 5 includes: a binary code to thermometer code unit 51 , a pointer register 52 and a barrel shifter 53 .

[0062] The binary code to thermometer code unit 51 is used to convert the binary digital code into a thermometer code.

[0063] The pointer register 52 is used to record the first unused unit current unit each time as the starting point for the next selection.

[0064] The barrel shifter 53 is used to shift the thermometer code according to the starting point recorded in the pointer register and output the shifted code to the current digital-to-analog converter.

[0065] Specifically, such as Figure 5 As shown in Figure 2 , the dynamic weighted averaging unit 5 consists of a binary code-to-thermometer code unit 51, a pointer register 52 (pointer register P[2:0]), and a barrel shifter 53, and generates a control signal S[6:0]. Under the operation of the dynamic weighted averaging unit 5, all DAC unit current cells are sequentially selected. The algorithm uses a pointer to record the first unused unit current cell each time, which serves as the starting point for the next selection. This effectively converts the noise and distortion caused by mismatch in the current DAC 6 into first-order high-pass noise errors.

[0066] In one embodiment, the circuit structure of the current digital-to-analog converter 6 is as follows: Figure 6 As shown, the current digital-to-analog converter 6 includes a register 61 , a low cross-point control circuit 62 and a digital-to-analog converter unit 63 .

[0067] The register 61 and the low-cross point control circuit 62 form a switch driving circuit, which is connected to the digital-to-analog converter unit 63 ; the digital-to-analog converter unit 63 outputs a feedback current to the first-stage integrator.

[0068] In one embodiment, the DAC unit 63 adopts a bipolar architecture.

[0069] Specifically, such as Figure 6 As shown. The current digital-to-analog converter 6 consists of a register 61, a low cross-point control circuit 62 and a digital-to-analog converter unit 63. The current digital-to-analog converter 6 is controlled by a seven-bit thermometer code. The register 61 and the low cross-point control circuit 62 form a switch drive circuit to generate a control switch signal, thereby controlling the output current of the seven digital-to-analog converter units 63, avoiding the situation where the two current sources are simultaneously turned off when the cross-point voltage of the complementary control signal is Vctrl / 2 to generate a peak current, thereby affecting the dynamic performance. This design not only speeds up the high and low level switching speed of the signal, but also further alleviates the impact of the clock feedthrough effect by reducing the high level voltage. Since the feedback point is set at the output end of the transconductance unit 21, the four-channel signal is transmitted by current superposition, so the current digital-to-analog converter 6 is selected. The digital-to-analog converter unit 63 adopts a bipolar architecture. Compared with the unipolar type, it can achieve the same output range with only half the total current.

[0070] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing, characterized in that: The multi-channel direct digital conversion sensor interface circuit comprises: A frequency modulator module is configured to modulate an N-channel low-frequency input signal into N non-overlapping high-frequency bands to generate an N-channel high-frequency band signal; N is an integer greater than 0; and the high-frequency band signal is a voltage domain signal; A first-stage integrator is configured to convert the received N-channel high-frequency band signals into current-domain signals, add them, subtract the summed signals from the feedback current output by the current digital-to-analog converter, and then perform integration processing to obtain a first integration result. The first-stage integrator includes: N transconductance units, two common-mode resistors, an operational amplifier, and two integrating capacitors. The positive ends of all transconductance units are connected to the first end of the first common-mode resistor, the second end of the first common-mode resistor is connected to the first end of the second common-mode resistor, the negative ends of all transconductance units are connected to the second end of the second common-mode resistor, the first end of the first common-mode resistor is connected to the positive input terminal of the operational amplifier, the second end of the second common-mode resistor is connected to the negative input terminal of the operational amplifier, the positive end of the operational amplifier is connected to one end of the first integrating capacitor, the other end of the first integrating capacitor is connected to the negative output terminal of the operational amplifier, the negative end of the operational amplifier is connected to one end of the second integrating capacitor, and the other end of the second integrating capacitor is connected to the positive output terminal of the operational amplifier; The transconductance unit is used to convert the high-frequency band signal generated by the frequency modulator module into a current signal, and perform current superposition at the output node to achieve linear conversion from voltage to current; A second-stage proportional integrator is configured to perform integration and feedforward superposition processing on the first integration result to obtain a second integration result; a successive approximation quantizer, configured to sample the second integration result and generate a corresponding binary digital code; a dynamic weighted averaging unit, configured to convert the binary digital code into a thermometer code, and process the thermometer code through a round-robin control strategy to obtain a thermometer code after dynamic weighted averaging; The current digital-to-analog converter is used to generate a corresponding feedback current according to the thermometer code after dynamic weighted averaging, and feed the feedback current back to the first-stage integrator.

2. The multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The frequency modulator module includes N frequency modulation units, each frequency modulation unit is used to modulate a low-frequency channel input signal through a square wave carrier, and the spectrum of each low-frequency channel input signal is up-converted to a preset range of N different high-frequency fundamental carrier frequencies and odd harmonic frequencies.

3. The multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The second-stage proportional integrator includes: two integrating resistors, two proportional resistors, a first operational amplifier, and two first integrating capacitors; One end of the first integrating resistor is connected to the first output end of the first-stage integrator, the other end of the first integrating resistor is connected to the positive input end of the first operational amplifier, one end of the first proportional resistor is connected to the positive input end of the first operational amplifier, the other end of the first proportional resistor is connected to one end of the first first integrating capacitor, and the other end of the first first integrating capacitor is connected to the negative output end of the first operational amplifier; one end of the second integrating resistor is connected to the second output end of the first-stage integrator, the other end of the second integrating resistor is connected to the negative input end of the first operational amplifier, one end of the second proportional resistor is connected to the negative input end of the first operational amplifier, the other end of the second proportional resistor is connected to one end of the second first integrating capacitor, and the other end of the second first integrating capacitor is connected to the positive output end of the first operational amplifier.

4. The multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The successive approximation quantizer is a three-bit quantizer controlled by asynchronous logic, which is used to sample the second integration result output by the second-stage integrator, convert it into a three-bit binary digital code through successive approximation logic, and output the binary digital code.

5. The multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The dynamic weighted averaging unit includes: a binary code to thermometer code unit, a pointer register and a barrel shifter; The binary code to thermometer code unit is used to convert the binary digital code into a thermometer code; The pointer register is used to record the first unused unit current unit each time through a pointer as the starting point for the next selection. The barrel shifter is used to shift the thermometer code according to the starting point recorded in the pointer register and output it to the current digital-to-analog converter.

6. The multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing according to claim 1, characterized in that: The current digital-to-analog converter includes: a register, a low cross-point control circuit and a digital-to-analog converter unit; The register and the low cross point control circuit form a switch driving circuit, and the switch driving circuit is connected to the digital-to-analog converter unit; the digital-to-analog converter unit outputs a feedback current to the first-stage integrator.

7. The multi-channel direct digital conversion sensing interface circuit based on current domain frequency division multiplexing according to claim 6, characterized in that: The digital-to-analog converter unit adopts a bipolar architecture.

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