Log likelihood ratio mapping table in flash storage system

Abstract

Read data associated with a flash storage device is received. One of the plurality of LLR mapping tables is selected, and a set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has the same finite precision as a finite precision low density parity check (LDPC) decoder. Error corrected read data is generated using the set of LLR values, wherein the finite precision LDPC decoder has the same finite precision as the set of LLR values. And outputting the read data subjected to error correction.

Description

This case is a divisional application. The invention name of the parent case is "Log-likelihood ratio mapping table in flash storage system", the application date is May 24, 2022, and the application number is 202210568127.8. Background Art

[0001] Flash memory systems store information in the form of electrical charge. Over time, flash memory media degrades as the number of program or erase cycles increases, causing the flash memory media to "leak" and introduce errors into the stored data. High temperatures may also introduce errors into the stored data. Many flash memory systems use low-density parity-check (LDPC) codes to remove errors from data stored on the flash memory media.

[0002] There are multiple technologies and / or methods for realizing LDPC decoding system.When LDPC coded data is decoded, iterative message passing (MP) decoding is one of the most efficient ways to realize near optimal performance.Minimum sum (min-sum) decoding technique (a type of MP decoder) is attractive due to its low complexity.For example, iterative MP decoding, minimum sum decoding, etc.) optimized and / or improved new flash storage and / or LDPC system of the performance of specific LDPC decoder method will be desirable.For example, if this new flash storage and / or LDPC system reduces power consumption and / or decoding delay, then will be desirable. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings.

[0004] Figure 1 is a flow chart illustrating an embodiment of a process for performing low density parity check (LDPC) decoding using multiple log-likelihood ratio (LLR) mapping tables.

[0005] Figure 2 is a diagram illustrating an embodiment of an LDPC decoding system including a plurality of LLR tables.

[0006] Figure 3 is a diagram illustrating an embodiment of an LLR mapping table with 1-bit input and 4-bit output.

[0007] Figure 4 is a graph illustrating an embodiment of a frame error rate associated with an LLR mapping table that generates 4-bit precision LLR values ​​for a soft LDPC decoder.

[0008] Figure 5 is a flow diagram illustrating an embodiment of a process for selecting an LLR mapping table based at least in part on a decoding attempt count.

[0009] Figure 6 is a diagram illustrating an embodiment of an LLR mapping table with 2-bit soft input and 4-bit output.

[0010] Figure 7 is a flow chart illustrating an embodiment of a process of selecting a soft input LLR mapping table when all hard input LLR mapping tables have been selected.

[0011] Fig. 8A is a diagram illustrating an embodiment of a sequence of LLR mapping tables starting with a hard input LLR mapping table when a flash storage medium is in a high SNR state.

[0012] Figure 8B is a diagram illustrating an embodiment of a sequence of LLR mapping tables starting with a soft input LLR mapping table when a flash storage medium is in a low SNR state. DETAILED DESCRIPTION

[0013] The present invention can be implemented in many ways, including as a process; an apparatus; a system; a material composition; a computer program product embodied on a computer-readable storage medium; and / or a processor, such as a processor configured to execute instructions stored on and / or provided by a memory coupled to the processor. In this specification, these implementations or any other form that the present invention can take can be referred to as technology. In general, within the scope of the present invention, the order of the steps of the disclosed process can be changed. Unless otherwise stated, components such as processors or memories described as being configured to perform tasks can be implemented as general components that are temporarily configured to perform the task at a given time, or as specific components manufactured to perform the task. As used herein, the term "processor" refers to one or more devices, circuits, and / or processing cores configured to process data (such as computer program instructions).

[0014] A detailed description of one or more embodiments of the present invention is provided below, together with the accompanying drawings that illustrate the principles of the present invention. The present invention is described in conjunction with such embodiments, but the present invention is not limited to any embodiment. The scope of the present invention is limited only by the claims, and the present invention encompasses many alternatives, modifications and equivalents. Many specific details are set forth in the following description to provide a comprehensive understanding of the present invention. These details are provided for illustrative purposes, and the present invention can be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical materials known in the technical field related to the present invention are not described in detail so that the present invention will not be unnecessarily obscured.

[0015] Low-density parity-check (LDPC) codes can be conveniently represented by a bipartite graph called a Tanner graph. There are two types of nodes in a Tanner graph: variable nodes (VN) and check nodes (CN). Each variable node (or check node) corresponds to a column (or row) of a parity-check matrix (H). LDPC codes are attractive because they are close to the Shannon limit.

[0016] Iterative MP decoders (a type of LDPC decoder) are popular because they can be implemented in efficient, high-speed software and / or hardware embodiments. A typical iterative message passing (MP) decoder alternates between two phases: a "VN-to-CN" phase, during which the VN sends messages to the CN along its neighboring edges; and a "CN-to-VN" phase, during which the CN sends messages to its neighboring VNs. Messages are updated at each CN or VN using incoming information from neighboring edges (i.e., connected nodes). In the initialization step of the decoding process, VN i forwards the same message, i.e., the log-likelihood ratio (LLR) value, to all of its neighboring CNs.

[0017] In some existing flash memory systems using LDPC codes, the LLR values ​​used during the initialization step are is obtained from a flash channel model located between the flash storage medium and the LDPC decoder (e.g., in the flash storage read interface). The flash channel model is estimated offline and its associated parameters are adjusted over time, for example, as the flash storage medium degrades (e.g., depending on the number of programming or erase cycles experienced by the flash storage medium, temperature, etc.). Note that in the case of the flash channel model, the LLR values is dynamically calculated for each data bit. As expected, a flash channel model is used to generate the LLR values ​​that are input to the iterative MP (LDPC) decoder is resource intensive and / or has significant latency.

[0018] Various embodiments of the technology of using multiple LLR mapping tables to generate LLR values ​​input to a finite precision LDPC decoder are described herein. In some embodiments, the finite precision LDPC decoder includes an iterative MP decoder and / or a minimum sum decoder. In some embodiments, the LLR mapping table is optimized to avoid certain artifacts (artifact) and / or noise floors (floor) associated with saturation, some finite precision LDPC decoders are susceptible to these artifacts and / or noise floors, and infinite precision and / or "perfect" LDPC decoders are not susceptible to these artifacts and / or noise floors. For example, the LLR mapping table can intentionally avoid or exclude the maximum (possible) magnitude for a given number of bits to avoid artifacts and / or error traps caused by saturation due to a large number of values. Various embodiments will be described in more detail below.

[0019] Figure 1 is a flow chart illustrating an embodiment of a process for performing low density parity check (LDPC) decoding using multiple log-likelihood ratio (LLR) mapping tables. In some embodiments, Figure 1 The process is performed by an LDPC decoding system. For example, such an LDPC decoding system may include an LLR mapping block having a plurality of LLR mapping tables, and a finite precision LDPC decoder. In some embodiments, the LDPC decoding system communicates with a (e.g., separate) flash storage read interface (e.g., implemented on a different device or system). Alternatively, the LDPC decoding system may be integrated with the flash storage read interface (e.g., on the same device or system).

[0020] At 100, read data associated with a flash storage device is received. For example, the read data may be received from a flash storage read interface, which in turn interfaces with the flash storage device. In a flash storage device, information is stored as an electric charge. Conceptually, reading the flash storage device is performed by comparing the stored charge to one or more read thresholds, where the number of read thresholds depends on the number of bits stored per cell. In various embodiments, a cell may store a single bit (e.g., a single-level cell (SLC)), two bits (e.g., a multi-level cell (MLC)), and so on. Using the example of a single-level cell (SLC), if the stored charge exceeds the read threshold, a 0 is output as a read bit (as an example); if the stored charge does not exceed a particular read threshold, a 1 is output as a read bit.

[0021] In various embodiments, the read data received at step 100 (e.g., from a flash storage read interface) includes hard read data or soft read data. For example, if a particular implementation of a flash storage read interface is configured to output hard read data, then a flash storage read interface to an SLC flash storage device (as an example) outputs a value of 0 or 1 for each cell without any indication of reliability or certainty associated with the (e.g., read) value.

[0022] Alternatively, if the read data received at step 100 is soft read data (e.g., because the flash storage read interface is so configured), the flash storage read interface may output (e.g., read or report) a value, and an associated certainty, confidence, or reliability in the value. For example, the flash storage read interface may perform multiple reads using different read thresholds, and use these multiple sets of (e.g., raw) read data to generate (e.g., read or report) a value and an associated reliability. As a practical matter, many current flash storage systems return at most 2 bits of reliability information due to the amount of internal circuit complexity that grows exponentially with each bit of reliability information. It is noted that generating soft read data is time consuming and processing resource intensive (e.g., because performing multiple reads on the flash storage medium is time consuming and processing resource intensive).

[0023] At 102, one of a plurality of log-likelihood ratio (LLR) mapping tables is selected. For example, there may be a predefined order or sequence in which the LLR mapping tables are selected and used. For example, a first LLR mapping table may be selected to generate a first set of LLR values, and then a second LLR mapping table may be selected (if necessary) to generate a second set of LLR values, and so on. In some embodiments, the (next) LLR mapping table to be used is selected dynamically and / or in real time (e.g., based on information from previous decoding attempts). For example, if the current set of LLR values ​​results in an abnormally large number of unsatisfied checks (e.g., this is determined by comparing the number of unsatisfied checks to a threshold, where the threshold may be fixed or alternatively based on a moving average over some recent time window or attempt), the maximum value of the next LLR set is selected to be smaller.

[0024] As will be described in more detail below, in some embodiments, the first LLR mapping table that is selected (e.g., selected when a new block of data is read from the flash storage medium) depends on the state of the flash storage medium. For example, if the flash storage medium is "leaky" because it has undergone a large amount of programming and / or erasing that wears out the flash storage medium, and / or because the flash storage medium is hot (both of which increase the number of errors in the (e.g., original) read data), then in some embodiments, the system starts with the LLR mapping table associated with the lowest error floor. Alternatively, at the beginning of the flash storage medium and / or when the flash storage medium is cool, the error rate may be lower, and the LLR mapping table associated with the lowest average number of iterations is initially and / or first selected (e.g., selected when a new block of data is read from the flash storage medium) (which is beneficial for power savings and / or latency).

[0025] At 104, a set of one or more LLR values ​​is generated using the read data and the selected LLR mapping table, wherein each LLR value in the set of LLR values ​​has the same precision as a finite precision low density parity check (LDPC) decoder. In one example described in more detail below, the LLR mapping block generates LLR values ​​with four (4) bits of precision (e.g., because the downstream LDPC decoder is configured to input LLR values ​​with this level of precision).

[0026] At 106, error-corrected read data is generated using the set of LLR values ​​and a finite precision LDPC decoder having the same finite precision as the set of LLR values. That is, the level or amount of precision in the LLR values ​​generated at step 104 is intentionally and / or specifically matched to the finite precision of the LDPC decoder. In some embodiments, the LLR mapping table (e.g., which performs steps 100 and 102) and the LDPC decoder (e.g., which performs steps 104, 106, and 108) are implemented in the same system or device (e.g., the same ASIC or FPGA), and thus the level or degree of finite precision of the LDPC decoder is known, and the LLR mapping table can be designed and / or configured accordingly.

[0027] At 108, the error-corrected read data is output. For example, if the syndrome in the LDPC decoder is all zero at the end of the decoding iteration, the decoding is declared successful, and the error-corrected data is output by the LDPC decoder. In some embodiments, the error-corrected read data is output to an application that presents or displays the stored information to a user.

[0028] Graphical execution Figure 1 A block diagram of an exemplary system that illustrates the process described in the may be helpful. The following figure depicts one such exemplary system.

[0029] Figure 2 is a diagram illustrating an embodiment of an LDPC decoding system including multiple LLR tables.In some embodiments, some or all of the blocks shown herein are implemented in hardware (eg, in an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc.).

[0030] A flash memory device (200) stores information in the form of electrical charge. In this example, the flash memory device (200) is pre-programmed with one or more default read thresholds (202), which are (one or more) default thresholds for performing reads. (Alternatively, the flash memory read interface (204) may provide the flash memory device (200) with one or more dynamic read thresholds (206) to be used, or program the flash memory device (200) with one or more dynamic read thresholds (206) to be used instead). In the case of SLC cells (i.e., single-bit cells), for a given SLC cell, the raw read bit is either 0 (e.g., the stored charge exceeds the read threshold) or 1 (e.g., the stored charge does not exceed the read threshold). Raw read data (e.g., a sequence of raw read bits) is passed from the flash memory device (200) to the flash memory read interface (204).

[0031] The flash memory read interface (204) passes the interface read data to the LDPC decoding system (208) having multiple LLR tables. The interface read data is called interface read data because it comes from the flash memory read interface (204) and is used to distinguish it from the original read data from the flash memory device (200).

[0032] In some embodiments, the raw read data from the flash memory device (200) is the same as the interface read data from the flash memory read interface (204). For example, the flash memory read interface (204) may be configured to output hard read data, and the raw read data from the flash memory device (200) is passed through the flash memory read interface (204) without modification.

[0033] Alternatively, in some embodiments, the raw read data from the flash memory device (200) is not the same as the interface read data from the flash memory read interface (204). For example, the flash memory read interface (204) may be configured to output soft interface read data. In some such embodiments, the flash memory read interface (204) does so by performing multiple reads of the flash memory device (200) using different read thresholds to obtain multiple sets of raw read data. The flash memory read interface (204) then uses the multiple sets of raw read data to generate soft interface read data.

[0034] In some embodiments, the flash storage read interface (204) performs additional operations and / or processing on the raw read data to generate the interface read data. For example, the data stored on the flash storage device (200) may be scrambled, and the flash storage read interface (204) may descramble the raw read data to generate the interface read data. This is exemplary only and is not intended to be limiting.

[0035] The flash memory read interface (204) passes the interface read data to the LDPC decoding system (208). Within the LDPC decoding system (208), a copy of the interface read data is stored by a buffer (210). The interface read data is also input to an LLR mapping block (212) that includes a plurality of LLR mapping tables (214a-214b). For simplicity and ease of explanation, the LLR mapping block (212) in this example and the following figure advances through the LLR mapping tables (214a-214b) in a predefined and / or fixed order, which is: first select and use the first LLR mapping table (214a), then the second LLR mapping table (214b), and so on. Thus, the appropriate LLR mapping table is selected based on the number of LDPC decoding attempts or index (at least in this example). In some embodiments, the LLR mapping table is selected based on real-time information or parameters (e.g., information from a previous LDPC decoding attempt that failed). For example, an unusually large number of unsatisfied checks indicates that the next LLR table must be selected to have a smaller value.

[0036] The LLR values ​​are passed from the LLR mapping block (212) to the finite precision LDPC decoder (216). For example, the finite precision LDPC decoder (216) may have or otherwise be configured to input LLR values ​​having 4-bit precision, and the LLR values ​​generated by the LLR mapping block (212) are configured to match that level of bit precision. In this example, for this initial decoding attempt, the LDPC decoder (216) performs up to a maximum number of decoding iterations. If the syndrome is all zero after any decoding iteration, the decoding is declared successful, and the error-corrected read data is output by the LDPC decoding system (208).

[0037] If the LDPC decoder (216) reaches a maximum number of decoding iterations without success, the LDPC decoder (216) is stopped or otherwise interrupted and a new set of LLR values ​​is obtained from the LLR mapping block (212) using a different LLR mapping table (e.g., the next LLR mapping table in a predefined order). When the LLR values ​​are generated a second time or later, the interface read data stored in the buffer (210) is obtained and used. By using the stored read data from the buffer, repeated reads of the flash memory device (200) can be avoided. This is desirable because (repeated) reads of the flash memory device (200) are overwhelmingly more expensive (e.g., in terms of power and latency) than other operations in the system shown here.

[0038] A second set of LLR values ​​(e.g., generated from a second LLR mapping table (214b)) is passed from the LLR mapping block (212) to a finite precision LDPC decoder (216), which (e.g., after being reset) begins decoding using the second set of LLR values. If the finite precision LDPC decoder (216) is again unsuccessful after the maximum number of decoding iterations, a third set of LLR values ​​is generated using a third LLR mapping table and the stored read values, and so on.

[0039] Briefly return to Figure 1 The LLR mapping block (212) is an example of a device or block that performs step 100 (e.g., receiving stored read data from the buffer (210) or interfacing read data from the flash storage read interface (204)), step 102, and step 104. The finite precision LDPC decoder (216) is an example of a device or block that performs step 106.

[0040] In some embodiments, the finite precision LDPC decoder (216) performs iterative message passing (MP), wherein the LDPC decoder switches between two phases: a VN-to-CN phase, during which variable nodes send messages to check nodes along their adjacent edges; and a CN-to-VN phase, during which check nodes send messages to their adjacent variable nodes. For example, in the CN-to-VN message update phase, check node j uses the incoming message and (one or more) check node update rules to calculate and forward the new CN-to-VN. Similarly, in the VN-to-CN message update phase, variable node i processes its incoming message and forwards it according to (one or more) variable node update rules. A quasi-cyclic (QC) structure is desirable because it enables efficient, high-speed software or hardware implementations. In the case of iterative message passing, the decoder inputs LLR values.

[0041] In some embodiments, the finite precision LDPC decoder (216) performs iterative min-sum decoding. Iterative min-sum decoding is a subset of iterative message passing, where the CN update rule includes a minimum value operation as well as a sum operation, hence the "min-sum" name. As with iterative message passing, the min-sum decoder inputs LLR values. It should be noted that the LLR input to the min-sum decoder can be scaled if desired, while the input to other types of LDPC decoders (such as, sum-product decoders) must be precise and cannot be scaled.

[0042] The exemplary LDPC implementations and / or methods described above (eg, iterative MP decoding, min-sum decoding, etc.) are well known, and for the sake of brevity, additional details not directly related to the technique(s) described herein are not described.

[0043] The following figures depict some exemplary LLR mapping tables and their associated benefits.

[0044] Figure 3 is a diagram illustrating an embodiment of an LLR mapping table with 1-bit input and 4-bit output. In some embodiments, Figure 2 The LLR mapping tables (214a-214b) in are implemented as shown. As in the previous examples, the LLR mapping tables (300-302) shown here have a predefined sequence or ordering in which they are used to generate LLR values ​​for the LDPC decoder.

[0045] The first LLR mapping table (300) maps read bit 0 to LLR value 6, and maps read bit 1 to LLR value -6. In this example, the first LLR mapping table (300) of {-6; 6} is selected as the first LLR mapping table because it has the lowest average number of iterations before LDPC decoding is successful (e.g., based on simulation). This is desirable in the long run because fewer decoding iterations means less power consumed and shorter latency considerations.

[0046] If LDPC decoding is unsuccessful using the LLR values ​​generated by using the first LLR mapping table (300), a second set of LLR values ​​is generated by selecting and using a second LLR mapping table (301). The second LLR mapping table (301) maps read bit 0 to LLR value 4 and read bit 1 to LLR value -4.

[0047] The simulations reveal that the second LLR mapping table (301) has the lowest error floor among all the simulated LLR mapping tables, and therefore it is designated as the second LLR mapping table in the sequence. The first LLR mapping table (300) using {-6; 6} is desirable as a first choice because it keeps power and latency low in the long term (and sufficient to decode many or most read data), but if LDPC decoding is unsuccessful with the first LLR mapping table of {-6; 6}, the second LLR mapping table (301) using {-4; 4} is an attractive next choice because it has the lowest error floor (e.g., and therefore has the best chance of successful decoding).

[0048] If the LDPC decoding is still unsuccessful, a third LLR mapping table (302) of {-5; 5} is selected and used to generate a third set of LLR values. For example, the LDPC decoder may be stuck in a trapping set, but the third set of LLR values ​​(which has slightly different values) is sufficient to avoid or "pop out" the trapping set and / or otherwise allow the LDPC decoder to correctly converge on the error-corrected data.

[0049] In this example with 4 bits of precision, the LLR values ​​have a full or maximum range of [-7; 7], but none of the LLR mapping tables (e.g., {-6; 6} (300), {-4; 4} (301), and {-5; 5} (302)) use this full range and / or maximum (possible) magnitude. Configuring the LLR mapping tables (e.g., 300-302) to avoid the maximum (possible) magnitude (7 in this case) can reduce or mitigate certain artifacts that a finite precision LDPC decoder may suffer in some cases. For example, when processing finite precision quantized values ​​(e.g., according to a message passing update rule and / or using a min-sum operation in min-sum decoding), artifacts may occur in some cases that would not occur in a perfect LDPC decoder with infinite precision. These saturation and / or finite precision related artifacts can be mitigated and / or avoided by using an LLR mapping table that produces LLR values ​​that avoid the maximum possible magnitude for a given level of precision (e.g., not generating LLR values ​​with a magnitude of 7 for 4 bits of precision). This in turn improves the performance of the LDPC decoder (eg, better chance of successful decoding).

[0050] As shown herein, in some embodiments, none of the plurality of LLR mapping tables maps to an LLR value having a maximum magnitude associated with limited precision. Figure 3 None of the exemplary LLR mapping tables (300-302) in FIG. 1 maps to an LLR value having a magnitude of 7.

[0051] The following figure illustrates an example of (frame) error rate performance when using different LLR mapping tables.

[0052] Figure 4 is a graph illustrating an embodiment of a frame error rate associated with an LLR mapping table that generates 4-bit precision LLR values ​​for a soft LDPC decoder. In the example shown, the x-axis of the graph shows the residual bit error rate (RBER) (e.g., in the read data), and the y-axis shows the frame error rate (FER) after soft decoding (e.g., input reliability information) by an LDPC decoder having 4-bit precision that decodes 4kB of the read data at a time. Note that the RBER values ​​are arranged in descending order from left to right along the x-axis, so the leftmost group of data points (406) are associated with the decoding results when the read data is at a low SNR level, and the rightmost group of data points (408) are associated with the decoding results when the read data is at a high SNR level.

[0053] The first error performance function (which includes data points 402a and 402b) is associated with a 4-bit precision LLR mapping table of {-6;6} with a code rate of 91.5%. As shown in the graph, at high SNR levels (see, e.g., data point 400b), large LLR magnitudes (e.g., magnitude 6 out of a maximum magnitude of 7) of the {-6;6} LLR mapping table produce some (almost) saturated but erroneous messages that are located in small error-prone substructures that become difficult to correct. This then forms an error floor (410), which is undesirable because the system is unable to utilize better quality read data and is unable to produce better quality results accordingly.

[0054] To mitigate and / or break through the error floor (410), the high LLR magnitude of the {-6; 6} LLR mapping table can be reduced to {-4; 4}. The second function (which includes data points 402a and 402b) shows the corresponding error function of the {-4; 4} LLR mapping table with a code rate of 91.5%. It is noted that the high SNR data point (402b) of the LLR mapping table does not exhibit a significant error floor. With the lower magnitude of the {-4; 4} LLR mapping table, the messages do not get stuck in the error-prone substructure as frequently as with the larger magnitude {-6; 6} LLR mapping table.

[0055] Thus, even at low SNR levels, the {-4;4} LLR mapping table (see data point 402a) has a slightly higher FER than the {-6;6} LLR mapping table (see data point 400a), which tends to decode read data faster (e.g., having a lower or lowest average number of LDPC decoding iterations before decoding success) when evaluated and / or simulated over a range of RBER levels. As described above, this is desirable for power and / or performance reasons, and thus in some embodiments, the {-4;4} LLR mapping table is selected first.

[0056] If the first LLR mapping table is unsuccessful, a third data set (which includes data points 404a and 404b) is associated with using the LLR mapping table of {-4; 4} and the LLR mapping table of {-6; 6} (if necessary). Note that the combined use of these two LLR mapping tables will always produce the lowest error floor among the three examples shown, but for the purpose of first selecting which LLR mapping table to use, those data points (e.g., 404a and 404b) are not relevant and are therefore not considered.

[0057] The following figure describes an example of a process in which an LLR mapping table is selected based on a decoding attempt count.

[0058] Figure 5is a flow chart illustrating an embodiment of a process for selecting an LLR mapping table based at least in part on a decoding attempt count. In some embodiments, Figure 1 Step 102 in uses the process shown here to select an LLR mapping table from the plurality of LLR mapping tables. Figure 2 In the exemplary block diagram shown in , the LLR mapping block ( 212 ) may perform the example processes described herein.

[0059] At 500, a decoding attempt count associated with a finite precision LDPC decoder is received. The count tracks which decoding attempt this is for the LDPC decoder. For example, if the count is 1, this is the first decoding attempt; if the count is 2, this is the second decoding attempt, and so on.

[0060] At 502, in the event that the decoding attempt count is the first attempt (e.g., the count is 1), the LLR mapping table associated with the lowest average number of decoding iterations is selected from the plurality of LLR mapping tables as the selected LLR mapping table. For example, the first LLR mapping table (300) of {-6; 6} may be selected at step 502. As described above, for power and latency reasons, it may be desirable to select and use the LLR mapping table associated with the lowest number of decoding iterations (e.g., before decoding is successful).

[0061] At 504, in the event that the decoding attempt count is the second attempt, the LLR mapping table associated with the lowest error floor is selected from the plurality of LLR mapping tables as the selected LLR mapping table. For example, the second LLR mapping table (301) of {-4; 4} may be selected at step 504. As described above, this mapping may have the best chance of successfully decoding any (interface) read data that remains uncorrected because this mapping has the lowest error floor.

[0062] Briefly return to Figure 2 In some embodiments, the interface read data output by the flash storage read interface (204) includes or contains soft information (e.g., reliability associated with a reported or read value). The following figure depicts an example where the LLR mapping tables (214a-214b) are configured to input 2-bit soft read data and output LLR values ​​with 4-bit precision.

[0063] Figure 6 is a diagram illustrating an embodiment of an LLR mapping table with 2-bit soft input and 4-bit output. In some embodiments, Figure 2The LLR mapping tables (214a-214b) in are implemented as shown. In this example, the read bits on the left are reliability bits, and the read bits on the right are value bits. Reliability 0 indicates that the corresponding read value is unreliable, and reliability 1 indicates that the corresponding read value is reliable.

[0064] The fourth LLR mapping table (600) maps read bit 10 (i.e., a reliable read value of 0) to an LLR value of 6, read bit 00 (i.e., an unreliable read value of 0) to an LLR value of 2, read bit 01 (i.e., an unreliable read value of 1) to an LLR value of -2, and read bit 11 (i.e., a reliable read value of 1) to an LLR value of -6. In other words, the sign (e.g., + or -) of the generated LLR value indicates the value (e.g., a value of 0 or 1), and more reliable information has a greater magnitude (e.g., more severely affects the LDPC decoder). In this example, the fourth LLR mapping table (600) has the lowest average number of decoding iterations.

[0065] As in the previous content, the LLR mapping tables (600-602) shown here have a predefined sequence or ordering in which they are used to generate LLR values ​​for the LDPC decoder.The fourth LLR mapping table (600) is selected first to generate LLR values.

[0066] If LDPC decoding fails (e.g., after reaching the maximum number of iterations), the fifth LLR mapping table (601) is selected and used, which maps read bits 10, 00, 01, and 11 to LLR values ​​4, 2, -2, and -4, respectively. In this example, the fifth LLR mapping table (601) has the lowest error floor.

[0067] If the LDPC decoding fails again, the sixth LLR mapping table (602) is selected and used, which maps the read bits 10, 00, 01 and 11 to LLR values ​​5, 2, -2 and -5 respectively.

[0068] Briefly return to Figure 3 In some embodiments, the system will start using hard (interface) read data first (e.g., at the beginning of the life of an LDPC flash storage system when the flash storage medium (200) has low program and erase counts) because hard (interface) read data is less resource intensive to generate and there are relatively few errors at this point in the life of the system. In other words, when the flash storage medium (200) is new, Figure 3 The hard (interface) read data and hard input LLR mapping tables (300-302) in are sufficient to perform error correction on the stored data.

[0069] In some embodiments, if, after going through all hard input LLR mapping tables (e.g., Figure 3 300-302 in ), if LDPC decoding is unsuccessful, then soft (interface) read data is obtained (e.g., the flash memory read interface is instructed to generate and / or obtain such soft information), and a soft input LLR mapping table (e.g., Figure 6 600-602 in ). The following figure depicts an example of this.

[0070] Figure 7 is a flow chart illustrating an embodiment of a process for selecting a soft input LLR mapping table when all hard input LLR mapping tables have been selected. In some embodiments, Figure 1 Step 102 in includes the process shown here of selecting an LLR mapping table from the plurality of LLR mapping tables. Figure 2 The LLR mapping block (212) in is one example of a block that performs the example processes described herein.

[0071] At 700, it is determined whether all hard input LLR maps in the plurality of LLR maps have been selected. Figure 3 In some cases, the added noise and / or errors may be so large (e.g., the flash storage medium may be very hot and / or at the end of its life, and therefore very "leaky") that all three LDPC decoding attempts fail using the three sets of LLR values ​​generated from the three LLR mapping tables (300-302).

[0072] If at decision fork 702, all hard input LLR mapping tables in the plurality of LLR mapping tables have not been selected 702, then at 706, an unselected hard input LLR mapping table is selected from the plurality of LLR mapping tables as the selected LLR mapping table. For example, if Figure 3 If the second LLR mapping table (301) is selected, the third LLR mapping table (302) will be selected next.

[0073] Briefly return to Figure 2 , the flash memory read interface (204) generating soft interface read data may be processing resource intensive and / or time consuming. Thus, the system may preferably attempt to decode the read data using hard (interface) read data until those LLR mapping tables (and corresponding LDPC decoding attempts) have been exhausted. Only then will the system switch to the more processing resource intensive and / or time consuming hard (interface) read data.

[0074] If at decision fork 702, all hard input LLR mapping tables in the plurality of LLR mapping tables have been selected, then at 704, an unselected soft input LLR mapping table is selected from the plurality of LLR mapping tables as the selected LLR mapping table. Figure 6 , the fourth LLR mapping table (600) will be selected next (eg, because it is associated with the lowest average number of iterations, which is beneficial for power saving and / or latency).

[0075] The exemplary (sub)process shown here involves selecting an LLR mapping table. Outside of this (sub)process, the LLR mapping block (e.g., Figure 2 212) can communicate with the flash storage read interface (e.g., Figure 2 204) to communicate with the selected LLR mapping table to receive the appropriate type of interface read data (e.g., hard or soft interface read data) that matches the selected LLR mapping table. Figure 1 Step 100 in may include: if the LLR mapping block has only hard interface read data, requesting and receiving soft interface read data.

[0076] As described above, there may be a predefined sequence or order in which the LLR mapping tables are selected and used. In some embodiments, the system adaptively changes which LLR mapping table in the sequence is selected and used first (e.g., based on the SNR of the read data, the current state of the flash storage medium, the current state of the LDPC decoder, and / or the temperature of the flash storage medium, etc.). The following figure shows an example of this.

[0077] Fig. 8A is a diagram illustrating an embodiment of a sequence of LLR mapping tables starting with a hard input LLR mapping table when the flash storage medium is in a high SNR state. Figure 2 The flash storage medium (200) in may be at the beginning of its life, the temperature may be low (e.g., less than 30° C.), and / or the LDPC decoder may have infrequent and / or few decoding failures. All of these may be indications that the flash storage medium is in a high SNR state. In this example, if the system determines that the flash storage medium is in such a high SNR state, the system selects the first hard input LLR mapping table (800a) as the initial table (812a), for example when a new read instruction is received and new interface read data is output by the flash storage read interface. In the event of continued LDPC decoder failures, the system will then sequentially traverse the second and third hard input LLR mapping tables (802a and 804a) and then the three soft input LLR mapping tables (806a, 808a, and 810a).

[0078] Figure 8Bis a diagram illustrating an embodiment of a sequence of LLR mapping tables starting with a soft input LLR mapping table when a flash storage medium is in a low SNR state. In this example, the flash storage medium is in a low SNR state. For example, if the flash storage medium is at the end of its life and the flash storage medium is "leaky", this may be a permanent condition. Alternatively, if the flash storage medium is new but hot, this may be a temporary condition. In some embodiments, state information associated with an LDPC decoder and / or output from the LDPC decoder is used to determine whether the flash storage medium is in a low SNR state (e.g., frequent LDPC decoding failures over a certain window of recent attempts and when compared to a threshold failure rate).

[0079] In this example, if the system determines that the flash storage medium is in a low SNR state (e.g., based on one or more of the inputs described below), the system will use the first soft input LLR mapping table (806b) as the initial table (812b), thereby completely bypassing or otherwise skipping the hard input LLR mapping tables (800b, 802b, and 804b), and if the LDPC decoder continues to fail, use the second and third soft input LLR mapping tables (808b and 810b). Although it may be more expensive and / or time-consuming to initially obtain or generate soft interface read data (for use with the soft input LLR mapping tables), the overall read response time can be shorter because the system starts with a stronger error correction capability when using soft inputs (e.g., rather than initially wasting time with less capable hard inputs).

[0080] In some cases, some other LLR mapping is selected as the initial table. For example, if the second hard input LLR mapping table (802b) has a lower error floor than the first hard input LLR mapping table (800b), especially in low SNR conditions, the second hard input LLR mapping table (802b) can be selected as the initial table. This can improve error correction capabilities without the expense of obtaining or generating soft interface read data.

[0081] As shown in this example, in some embodiments, the plurality of LLR mapping tables have a first predefined selection (eg, Figure 8B The method further comprises: determining whether the flash memory device is in a low signal-to-noise ratio (SNR) state; and selecting an LLR mapping table other than the first predefined selection (e.g., Figure 8B The first soft input LLR mapping table (806b) in is used as the initial table.

[0082] In some embodiments, a determination as to whether a flash memory device is in a low SNR state is based at least in part on one or more of: a temperature of the flash memory device, a number of program or erase cycles associated with the flash memory device (i.e., the age of the flash memory device), or failure status information associated with a finite precision LDPC decoder (e.g., the LDPC decoder has failed more than a threshold number of times over a certain window of recent decoding attempts).

[0083] Although the foregoing embodiments have been described in some detail for the purpose of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways to implement the invention. The disclosed embodiments are illustrative rather than restrictive.

Claims

1. A system for performing low density parity check (LDPC) decoding using a plurality of log likelihood ratio (LLR) mapping tables, comprising: LLR map block, where: The LLR mapping block receives read data associated with a flash memory device in a flash memory device state, the flash memory device state comprising one or more of: a low signal-to-noise ratio (SNR) state or a high SNR state; The LLR mapping block selects one of a plurality of LLR mapping tables based at least in part on a flash memory device state and a decode attempt count associated with a finite precision LDPC decoder, wherein selecting one of the plurality of LLR mapping tables comprises determining the flash memory device state based at least in part on one or more of: a temperature of the flash memory device, a number of program or erase cycles associated with the flash memory device, or fail status information associated with the finite precision LDPC decoder; and The LLR mapping block generates a set of one or more LLR values ​​using the read data and the selected LLR mapping table, wherein each LLR value in the set of LLR values ​​has the same finite precision as the finite precision LDPC decoder; and A finite precision LDPC decoder with the same finite precision as the set of LLR values, where: A finite precision LDPC decoder uses the set of LLR values ​​to generate error-corrected read data; and The finite precision LDPC decoder outputs error-corrected read data.

2. The system of claim 1, further comprising a flash memory device.

3. The system according to claim 1, further comprising: Flash memory device; as well as Flash memory read interface, where: The flash memory read interface receives raw read data from the flash memory device; as well as The flash memory read interface uses raw read data from the flash memory device to generate read data associated with the flash memory device that is received by the LLR mapping block, including by generating a value and a reliability. 4 . The system of claim 1 , wherein the flash memory device state comprises one or more of: a low signal-to-noise ratio (SNR) state or a high SNR state.

5. The system of claim 1, wherein a first number of bits associated with the read data is strictly less than a second number of bits associated with the finite precision LDPC decoder.

6. The system of claim 1, wherein selecting one of the plurality of LLR mapping tables comprises advancing through a predefined selection sequence associated with the plurality of LLR mapping tables according to a decoding attempt count associated with a finite precision LDPC decoder.

7. The system of claim 1, wherein the LLR mapping block and the finite precision LDPC decoder are co-located on one or more of: the same application specific integrated circuit (ASIC) or the same field programmable gate array (FPGA).

8. A system for performing low density parity check (LDPC) decoding using a plurality of log likelihood ratio (LLR) mapping tables, comprising: LLR map block, where: The LLR mapping block receives read data associated with a flash memory device in a flash memory device state, the flash memory device state comprising one or more of: a low signal-to-noise ratio (SNR) state or a high SNR state; The LLR mapping block selects one of a plurality of LLR mapping tables based at least in part on a flash memory state and a decoding attempt count associated with a finite precision LDPC decoder, wherein selecting one of the plurality of LLR mapping tables comprises: In case the flash memory device state is a high SNR state, selecting a first LLR mapping table in a predefined selection sequence associated with the plurality of LLR mapping tables as an initial table; and In case the flash memory device state is a low SNR state, selecting a second LLR mapping table as an initial table after a first LLR mapping table in a predefined selection sequence associated with the plurality of LLR mapping tables; and The LLR mapping block generates a set of one or more LLR values ​​using the read data and the selected LLR mapping table, wherein each LLR value in the set of LLR values ​​has the same finite precision as the finite precision LDPC decoder; and A finite precision LDPC decoder with the same finite precision as the set of LLR values, where: A finite precision LDPC decoder uses the set of LLR values ​​to generate error-corrected read data; and The finite precision LDPC decoder outputs error-corrected read data.

9. The system of claim 8, wherein: The first LLR mapping table comprises a hard input LLR mapping table; and The second LLR mapping table includes a soft-input LLR mapping table.

10. A system for performing low density parity check (LDPC) decoding using a plurality of log likelihood ratio (LLR) mapping tables, comprising: LLR map block, where: The LLR mapping block receives read data associated with the flash memory device in the flash memory device state; The LLR mapping block selects one of a plurality of LLR mapping tables based at least in part on a flash memory device state and a decoding attempt count associated with a finite precision LDPC decoder, wherein selecting one of the plurality of LLR mapping tables comprises: determining whether all hard input LLR mapping tables of the plurality of LLR mapping tables have been selected; In a case where it is determined that all hard input LLR mapping tables in the plurality of LLR mapping tables have been selected, selecting an unselected soft input LLR mapping table from the plurality of LLR mapping tables as a selected LLR mapping table; and In a case where it is determined that all hard-input LLR mapping tables in the plurality of LLR mapping tables have not been selected, selecting an unselected hard-input LLR mapping table from the plurality of LLR mapping tables as a selected LLR mapping table; and The LLR mapping block generates a set of one or more LLR values ​​using the read data and the selected LLR mapping table, wherein each LLR value in the set of LLR values ​​has the same finite precision as the finite precision LDPC decoder; and A finite precision LDPC decoder with the same finite precision as the set of LLR values, where: A finite precision LDPC decoder uses the set of LLR values ​​to generate error-corrected read data; and The finite precision LDPC decoder outputs error-corrected read data.

11. A method for performing low density parity check (LDPC) decoding using a plurality of log likelihood ratio (LLR) mapping tables, comprising: At the LLR mapping block, receiving read data associated with a flash memory device in a flash memory device state, the flash memory device state comprising one or more of: a low signal-to-noise ratio (SNR) state or a high SNR state; At the LLR mapping block, selecting one of a plurality of LLR mapping tables based at least in part on a flash memory device state and a decode attempt count associated with a finite precision LDPC decoder, wherein selecting one of the plurality of LLR mapping tables comprises determining the flash memory device state based at least in part on one or more of: a temperature of the flash memory device, a number of program or erase cycles associated with the flash memory device, or fail status information associated with the finite precision LDPC decoder; generating a set of one or more LLR values ​​using the read data and the selected LLR mapping table, wherein each LLR value in the set of LLR values ​​has the same finite precision as a finite precision LDPC decoder; At a finite precision LDPC decoder, using the set of LLR values ​​to generate error-corrected read data; as well as Error-corrected read data is output by the finite precision LDPC decoder.

12. The method according to claim 11, further comprising: At the flash memory read interface, receiving raw read data from the flash memory device; as well as At the flash memory read interface, raw read data from the flash memory device is used to generate read data associated with the flash memory device that is received by the LLR mapping block, including by generating a value and a reliability.

13. The method of claim 11, wherein the flash memory device state comprises one or more of: a low signal-to-noise ratio (SNR) state or a high SNR state.

14. The method of claim 11, wherein a first number of bits associated with the read data is strictly less than a second number of bits associated with a finite precision LDPC decoder.

15. The method of claim 11, wherein selecting one of the plurality of LLR mapping tables comprises advancing through a predefined selection sequence associated with the plurality of LLR mapping tables according to a decoding attempt count associated with a finite precision LDPC decoder.

16. The method of claim 11, wherein the LLR mapping block and the finite precision LDPC decoder are co-located on one or more of: the same application specific integrated circuit (ASIC) or the same field programmable gate array (FPGA).

17. A method for performing low density parity check (LDPC) decoding using a plurality of log likelihood ratio (LLR) mapping tables, comprising: At the LLR mapping block, receiving read data associated with a flash memory device in a flash memory device state, the flash memory device state comprising one or more of: a low signal-to-noise ratio (SNR) state or a high SNR state; At the LLR mapping block, one of a plurality of LLR mapping tables is selected based at least in part on a flash memory state and a decoding attempt count associated with a finite precision LDPC decoder, wherein selecting one of the plurality of LLR mapping tables comprises: In case the flash memory device state is a high SNR state, selecting a first LLR mapping table in a predefined selection sequence associated with the plurality of LLR mapping tables as an initial table; and selecting, in a case where the flash memory device state is a low SNR state, a second LLR mapping table as an initial table after a first LLR mapping table in a predefined selection sequence associated with the plurality of LLR mapping tables; generating a set of one or more LLR values ​​using the read data and the selected LLR mapping table, wherein each LLR value in the set of LLR values ​​has the same finite precision as a finite precision LDPC decoder; At a finite precision LDPC decoder, using the set of LLR values ​​to generate error-corrected read data; and Error-corrected read data is output by the finite precision LDPC decoder.

18. The method of claim 17, wherein: The first LLR mapping table comprises a hard input LLR mapping table; and The second LLR mapping table includes a soft-input LLR mapping table.

19. A method for performing low density parity check (LDPC) decoding using a plurality of log likelihood ratio (LLR) mapping tables, comprising: receiving, at an LLR mapping block, read data associated with a flash memory device in a flash memory device state; At the LLR mapping block, one of a plurality of LLR mapping tables is selected based at least in part on a flash memory state and a decoding attempt count associated with a finite precision LDPC decoder, wherein selecting one of the plurality of LLR mapping tables comprises: determining whether all hard input LLR mapping tables of the plurality of LLR mapping tables have been selected; In a case where it is determined that all hard input LLR mapping tables in the plurality of LLR mapping tables have been selected, selecting an unselected soft input LLR mapping table from the plurality of LLR mapping tables as a selected LLR mapping table; and In a case where it is determined that all hard-input LLR mapping tables in the plurality of LLR mapping tables have not been selected, selecting an unselected hard-input LLR mapping table from the plurality of LLR mapping tables as a selected LLR mapping table; generating a set of one or more LLR values ​​using the read data and the selected LLR mapping table, wherein each LLR value in the set of LLR values ​​has the same finite precision as a finite precision LDPC decoder; At a finite precision LDPC decoder, using the set of LLR values ​​to generate error-corrected read data; and Error-corrected read data is output by the finite precision LDPC decoder.

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