Clock synchronization method and device and 3D interconnection supercomputing system

Abstract

The invention provides a clock synchronization method and device and a 3D interconnection supercomputing system. The method comprises the following steps: constructing a global clock tree through a plurality of blade servers based on the 3D interconnection supercomputing system; setting the same clock module for each blade server; generating a clock signal through the clock module of the primary master clock node of the global clock tree, and distributing the clock signal to the clock modules of the correspondingly connected secondary master clock nodes and the primary slave clock nodes; continuously distributing the received clock signals to the clock modules of the correspondingly connected secondary slave clock nodes through the clock modules of the secondary master clock nodes; communication between any computing nodes of the 3D interconnection supercomputing system is synchronized based on the same clock signal, and the requirements for low delay performance and high clock precision of the 3D interconnection supercomputing system are met.

Description

Technical Field

[0001] The present application relates to the field of clock synchronization communication technology, and in particular to a clock synchronization method, device and 3D interconnected supercomputer system. Background Art

[0002] Supercomputing systems use supercomputer technology, use multiple CPU groups to form multiple computing nodes, and collaborate to solve problems through high-speed Internet networks. Among them, the computing nodes of traditional supercomputing systems are mainly interconnected by Ethernet or IB networks and exchange data through switches. Because switches need to cache received data and then forward it to the corresponding computing nodes when exchanging data, traditional supercomputing systems have large transmission delays.

[0003] With the explosive growth of industrial applications of AI large models and molecular dynamics simulation, the requirements for low communication latency in supercomputing systems are getting higher and higher. The P2P direct 3D interconnection architecture uses a direct connection between computing nodes to form a 3D interconnection network with extremely low IO latency performance. In order to ensure reliable communication between any nodes in this 3D interconnection architecture, a global synchronous clock is required so that all transmissions are referenced to the same source clock.

[0004] However, supercomputer systems using 3D interconnection architecture are mainly aimed at large networks, supporting millions of devices, and their extremely low latency transmission requires high clock accuracy. The clock system widely used in telecommunications networks cannot meet the clock accuracy requirements of supercomputer systems with 3D interconnection architecture. For example, the clock jitter quality is poor, only reaching 50ns; and its architecture is too complex and the cost is too high, making it unsuitable for direct application in supercomputer systems with 3D interconnection architecture. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the purpose of the present application is to provide a clock synchronization method, device and 3D interconnected supercomputer system to solve the problems that the existing clock system cannot meet the low latency performance and high clock accuracy requirements of the 3D interconnected supercomputer system, and the system architecture is complex and the clock synchronization cost is high.

[0006] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a clock synchronization method for synchronizing clock signals between multiple blade servers in a 3D interconnected supercomputer system, the clock synchronization method comprising: grouping multiple blade servers of the 3D interconnected supercomputer system to generate multiple blade server groups, and selecting a blade server group as a first blade server group and the remaining blade server groups as second blade server groups; selecting a blade server of the first blade server group to be configured as a first-level master clock node, and configuring the remaining blade servers of the first blade server group as first-level slave clock nodes; selecting a blade server from each of the second blade server groups to be configured as a second-level master clock node, and configuring the remaining blade servers of each of the second blade server groups as second-level slave clock nodes; connecting each first-level slave clock node and each second-level master clock node to the first-level master clock node, and connecting each second-level slave clock node to the second-level master clock node of the same group, so as to construct a global clock tree; setting a clock module for each blade server, and synchronizing the clock signals of each clock node of the global clock tree through each clock module.

[0007] In some embodiments of the first aspect of the present application, the method of synchronizing the clock signals of each clock node of the global clock tree through each clock module includes: generating a clock signal through the clock module of the first-level master clock node, and distributing it to the clock modules of each correspondingly connected second-level master clock node and the clock modules of each first-level slave clock node; and continuing to distribute the received clock signal to the clock modules of each correspondingly connected second-level slave clock node through the clock module of each second-level master clock node.

[0008] In some embodiments of the first aspect of the present application, a clock input unit is used to receive a clock signal distributed by other clock modules and use it as a first clock signal; a clock source unit is used to generate a new clock signal and use it as a second clock signal; a clock selection unit is connected to the clock source unit and the clock input unit, and is used to select the first clock signal or the second clock signal as a reference clock signal according to the clock node type of the blade server where the current clock module is located; a clock recovery unit is connected to the clock selection unit, and is used to perform clock recovery on the reference clock signal to obtain a working clock signal that is synchronized with the reference clock signal and has low clock jitter; a clock output unit is connected to the clock recovery unit, and is used to distribute the working clock signal to other clock modules.

[0009] In some embodiments of the first aspect of the present application, according to the clock node type of the blade server where the current clock module is located, the method of selecting the first clock signal or the second clock signal as the reference clock signal includes: determining whether the clock node type of the blade server where the current clock module is located is a first-level master clock node; if it is a first-level master clock node, selecting the second clock signal as the reference clock signal; otherwise, selecting the first clock signal as the reference clock signal.

[0010] In some embodiments of the first aspect of the present application, each blade server group is installed in multiple frames of a rack, and the blade servers of the same blade server group are installed in different slots of the same frame; each blade server includes a unique identification code for identifying the physical location of each blade server; wherein the physical location of the blade server includes: the rack, frame and installation slot to which the blade server belongs; through the unique identification code of each blade server, the corresponding blade server can be configured as a clock node of different types.

[0011] In some embodiments of the first aspect of the present application, each secondary master clock node is connected to the primary master clock node via a clock cable; each first-level slave clock node is connected to the primary master clock node via a backplane; and each secondary slave clock node is connected to the secondary master clock node of the same group via a backplane.

[0012] In some embodiments of the first aspect of the present application, the clock cable uses a multi-point low voltage differential signal level standard to transmit the clock signal.

[0013] In some embodiments of the first aspect of the present application, the clock synchronization method also includes: when the first-level master clock node fails, configuring the first-level master clock node as a new second-level master clock node, and configuring the corresponding original first-level slave clock node as a new second-level slave clock node; selecting an original second-level master clock node to be configured as a new first-level master clock node, and configuring the original second-level slave clock node connected to the clock node as a new first-level slave clock node; the remaining original second-level master clock nodes and original second-level slave clock nodes remain unchanged.

[0014] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a clock synchronization device for synchronizing clock signals between multiple blade servers in a 3D interconnected supercomputer system, the clock synchronization device comprising: a clock tree construction module, used to construct a global clock tree based on multiple blade servers of the 3D interconnected supercomputer system; a clock signal synchronization module, connected to the clock tree construction module, used to set a clock module for each blade server, and synchronize the clock signals of each clock node of the global clock tree through each clock module; wherein the construction method of the global clock tree comprises: grouping the multiple blade servers of the 3D interconnected supercomputer system to generate multiple blade server groups, and selecting A blade server group is used as the first blade server group, and the remaining blade server groups are used as the second blade server groups; a blade server of the first blade server group is selected and configured as a first-level master clock node, and the remaining blade servers of the first blade server group are configured as first-level slave clock nodes; a blade server is selected from each of the second blade server groups and configured as a second-level master clock node, and the remaining blade servers of each of the second blade server groups are configured as second-level slave clock nodes; each first-level slave clock node and each second-level master clock node are respectively connected to the first-level master clock node, and each second-level slave clock node is respectively connected to the second-level master clock node of the same group to build a global clock tree.

[0015] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a 3D interconnected supercomputer system, the 3D interconnected supercomputer system comprising: a plurality of blade servers and the clock synchronization device; wherein the blade servers are connected to each other and are respectively connected to the clock synchronization device; the clock synchronization device is used for synchronizing clock signals between the plurality of blade servers, comprising: a clock tree construction module, used for constructing a global clock tree based on the blade servers; wherein the construction method of the global clock tree comprises: grouping the blade servers to generate a plurality of blade server groups, and selecting a blade server group as a first blade server group, and the remaining blade server groups as second blade server groups; selecting a blade server group of the first blade server group; The blade server is configured as a first-level master clock node, and the remaining blade servers of the first blade server group are configured as first-level slave clock nodes; one blade server is selected from each of the second blade server groups and configured as a second-level master clock node, and the remaining blade servers of each second blade server group are configured as second-level slave clock nodes; each first-level slave clock node and each second-level master clock node are respectively connected to the first-level master clock node, and each second-level slave clock node is respectively connected to the second-level master clock node of the same group to build a global clock tree; a clock signal synchronization module is connected to the clock tree construction module, which is used to set a clock module for each blade server, and synchronize the clock signal of each clock node of the global clock tree through each clock module.

[0016] As described above, the present application provides a clock synchronization method, device and 3D interconnected supercomputer system, which constructs a global clock tree based on multiple blade servers of the 3D interconnected supercomputer system; sets the same clock module for each blade server; generates a clock signal through the clock module of the first-level master clock node of the global clock tree, and distributes it to the clock modules of the correspondingly connected second-level master clock nodes and the first-level slave clock nodes; and continues to distribute the received clock signal to the clock modules of the correspondingly connected second-level slave clock nodes through the clock modules of the second-level master clock nodes. The present application has the following beneficial effects: The present application realizes that the communication between any computing nodes of the 3D interconnected supercomputer system is synchronized based on the same clock signal, and meets the low latency performance and high clock accuracy requirements of the 3D interconnected supercomputer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Shown is a flowchart of a clock synchronization method in an embodiment of the present application.

[0018] Figure 2 Shown is a schematic diagram of the structure of a global clock tree in an embodiment of the present application.

[0019] Figure 3 Shown is a structural schematic diagram of a clock module in an embodiment of the present application.

[0020] Figure 4 Shown is a structural schematic diagram of a clock synchronization device in an embodiment of the present application.

[0021] Figure 5 Shown is a schematic diagram of the structure of a 3D interconnected supercomputer system in one embodiment of the present application. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0023] In order to solve the problems in the above-mentioned background technology, the present invention provides a clock synchronization method, device and 3D interconnected supercomputer system, aiming to solve the problems that the existing clock system cannot meet the low latency performance and high clock accuracy requirements of the 3D interconnected supercomputer system, as well as the complex system architecture and high clock synchronization cost, thereby ensuring that the communication between any computing nodes of the 3D interconnected supercomputer system achieves global clock synchronization. At the same time, in order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention are further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0024] like Figure 1 FIG. 2 is a flow chart showing a clock synchronization method in an embodiment of the present invention. The clock synchronization method in this embodiment is used for synchronizing clock signals between multiple blade servers in a 3D interconnected supercomputer system.

[0025] The 3D interconnected supercomputer system includes multiple blade servers, each of which can accommodate multiple computing nodes. By directly connecting several computing nodes for communication and optimizing the layout of each computing node in three-dimensional space, the complexity and workload of communication between computing nodes can be reduced, providing solutions for the challenges of high-dimensional data processing, complex system simulation and large-scale parallel computing, and showing great potential in dealing with efficiency bottlenecks in scientific computing scenarios. The 3D interconnected supercomputer system has extremely low IO latency performance. In order to ensure reliable communication between any nodes, the clock synchronization method described in this embodiment can support each computing node of the 3D interconnected supercomputer system to achieve global synchronization of clocks.

[0026] The clock synchronization method mainly includes the following steps.

[0027] Step S1: grouping a plurality of blade servers of the 3D interconnected supercomputer system to generate a plurality of blade server groups, and selecting a blade server group as a first blade server group and the remaining blade server groups as second blade server groups.

[0028] In one embodiment, each blade server group of the 3D interconnected supercomputer system is installed in multiple frames of a rack, and each blade server of the same blade server group is installed in different slots of the same frame. Each blade server can accommodate multiple computing nodes. Among them, the frame in which the first blade server group is installed is referred to as the first frame, and the frame in which the second blade server group is installed is referred to as the second frame. Take a 3D interconnected supercomputer system with 512 computing nodes as an example: the 3D interconnected supercomputer system includes a total of 64 blade servers, which are respectively installed in 8 frames of two racks; each frame is installed with 8 blade servers and connected through a backplane; each blade server can accommodate 8 nodes.

[0029] In this embodiment, each blade server includes a unique identification code for identifying the physical location of each blade server. Therefore, the corresponding blade server is configured as a clock node of a different type through the unique identification code of each blade server, thereby constructing a global clock tree of the 3D interconnected supercomputer system.

[0030] like Figure 2 As shown, the global clock tree includes: a primary master clock node, multiple primary slave clock nodes, multiple secondary master clock nodes and multiple secondary slave clock nodes. The construction method of the global clock tree includes steps S2 to S4.

[0031] Step S2: Select a blade server of the first blade server group and configure it as a primary master clock node, and configure the remaining blade servers of the first blade server group as primary slave clock nodes.

[0032] In a specific embodiment, a blade server in the first chassis is selected to be configured as a primary master clock node, and the remaining blade servers in the same chassis are configured as primary slave clock nodes.

[0033] Step S3: Select one blade server from each of the second blade server groups and configure it as a secondary master clock node, and configure the remaining blade servers in each of the second blade server groups as secondary slave clock nodes.

[0034] In a specific embodiment, a blade server is selected from each second machine frame and configured as a secondary master clock node, and the remaining blade servers in each second machine frame are configured as secondary slave clock nodes.

[0035] That is, Figure 2 As shown, one blade server is selected in each chassis and configured as a primary master clock node or a secondary master clock node, and the remaining blade servers are correspondingly configured as primary slave clock nodes or secondary slave clock nodes.

[0036] Step S4: Connect each primary slave clock node and each secondary master clock node to the primary master clock node respectively, and connect each secondary slave clock node to the secondary master clock node of the same group respectively, so as to construct a global clock tree.

[0037] In a specific embodiment, each secondary master clock node is connected to the primary master clock node through a clock cable; each primary slave clock node is connected to the primary master clock node through a backplane; each secondary slave clock node is connected to the secondary master clock node of the same group through a backplane. Preferably, the clock cable adopts the multi-point low voltage differential signaling level (MLVDS) standard for clock signal transmission.

[0038] In this embodiment, the present application uses a dedicated clock cable and backplane to transmit the clock signal, which can ensure that the clock jitter performance of the clock signal reaches below picoseconds, thereby meeting the high clock accuracy requirements of the 3D interconnected supercomputing system.

[0039] Step S5: setting a clock module for each blade server, and synchronizing the clock signal of each clock node of the global clock tree through each clock module.

[0040] In one embodiment, if Figure 2 As shown, step S5 includes: generating a clock signal through the clock module of the first-level master clock node, and distributing it to the clock modules of the correspondingly connected second-level master clock nodes and the clock modules of the first-level slave clock nodes; and further distributing the received clock signal to the clock modules of the correspondingly connected second-level slave clock nodes through the clock modules of the second-level master clock nodes.

[0041] In one embodiment, if Figure 3 As shown, each clock module includes: a clock input unit, a clock source unit, a clock selection unit, a clock recovery unit and a clock output unit.

[0042] Specifically, the clock selection unit is connected to the clock source unit and the clock input unit respectively, and the clock selection unit, the clock recovery unit and the clock output unit are connected in sequence. In addition, the clock input unit of the current clock module can be connected to the clock output unit of other clock modules. Figure 3 As shown, the clock input units of the first-level slave clock node and the second-level master clock node are respectively connected to the clock output unit of the first-level master clock node, and the clock input unit of the second-level slave clock node is connected to the clock output unit of its corresponding second-level master clock node.

[0043] The clock input unit is used to receive a clock signal distributed by other clock modules and use it as a first clock signal.

[0044] The clock source unit is used to generate a new clock signal and use it as the second clock signal.

[0045] The clock selection unit is used to select the first clock signal or the second clock signal as the reference clock signal according to the clock node type of the blade server where the current clock module is located. In a specific embodiment, the specific working method of the clock selection unit includes: judging whether the clock node type of the blade server where the current clock module is located is a first-level master clock node; if it is a first-level master clock node, selecting the second clock signal as the reference clock signal; otherwise, selecting the first clock signal as the reference clock signal. That is, the reference clock signal of the first-level master clock node is the clock signal generated by the clock source unit of its own clock module; the reference clock signal of the first-level slave clock node and the second-level master clock node is the clock signal distributed by the received first-level master clock node; the reference clock signal of the second-level slave clock node is the clock signal distributed by the correspondingly connected second-level master clock node.

[0046] The clock recovery unit is used to perform clock recovery on the reference clock signal to obtain a working clock signal that is synchronized with the reference clock signal and has low clock jitter. Due to noise and interference during the transmission process, the clock signal may be unstable or lost. On the one hand, the clock recovery unit can detect the clock quality of the corresponding reference clock signal, and perform noise filtering and anti-interference operations on the reference clock signal; on the other hand, it can monitor the clock state of the reference clock signal, and perform fault diagnosis, alarm and fault handling on it; thereby, the frequency and phase and other parameters of the reference clock signal can be adjusted as needed, providing a working clock signal with high precision, high stability, flexibility and maintainability. In the present application, the working clock signal of each clock module can not only meet the requirements of extremely low latency transmission, but its clock jitter quality can reach 1 picosecond, which can also meet the requirements of clock accuracy.

[0047] The clock output unit is used to distribute the working clock signal to other clock modules.

[0048] In a specific embodiment, if Figure 3 As shown, the method of synchronizing the clock signals of the clock nodes of the global clock tree through the clock modules includes:

[0049] ① Generate a clock signal as the first synchronization clock signal of each clock node through the clock source unit of the clock module of the first-level master clock node, and distribute the first synchronization clock signal to the clock input units of the clock modules of each connected second-level master clock node and each first-level slave clock node through its clock output unit.

[0050] ② The clock selection unit of the clock module of each first-level slave clock node selects the first synchronization clock signal distributed by the first-level master clock node as its own reference clock signal, and obtains a working clock signal that is synchronized with the first synchronization clock signal and has low clock jitter through its clock recovery unit, thereby achieving synchronization with the clock signal of the first-level master clock node.

[0051] ③ The clock selection unit of the clock module of each secondary master clock node selects the first synchronization clock signal distributed by the first master clock node as its own reference clock signal, and obtains a working clock signal that is synchronized with the first synchronization clock signal and has low clock jitter through its clock recovery unit, thereby achieving synchronization with the clock signal of the first master clock node; at the same time, the working clock signal is distributed as the second synchronization clock signal to the clock input unit of the clock module of each correspondingly connected secondary slave clock node.

[0052] ④ The clock selection unit of the clock module of each secondary slave clock node selects the second synchronization clock signal distributed by the secondary master clock node as its own reference clock signal, and obtains a working clock signal that is synchronized with the second synchronization clock signal and has low clock jitter through its clock recovery unit, thereby achieving clock signal synchronization with the secondary master clock node, and finally achieving clock signal synchronization with the primary master clock node.

[0053] In this embodiment, by setting the same clock module for each blade server serving as a clock node, each blade server can be configured as a primary master clock node to provide a source clock signal for synchronization, so that each clock node, i.e., each blade server and the computing nodes therein, are synchronized based on the same source clock signal and meet the low clock jitter requirements.

[0054] In addition, the purpose of the design of the present application is to set the same clock module for each blade server serving as a clock node, and use a bus topology to connect the primary master clock node and the secondary master clock node, so that the primary master clock node and the secondary master clock node can back up each other. When the primary master clock node fails, each clock node can be reconfigured and the global clock tree can be rebuilt, thereby ensuring the robustness of clock synchronization.

[0055] In one embodiment, the clock synchronization method also includes: when the first-level master clock node fails, configuring the first-level master clock node as a new second-level master clock node, and configuring the corresponding original first-level slave clock node as a new second-level slave clock node; selecting an original second-level master clock node to be configured as a new first-level master clock node, and configuring the original second-level slave clock node connected to the clock node as a new first-level slave clock node; the remaining original second-level master clock nodes and original second-level slave clock nodes remain unchanged.

[0056] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first XX and the second XX are only used to distinguish different XXs, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0057] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0058] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0059] like Figure 4 , which shows a schematic diagram of the structure of a clock synchronization device 100 in an embodiment of the present invention. The clock synchronization device 100 is used for clock signal synchronization between multiple blade servers in a 3D interconnected supercomputer system, and includes: a clock tree construction module 101 and a clock signal synchronization module 102.

[0060] Specifically, the clock tree construction module 101 is used to construct a global clock tree based on multiple blade servers of the 3D interconnected supercomputer system. The clock signal synchronization module 102 is connected to the clock tree construction module 101, and is used to set a clock module for each blade server, and synchronize the clock signal of each clock node of the global clock tree through each clock module.

[0061] Among them, the clock tree construction module 101 constructs a global clock tree in the following manner: grouping multiple blade servers of the 3D interconnected supercomputer system to generate multiple blade server groups, and selecting a blade server group as the first blade server group and the remaining blade server groups as the second blade server groups; selecting a blade server of the first blade server group to be configured as a first-level master clock node, and configuring the remaining blade servers of the first blade server group as first-level slave clock nodes; selecting a blade server from each of the second blade server groups to be configured as a second-level master clock node, and configuring the remaining blade servers of each of the second blade server groups as second-level slave clock nodes; connecting each first-level slave clock node and each second-level master clock node to the first-level master clock node, and connecting each second-level slave clock node to the second-level master clock node of the same group, so as to construct a global clock tree.

[0062] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0063] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0064] like Figure 5 , which shows a schematic diagram of the structure of a 3D interconnected supercomputer system in an embodiment of the present invention. The 3D interconnected supercomputer system comprises: a plurality of blade servers 200 and the clock synchronization device 100 described above.

[0065] The blade servers are connected to each other and are respectively connected to the clock synchronization device; the clock synchronization device 100 is used for synchronizing clock signals between multiple blade servers 200, including:

[0066] The clock tree construction module 101 is used to construct a global clock tree based on each blade server 200; wherein the construction method of the global clock tree includes: grouping each blade server 200 to generate multiple blade server groups, and selecting a blade server group as the first blade server group, and the remaining blade server groups as the second blade server groups; selecting a blade server 200 of the first blade server group to be configured as a first-level master clock node, and configuring the remaining blade servers 200 of the first blade server group as first-level slave clock nodes; selecting a blade server 200 from each of the second blade server groups to be configured as a second-level master clock node, and configuring the remaining blade servers 200 of each of the second blade server groups as second-level slave clock nodes; connecting each first-level slave clock node and each second-level master clock node to the first-level master clock node, and connecting each second-level slave clock node to the second-level master clock node of the same group, so as to construct a global clock tree;

[0067] The clock signal synchronization module 102 is connected to the clock tree construction module 101 and is used to set a clock module for each blade server 200 and synchronize the clock signal of each clock node of the global clock tree through each clock module.

[0068] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0069] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0070] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0071] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0072] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0073] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0074] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media integrations. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs), etc.).

[0075] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0076] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0077] In summary, the present application provides a clock synchronization method, device and 3D interconnected supercomputer system, which constructs a global clock tree by multiple blade servers based on the 3D interconnected supercomputer system; sets the same clock module for each blade server; generates a clock signal through the clock module of the first-level master clock node of the global clock tree, and distributes it to the correspondingly connected second-level master clock nodes and the clock modules of each first-level slave clock node; the clock module of each second-level master clock node continues to distribute the received clock signal to the clock modules of each correspondingly connected second-level slave clock nodes; the present application realizes that the communication between any computing nodes of the 3D interconnected supercomputer system is synchronized based on the same clock signal, and meets the low latency performance and high clock accuracy requirements of the 3D interconnected supercomputer system.

[0078] Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0079] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A clock synchronization method for synchronizing clock signals between multiple blade servers in a 3D interconnected supercomputer system, characterized in that: include: Grouping a plurality of blade servers of the 3D interconnected supercomputer system to generate a plurality of blade server groups, and selecting a blade server group as a first blade server group and the remaining blade server groups as second blade server groups; Selecting a blade server of the first blade server group to be configured as a primary master clock node, and configuring the remaining blade servers of the first blade server group to be primary slave clock nodes; Selecting one blade server from each of the second blade server groups to be configured as a secondary master clock node, and configuring the remaining blade servers in each of the second blade server groups to be secondary slave clock nodes; Connecting each primary slave clock node and each secondary master clock node to the primary master clock node respectively, and connecting each secondary slave clock node to the secondary master clock node of the same group respectively, so as to construct a global clock tree; A clock module is provided for each blade server, and clock signals of each clock node of the global clock tree are synchronized through each clock module.

2. The clock synchronization method according to claim 1, characterized in that: The method of synchronizing the clock signals of the clock nodes of the global clock tree by the clock modules includes: Generate a clock signal through the clock module of the primary master clock node, and distribute it to the clock modules of the correspondingly connected secondary master clock nodes and the clock modules of the primary slave clock nodes; The clock module of each secondary master clock node further distributes the received clock signal to the clock modules of each correspondingly connected secondary slave clock node.

3. The clock synchronization method according to claim 2, characterized in that: Each clock module includes: A clock input unit, used to receive a clock signal distributed by other clock modules and use it as a first clock signal; A clock source unit, used for generating a new clock signal and using it as a second clock signal; A clock selection unit, connected to the clock source unit and the clock input unit, and configured to select the first clock signal or the second clock signal as a reference clock signal according to a clock node type of the blade server where the current clock module is located; A clock recovery unit, connected to the clock selection unit, for performing clock recovery on the reference clock signal to obtain a working clock signal that is synchronized with the reference clock signal and has low clock jitter; A clock output unit is connected to the clock recovery unit and is used to distribute the working clock signal to other clock modules.

4. The clock synchronization method according to claim 3, characterized in that: According to the clock node type of the blade server where the current clock module is located, the method of selecting the first clock signal or the second clock signal as the reference clock signal includes: Determine whether the clock node type of the blade server where the current clock module is located is a primary master clock node; If it is a primary master clock node, the second clock signal is selected as the reference clock signal; otherwise, the first clock signal is selected as the reference clock signal.

5. The clock synchronization method according to claim 1, characterized in that: Each blade server group is installed in multiple frames of the rack, and each blade server of the same blade server group is installed in different slots of the same frame; Each blade server includes a unique identification code for identifying the physical location of each blade server; The physical location of the blade server includes: the rack to which the blade server belongs, the frame and the slot where it is installed; through the unique identification code of each blade server, the corresponding blade server can be configured as a clock node of different types.

6. The clock synchronization method according to claim 1, characterized in that: Each secondary master clock node is connected to the primary master clock node through a clock cable; each primary slave clock node is connected to the primary master clock node through a backplane; Each secondary slave clock node is connected to a secondary master clock node of the same group through a backplane.

7. The clock synchronization method according to claim 6, characterized in that: The clock cable uses a multi-point low voltage differential signal level standard to transmit clock signals.

8. The clock synchronization method according to claim 1, characterized in that: The clock synchronization method further comprises: When the primary master clock node fails, the primary master clock node is configured as a new secondary master clock node, and the corresponding original primary slave clock node is configured as a new secondary slave clock node; Select an original secondary master clock node to be configured as a new primary master clock node, and configure an original secondary slave clock node connected to the clock node as a new primary slave clock node; The remaining original secondary master clock nodes and original secondary slave clock nodes remain unchanged.

9. A clock synchronization device for synchronizing clock signals between multiple blade servers in a 3D interconnected supercomputer system, characterized in that: include: A clock tree construction module, used to construct a global clock tree based on multiple blade servers of the 3D interconnected supercomputing system; A clock signal synchronization module, connected to the clock tree construction module, used to set a clock module for each blade server, and synchronize the clock signal of each clock node of the global clock tree through each clock module; Among them, the method of constructing the global clock tree includes: grouping multiple blade servers of the 3D interconnected supercomputer system to generate multiple blade server groups, and selecting a blade server group as the first blade server group, and the remaining blade server groups as the second blade server groups; selecting a blade server of the first blade server group to be configured as a first-level master clock node, and configuring the remaining blade servers of the first blade server group as first-level slave clock nodes; selecting a blade server from each of the second blade server groups to be configured as a second-level master clock node, and configuring the remaining blade servers of each of the second blade server groups as second-level slave clock nodes; connecting each first-level slave clock node and each second-level master clock node to the first-level master clock node, and connecting each second-level slave clock node to the second-level master clock node of the same group, so as to construct a global clock tree.

10. A 3D interconnected supercomputer system, characterized in that: include: A plurality of blade servers and a clock synchronization device as claimed in claim 9; Wherein, each blade server is connected to each other and is respectively connected to the clock synchronization device; The clock synchronization device is used for synchronizing clock signals between multiple blade servers, and includes: A clock tree construction module, used to construct a global clock tree based on each blade server; wherein the construction method of the global clock tree includes: grouping each blade server to generate multiple blade server groups, and selecting a blade server group as the first blade server group, and the remaining blade server groups as the second blade server groups; selecting a blade server of the first blade server group to be configured as a primary master clock node, and configuring the remaining blade servers of the first blade server group as primary slave clock nodes; selecting a blade server from each of the second blade server groups to be configured as a secondary master clock node, and configuring the remaining blade servers of each of the second blade server groups as secondary slave clock nodes; connecting each primary slave clock node and each secondary master clock node to the primary master clock node, and connecting each secondary slave clock node to the secondary master clock node of the same group, so as to construct a global clock tree; The clock signal synchronization module is connected to the clock tree construction module and is used to set a clock module for each blade server and synchronize the clock signal of each clock node of the global clock tree through each clock module.

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