Custom frequency offset compensation method and system based on CSS modulation network

Abstract

The invention discloses a custom frequency offset compensation method and system based on a CSS modulation network. The method comprises the following steps: initialization setting: customizing redundant bits, and selecting a spreading factor (SF), a bandwidth (BW) and a coding rate (CR); constructing a data packet and transmitting the data packet after interleaving and coding, inserting the user-defined redundant bits in the process of coding the data packet, setting the Header of the data packet to be 12 bits, the first to eighth bits being used for indicating the length of the data packet, the ninth to eleventh bits being used for indicating the selected coding rate, and the twelfth bit being a parity check bit; and at a receiving end, calculating the offset of each symbol in each data packet by using the user-defined redundant bit as a reference signal, and further performing symbol-level correction and supplement on the offset of the data packet. According to the method, the problem of severe frequency deviation possibly occurring in a severe environment of the CSS modulation network is solved, and the stability of network performance is ensured.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and more specifically, to a custom frequency offset compensation method and system based on a CSS modulation network. Background Art

[0002] CSS (Chirp Spread Spectrum modulation) modulation is a wireless communication technology that transmits data based on linear frequency modulation signals. By mapping information into frequency signals that change linearly over time, CSS can use Up Chirp with increasing frequency or Down Chirp with decreasing frequency for data transmission. The main advantages of CSS modulation are its strong anti-interference ability and long-distance communication performance. This unique technology enables signals to propagate over a larger frequency range, ensuring stable communication effects in environments with high noise or severe multipath interference. In addition, CSS modulation has low power consumption and is particularly suitable for low-power devices that need to run for a long time. In low-power wide area networks (LPWAN) of the Internet of Things, such as LoRa and ChirpIoT TM CSS modulation is widely used. Relying on its characteristics, it realizes long-distance and low-power data transmission, which is suitable for scenarios such as remote sensor networks, smart cities and agricultural monitoring. The flexibility and robustness of CSS modulation also make it widely used in military communications, satellite communications, industrial automation and other fields with high requirements for reliability and anti-interference. However, in extreme low temperature environments (such as below 0°C), the frequency offset is significantly increased by the rate of temperature change, which in turn affects the communication quality. Therefore, designing a robust frequency offset compensation algorithm has become one of the key issues in current research.

[0003] In the prior art, the frequency offset is usually estimated based on the unique structure of the CSS modulation network. The structure of its data packet is divided into three main parts, namely the preamble, the frame start flag and the data part. Since the preamble is composed of the Basic Up Chirp, after multiplying it with the Basic Down Chirp of the SFD, the signal will be converted into a single-frequency signal, so that the energy of the signal will be concentrated on a single frequency. By performing FFT (Fast Fourier Transform) on the signal, the signal can be converted from the time domain to the frequency domain. In theory, the result of multiplying the Basic Up Chirp and the Basic Down Chirp will have a peak at the 0 frequency. By measuring the offset of the peak, the frequency offset can be estimated.

[0004] After analysis, the above scheme of estimating the frequency offset of the overall signal through the preamble is only applicable when the frequency offset is relatively stable. If the frequency offset of the signal changes drastically, the frequency offset of each Chirp will no longer be consistent, which makes the method of simply relying on the preamble for frequency offset estimation no longer effective. In this case, a more complex algorithm is needed to process the frequency offset estimation. Summary of the invention

[0005] The object of the present invention is to overcome the above-mentioned defects of the prior art and provide a method and system for user-defined frequency offset compensation based on a CSS modulation network.

[0006] According to a first aspect of the present invention, a method for self-defined frequency offset compensation based on a CSS modulation network is provided. The method comprises the following steps:

[0007] Initialization settings, including customizing redundant bits, selecting spreading factor SF, bandwidth BW and coding rate CR;

[0008] Constructing a data packet and transmitting it after interleaving encoding, wherein the custom redundant bit is inserted in the process of encoding the data packet, the header of the data packet is set to 12 bits, the 1st to 8th bits are used to indicate the length of the data packet, the 9th to 11th bits are used to indicate the selected coding rate, and the 12th bit is a parity check bit;

[0009] At the receiving end, the custom redundant bit is used as a reference signal to calculate the offset of each symbol in each data packet, and then the offset of the data packet is corrected and supplemented at the symbol level.

[0010] According to a second aspect of the present invention, a custom frequency offset compensation system based on a CSS modulation network is provided. The system includes a transmitting end and a receiving end, wherein:

[0011] The sending end performs: initialization settings, including customizing redundant bits, selecting spreading factor SF, bandwidth BW and coding rate CR;

[0012] Constructing a data packet and transmitting it after interleaving encoding, wherein the custom redundant bit is inserted in the process of encoding the data packet, the header of the data packet is set to 12 bits, the 1st to 8th bits are used to indicate the length of the data packet, the 9th to 11th bits are used to indicate the selected coding rate, and the 12th bit is a parity check bit;

[0013] Execution at the receiving end: using the custom redundant bit as a reference signal, calculating the offset of each symbol in each data packet, and then performing symbol-level correction and supplement on the offset of the data packet.

[0014] Compared with the prior art, the advantage of the present invention is that, in order to address the problem that the frequency offset of the CSS modulation network is unstable and the amplitude is too large in extreme environments, the present invention designs a frequency offset compensation method based on the CSS modulation network, which can accurately calculate the frequency offset of each Chirp, ensuring that the node can be correctly decoded even in extreme environments, thereby ensuring the stability of network performance.

[0015] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0017] Figure 1 is a schematic diagram of a frame structure based on a CSS modulation network according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the structure of a Header packet of a custom frequency offset compensation method according to an embodiment of the present invention;

[0019] Figure 3 is a process schematic diagram of a custom frequency offset compensation method according to an embodiment of the present invention;

[0020] Figure 4 is a flow chart of a custom frequency offset compensation method based on a CSS modulation network according to an embodiment of the present invention;

[0021] Figure 5 The figure is a schematic diagram of the overall process of a custom frequency offset compensation method based on a CSS modulation network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0023] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0024] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0025] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0026] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0027] In the following, the existing frame structure based on the CSS modulation network, the frame structure of the custom frequency offset compensation solution designed by the present invention, and the application process of the present invention will be introduced respectively.

[0028] 1. Frame structure based on CSS modulation network

[0029] First, the unique frame structure of the CSS modulation network is introduced, such as Figure 1 As shown in the figure, the structure of its data packet is divided into three main parts: preamble, start frame delimiter (SFD) and data. The preamble consists of 6 to 65535 Basic Up Chirps and two chirps that identify the network ID. This is followed by 2.25 Basic Down Chirps, which serve as the start frame flag (SFD) and mark the beginning of the data part. The data part contains the header, payload and CRC check. The header consists of the first 8 chirps, occupying 20 bits, which are specifically used to represent the following information: Payload length (8 bits), data coding rate CR (3 bits), CRC check flag (1 bit), and CRC check of the header field (8 bits). The remaining chirps constitute the Payload part, and the last 2 bytes are CRC check, which is used to verify the integrity of the entire data packet.

[0030] In order to enhance the stability of data packets, the CSS modulation network introduces a low data rate optimization mode (LDR), which adds 2 redundant bits after the valid data bits so that the receiver can track the signal more accurately, thereby reducing the bit error rate. However, through a large number of experiments in extreme environments (below 0 degrees Celsius), it is found that the offset of a symbol can reach more than 8, and 2 bits of redundancy can only correct up to 4 (2 2 Therefore, in order to better cope with the frequency offset in different environments, the present invention proposes an adaptive frequency offset compensation method based on a CSS modulation network.

[0031] 2. The frame structure of the custom frequency offset compensation solution designed by the present invention.

[0032] In the custom mode, the present invention redesigns the Header structure of the CSS modulation network, see Figure 2 As shown in the figure, the original 20 bits are reduced to 12 bits, and the 8-bit CRC check is removed. In the designed 12-bit packet structure, the first 8 bits are the packet length (0-255), bits 9-11 are CR (coding rate), which can be selected as 4 / 5, 4 / 6, 4 / 7, 4 / 8, and the 12th bit is the parity bit. For the new packet header design, in the subsequent encoding process, redundant bits x are introduced and a coding rate of 4 / 8 is used, which is sufficient to ensure the correctness of the data packet, so only a simple parity check is needed for data error detection. The redundant bit x satisfies the following formula:

[0033]

[0034] Wherein, SF represents the spreading factor. According to formula (1), the corresponding relationship between the spreading factor and the redundant bit x can be calculated, see Table 1.

[0035] In another embodiment, the correspondence between the commonly used spreading factors SF and the redundant bits x may also be pre-stored to improve the calculation efficiency.

[0036] For example, when the spreading factor (SF) is 7, the redundant bit x can be set to a maximum value of 4, thereby protecting a maximum of 16 (2 4 ) frequency deviations, making this design sufficient to cope with frequency deviations in harsh environments and ensure the reliability of data transmission.

[0037] Table 1: Correspondence between spreading factor and custom redundant bits

[0038] SF Customize the maximum value of redundant bits (bit) Protection offset bit 7 4 15 8 5 31 9 6 63 10 7 127 11 8 255 1 2 9 511

[0039] Specifically, the packet length N pkl It can be obtained by the following formula (2), rounded up:

[0040]

[0041] Among them, PL is the number of bytes in the data packet; IH is the packet header flag, 0 means the packet header mode is not enabled, 1 means the packet header mode is enabled; CR is the coding rate, which can be 4 / 5, 4 / 6, 4 / 7 or 4 / 8; SF is the spreading factor; x is the redundant bit set in the custom mode.

[0042] It is worth noting that since the first 8 symbols are fixedly coded at a rate of 4 / 8, the minimum packet length is 8. Under this design, subsequent data packets except the header part use a custom CR coding rate. In order to further ensure the accuracy of the data packets, the CRC mode can be enabled by default, that is, the parity check method is used.

[0043] 3. Customized Frequency Offset Compensation Scheme of the Present Invention

[0044] Figure 3 The figure is a schematic diagram of the overall custom frequency offset compensation algorithm. The first 8 symbols of the structure form a fixed part, namely the first interleaved block. The length of the subsequent interleaved blocks is determined by the selected coding rate (CR). This design allows each symbol to protect a maximum of 2 x -1 bit offset. It helps to ensure the accuracy of data in the early stage of data packet transmission, thereby effectively reducing the error rate and improving the reliability of transmission.

[0045] In summary, the purpose of the present invention is to solve the problem of severe frequency offset that may be caused by CSS modulation network in harsh environment (below zero degrees Celsius). In this case, the traditional method of correcting frequency offset by multiplying the Basic Up Chirp and Basic Down Chirp in the preamble and SFD will no longer be effective. In order to solve this problem, the present invention adds a customized x-bit redundancy to compensate and correct the frequency offset in harsh environment, thereby ensuring the communication correctness of the CSS modulation network and guaranteeing the performance of the network.

[0046] Specifically, combined Figure 4 and Figure 5 As shown, for actual scenarios, the adaptive frequency offset compensation method based on the CSS modulation network provided by the present invention includes:

[0047] Step S1, the transmitting end performs initialization settings, including defining x redundant bits, selecting a spreading factor and a coding rate.

[0048] First, the CSS modulation network is initialized, including customizing x-bit redundancy, selecting spreading factor (SF), bandwidth (BW), coding rate (CR), transmission power and other parameters. Since the header structure is fixed to 12 bits, when the spreading factor is selected as 7, the maximum value of x is 4, which must meet the conditions of formula (1). When the spreading factor ranges from 7 to 12, the maximum value of x will vary according to different spreading factors, ranging from 4 to 9.

[0049] Step S2: The sending end constructs a data packet and inserts x redundant bits during the encoding process, and then transmits it to the receiving end.

[0050] When constructing the header, first calculate the length of the data packet using formula (2) and fill it into the first 8 bits of the header. Then, fill it into the 9th to 11th bits of the header according to the selected coding rate. Finally, perform a parity check on the first 11 bits of data, and fill the check result into the 12th bit, thus completing a complete header structure. This design ensures the integrity and accuracy of the data packet.

[0051] Furthermore, the transmitting end performs interleaving encoding and other processes on the constructed data packet and transmits it to the receiving end. The specific transmission process of the signal is not described in detail in the present invention. In the interleaving process, the size of each interleaving block is 4 / CR*(SF), of which 4 / CR*x bits are redundant bits added to compensate for severe frequency offsets, which are usually set to 0. Therefore, in the standard data packet, it can be seen that x bits of valid data in each symbol are 0 (that is, by setting x bits of redundant bits to 0 as reference signals), which can be used as reference signals.

[0052] Step S3: The receiving end calculates the offset of each symbol and performs frequency offset compensation according to the value of the x redundant bits of each symbol in the received signal.

[0053] For the receiving end, by comparing the actual received data packet signal with the reference signal, the offset of each symbol in each data packet can be accurately calculated, so as to make symbol-level corrections and supplements to the offset of the data packet. For example, in the received signal, if the value of the last x bits of a symbol is 7, it means that the symbol differs from the known reference signal by 7 units. The difference of these 7 units is exactly the frequency offset of the symbol. Therefore, in order to ensure the accuracy of the signal, the received signal needs to be compensated for the 7-bit offset.

[0054] Accordingly, the present invention also provides a custom frequency offset compensation system based on a CSS modulation network, which is used to implement one or more aspects of the above method. For example, the system includes a transmitting end and a receiving end, wherein: the transmitting end performs: initialization settings, including custom redundant bits, selection of a spreading factor SF, a bandwidth BW, and a coding rate CR; constructs a data packet and transmits it after interleaving coding, wherein the custom redundant bits are inserted in the process of encoding the data packet, and the header of the data packet is set to 12 bits, the 1st to 8th bits are used to indicate the length of the data packet, the 9th to 11th bits are used to indicate the selected coding rate, and the 12th bit is a parity check bit; at the receiving end, the following is performed: using the custom redundant bits as a reference signal, calculating the offset of each symbol in each data packet, and then performing symbol-level correction and supplementation on the offset of the data packet.

[0055] In summary, the present invention designs a unique adaptive frequency offset compensation method by adding custom x-bit redundancy, and significantly improves the reliability of the CSS modulation network and the accuracy of data transmission by adding redundant bits in harsh environments, ensuring stable communication in various environments.

[0056] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0057] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0058] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0059] The computer program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, Python, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present invention.

[0060] Various aspects of the present invention are described herein with reference to the flow charts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flow chart and / or block diagram and the combination of each box in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0061] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0062] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0063] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a part of a module, a program segment or an instruction, and a part of the module, a program segment or an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that it is equivalent to implement it by hardware, implement it by software, and implement it by combining software and hardware.

[0064] Embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present invention is defined by the appended claims.

Claims

1. A custom frequency offset compensation method based on a CSS modulation network, comprising the following steps: Initialization settings, including customizing redundant bits, selecting spreading factor SF, bandwidth BW and coding rate CR; Constructing a data packet and transmitting it after interleaving encoding, wherein the custom redundant bit is inserted in the process of encoding the data packet, the header of the data packet is set to 12 bits, the 1st to 8th bits are used to indicate the length of the data packet, the 9th to 11th bits are used to indicate the selected coding rate, and the 12th bit is a parity check bit; At the receiving end, the custom redundant bit is used as a reference signal to calculate the offset of each symbol in each data packet, and then the offset of the data packet is corrected and supplemented at the symbol level.

2. The method according to claim 1, characterized in that: The custom redundant bits satisfy the following formula: Wherein, SF represents the spreading factor, and x represents the custom redundant bit.

3. The method according to claim 1, characterized in that The length N of the constructed data packet is calculated according to the following formula: pkl , and round up: Among them, PL is the number of bytes in the data packet; IH is the header flag bit, 0 means the header mode is not enabled, 1 means the header mode is enabled; CR is the coding rate; x is the custom redundant bit.

4. The method according to claim 3, characterized in that The coding rate CR takes a value of 4 / 5, 4 / 6, 4 / 7 or 4 / 8.

5. The method according to claim 1, characterized in that: The maximum value of the custom redundant bit x varies according to different spreading factors, and ranges from 4 to 9.

6. The method according to claim 1, characterized in that The CSS modulation network is a low power wide area network of the Internet of Things.

7. The method according to claim 6, characterized in that The low-power wide area network includes LoRa network and ChirpIoT TM network.

8. The method according to claim 1, characterized in that For the constructed data packet, the first 8 symbols are fixedly coded at a rate of 4 / 8.

9. A custom frequency offset compensation system based on a CSS modulation network, comprising a transmitting end and a receiving end, wherein: The sending end performs: initialization settings, including customizing redundant bits, selecting spreading factor SF, bandwidth BW and coding rate CR; Constructing a data packet and transmitting it after interleaving encoding, wherein the custom redundant bit is inserted in the process of encoding the data packet, the header of the data packet is set to 12 bits, the 1st to 8th bits are used to indicate the length of the data packet, the 9th to 11th bits are used to indicate the selected coding rate, and the 12th bit is a parity check bit; Execution at the receiving end: using the custom redundant bit as a reference signal, calculating the offset of each symbol in each data packet, and then performing symbol-level correction and supplement on the offset of the data packet.

10. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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