Memory device and method of manufacturing the same

Abstract

The invention relates to a memory device and a manufacturing method thereof. A memory device may include a stacked structure comprised of first material layers and second material layers alternately stacked. The stack structure also includes a channel layer inside the stack structure. The channel layer may include a first sub-channel layer, a liner layer formed along an inner wall of the first sub-channel layer, and a second sub-channel layer formed along an inner wall of the liner layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0084014 filed on June 29, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a memory device and a method of manufacturing the memory device, and more particularly, the present disclosure relates to a memory device including a cell plug extending in a vertical direction and a method of manufacturing the memory device. Background Art

[0004] The memory device may include a nonvolatile memory device in which stored data remains intact even if power is interrupted. According to the structure in which the memory cells are arranged, the nonvolatile memory device may be divided into a two-dimensional structure and a three-dimensional structure. The memory cells of the nonvolatile memory device having a two-dimensional structure may be arranged in a single layer above a substrate, and the memory cells of the nonvolatile memory device having a three-dimensional structure may be stacked in a vertical direction above a substrate. Since the integration of the nonvolatile memory device having a three-dimensional structure is higher than that of the nonvolatile memory device having a two-dimensional structure, electronic devices using the nonvolatile memory device having a three-dimensional structure have been increasingly used recently. Summary of the invention

[0005] Embodiments provide a memory device and a method of manufacturing the same, which can improve the operational reliability of the memory device.

[0006] According to one aspect of the present disclosure, a memory device is provided, comprising: a stacked structure; and a channel layer inside the stacked structure, wherein the channel layer comprises: a first sub-channel layer; a liner layer formed along an inner wall of the first sub-channel layer; and a second sub-channel layer formed along an inner wall of the liner layer.

[0007] According to another aspect of the present disclosure, a method for manufacturing a memory device is provided, the method comprising: forming a stack structure in which a first material layer and a second material layer are alternately stacked; forming an opening inside the stack structure; forming a first sub-channel layer in the opening; forming a lining layer along an inner wall of the first sub-channel layer; and forming a second sub-channel layer along an inner wall of the lining layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be described more fully below with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the example embodiments to those skilled in the art.

[0009] In the accompanying drawings, dimensions may be exaggerated for ease of illustration. It should be understood that when an element is referred to as being "between two elements," the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0010] Figure 1 is a block diagram illustrating functional elements of a memory device according to one embodiment of the present disclosure.

[0011] Figure 2 is a circuit diagram showing components included in a memory device according to one embodiment of the present disclosure.

[0012] Figure 3A and Figure 3B is a vertical cross-sectional view showing the structure of a memory device according to one embodiment of the present disclosure.

[0013] 4A to 4H is a view showing steps of a method of manufacturing a memory device according to an embodiment of the present disclosure. 4A to 4H It also shows the features described in the claims, including Figure 3A and Figure 3B The inner and outer walls of the memory device components shown in FIG. 1 , which walls are hereinafter referred to as Figure 3A and Figure 3B Described as shown in .

[0014] Figure 5A and Figure 5B is a vertical cross-sectional view illustrating a cross section of a memory device including a cell plug according to one embodiment of the present disclosure.

[0015] Figure 6 is a diagram showing a memory card system to which the memory device of the present disclosure is applied.

[0016] Figure 7 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0017] The specific structural or functional descriptions disclosed herein are only used to illustrate embodiments of the concepts according to the present disclosure. Embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0019] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0020] refer to Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0021] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly connected to the first to i-th memory blocks BLK1 to BLKi.

[0022] The first to i-th memory blocks BLK1 to BLKi may be formed in a three-dimensional structure. The memory block having the three-dimensional structure may include memory cells stacked in a vertical direction over a substrate.

[0023] The memory cell can store one bit or two bits or more of data according to the programming method. For example, the method of storing one bit of data in one memory cell is called a single-level cell (SLC) method, and the method of storing two bits of data in one memory cell is called a multi-level cell (MLC) method. The method of storing three bits of data in one memory cell is called a triple-level cell (TLC) method, and the method of storing four bits of data in one memory cell is called a quad-level cell (QLC) method. In addition, five or more bits of data can be stored in one memory cell.

[0024] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0025] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 is configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0026] The programming voltage is a voltage applied to a selected word line among word lines WL in a programming operation, and can be used to increase the threshold voltage of a memory cell connected to the selected word line. The on-voltage can be applied to the drain selection line DSL or the source selection line SSL, and is used to turn on the drain selection transistor or the source selection transistor. The cut-off voltage can be applied to the drain selection line DSL or the source selection line SSL, and is used to turn off the drain selection transistor or the source selection transistor. For example, the cut-off voltage can be set to 0V. The precharge voltage is a voltage higher than 0V and can be applied to the bit line in a read operation. The verification voltage can be used in a verification operation to determine whether the threshold voltage of the selected memory cell has increased to a target level. The verification voltage can be set to various levels according to the target level and applied to the selected word line.

[0027] In a read operation of a selected memory cell, a read voltage may be applied to a selected word line. For example, the read voltage may be set to various levels according to the programming mode of the selected memory cell. The pass voltage is a voltage applied to an unselected word line in a programming or read operation, and may be used to turn on a memory cell connected to an unselected word line. The erase voltage may be used in an erase operation to erase a memory cell included in a selected memory block, and may be applied to a source line SL.

[0028] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first to i-th memory blocks BLK1 to BLKi through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0029] The page buffer group 140 may include a page buffer (not shown) connected to each of the first to i-th memory blocks BLK1 to BLKi. The page buffer (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi, respectively, through the bit lines BL. In a read operation, the page buffer (not shown) may sense a current or voltage of the bit line BL (which varies according to a threshold voltage of a selected memory cell) and temporarily store the sensed data in response to a page buffer control signal PBSIG.

[0030] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL and transmit an enable signal through the column line. The page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0031] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and transmit data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0032] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation of a memory block selected by the address and output read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation of the selected memory block.

[0033] Figure 2 is a circuit diagram showing components included in a memory device according to one embodiment of the present disclosure.

[0034] refer to Figure 2, the first memory block BLK1 may include a string ST connected between the first bit line to the nth bit line BL1 to BLn and the source line SL. The first bit line to the nth bit line BL1 to BLn extend along the Y direction and are arranged to be spaced apart from each other along the X direction. Therefore, the string ST may also be arranged to be spaced apart from each other along the X and Y directions. For example, the string ST may be connected between the first bit line BL1 and the source line SL, and the string ST may be arranged between the nth bit line BLn and the source line SL. The string ST may extend along the Z direction.

[0035] Any one string ST connected to the n-th bit line BLn among the strings ST will be described as an example The string ST may include a source select transistor SST, first to j-th memory cells MC1 to MCj, and a drain select transistor DST. Figure 2 The first memory block BLK1 shown in FIG. 1 is a diagram schematically showing the structure of a memory block, and therefore, the number of source selection transistors SST, first to jth memory cells MC1 to MCj, and drain selection transistors DST included in the string ST may vary depending on the memory device.

[0036] The gate of the source selection transistor SST included in different strings ST can be connected to the first source selection line or the second source selection line SSL1 or SSL2, the gate of the first to jth memory cells MC1 to MCj included in different strings ST can be connected to the first to jth word lines WL1 to WLj, and the gate of the drain selection transistor DST included in different strings ST can be connected to any one of the first to fourth drain selection lines DSL1 to DSL4.

[0037] The lines connected to the first memory block BLK1 will be described in detail. The source selection transistors SST arranged along the X direction may be connected to the same source selection line, and the source selection transistors SST arranged along the Y direction may be connected to source selection lines isolated from each other. For example, some of the source selection transistors SST arranged along the Y direction may be connected to the first source selection line SSL1, and other source selection transistors of the source selection transistors SST arranged along the Y direction may be connected to the second source selection line SSL2. The second source selection line SSL2 may be a line isolated from the first source selection line SSL1. Therefore, the voltage applied to the first source selection line SSL1 may be equal to or different from the voltage applied to the second source selection line SSL2.

[0038] Memory cells formed in the same layer among the first to j-th memory cells MC1 to MCj may be connected to the same word line. For example, the first memory cell MC1 included in the different strings ST may be commonly connected to the first word line WL1, and the j-th memory cell MCj included in the different strings ST may be commonly connected to the j-th word line WLj. A group of memory cells included in the different strings ST and connected to the same word line may be designated as a page, and programming and reading operations may be performed in units of pages.

[0039] The drain selection transistors DST arranged in the Y direction may be respectively connected to the first to fourth drain selection lines DSL1 to DSL4 isolated from each other. Specifically, the drain selection transistors DST arranged along the X direction may be connected to the same drain selection line, and the drain selection transistors DST arranged along the Y direction may be connected to the first to fourth drain selection lines DSL1 to DSL4 isolated from each other. Since the first to fourth drain selection lines DSL1 to DSL4 are isolated from each other, different voltages may be applied to the first to fourth drain selection lines DSL1 to DSL4.

[0040] Figure 3A and Figure 3B is a vertical cross-sectional view showing the structure of a memory device according to one embodiment of the present disclosure. Figure 3A is a vertical cross-sectional view showing a cross section of a cell plug CP according to the present disclosure. Figure 3B is a plan view showing the layout of cell plugs CP according to the present disclosure.

[0041] refer to Figure 3A , the memory device may include a stacked structure STK. The stacked structure STK may include conductive layers CD and interlayer insulating layers IL that are alternately stacked. The conductive layers CD and the interlayer insulating layers IL may be alternately stacked in the Z direction. For example, the stacked structure STK may be formed by alternately stacking sacrificial layers and interlayer insulating layers IL and replacing the sacrificial layers with conductive layers CD. The conductive layers CD may correspond to Figure 2 The drain selection line DSL1, DSL2, DSL3 or DSL4, the first to j-th word lines WL1 to WLj, and the source selection line SSL1 or SSL2 are shown in FIG.

[0042] The memory device may include a cell plug CP inside the stack structure STK. The cell plug CP may be disposed inside the alternately stacked conductive layers CD and the interlayer insulating layers IL. For example, the stack structure STK may include an opening OP, and the cell plug CP may be formed in the opening OP. The cell plug CP may extend in the Z direction. The cell plug CP may correspond to Figure 2 Each of the strings ST shown in . Figure 2 The first to j-th memory cells MC1 to MCj shown in FIG. 5 may be respectively formed at locations where the cell plugs CP and the conductive layers CD intersect each other.

[0043] refer to Figure 3A and Figure 3B , the cell plug CP may include: a memory layer ML formed along an inner wall IW1 of the opening OP; a channel layer CH formed along an inner wall IW2 of the memory layer ML; and a pillar CO inside the channel layer CH. The pillar CO may be formed inside the channel layer CH and have a pillar shape. The memory layer ML may be formed along an outer wall OW1 of the channel layer CH. For example, the memory layer ML may surround an outer surface of the channel layer CH. The channel layer CH may be formed on an inner wall IW2 of the memory layer ML. The inner wall IW2 of the memory layer ML and the outer wall OW1 of the channel layer CH are in direct contact with each other and are considered to "face" each other herein.

[0044] Each of the memory layer ML, the channel CH, and the pillars CO may extend in the Z direction. Each of the memory layer ML, the channel CH, and the pillars CO may extend through all alternately stacked layers such that the memory layer ML, the channel CH, and the pillars C penetrate the stack structure STK or only penetrate a portion of the stack structure ST.

[0045] Each of the memory layer ML and the channel layer CH may be formed of at least two different materials. For example, each of the memory layer ML and the channel layer CH may be formed of three layers. The column CO may be formed of an insulating layer or a conductive layer.

[0046] The memory layer ML may include a blocking layer BX, a charge trap layer CT, or a tunnel insulating layer TX, or a combination of at least two thereof. The blocking layer BX may be formed along the inner wall IW1 of the opening OP. The charge trap layer CT may be formed along the inner wall IW3 of the blocking layer BX, and the tunnel insulating layer TX may be formed along the inner wall IW4 of the charge trap layer CT. The tunnel insulating layer TX may surround the outer surface OW1 of the channel layer CH. The charge trap layer CT may surround the outer surface of the tunnel insulating layer TX. The blocking layer BX may surround the outer surface of the charge trap layer CT. Each of the blocking layer BX, the charge trap layer CT, and the tunnel insulating layer TX may extend in the Z direction. The blocking layer BX and the tunnel insulating layer TX may be formed of an oxide layer (e.g., silicon oxide) or an oxynitride layer (e.g., a silicon oxynitride layer), or any combination thereof. The charge trap layer CT is a charge storage layer, and may include a nitride layer or a variable resistance material.

[0047] The channel layer CH may include a first sub-channel layer C1, a liner layer LL, and a second sub-channel layer C2. For example, the first sub-channel layer C1 may be formed along the inner wall IW2 of the memory layer ML (e.g., the tunnel insulating layer TX), the liner layer LL may be formed along the inner wall IW5 of the first sub-channel layer C1, and the second sub-channel layer C2 may be formed along the inner wall IW6 of the liner layer LL. In addition, the liner layer LL may be formed on the outer wall OW3 of the second sub-channel layer C2, and the first sub-channel layer C1 may be formed on the outer wall OW2 of the liner layer LL. For example, the liner layer LL may surround the side surface of the second sub-channel layer C2, and the first sub-channel layer C1 may surround the side surface of the liner layer LL. Each of the first sub-channel layer C1, the second sub-channel layer C2, and the liner layer LL may extend in the Z direction. Each of the first sub-channel layer C1, the second sub-channel layer C2, and the liner layer LL may penetrate the stacked structure STK. The first sub-channel layer C1, the second sub-channel layer C2, and the liner layer LL may have pillar shapes, and the pillars have different diameters.

[0048] The first sub-channel layer C1 may include an undoped silicon layer. The undoped silicon layer may be a silicon layer into which any impurities are not doped.

[0049] The first sub-channel layer C1 may have a first width W1. The first sub-channel layer C1 may be formed to be thicker than the liner layer LL or the second sub-channel layer C2. For example, the width of the first sub-channel layer C1 may be between 100 and 200 nm. Within.

[0050] The second sub-channel layer C2 may include a silicon layer doped with a group III element "impurity" such as boron, aluminum, gallium, indium, etc. For example, the second sub-channel layer C2 may include a silicon layer doped with boron (B). The second sub-channel layer C2 formed of silicon doped with a group XIII element (e.g., boron) may include holes as charge carriers.

[0051] The second sub-channel layer C2 may have a second width W2 narrower than the first width W1. The second sub-channel layer C2 may be formed to be thinner than the first sub-channel layer C1, and may be formed to be thicker than the liner layer LL. For example, the width of the second sub-channel layer C2 may be about 1000 Å.

[0052] The liner layer LL may be an insulating layer. For example, the liner layer LL may be an oxide layer, an oxynitride layer, or an oxide layer doped with a metal. The liner layer LL may isolate the first sub-channel layer C1 and the second sub-channel layer C2 from each other between the first sub-channel layer C1 and the second sub-channel layer C2. The liner layer LL may block or interrupt impurities or charge carriers (e.g., holes) included in the second sub-channel layer C2 from leaking into the first sub-channel layer C1.

[0053] The liner layer LL may have a third width W3 narrower than the second width W2. The width of the liner layer LL may be smaller than the width of each of the first sub-channel layer C1 and the second sub-channel layer C2. For example, the width of the liner layer LL may be approximately The liner layer LL may have a thinner thickness than the first and second sub-channel layers C1 and C2 so that the first and second sub-channel layers C1 and C2 are not electrically insulated from each other while being isolated from each other.

[0054] According to the present disclosure, when the channel layer CH includes a first sub-channel layer C1, a liner layer LL, and a second sub-channel layer C2, the number of charge carriers (e.g., holes) included in the channel layer CH can be larger than that of an existing channel layer that does not include the liner layer LL. For example, since the liner layer LL is located on the outer wall of the second sub-channel layer C2 doped with impurities, the concentration of impurities (e.g., boron) doped into the second sub-channel layer C2 can be increased compared to the existing channel layer, and thus the channel layer CH can include a large number of charge carriers (e.g., holes) compared to the existing channel layer. Therefore, according to the present disclosure, the original threshold voltage (VVT) of the memory cell (e.g., MC1 to MCj) can be increased, the diffusion of charge carriers (e.g., holes) can be reduced, and the reliability (e.g., retention) of the memory device can be improved.

[0055] 4A to 4H is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0056] refer to Figure 4A , a preliminary stacked structure pSTK can be formed, in which the first material layer SF and the second material layer IL are alternately stacked. The first material layer SF can be formed of a material that can be selectively removed in a subsequent process. The second material layer IL can be formed of an insulating material. The first material layer SF can be formed of a material having an etching selectivity different from that of the second material layer IL. For example, the first material layer SF can be formed of a nitride layer. The second material layer IL can be an oxide layer (e.g., a silicon oxide layer).

[0057] refer to Figure 4B , an opening OP may be formed inside the preliminary stacked structure pSTK. The opening OP may penetrate the first material layers SF and the second material layers IL that are alternately stacked. The opening OP may have a columnar shape extending in the Z direction. An anisotropic dry etching process may be performed to form the opening OP at a designated position.

[0058] refer to Figure 4C, the memory layer ML may be formed along the inner wall IW1 of the opening OP. For example, a barrier layer BX may be formed along the inner wall IW1 of the opening OP, a charge trap layer CT may be formed along the inner wall IW3 of the barrier layer BX, and a tunnel insulating layer TX may be formed along the inner wall IW4 of the charge trap layer CT. The barrier layer BX and the tunnel insulating layer TX may be formed of an oxide layer (e.g., silicon oxide), an oxynitride layer (e.g., a silicon oxynitride layer), or any combination thereof. The charge trap layer CT may be formed of a nitride layer or a variable resistance material.

[0059] refer to Figure 4D , the first sub-channel layer C1 may be formed in the opening OP. For example, the first sub-channel layer C1 may be formed along the inner wall IW2 of the memory layer ML. That is, the first sub-channel layer C1 may be formed on the inner wall IW2 of the memory layer ML.

[0060] The first sub-channel layer C1 may be formed of undoped silicon. The first sub-channel layer C1 may be formed by a process of depositing undoped silicon on the inner wall IW2 of the memory layer ML.

[0061] refer to Figure 4E , a liner layer LL may be formed along the inner wall IW5 of the first sub-channel layer C1. That is, a liner layer LL may be formed on the inner wall IW5 of the first sub-channel layer C1. The liner layer LL may be formed to have a thickness thinner than that of the first sub-channel layer C1. The liner layer LL may be formed of an insulating layer. For example, the liner layer LL may be formed of an oxide layer. The liner layer LL may be formed by a process of depositing an insulating liner layer LL on the inner wall IW5 of the first sub-channel layer C1.

[0062] refer to Figure 4F , the second sub-channel layer C2 may be formed along the inner wall IW6 of the liner layer LL. That is, the second sub-channel layer C2 may be formed on the inner wall IW6 of the liner layer LL. The second sub-channel layer C2 may be formed to have a thickness thinner than that of the first sub-channel layer C1 and thicker than that of the liner layer LL.

[0063] The second sub-channel layer C2 may be formed of silicon doped with impurities. The impurities may be group XIII elements. For example, the impurities may be boron.

[0064] The second sub-channel layer C2 can be formed by a process of doping impurities into a silicon layer formed on the inner wall IW6 of the pad layer LL. For example, a silicon layer can be formed along the inner wall IW6 of the pad layer LL. Subsequently, impurities can be injected into the silicon layer through the opening OP. For example, impurities can be injected into the silicon layer by an inclined ion implantation process. The inclined ion implantation process can be an ion implantation process in which the angle formed by the direction of the injected impurities and the substrate is less than 90 degrees. The silicon layer into which the impurities are injected can constitute the second sub-channel layer C2.

[0065] The first sub-channel layer C1, the liner layer LL, and the second sub-channel layer C2 formed in the opening OP may constitute a channel layer CH. The channel layer CH may include the first sub-channel layer C1, the liner layer LL, and the second sub-channel layer C2, which are sequentially formed.

[0066] refer to Figure 4G , the column CO may be filled inside the second sub-channel layer C2. For example, the column CO may be filled in a region surrounded by the second sub-channel layer C2. The memory layer ML, the channel layer CH, and the column CO formed in the opening OP may constitute a cell plug CP. The column CO may be formed of an insulating layer or a conductive layer.

[0067] refer to Figure 4H , the first material layer SF can be replaced by the third material layer CD, thereby forming a stacked structure STK. Figure 4H OP, but a trench penetrating the preliminary stacked structure pSTK may be formed. The first material layer SF exposed by the trench may be removed. While the first material layer SF is removed, the cell plug CP filled in the opening OP may support the second material layer IL. The third material layer CD may be filled in the region where the first material layer SF is removed, i.e., between the second material layers IL. The third material layer CD may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polycrystalline silicon (poly-Si). Each third material layer in the third material layer CD may be used as a gate line, such as a drain select line, a word line, or a source select line.

[0068] Figure 5A and Figure 5B is a view showing a portion of a memory device including a cell plug according to one embodiment of the present disclosure. Figure 5A and Figure 5B Some of the various embodiments may be shown, wherein Figure 3A and Figure 3B as well as 4A to 4H The cell plug CP described in the above may be included in the memory device. However, Figure 5A and Figure 5BCorresponding to some examples to which the present disclosure can be applied. Any memory device, even when it does not correspond to Figure 5A or Figure 5B The embodiments shown in the figure may also be included in the scope of the present disclosure as long as it includes Figure 3A and Figure 3B as well as 4A to 4H The channel layer CH described in .

[0069] refer to Figure 5A and Figure 5B , the memory device may include a stack structure STK and a cell plug CP inside the stack structure STK, the stack structure STK including conductive layers CD and interlayer insulating layers IL stacked alternately. The cell plug CP may include a channel layer CH and a memory layer ML between the channel layer CH and the stack structure STK. The channel layer CH may be used as Figure 2 A portion of the memory layer ML (eg, the charge trap layer CT) may be used as a channel region of the string ST shown in FIG. Figure 2 The data storage areas of the memory cells MC1 to MCj shown in FIG.

[0070] The memory device may include a bit line BL connected to a cell plug CP. The cell plug CP may be connected to the bit line BL through a bit line contact 67A. The channel layer CH may be electrically connected to the bit line BL via the bit line contact 67A. The bit line contact 67A and the bit line BL may be disposed inside the first insulating structure 69.

[0071] The memory device may include a source line SL connected to the cell plug CP. An end of the channel layer CH may be connected to the source line SL. The source line SL may include at least one of an n-type impurity (eg, a group XV element) and a p-type impurity (eg, a group XIII element).

[0072] The memory device may include a semiconductor substrate 71 , a peripheral circuit structure PS, a second insulating structure 79 , and a plurality of interconnections 77A.

[0073] The peripheral circuit structure PS may include a region overlapping the source line SL, the stack structure STK, and the bit line BL. The peripheral circuit structure PS may include a plurality of transistors, capacitors, resistors, etc., which constitute Figure 1 The peripheral circuit structure PS can be as shown in FIG. Figure 5A adjacent to the source line SL as shown in Figure 5B is shown adjacent to the bit line BL.

[0074] The semiconductor substrate 71 may include an active region 71A separated by an isolation layer (not shown). The peripheral circuit structure PS may include at least one transistor. The transistor may include a gate insulating layer 73 and a gate electrode 75 stacked on the active region 71A of the semiconductor substrate 71, and a source / drain junction 71J formed in the active region 71 on both sides of the gate electrode 75. The plurality of interconnects 77A may include sub-interconnects individually connected to the gate electrode 75 and the source / drain junction 71J.

[0075] The semiconductor substrate 71 and the peripheral circuit structure PS may be covered with a second insulating structure 79 , and a plurality of interconnections 77A may be disposed inside the second insulating structure 79 .

[0076] refer to Figure 5A , the process of forming the source line SL, the stack structure STK and the cell plug CP may be performed on the peripheral circuit structure PS. For example, after the source line SL is formed on the peripheral circuit structure PS, the process of forming the stack structure STK and the cell plug CP may be performed on the source line SLK.

[0077] refer to Figure 5B , the process of forming the peripheral circuit structure PS and the process of forming the source line SL, the stack structure STK and the cell plug CP can be performed individually. The memory device may also include a first contact portion 67B and a first bonding pad BP1 disposed in the first insulating structure 69, and a second contact portion 77B and a second bonding pad BP2 disposed in the second insulating structure 79. The first bonding pad BP1 and the second bonding pad BP2 may be connected to each other through a bonding process. The process of forming the source line SL may be performed after the bonding process.

[0078] remove Figure 5A and Figure 5B Memory devices having various structures other than the structure shown in may be included in the scope of the present disclosure as long as the channel layer CH included in the cell plug CP includes the first sub-channel layer C1, the liner layer LL, and the second sub-channel layer C2.

[0079] Figure 6 is a diagram showing a memory card system to which a memory device of the present disclosure is applied.

[0080] refer to Figure 6 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0081] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control programming, reading, or erasing operations, or control background operations of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0082] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. For example, the controller 3100 can communicate with an external device through at least one communication protocol in various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), firewire, a universal flash storage device (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one communication protocol in the various communication protocols mentioned above.

[0083] The memory device 3200 may include a memory unit and is configured to Figure 1 The memory device 100 shown in FIG. 1 is the same as that in FIG.

[0084] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a universal flash storage device (UFS).

[0085] Figure 7 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0086] refer to Figure 7, the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0087] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of various interfaces, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0088] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured to Figure 1 The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0089] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive the power PWR input from the host 4100 and be charged with the power PWR. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide power to the SSD 4200. For example, the auxiliary power supply 4230 may be located in the SSD 4200, or located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0090] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or temporarily store metadata (e.g., a mapping table) of the memory devices 4220 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0091] According to the present disclosure, the amount of charge carriers included in a channel layer of a cell plug is increased, thereby improving operational reliability, particularly retention of a memory device.

[0092] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0093] In the above-described embodiments, all steps or some steps may be selectively performed, and steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be clear to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0094] Meanwhile, exemplary embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, these terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many changes within the spirit and scope of the present disclosure. It should be clear to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: Stacked structure; as well as A channel layer, inside the stacked structure, The channel layer comprises: a first sub-channel layer; a liner layer formed along an inner wall of the first sub-channel layer; and The second sub-channel layer is formed along the inner wall of the liner layer. 2 . The memory device of claim 1 , wherein the first sub-channel layer comprises an undoped silicon layer. 3 . The memory device of claim 1 , wherein the second sub-channel layer comprises a silicon layer doped with impurities. The memory device of claim 3 , wherein the impurity is a Group XIII element. The memory device of claim 3 , wherein the impurity is boron. The memory device of claim 1 , wherein the liner layer is an insulating layer.

7. The memory device of claim 1, wherein The first sub-channel layer has a first width, and The second sub-channel layer has a second width smaller than the first width. 8 . The memory device of claim 7 , wherein the liner layer has a third width that is smaller than the second width. 9 . The memory device of claim 1 , wherein each of the first sub-channel layer, the second sub-channel layer, and the liner layer penetrates the stack structure. 10 . The memory device of claim 1 , wherein the liner layer is formed between the first sub-channel layer and the second sub-channel layer. 11 . The memory device of claim 1 , wherein the liner layer is formed along an outer wall of the second sub-channel layer. 12 . The memory device of claim 1 , further comprising a memory layer on an outer wall of the channel layer. 13 . The memory device of claim 12 , wherein the memory layer comprises a blocking layer, a charge trap layer, and a tunnel insulating layer.

14. The memory device of claim 13, wherein The tunnel insulating layer surrounds the side surface of the first sub-channel layer, The charge trap layer surrounds the side surface of the tunnel insulating layer, and The blocking layer surrounds a side surface of the charge trap layer.

15. The memory device of claim 1, further comprising a pillar inside the channel layer. 16 . The memory device of claim 1 , wherein the stack structure comprises conductive layers and interlayer insulating layers that are alternately stacked.

17. A method of manufacturing a memory device, the method comprising: forming a stacking structure in which first material layers and second material layers are alternately stacked; forming an opening inside the stacked structure; forming a first sub-channel layer in the opening; forming a liner layer along an inner wall of the first sub-channel layer; as well as A second sub-channel layer is formed along an inner wall of the liner layer.

18. The method according to claim 17, further comprising: Before forming the first sub-channel layer, a memory layer is formed along an inner wall of the opening.

19. The method of claim 18, wherein forming the memory layer comprises: forming a barrier layer along the inner wall of the opening; forming a charge trap layer along the inner wall of the barrier layer; as well as A tunnel insulating layer is formed along an inner wall of the charge trap layer.

20. The method according to claim 17, wherein the first sub-channel layer is formed of undoped silicon. The method of claim 17 , wherein the liner layer is an insulating layer.

22. The method of claim 17, wherein the second sub-channel layer is silicon doped with impurities.

23. The method according to claim 22, wherein the step of forming the second sub-channel layer comprises: forming a silicon layer along the inner wall of the liner layer; as well as Impurities are implanted into the silicon layer.

24. The method of claim 23, wherein the implanting of impurities into the silicon layer is performed by a tilted ion implantation process in which an angle formed by a direction in which the impurities are implanted and a substrate is less than 90 degrees.

25. The method of claim 22, wherein the impurity is a Group XIII element.

26. The method of claim 22, wherein the impurity is boron.

27. The method of claim 17, further comprising: After forming the second sub-channel layer, the inside of the second sub-channel layer is filled with pillars.

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