Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The method for manufacturing the semiconductor structure comprises the following steps: sequentially forming a second semiconductor layer and a stacked structure on a first semiconductor layer, wherein the stacked structure comprises a bottom dielectric layer close to the second semiconductor layer; forming a plurality of channel holes penetrating through the stacked structure and the second semiconductor layer and extending to the first semiconductor layer, and forming an epitaxial layer extending to the bottom dielectric layer on the bottoms of the channel holes through epitaxial growth; and forming a channel structure on the epitaxial layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the storage density requirements for semiconductor structures such as three-dimensional semiconductor memory devices are becoming higher and higher. However, as the number of stacked layers in the semiconductor structure increases, the aspect ratio of the channel structure becomes larger and larger, which makes the height difference of multiple channel structures larger and larger, which in turn easily leads to the overall performance degradation of the semiconductor structure. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The method comprises: sequentially forming a second semiconductor layer and a stacked structure on a first semiconductor layer, wherein the stacked structure comprises a bottom dielectric layer close to the second semiconductor layer; forming a plurality of channel holes penetrating the stacked structure and the second semiconductor layer and extending to the first semiconductor layer, and epitaxially growing an epitaxial layer extending to the bottom dielectric layer at the bottom of the channel holes; and forming a channel structure on the epitaxial layer.

[0005] In one embodiment, an epitaxial layer extending to the bottom dielectric layer is formed by epitaxial growth at the bottom of the channel hole, including: a plurality of epitaxial layers extending to the bottom dielectric layer and having relatively flat top surfaces are formed by epitaxial growth at the bottom of the plurality of channel holes, wherein the top surface is the surface of the epitaxial layer extending to the bottom dielectric layer, and the channel structure is located on the top surface.

[0006] In one embodiment, a method for manufacturing a semiconductor structure includes: forming an insulating layer on a first semiconductor layer; forming a groove penetrating the insulating layer, wherein a channel hole is opposite to the groove along a stacking direction of a stacking structure; and forming a second semiconductor layer on the insulating layer, wherein the second semiconductor layer contacts the first semiconductor layer through the groove, and the stacking structure is located on the second semiconductor layer.

[0007] In one embodiment, forming the second semiconductor layer on the insulating layer includes: depositing an initial second semiconductor layer on the insulating layer; and performing an annealing process on the initial second semiconductor layer to form the second semiconductor layer.

[0008] In one embodiment, forming the second semiconductor layer on the insulating layer includes: forming an initial second semiconductor layer by epitaxial growth on the insulating layer; and performing an annealing process on the initial second semiconductor layer to form the second semiconductor layer.

[0009] In one embodiment, the channel structure includes a functional layer and a channel layer in sequence from the outside to the inside, and the method also includes: removing the first semiconductor layer, the insulating layer, the second semiconductor layer and the epitaxial layer to expose the functional layer; removing the exposed functional layer to expose the channel layer; and forming a conductive layer covering the exposed channel layer.

[0010] In one embodiment, removing the first semiconductor layer, the insulating layer, the second semiconductor layer, and the epitaxial layer includes: removing the first semiconductor layer, the insulating layer, the second semiconductor layer, and the epitaxial layer by a mechanical grinding process.

[0011] In one embodiment, the annealing process includes at least one of a rapid thermal annealing process and an excimer laser annealing process.

[0012] In one embodiment, the material of the first semiconductor layer includes single crystal silicon.

[0013] In one embodiment, the method for manufacturing a semiconductor structure further includes: forming a bonding layer on a side of the stack structure away from the bottom dielectric layer.

[0014] Another aspect of the present application provides a semiconductor structure, which includes: a stacked structure; a conductive layer on the stacked structure; and a plurality of channel structures penetrating the stacked structure and extending to the conductive layer, wherein the bottom surfaces of the plurality of channel structures extending to the conductive layer are relatively flat.

[0015] In one embodiment, the bottom surfaces being relatively flat includes a height difference of the plurality of bottom surfaces being in a range of 0 nm to 50 nm.

[0016] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0017] In one or more embodiments of the present application, the epitaxial layer extending to the bottom dielectric layer is formed by epitaxial growth at the bottom of the channel hole, which is beneficial to control the height of the portions of the epitaxial layers extending to the bottom dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0019] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0020] Figures 2 to 10 is a process step diagram for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0021] Fig.11 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0022] Fig. 12A and Fig. 12B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0024] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first semiconductor layer discussed in this application may also be referred to as the second semiconductor layer, and vice versa.

[0025] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0026] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0027] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0028] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0030] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0032] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0033] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0034] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, sequentially forming a second semiconductor layer and a stacked structure on a first semiconductor layer, wherein the stacked structure includes a bottom dielectric layer close to the second semiconductor layer; S1200, forming a plurality of channel holes penetrating the stacked structure and the second semiconductor layer and extending to the first semiconductor layer, and epitaxially growing an epitaxial layer extending to the bottom dielectric layer at the bottom of the channel holes; and S1300, forming a channel structure on the epitaxial layer. Steps S1100 to S1300 will be described in detail below.

[0035] In the exemplary embodiment of the present application, Figure 6 As shown, a second semiconductor layer 1200 and a stacked structure 1300 may be sequentially formed on the first semiconductor layer 1100 , wherein the stacked structure 1300 includes a bottom dielectric layer 1310 adjacent to the second semiconductor layer 1200 .

[0036] Exemplarily, the material of the first semiconductor layer 1100 may include a single semiconductor material, such as single crystal silicon, etc. Of course, it should be understood that in another embodiment, the material of the first semiconductor layer 1100 may include a polycrystalline silicon semiconductor material or at least one of other semiconductor materials known in the art. The first semiconductor layer 1100 can not only be used to provide mechanical support for the second semiconductor layer 1200 and the stacked structure 1300 thereon, but also provide a space for epitaxial growth of the epitaxial layer formed subsequently.

[0037] The material of the second semiconductor layer 1200 may include a single semiconductor material, for example, single crystal silicon, etc. Of course, it should be understood that in another embodiment, the material of the second semiconductor layer 1200 may also include polycrystalline silicon semiconductor material or at least one of other semiconductor materials known in the art. The second semiconductor layer 1200 may provide a space for epitaxial growth of the epitaxial layer formed subsequently.

[0038] For example, the first semiconductor layer 1100, the second semiconductor layer 1200 and the stacked structure 1300 may be sequentially formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. For example, the second semiconductor layer 1200 may also be formed by an epitaxial growth process. The epitaxial growth process may include, but is not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE) or any combination thereof.

[0039] like Figures 2 to 5 As shown, the process of forming the first semiconductor layer 1100 and the second semiconductor layer 1200 provided in an exemplary embodiment of the present application.

[0040] Specifically, an insulating layer 1400 ( Figure 2 ); forming a trench 100 penetrating the insulating layer 1400 ( Figure 3 ); and forming a second semiconductor layer 1200 on the insulating layer 1400 ( Figure 5 ), wherein the second semiconductor layer 1200 may contact the first semiconductor layer 1100 through the groove 100. For example, the channel hole formed subsequently may be opposite to the groove 100 along the stacking direction of the stacking structure 1300. In other words, the position of the groove 100 may be used as a calibration position of the channel hole formed subsequently.

[0041] The material of the insulating layer 1400 may include silicon dioxide, silicon nitride, aluminum oxide or other insulating materials, or a combination of the above insulating materials. In one embodiment of the present application, the material of the insulating layer 1400 may be silicon dioxide, and one or more thin film deposition processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to deposit silicon dioxide to form the insulating layer 1400. In another embodiment of the present application, the material of the insulating layer 1400 may be silicon dioxide, and an oxidation method may be used to oxidize the first semiconductor layer 1100 to form the insulating layer 1400. The insulating layer 1400 is mainly used to achieve mutual isolation between the channel structures formed subsequently.

[0042] For example, Figure 3As shown, forming the trench 100 penetrating the insulating layer 1400 may include: etching the insulating layer 1400 to form the trench 100 exposing the first semiconductor layer 1100 in the insulating layer 1400. Exemplarily, the etching of the insulating layer 1400 may stop on the first semiconductor layer 1100, that is, the first semiconductor layer 1100 may serve as an etch stop layer for etching the insulating layer 1400.

[0043] By way of example, the groove 100 may be a groove of any suitable shape, such as a rectangular groove and / or a through hole, penetrating the insulating layer 1400. The insulating layer 1400 may have a plurality of rectangular grooves and / or through holes distributed in an array. The present application only exemplifies the shape of the groove 100 and does not specifically limit it. In addition, the present application does not specifically limit the size of the rectangular groove and / or through hole, etc., and the size of the rectangular groove and / or through hole can be reasonably set according to the actual process.

[0044] In one embodiment of the present application, Figure 5 As shown, forming the second semiconductor layer 1200 on the insulating layer 1400 may include: depositing an initial second semiconductor layer 1200′ ( Figure 4 ); and performing an annealing process on the initial second semiconductor layer 1200' to form a second semiconductor layer 1200 ( Figure 5 ). At this time, the material of the initial second semiconductor layer 1200' may be polycrystalline silicon, which may be changed into single crystal silicon after annealing. In other words, the initial second semiconductor layer 1200' formed by deposition may be changed into the second semiconductor layer 1200 after annealing.

[0045] In another embodiment of the present application, Figure 5 As shown, forming the second semiconductor layer 1200 on the insulating layer 1400 may include: epitaxially growing an initial second semiconductor layer 1200' on the insulating layer 1400; and performing an annealing process on the initial second semiconductor layer 1200' to form the second semiconductor layer 1200 ( Figure 5 ). At this time, the material of the initial second semiconductor layer 1200' can be single crystal silicon, and the single crystal silicon formed by epitaxial growth can be changed into single crystal silicon with greater structural strength after annealing process. In other words, the initial second semiconductor layer 1200' formed by epitaxial growth can be changed into the second semiconductor layer 1200 after annealing process.

[0046] Exemplarily, the annealing process may include at least one of a rapid thermal annealing process and an excimer laser annealing process.

[0047] The excimer laser annealing process can utilize excimer laser to uniformly irradiate the initial second semiconductor layer 1200', generate a large amount of energy in a relatively short time, so that the initial second semiconductor layer 1200' is melted by high temperature, and then the molten polysilicon and / or single crystal silicon material is crystallized again from the first semiconductor layer 1100 to the second semiconductor layer 1200. Since the laser is pulsed, and the laser pulse is about tens of nanoseconds, the total action time of the excimer laser annealing treatment is relatively short, so that the damage to the first semiconductor layer 1100 can be reduced while the initial second semiconductor layer 1200' is changed into the second semiconductor layer 1200.

[0048] In addition, the excimer laser annealing process can quickly crystallize, reduce the stress of the second semiconductor layer 1200 formed by crystallization, and reduce the filling voids of the second semiconductor layer 1200. Specifically, a local area of ​​the initial second semiconductor layer 1200' irradiated by the excimer laser can be melted into liquid silicon, and the molten liquid silicon can be recrystallized, and the position of the void can be changed or the size of the void can be reduced during the recrystallization process, and further, the existing voids can be reduced.

[0049] The rapid thermal annealing process is a single-chip heat treatment process with a fast heating speed and a short holding time. The heating rate can reach 10 to 100 degrees Celsius per second. Generally, infrared halogen lamps or resistor rods are used for heating. The current and power are very large during heating. It is an important process in semiconductor manufacturing and can be used for thermal annealing after ion implantation, rapid activation of impurities, rapid thermal oxidation, chemical vapor deposition, epitaxial growth and other processes. This heat treatment method can save a lot of heat treatment time and reduce production costs. In the present application, the initial second semiconductor layer 1200' can be processed by a rapid thermal annealing process to change the initial second semiconductor layer 1200' into the second semiconductor layer 1200.

[0050] like Figure 6 As shown, the process of forming the stack structure 1300 , the epitaxial layer 1500 and the channel structure 1600 provided in the exemplary embodiment of the present application.

[0051] For example, a bottom dielectric layer 1310 may be formed on the surface of the second semiconductor layer 1200 , and dielectric layers 1320 and sacrificial layers 1330 may be alternately stacked on the bottom dielectric layer 1310 to form the stacked structure 1300 .

[0052] The bottom dielectric layer 1310 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and a dielectric layer 1320 and a sacrificial layer 1330 may be sequentially stacked to form the stacked structure 1300. It should be understood that the number and thickness of the dielectric layer 1320 and the sacrificial layer 1330 are not limited to Figure 6 The numbers and thicknesses shown in the figure, without departing from the concept of the present application, those skilled in the art can set any number and thickness of dielectric layer 1320 and sacrificial layer 1330 as needed. In addition, the thickness of the bottom dielectric layer 1310 can be greater than the thickness of the dielectric layer 1320 or the sacrificial layer 1330. The materials of the bottom dielectric layer 1310, the dielectric layer 1320 and the sacrificial layer 1330 can be selected from suitable materials known in the art, for example, the materials of the bottom dielectric layer 1310 and the dielectric layer 1320 can include oxides such as silicon oxide, and the material of the sacrificial layer 1330 can include nitrides such as silicon nitride.

[0053] For example, a plurality of channel holes 1610 penetrating the stacked structure 1300 and the second semiconductor layer 1200 and extending to the first semiconductor layer 1100 may be formed, and an epitaxial layer 1500 extending to the bottom dielectric layer 1310 may be formed by epitaxial growth at the bottom of the channel holes 1610 .

[0054] For example, the channel hole 1610 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole 1610 may have a cylindrical or columnar shape extending in the stacking direction in the stacked structure 1300, the second semiconductor layer 1200, and the first semiconductor layer 1100.

[0055] Exemplarily, the channel hole 1610 and the trench 100 may be formed by the same mask plate, so that the channel hole 1610 may be opposite to the trench 100 along the stacking direction. In other words, the channel hole 1610 may penetrate the second semiconductor layer 1200 filled in the trench 100, and the opening size of the channel hole 1610 may be the same as the width of the trench 100.

[0056] As the number of stacked layers of the stacked structure 1300 increases, the aspect ratio of the channel hole 1610 penetrating the stacked structure 1300 becomes larger and larger, and the depth difference of the channel hole 1610 extending to the first semiconductor layer 1100 becomes larger and larger.

[0057] Exemplarily, the epitaxial layer 1500 may be formed by filling a portion of the channel hole 1610 with a semiconductor material epitaxially grown from the first semiconductor layer 1100 and the second semiconductor layer 1200 via the channel hole 1610, wherein the epitaxial layer 1500 may extend from the bottom of the channel hole 1610 to the bottom dielectric layer 1310. The material of the epitaxial layer 1500 may be the same as that of the first semiconductor layer 1100 and the second semiconductor layer 1200, for example, the material of the epitaxial layer 1500 may include single crystal silicon. The manufacturing process for epitaxially growing the epitaxial layer 1500 may include, but is not limited to, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof.

[0058] For example, the plurality of epitaxial layers 1500 formed by epitaxial growth through the plurality of channel holes 1610 may have substantially flush top surfaces. In other words, the top surfaces of the plurality of epitaxial layers 1500 extending to the bottom dielectric layer 1310 may be relatively flush, for example, the plurality of top surfaces are substantially flush with the trimming plane S.

[0059] For example, some of the epitaxial layers 1500 may have gaps, and some of the epitaxial layers 1500 may not have gaps. The materials of the first semiconductor layer 1100, the second semiconductor layer 1200, and the epitaxial layer 1500 may all include single crystal silicon, so as to achieve epitaxial growth on the single crystal silicon layer to form a single crystal silicon epitaxial layer, which is conducive to making the multiple single crystal silicon epitaxial layers have substantially flush top surfaces.

[0060] In the present application, multiple epitaxial layers 1500 are formed by epitaxially growing from the first semiconductor layer 1100 and the second semiconductor layer 1200, so that the top surfaces of the multiple epitaxial layers 1500 extending to the bottom dielectric layer 1310 are substantially flush with the cut surface S. This is conducive to making multiple channel structures subsequently formed on the top surface have the same height, thereby facilitating improving the conductive performance and structural stability of the semiconductor structure.

[0061] In an exemplary embodiment of the present application, a channel structure 1600 may be formed on the top surface. Specifically, a functional layer 1670 and a channel layer 1660 may be formed in sequence from outside to inside in the remaining space of the channel hole 1610; and a channel filling dielectric layer 1680 and a channel plug (not shown) may be formed. It should be understood that the channel structure 1600 extends to the bottom dielectric layer 1310 along the stacking direction.

[0062] The functional layer 1670 may include a blocking layer 1630 formed on the inner wall of the channel hole 1610 to block the outflow of charges, a charge capture layer 1640 formed on the surface of the blocking layer 1630 to store charges during the operation of the semiconductor structure, and a tunneling layer 1650 formed on the surface of the charge capture layer 1640.

[0063] In some embodiments, the functional layer 1670 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 1670 may have a structure different from the ONO configuration. The channel layer 1660 may be formed on the surface of the tunneling layer 1650 and can be used to transport the required charges (electrons or holes).

[0064] For example, as an option, according to one embodiment of the present application, a functional layer 1670 may be formed on the inner wall and bottom surface of the remaining space of the channel hole 1610, and a channel layer 1660 may be formed on the surface of the tunneling layer 1650 of the functional layer 1670 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0065] In addition, the channel structure 1600 also includes a channel plug formed at one end of the channel layer 1660 away from the bottom dielectric layer 1310 (which can be understood as the top of the channel structure 1600). Specifically, after forming the functional layer 1670 and the channel layer 1660, the channel hole 1610 can be filled with a channel filling dielectric layer 1680. The channel filling dielectric layer 1680 can include an oxidized dielectric layer, such as silicon oxide. Further, during the filling process, a plurality of insulating gaps can be formed in the channel filling dielectric layer 1680 by controlling the channel filling process to relieve structural stress. Then, a channel plug is formed in the portion of the channel filling dielectric layer 1680 located at the top of the channel hole 1610. The material of the channel plug can be prepared from the same material as the channel layer 1660, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer 1660.

[0066] In the exemplary embodiment of the present application, Figure 7 As shown, the sacrificial layer 1330 may be replaced with the gate layer 1340 through a gate replacement process. Specifically, a gate gap (not shown) may be formed that penetrates the stacked structure 1300; then, the sacrificial layer 1330 may be removed through the gate gap, and a conductive material may be filled in the removed space to form the gate layer 1340. After the gate layer 1340 is formed, the gate gap may be filled to form a gate gap structure (not shown).

[0067] In the exemplary embodiment of the present application, a bonding layer (not shown) is formed on one side of the stack structure 1300 away from the bottom dielectric layer 1310. The bonding layer can be used to bond the semiconductor structure 1000 to another semiconductor structure such as a peripheral circuit chip (not shown).

[0068] Figure 8 For the general Figure 7 Schematic diagram of a structure in which the structure is flipped 180° and then thinned. For example, the first semiconductor layer 1100, the insulating layer 1400, the second semiconductor layer 1200 and the epitaxial layer 1500 can be removed to expose the functional layer 1670 ( Figure 8 ); removing the exposed functional layer 1670 to expose the channel layer 1660 ( Fig. 9 ); and forming a conductive layer 1700 covering the exposed channel layer 1660 ( Fig.10 ).

[0069] Specifically, Figure 8 As shown, the first semiconductor layer 1100, the insulating layer 1400, the second semiconductor layer 1200 and the epitaxial layer 1500 may be removed from one side of the first semiconductor layer 1100 by a planarization process until the functional layer 1670 is exposed. For example, the first semiconductor layer 1100, the insulating layer 1400, the second semiconductor layer 1200 and the epitaxial layer 1500 may be removed by a chemical mechanical polishing (CMP) process until the functional layer 1670 is exposed.

[0070] like Fig. 9 As shown, the exposed functional layer 1670 can be removed until the channel layer 1660 is exposed. By way of example, multiple wet etching processes or a combination of dry and wet etching processes can be used to remove the blocking layer 1630, the charge capture layer 1640, and the tunneling layer 1650 to expose the end surface of the channel layer 1660 close to the bottom dielectric layer 1310. It should be understood that in this removal process, exposing the end of the channel layer 1660 close to the bottom dielectric layer 1310 can achieve the purpose of the present application. To this end, the present application only introduces a removal process by way of example, and does not specifically limit the removal process used. As another option, the sidewall region of a portion of the channel layer 1660 close to the bottom dielectric layer 1310 can be removed. By way of example, the end of the channel layer 1660 exposed after removing the blocking layer 1630, the charge capture layer 1640, and the tunneling layer 1650 can be highly doped. For example, the exposed end of the channel layer 1660 may be subjected to N-type high doping, such as N-type doping by processes such as ion implantation IMP. The N-type doping may include any suitable N-type dopant, such as phosphorus (P), arsenic (Ar) or antimony (Sb), to increase the conductivity of the end of the channel layer 1660 close to the bottom dielectric layer 1310.

[0071] In an exemplary embodiment of the present application, a plurality of air gaps are generated during the process of removing the blocking layer 1630, the charge trapping layer 1640, and the tunneling layer 1650. Fig.10 As shown, after the end of the channel layer 1660 close to the bottom dielectric layer 1310 is highly doped, a conductive material can be filled in the air gap by, for example, a deposition process, so that a conductive layer 1700 can be formed at the end of the channel layer 230 close to the bottom dielectric layer 1310, so that the conductive layer 1700 is connected to the channel layers 1660 of the multiple channel structures 1600. Exemplarily, a planarization process, such as a mechanical chemical polishing CMP process, can be used to perform a planarization process on the formed conductive layer 1700. The material of the conductive layer 1700 can be a conductive material, such as polysilicon or doped polysilicon. The conductive layer 1700 can be used as a common source structure of the multiple channel structures 1600.

[0072] Fig.10 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0073] The semiconductor structure may include a stacked structure 1300 , a conductive layer 1700 , and a plurality of channel structures 1600 .

[0074] The stacked structure 1300 may include a bottom dielectric layer 1310 and dielectric layers 1320 and gate layers 1340 alternately stacked on the bottom dielectric layer 1310. It should be understood that the number and thickness of the dielectric layers 1320 and the gate layers 1340 are not limited to Fig.10 The number and thickness shown in the figure, without departing from the concept of the present application, those skilled in the art can set any number and thickness of dielectric layer 1320 and gate layer 1340 as needed. In addition, the materials of bottom dielectric layer 1310, dielectric layer 1320 and gate layer 1340 can be selected from suitable materials known in the art, for example, the materials of bottom dielectric layer 1310 and dielectric layer 1320 can include oxides. The material of gate layer 1340 can include a combination of metals and / or metal compounds.

[0075] The conductive layer 1700 may be located on the stacked structure 1300. Specifically, the conductive layer 1700 may be located on the bottom dielectric layer 1310. The conductive layer 1700 may be made of a conductive material, such as polysilicon or doped polysilicon.

[0076] The plurality of channel structures 1600 may penetrate the stacked structure 1300 and extend to the conductive layer 1700. The conductive layer 1700 may be used as a common source structure of the plurality of channel structures 1600. The channel structure 1600 may include a functional layer 1670, a channel layer 1660 and a channel filling dielectric layer 1680 from the outside to the inside.

[0077] The functional layer 1670 may include a blocking layer 1630 formed on the inner wall of the channel hole 1610 to block the outflow of charges, a charge capture layer 1640 formed on the surface of the blocking layer 1630 to store charges during the operation of the semiconductor structure, and a tunneling layer 1650 formed on the surface of the charge capture layer 1640.

[0078] The blocking layer 1630 may include one or more layers, which may include one or more materials. The materials for the blocking layer 1630 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The charge trapping layer 1640 may include one or more layers, which may include one or more materials. The materials for the charge trapping layer 1640 may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. The tunneling layer 1650 may include one or more layers, which may include one or more materials. The materials for the tunneling layer 1650 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. Exemplarily, the functional layer 1670 may include an oxide-nitride-oxide (ONO) structure. Of course, it should be understood that the functional layer 1670 may also have a structure different from the ONO configuration. For example, the functional layer 1670 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer.

[0079] The channel layer 1660 may include silicon, such as amorphous silicon, polycrystalline silicon or monocrystalline silicon. The material of the channel layer 1660 includes but is not limited to P-type doped polycrystalline silicon. The channel filling dielectric layer 1680 may include an oxidized dielectric layer, such as silicon oxide. The channel filling dielectric layer 1680 may have multiple insulating gaps to reduce structural stress.

[0080] For example, the channel structure 1600 may further include a channel plug located at one end of the channel layer 1660 away from the bottom dielectric layer 1310. The channel plug may be made of the same material as the channel layer 1660, such as N-type doped or P-type doped polysilicon. The channel plug may be connected to the channel layer 1660.

[0081] In an exemplary embodiment of the present application, bottom surfaces of the plurality of channel structures 1600 extending to the conductive layer 1700 may be relatively flush. Exemplarily, the relatively flush bottom surfaces include a height difference of the plurality of bottom surfaces being in the range of 0 nm to 50 nm.

[0082] The present application can effectively reduce the height of the bottom surface extending to the conductive layer 1700 while ensuring that the bottom surfaces of the multiple channel structures 1600 all extend to the conductive layer 1700 by setting the height difference of the multiple bottom surfaces within the range of 0nm to 50nm, thereby facilitating the reduction of the collapse of the channel structure 1600 in the actual process. In addition, by setting the height difference of the multiple bottom surfaces within the range of 0nm to 50nm, the uniformity of the thickness of the bottom dielectric layer 1310 can be improved in the actual process, thereby facilitating the improvement of the stability of the gate-induced-drain-leakage (GIDL) auxiliary body bias generated when the semiconductor structure performs an erase operation.

[0083] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0084] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0085] Fig.11 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0086] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.11 As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0087] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0088] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig. 12AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.11 The host 18 in the memory card connector 24 is coupled. Fig. 12B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.11 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0089] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a second semiconductor layer and a stacked structure in sequence on the first semiconductor layer, wherein the stacked structure includes a bottom dielectric layer close to the second semiconductor layer; forming a plurality of channel holes penetrating the stacked structure and the second semiconductor layer and extending to the first semiconductor layer, and epitaxially growing an epitaxial layer extending to the bottom dielectric layer at the bottom of the channel holes; and A channel structure is formed on the epitaxial layer.

2. The method according to claim 1, characterized in that: Epitaxially growing an epitaxial layer extending to the bottom dielectric layer at the bottom of the channel hole, comprising: A plurality of epitaxial layers extending to the bottom dielectric layer and having relatively flat top surfaces are formed by epitaxial growth at the bottom of the plurality of channel holes, wherein the top surface is the surface of the epitaxial layer extending to the bottom dielectric layer, and the channel structure is located on the top surface.

3. The method according to claim 1, characterized in that The method comprises: forming an insulating layer on the first semiconductor layer; forming a trench penetrating the insulating layer, wherein the channel hole is opposite to the trench along a stacking direction of the stacking structure; and The second semiconductor layer is formed on the insulating layer, wherein the second semiconductor layer is in contact with the first semiconductor layer through the groove, and the stacked structure is located on the second semiconductor layer.

4. The method according to claim 3, characterized in that Forming a second semiconductor layer on the insulating layer, comprising: Depositing an initial second semiconductor layer on the insulating layer; and The initial second semiconductor layer is subjected to an annealing process to form the second semiconductor layer.

5. The method according to claim 3, characterized in that: Forming a second semiconductor layer on the insulating layer, comprising: epitaxially growing an initial second semiconductor layer on the insulating layer; and The initial second semiconductor layer is subjected to an annealing process to form the second semiconductor layer.

6. The method according to claim 3, characterized in that The channel structure includes a functional layer and a channel layer in sequence from outside to inside, and the method further includes: removing the first semiconductor layer, the insulating layer, the second semiconductor layer and the epitaxial layer to expose the functional layer; removing the exposed functional layer to expose the channel layer; and A conductive layer is formed to cover the exposed channel layer.

7. The method according to claim 6, characterized in that Removing the first semiconductor layer, the insulating layer, the second semiconductor layer and the epitaxial layer includes: The first semiconductor layer, the insulating layer, the second semiconductor layer and the epitaxial layer are removed by a mechanical grinding process.

8. The method according to claim 4 or 5, characterized in that: The annealing process includes: at least one of a rapid thermal annealing process and an excimer laser annealing process.

9. The method according to any one of claims 1 to 5, characterized in that The material of the first semiconductor layer includes single crystal silicon.

10. The method according to any one of claims 1 to 7, characterized in that The method further comprises: A bonding layer is formed on a side of the stack structure away from the bottom dielectric layer.

11. A semiconductor structure, characterized in that: include: Laminated structure; a conductive layer located on the stacked structure; as well as A plurality of channel structures penetrate the stacked structure and extend to the conductive layer, wherein bottom surfaces of the plurality of channel structures extending to the conductive layer are relatively flat.

12. The semiconductor structure according to claim 11, characterized in that: The bottom surfaces are relatively flat including a plurality of bottom surfaces having a height difference in the range of 0 nm to 50 nm.

13. A storage system, characterized in that: include: At least one three-dimensional memory, each of the three-dimensional memory comprising the semiconductor structure according to claim 11 or 12; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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