Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display. The display panel is provided with a display area and a peripheral area; the display panel comprises a substrate, a transistor layer, a connection layer, a first electrode, a pixel definition layer, a light emitting layer and a second electrode. The transistor layer is arranged on one side of the substrate; the connecting layer is arranged on the surface of the transistor layer away from the substrate; the connecting layer is provided with a plurality of isolation grooves with concave side walls; the isolation groove comprises an inner isolation groove located in the display area and an outer isolation groove located in the peripheral area; the first electrode array is distributed on the surface, away from the substrate, of the connecting layer and located in the display area. The pixel definition layer and the first electrodes are arranged on the same surface of the connecting layer, and pixel openings for exposing the first electrodes are formed in the pixel definition layer; any inner isolation groove is arranged between two adjacent pixel openings; the light-emitting layer covers the pixel definition layer and the first electrode, and the light-emitting layer is disconnected on the side wall of the isolation groove; the second electrode covers the light-emitting layer. On the premise of preventing crosstalk and erosion, the production cost is reduced, and the production efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In electronic devices such as mobile phones and tablets, it is common to use organic light-emitting diodes (OLED) as display panels for light-emitting devices. Water vapor and oxygen from the outside may enter the display panel, corrode the organic light-emitting diodes, and easily cause packaging failure, affecting the light-emitting effect.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The present disclosure provides a display panel and a display device, which can reduce production costs and improve production efficiency under the premise of preventing crosstalk and corrosion.

[0005] According to one aspect of the present disclosure, there is provided a display panel having a display area and a peripheral area outside the display area, the display panel comprising:

[0006] substrate;

[0007] A transistor layer, disposed on one side of the substrate;

[0008] A connection layer is provided on a surface of the transistor layer away from the substrate; the connection layer is provided with a plurality of isolation grooves, the sidewalls of the isolation grooves are concave; the isolation grooves include inner isolation grooves located in the display area and outer isolation grooves located in the peripheral area;

[0009] A plurality of first electrodes are distributed in an array on a surface of the connection layer away from the substrate and located in the display area;

[0010] A pixel definition layer is disposed on the same surface of the connection layer as the first electrode and is provided with a pixel opening for exposing each of the first electrodes; the inner isolation groove is disposed between two adjacent pixel openings;

[0011] a light-emitting layer, covering the pixel definition layer and the first electrode, wherein the light-emitting layer is disconnected at a side wall of the isolation groove;

[0012] The second electrode covers the light-emitting layer.

[0013] In an exemplary embodiment of the present disclosure, the pixel openings are divided into a plurality of opening groups, one of the opening groups includes a plurality of the pixel openings, and an inner isolation groove is provided between two adjacent pixel openings in the same opening group.

[0014] In an exemplary embodiment of the present disclosure, the pixel openings of the same opening group are distributed along a first direction, the inner isolation groove between two adjacent pixel openings extends along a second direction, and the length of the inner isolation groove in the second direction is not less than the length of the pixel opening in the second direction; the first direction is perpendicular to the second direction.

[0015] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0016] An outer barrier dam is provided on a side of the connection layer away from the substrate and located in the peripheral area; the light emitting layer and the second electrode cover the outer barrier dam; and the outer isolation grooves are distributed on both sides of the outer barrier dam;

[0017] The encapsulation layer includes a first inorganic layer, an organic layer and a second inorganic layer, wherein the first inorganic layer covers the second electrode and extends to the peripheral area, the organic layer is arranged on the surface of the first inorganic layer away from the substrate and is limited to a side of the outer blocking dam close to the display area, and the second inorganic layer covers the organic layer and the first inorganic layer.

[0018] In an exemplary embodiment of the present disclosure, the isolation trench includes a first segment and a second segment that are sequentially connected, the first segment is located on a side of the second segment away from the substrate, and a boundary of an orthographic projection of the second segment on the substrate is located outside a boundary of an orthographic projection of the first segment on the substrate.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0020] an auxiliary electrode, disposed on a surface of the connection layer away from the substrate and spaced apart from the first electrode;

[0021] The pixel definition layer is provided with an auxiliary opening exposing the auxiliary electrode, the light emitting layer is disconnected at the auxiliary opening, and the second electrode is stacked with the auxiliary electrode in the auxiliary opening.

[0022] In an exemplary embodiment of the present disclosure, the auxiliary opening is provided between two adjacent opening groups.

[0023] In an exemplary embodiment of the present disclosure, each of the opening groups is distributed along the first direction and the second direction;

[0024] The auxiliary openings include first auxiliary openings extending along the second direction and second auxiliary openings extending along the first direction, the first auxiliary openings are distributed between the adjacent opening groups in the first direction; the second auxiliary openings are distributed between the adjacent opening groups in the second direction.

[0025] In an exemplary embodiment of the present disclosure, the length of the first auxiliary opening in the second direction is greater than the length of the opening group in the second direction;

[0026] A length of the second auxiliary opening in the first direction is greater than a length of the opening group in the first direction.

[0027] In an exemplary embodiment of the present disclosure, any two of the auxiliary openings are arranged at an interval.

[0028] In an exemplary embodiment of the present disclosure, the display panel is provided with an opening, and the display panel further comprises a transition area surrounding the opening, and the display area is located outside the transition area;

[0029] The isolation trench further includes a transition isolation trench, the transition isolation trench is located in the transition region, and the light-emitting layer is disconnected at a side wall of the transition isolation trench.

[0030] In an exemplary embodiment of the present disclosure, the connection layer includes at least one source / drain layer and a planar layer covering the source / drain layer, and the isolation trench is located in the planar layer.

[0031] In an exemplary embodiment of the present disclosure, the source-drain layer includes a first source-drain layer and a second source-drain layer, and the planar layer includes a first planar layer and a second planar layer;

[0032] The first source-drain layer is provided on a surface of the transistor layer away from the substrate, and the first flat layer covers the first source-drain layer; the second source-drain layer is provided on a surface of the first flat layer away from the substrate, and the second flat layer covers the second source-drain layer; the isolation trench at least penetrates the second flat layer;

[0033] The first electrode is disposed on a surface of the second planar layer away from the substrate.

[0034] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0035] In the display panel and display device disclosed herein, one pixel opening can define one light-emitting device, and the light-emitting layer can be disconnected by the inner concave of the isolation groove. The outer isolation groove can cut off the path of external water vapor and oxygen invading the display area along the light-emitting layer, thereby improving the packaging effect and reducing the risk of display abnormality; the inner isolation groove can block the current from being conducted along the light-emitting layer, thereby avoiding crosstalk between adjacent light-emitting devices. At the same time, the isolation groove can also block water vapor and oxygen from corroding the display area along the connection layer. In addition, each isolation groove is located in the connection layer and can be formed simultaneously by the same process, which is conducive to simplifying the process and reducing costs.

[0036] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0038] Figure 1 FIG. 1 is a top view of an embodiment of a display panel disclosed herein.

[0039] Figure 2 for Figure 1 The AA cross-section of the panel is shown in FIG.

[0040] Figure 3 for Figure 2 A cross-sectional view of part of the film layer of the display panel.

[0041] Figure 4 for Figure 1 The BB cross-section of the panel is shown in FIG.

[0042] Figure 5 for Figure 1 The CC cross-section of the panel is shown in FIG.

[0043] Figure 6 It is a partially enlarged schematic diagram of an embodiment of the display panel disclosed in the present invention. DETAILED DESCRIPTION

[0044] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0045] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" are used merely as labels and are not intended to limit the quantity of their objects.

[0046] The first direction and the second direction herein refer only to two vertical directions and are not limited to the vertical direction and the horizontal direction shown in the drawings.

[0047] The "same-layer arrangement" of A and B in this article means that A and B belong to different continuous or disconnected regions in the same film layer, and each region can be formed at the same time.

[0048] The present disclosure provides a display panel. Figure 1 As shown, the display panel may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA; or it may be an area surrounding the display area AA discontinuously. For example, the peripheral area WA may be distributed on both sides of the display area AA. The display area AA may be used to emit light to display an image, while the peripheral area WA does not emit light.

[0049] like Figure 2 As shown, the display panel may include a driving backplane BP, a light emitting device LD, and an encapsulation layer TFE. The light emitting device LD is arranged on one side of the driving backplane BP and can emit light under the driving of the driving backplane BP; the encapsulation layer TFE covers the light emitting device LD and is used to protect the light emitting device LD from being corroded by external water, oxygen and other impurities; wherein:

[0050] The driving backplane BP has a driving circuit, which can drive the light-emitting device LD to emit light to display an image. In some embodiments of the present disclosure, the driving backplane BP may include a substrate SU and a circuit layer located on one side of the substrate SU. The substrate SU may be a flat plate structure, and its material may be a hard material such as glass, or a flexible material such as polyimide. At the same time, the substrate SU may be a single-layer or multi-layer structure.

[0051] The circuit layer includes the above-mentioned driving circuit. For example, the driving circuit may include a pixel circuit located in the display area AA and a peripheral circuit located in the peripheral area WA. The pixel circuit may be a 3T1C, 7T1C, 8T1C or other structure. As long as it can drive the light-emitting device LD to emit light, its structure is not specifically limited. nTmC means that a pixel circuit includes n thin-film transistors (indicated by the letter "T") and m capacitors (indicated by the letter "C"). The number of pixel circuits may be the same as the number of light-emitting devices LD, and each light-emitting device LD is connected in a one-to-one correspondence. Of course, the same pixel circuit may also be connected to multiple light-emitting devices LD, which is not specifically limited here.

[0052] The peripheral circuit is connected to the pixel circuit and is used to input a driving signal to the pixel circuit so as to control the light emitting device LD to emit light. The peripheral circuit may include a gate driving circuit and a light emitting control circuit, and of course, may also include other circuits. The specific structure of the peripheral circuit is not particularly limited here.

[0053] The above-mentioned driving circuit may include multiple thin film transistors and capacitors, wherein the thin film transistors may be top-gate or bottom-gate thin film transistors, each thin film transistor may include an active layer and a gate arranged in an overlapping manner, and the active layers of each thin film transistor may be arranged in the same semiconductor layer; or, they may be arranged in multiple semiconductor layers, and the active layers of each thin film transistor may be distributed in different semiconductor layers. The material of the semiconductor layer may be polysilicon or metal oxide, which is not specifically limited here. At the same time, the thin film transistors and capacitors of the driving circuit may be connected by wiring to form a driving circuit.

[0054] like Figure 2 As shown, taking a top-gate thin film transistor as an example, in some embodiments of the present disclosure, the circuit layer may include a semiconductor layer SE, a first gate insulating layer GI1, a first gate layer GA1, a second gate insulating layer GI2, a second gate layer GA2, an interlayer dielectric layer ILD, and at least one source and drain layer and a planar layer, wherein:

[0055] The semiconductor layer SE may be disposed on one side of the substrate SU, and may be directly disposed on the substrate SU or disposed on a buffer layer stacked on the substrate SU. The material of the semiconductor layer SE may be polysilicon or metal oxide. The first gate insulating layer GI1 may cover the semiconductor layer SE, and its material may include inorganic insulating materials such as silicon nitride and silicon oxide. The first gate layer GA1 may be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU, and the material of the first gate layer GA1 may be metal such as molybdenum, copper, or other conductive materials. The second gate insulating layer GI2 may cover the first gate layer GA1. The material of the second gate insulating layer GI2 may include inorganic insulating materials such as silicon nitride and silicon oxide. The second gate layer GA2 may be disposed on the surface of the second gate insulating layer GI2 away from the substrate SU, and the material of the second gate layer GA2 may be metal such as molybdenum, copper, or other conductive materials. The active layer of the thin film transistor is located on the semiconductor layer SE, the gate is located on the first gate layer GA1, and the two plates of the capacitor are located on the first gate layer GA1 and the second gate layer GA2. The interlayer dielectric layer ILD covers the second gate layer GA2 , and the interlayer dielectric layer ILD may be a single-layer or multi-layer structure, and its material may include inorganic insulating materials such as silicon nitride and silicon oxide.

[0056] The source and drain layer can be arranged on the side of the interlayer dielectric layer ILD away from the substrate SU, and the planar layer can cover the source and drain layer. The source and drain layer can be made of conductive materials such as metal or metal oxide. The material of the planar layer can include organic materials such as resin for planarization. There can be only one source and drain layer in the circuit layer, or there can be two, three or more source and drain layers, and the driving circuit is formed by connecting the source and drain layers. For example:

[0057] In some embodiments of the present disclosure, the number of source and drain layers and planar layers may be two, namely, the first source and drain layer SD1, the first planar layer PLN1, the second source and drain layer SD2, and the second planar layer PLN2. The first source and drain layer SD1 may be arranged on the surface of the interlayer dielectric layer ILD away from the substrate SU, the first planar layer PLN1 covers the first source and drain layer SD1, the first planar layer PLN1 may directly cover the first source and drain layer SD1, or the first source and drain layer SD1 may be first covered with a passivation layer, and then the passivation layer is covered by the first planar layer PLN1. The second source and drain layer SD2 may be arranged on the surface of the first planar layer PLN1 away from the substrate SU, and the second planar layer PLN2 covers the second source and drain layer SD2. The first source and drain layer SD1 and the second source and drain layer SD2 are used to realize connection between at least part of the thin film transistors and between the thin film transistors and the capacitors, and are used to transmit drive signals. The type of drive signal and the specific pattern of each film layer depend on the specific structure of the drive circuit, and are not specifically limited here.

[0058] In some other embodiments of the present disclosure, there is one source / drain layer, which may be disposed on a surface of the interlayer dielectric layer ILD away from the substrate SU. There is one planar layer, and the planar layer covers the source / drain layer.

[0059] In other embodiments of the present disclosure, the number of source and drain layers and planar layers is three, namely, a first source and drain layer, a first planar layer, a second source and drain layer, a second planar layer, a third source and drain layer and a third planar layer. The first source and drain layer can be arranged on the surface of the interlayer dielectric layer away from the substrate SU, the first planar layer covers the first source and drain layer, and the first planar layer can cover the first source and drain layer; the second source and drain layer can be arranged on the surface of the first planar layer away from the substrate SU, and the second planar layer covers the second source and drain layer; the third source and drain layer can be arranged on the surface of the second planar layer away from the substrate SU, and the third planar layer covers the third source and drain layer.

[0060] Any source / drain layer may be a single layer or a multi-layer structure, and if a multi-layer structure is adopted, the source / drain layer may include multiple conductive layers. Figure 2 As shown, in some embodiments, the source-drain layer includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence in a direction away from the substrate SU. The first conductive layer and the third conductive layer may be made of the same material, which may be a chemically stable, corrosion-resistant metal or metal oxide conductive material. The material of the second conductive layer is different from the materials of the first conductive layer and the third conductive layer. The second conductive layer may be made of a material with a lower resistivity than the first conductive layer and the third conductive layer, so that the second conductive layer can be protected by the first conductive layer and the third conductive layer, and the conductive requirement is met by the second conductive layer. For example, the materials of the first conductive layer and the third conductive layer are Ti (titanium), and the material of the second conductive layer is AL (aluminum).

[0061] like Figure 2 As shown, the above circuit layer can be divided into a transistor layer DL and a connection layer CL, wherein:

[0062] The transistor layer DL may include the semiconductor layer SE, the first gate insulating layer GI1, the first gate layer GA1, the second gate insulating layer GI2, the second gate layer GA2 and the interlayer dielectric layer ILD; that is, the transistor layer DL includes the capacitor and the thin film transistor of the driving circuit.

[0063] The connection layer CL may include the source / drain layer and the planar layer, and the connection layer CL includes wiring connected to the thin film transistor and the capacitor, and the thin film transistor and the capacitor are connected to form a driving circuit through the wiring.

[0064] like Figure 2As shown, the light-emitting device LD can be arranged on the side of the connection layer CL away from the substrate SU. For example, the light-emitting device LD is arranged on the surface of the second flat layer PLN2 away from the substrate SU, and can be connected to the driving circuit. The light-emitting device LD can be an OLED (organic light-emitting diode) using organic light-emitting materials, or a Mini LED (sub-millimeter light-emitting diode, size 100μm-200μm), Micro LED (micro light-emitting diode, size not greater than 100μm) and LED (light-emitting diode, size greater than 200μm) using inorganic light-emitting materials, etc., without special limitation here, as long as it can emit light. The light-emitting device LD is located in the display area AA. Of course, in order to meet the uniformity of the process, some of the light-emitting devices LD can also be located in the peripheral area WA, but the light-emitting device LD located in the peripheral area WA can be floated and not emit light.

[0065] like Figure 2 As shown, taking the light emitting device LD as an OLED as an example, the light emitting device LD may include a first electrode ANO, a light emitting layer EL, and a second electrode CAT sequentially stacked in a direction away from the substrate SU. By applying an electrical signal to the first electrode ANO and the second electrode CAT, the light emitting layer EL may be stimulated to emit light. The specific light emitting principle is not described in detail here. The first electrode ANO may be used as an anode, and the second electrode CAT may be used as a cathode. The materials of the two may include conductive materials such as metals and metal oxides.

[0066] The light-emitting layer EL may include a plurality of light-emitting sublayers stacked in sequence in a direction away from the driving backplane BP, and the light-emitting sublayers include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer and an electron injection layer. Of course, other structures may also be used as long as they can cooperate with the first electrode ANO and the second electrode CAT to emit light. For example, the light-emitting layer EL may include a plurality of groups of light-emitting sublayers, a group of light-emitting sublayers may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer and an electron injection layer, and two adjacent groups of light-emitting sublayers may be connected by a charge generation layer or other film layers, so that a light-emitting device LD may include a plurality of sub-light-emitting devices connected in series. Among them, the light-emitting material layer may be distributed in an array, and the hole injection layer, the hole transport layer, the electron transport layer and the electron injection layer may be distributed in an entire layer; or, each film layer of the light-emitting layer EL may be distributed in an entire layer.

[0067] like Figure 2As shown, the display panel may further include a pixel definition layer PDL separating the light emitting devices LD, which may be arranged on the same side of the driving backplane BP as the light emitting devices LD, for example, the pixel definition layer PDL may be arranged on the side of the connection layer CL away from the substrate SU and on the same surface as the first electrode ANO, for example, the first electrode ANO and the pixel definition layer PDL are arranged on the surface of the second flat layer PLN2 away from the substrate SU. The first electrodes ANO are distributed in an array, the thickness of the pixel definition layer PDL is greater than the thickness of the first electrodes ANO, and covers a partial area of ​​each first electrode ANO, and the pixel definition layer PDL has a pixel opening PH exposing each first electrode ANO, and one pixel opening PH exposes one first electrode ANO.

[0068] In addition, a plurality of support columns may be provided on the pixel definition layer PDL, which may be used to support the mask used when evaporating the light-emitting layer EL. The support columns may be made of organic materials such as resin, and each support column may include at least two support columns with different thicknesses.

[0069] like Figure 2 As shown, the light-emitting layer EL and the second electrode CAT are both full-layer structures, and the light-emitting layer EL and the second electrode CAT are sequentially stacked on the first electrode ANO in the pixel opening PH, and one pixel opening PH can define the range of a light-emitting device LD. In some embodiments, the light-emitting devices LD emit the same color. In this case, a color filter layer can be provided on the side of the light-emitting device LD away from the driving backplane BP, and a color display can be achieved by combining the light filtering effect of the color filter layer with the light-emitting device LD. Alternatively, in other embodiments, the light-emitting material layer of the light-emitting layer EL can be distributed in an array, and the other light-emitting sub-layers are distributed in a whole layer, so that the light-emitting colors of different light-emitting devices LD can be different.

[0070] like Figure 2 , Figure 3 and Figure 6 As shown, the light emitting device LD can be divided into a plurality of pixels, and one pixel includes a plurality of light emitting devices LD. For example, one pixel may include three light emitting devices LD. Different light emitting devices LD of the same pixel may emit light of different colors or correspond to color filters of different colors. Accordingly, the pixel opening PH can be divided into a plurality of opening groups HG, one opening group HG corresponds to one pixel, and one opening group HG may include a plurality of pixel openings PH. For example, one opening group HG may include three pixel openings PH.

[0071] Each pixel opening PH may be distributed in an array along the first direction Y and the second direction X, and correspondingly, each opening group HG is also distributed in an array along the first direction Y and the second direction X. Each pixel opening PH of the same opening group HG may be distributed along the first direction Y. In some embodiments, the distance between two adjacent opening groups HG may be greater than the distance between two adjacent pixel openings PH in the same opening group HG. The first direction Y is perpendicular to the second direction X.

[0072] like Figure 2-Figure 5 As shown, the encapsulation layer TFE can cover each second electrode CAT to block external water vapor and oxygen to prevent the light-emitting device LD from being corroded. In some embodiments of the present disclosure, the encapsulation layer TFE can be encapsulated in a thin film manner, which may include a first inorganic layer CVD1, an organic layer IJP and a second inorganic layer CVD2, wherein:

[0073] The first inorganic layer CVD1 may cover each light emitting device LD, that is, the first inorganic layer CVD1 may cover the surface of the second electrode CAT away from the driving backplane BP. The material of the first inorganic layer CVD1 may include inorganic insulating materials such as silicon nitride and silicon oxide. The first inorganic layer CVD1 may be a whole layer structure, which may extend to the peripheral area WA.

[0074] The organic layer IJP may be disposed on the surface of the first inorganic layer CVD1 away from the driving backplane BP, and the boundary of the orthographic projection of the organic layer IJP on the driving backplane BP may be located in the peripheral area WA to ensure that the organic layer IJP can cover each light emitting device LD.

[0075] The second inorganic layer CVD2 can cover the organic layer IJP and the first inorganic layer CVD1 not covered by the organic layer IJP, and can block water and oxygen intrusion through the second inorganic layer CVD2, and achieve planarization through the organic layer IJP having fluidity before curing. The material of the second inorganic layer CVD2 may include inorganic insulating materials such as silicon nitride and silicon oxide.

[0076] In addition, if Figure 4 As shown, in order to limit the position of the organic layer IJP and prevent it from contacting the outside, an outer barrier dam Dam1 located in the peripheral area WA can be provided on the connection layer CL, and the outer barrier dam Dam1 is a ring structure provided around the display area AA. The outer barrier dam Dam1 can be provided on the surface of the connection layer CL away from the substrate SU, and at least part of the outer barrier dam Dam1 can be provided in the same layer as the pixel definition layer PDL so as to be formed at the same time and simplify the process; for example, the outer barrier dam Dam1 can include two layers of barrier structures, one layer of barrier structure is provided in the same layer as the pixel definition layer PDL, and the other layer is provided in the same layer as the above-mentioned support column. Of course, the outer barrier dam Dam1 can also have a barrier structure in the same layer as the flat layer, and the structure of the outer barrier dam Dam1 is not specifically limited here.

[0077] The first inorganic layer CVD1 can cover the outer barrier dam Dam1 and protrude in the area corresponding to the outer barrier dam Dam1. The organic layer IJP can be limited to the side of the outer barrier dam Dam1 close to the display area AA, that is, the inner side of the outer barrier dam Dam1. The second inorganic layer CVD2 can cover the organic layer IJP with the first inorganic layer CVD1 to prevent it from contacting the outside world, which is beneficial to prevent water and oxygen corrosion. The number of the outer barrier dam Dam1 can be one or more, and if multiple outer barrier dams Dam1 are used, they can be arranged in concentric rings.

[0078] In addition, the light-emitting layer EL made of organic light-emitting materials is easily corroded by water, oxygen and other impurities. If the light-emitting layer EL is continuously extended, the external water vapor and oxygen may corrode along the light-emitting layer EL toward the display area AA, affecting the light-emitting device LD in the display area AA. At the same time, for the entire structure light-emitting layer EL, there is not only a current between the first electrode ANO and the second electrode CAT, but also a lateral current, which leads to crosstalk between adjacent light-emitting devices LD and causes display abnormality.

[0079] In some embodiments of the present disclosure, an isolation column may be provided on the connection layer CL, and the isolation column may include an inner isolation column located in the display area AA and an outer isolation column located in the peripheral area WA, and the side wall of each isolation column is concave. In order to make the voltage of the second electrode CAT of each light-emitting device LD the same and to prevent the second electrode CAT from being affected by static electricity, it is necessary to ensure that the second electrode CAT is cut off in the peripheral area WA and is a whole in the display area AA. Therefore, the thickness of the inner isolation column is smaller than that of the outer isolation column, and the depth of the concave side wall of the inner isolation column is also smaller than the depth of the concave side wall of the outer isolation column, so that the inner isolation column only cuts off the light-emitting layer EL, and the second electrode CAT is continuous on the side wall of the inner isolation column, and the outer isolation column can cut off the light-emitting layer EL and the second electrode CAT.

[0080] However, in order to meet the needs of different stages, the processes of the inner and outer isolation columns are different and need to be formed separately, resulting in high process costs and low production efficiency.

[0081] In order to reduce costs and improve efficiency while preventing crosstalk and erosion, such as Figure 2-Figure 6 As shown, the inventors propose that an isolation groove SC recessed toward the substrate SU may be provided in the connection layer CL, and each isolation groove SC may be formed simultaneously by the same process, so as to simplify the process, improve efficiency and reduce cost.

[0082] In some embodiments of the present disclosure, an isolation groove SC may be provided in the second flat layer PLN2. The isolation groove SC may be recessed from the surface of the second flat layer PLN2 away from the substrate SU toward the substrate SU and at least penetrate the second flat layer PLN2. The isolation groove SC may expose the surface of the first flat layer PLN1 away from the substrate SU or extend into the first flat layer PLN1 and may or may not penetrate the first flat layer PLN1.

[0083] The isolation groove SC may include an inner isolation groove SC1 located in the display area AA and an outer isolation groove SC2 located in the peripheral area WA, and any inner isolation groove SC1 is disposed between two adjacent pixel openings PH. The sidewalls of each isolation groove SC are concave, so that the light-emitting layer EL is disconnected at the sidewalls of the isolation groove SC, thereby cutting off the light-emitting layer EL between two adjacent pixel openings PH, blocking the conduction path of the lateral current, and preventing crosstalk between adjacent light-emitting devices LD.

[0084] Furthermore, the second electrode CAT is also cut off at the sidewall of the inner isolation groove SC1. The inner isolation groove SC1 is not a ring structure surrounding the pixel opening PH, that is, the inner isolation groove SC1 does not completely surround the pixel opening PH, ensuring that the second electrode CAT of each light emitting device LD is an integrated structure.

[0085] like Figure 4 As shown, the outer isolation groove SC2 may be an annular structure surrounding the display area AA, which may use the concave sidewall to cut off at least part of the light-emitting sublayer of the light-emitting layer EL and the second electrode CAT, cut off the corrosion path of external water vapor and oxygen, reduce the risk of corrosion of the light-emitting device LD, and improve the packaging effect. The number of the outer isolation grooves SC2 may be one or more, and if multiple outer isolation grooves SC2 are used, they may be distributed in concentric rings and distributed on both sides of the outer barrier dam Dam1.

[0086] like Figure 1 and Figure 5 As shown, in some embodiments of the present disclosure, the display panel is further provided with an opening Ho, which may or may not completely penetrate the display panel. A camera device opposite to the opening Ho may be provided on the backlight side of the display panel, and the camera device may capture an image through the opening Ho. The boundary of the opening Ho may be located inside the boundary of the display area AA, or the boundary of the opening Ho may partially overlap with the boundary of the display area AA.

[0087] There may be a transition area CA between the display area AA and the opening Ho, and the transition area CA may be located outside the opening Ho and does not emit light. In some embodiments of the present disclosure, the boundary of the opening Ho is at a certain distance from the boundary of the display area AA, and the transition area CA is an annular area surrounding the opening Ho, and the display area AA is surrounded by the transition area CA. The light-emitting layer EL, the second electrode CAT and the encapsulation layer TFE may extend into the transition area CA, and an inner barrier dam Dam2 may be provided in the transition area CA, the first inorganic layer CVD1 covers the inner barrier dam Dam2, and the organic layer IJP may be limited between the inner barrier dam Dam2 and the outer barrier dam Dam1.

[0088] like Figure 5 As shown, the isolation groove SC may include a transition isolation groove SC3 located in the transition area CA, and the light-emitting layer EL is disconnected at the side wall of the transition isolation groove SC3 to prevent external water vapor and oxygen from invading the display area AA from the opening Ho. Further, the second electrode CAT may also be disconnected at the side wall of the transition isolation groove SC3. At the same time, there may be multiple transition isolation grooves SC3 in the transition area CA, and they are distributed on both sides of the inner barrier dam Dam2, that is, transition isolation grooves SC3 are provided between the inner barrier dam Dam2 and the opening Ho and between the inner barrier dam Dam2 and the display area AA. Each transition isolation groove SC3 may be annular and arranged around the opening Ho.

[0089] like Figure 2-Figure 5 As shown, there are various structures of the concave sidewall of the isolation trench SC, for example:

[0090] In some embodiments of the present disclosure, the isolation groove SC may include a first section SC11 and a second section SC12 that are sequentially connected in a direction close to the substrate SU, and the first section SC11 is located on a side of the second section SC12 that is away from the substrate SU. The boundary of the orthographic projection of the second section SC12 on the substrate SU is located outside the boundary of the orthographic projection of the first section SC11 on the substrate SU, so that the first section SC11 is narrower, and the second section SC12 is at least partially wider, and the first section SC11 forms a cantilever structure on the top of the second section SC12, so that the light-emitting layer EL and the second electrode CAT are disconnected at the side wall of the isolation groove SC and cannot extend continuously. The second section SC12 can shrink or expand in a direction close to the substrate SU.

[0091] Furthermore, to ensure that the isolation groove SC can cut off the light emitting layer EL, the depth of the isolation groove SC is greater than the thickness of the light emitting layer EL. If the second electrode CAT is to be cut off, the depth of the isolation groove SC is greater than the sum of the light emitting layer EL and the second electrode CAT.

[0092] In other embodiments of the present disclosure, the sidewall of the isolation trench SC may expand in a direction close to the substrate SU to form a trapezoidal cross section, and may also serve to cut off the light emitting layer EL and the second electrode CAT.

[0093] The distribution of the inner isolation grooves SC1 is described below by way of example:

[0094] like Figure 6 As shown, in some embodiments of the present disclosure, the distance between two adjacent opening groups HG may be greater than the distance between two adjacent pixel openings PH in the same opening group HG, and the inner isolation groove SC1 may not be set between the two adjacent opening groups HG, but only between two adjacent pixel openings PH in the same opening group HG, and one inner isolation groove SC1 is set between two adjacent pixel openings PH in the same opening group HG, so that the light-emitting layer EL between the two adjacent pixel openings PH is cut off by the inner isolation groove SC1, and the conduction path of the lateral current between the two adjacent light-emitting devices LD is cut off, thereby improving the crosstalk between the two adjacent light-emitting devices LD in the same pixel. At the same time, the second electrode CAT may also be disconnected at the side wall of the inner isolation groove SC1. The distance between two adjacent opening groups HG is the distance between the boundaries of two pixel openings PH in the two adjacent opening groups HG. For example, the distance between two adjacent opening groups HG in the first direction Y is the distance between the two pixel openings PH in the two adjacent opening groups HG that are closest to each other in the first direction Y; the distance between two adjacent opening groups HG in the second direction X is the distance between the two pixel openings PH in the two adjacent opening groups HG that are closest to each other in the second direction X.

[0095] Of course, in other embodiments of the present disclosure, an inner isolation groove SC may be provided between any two adjacent pixel openings PH, that is, an inner isolation groove SC may be provided between two adjacent opening groups HG and between two adjacent pixel openings PH of the same opening group HG.

[0096] like Figure 6 As shown, in some embodiments of the present disclosure, each pixel opening PH of the same opening group HG may be distributed along the first direction Y, and the inner isolation groove SC1 between two adjacent pixel openings PH may extend in a straight line along the second direction X, and the length of the inner isolation groove SC1 in the second direction X is greater than or equal to the length of the pixel opening PH in the second direction X, ensuring that the path of lateral current conduction between two adjacent light-emitting devices LD is cut off.

[0097] In addition, the inner isolation grooves SC1 between two adjacent rows of pixel openings PH are arranged in a straight line along the second direction X and are spaced apart, that is, the inner isolation grooves SC1 located in two adjacent opening groups HG are spaced apart and not connected. Further, the width of the inner isolation grooves SC1 in the first direction Y is smaller than the width of the pixel opening PH in the first direction Y.

[0098] When the above-mentioned isolation groove SC is formed in the connection layer CL, the isolation groove SC can be formed by using a mask layer in cooperation with at least one etching process. For example, an inorganic material such as silicon nitride can be used to form a patterned mask on the connection layer CL, and the area where the isolation groove SC needs to be formed is hollowed out to expose the connection layer CL. The exposed connection layer CL is then etched by a dry etching process, and the above-mentioned isolation groove SC with concave side walls is formed by both isotropic and anisotropic etching methods. The specific process is not particularly limited here.

[0099] like Figure 2 and Figure 6 As shown, in some embodiments of the present disclosure, the display panel further includes an auxiliary electrode AE, which may be disposed on a surface of the connection layer CL away from the substrate SU and spaced apart from the first electrode ANO, that is, the auxiliary electrode AE ​​and the first electrode ANO are disposed in the same layer and may be formed simultaneously by the same process, for example, the auxiliary electrode AE ​​and the first electrode ANO may be disposed on a surface of the second planar layer PLN2 away from the substrate SU. Of course, the first electrode ANO and the auxiliary electrode AE ​​may also be formed separately and independently.

[0100] The pixel definition layer PDL is provided with auxiliary openings AH exposing the auxiliary electrodes AE, and one auxiliary opening AH exposes one auxiliary electrode AE, that is, each auxiliary opening AH exposes each auxiliary electrode AE ​​in a one-to-one correspondence. The pixel definition layer PDL covers a portion of the edge of the auxiliary electrode E, so that the boundary of the bottom of the auxiliary opening AH is located inside the boundary of the auxiliary electrode AE ​​exposed by it.

[0101] The light-emitting layer EL is disconnected at the auxiliary opening AH, that is, the light-emitting layer EL is not formed in the auxiliary opening AH. For example, the light-emitting layer EL can be patterned using a mask, and the auxiliary opening AH can be hollowed out to cut off the lateral current of adjacent pixels. The second electrode CAT is in direct contact with the auxiliary electrode AE ​​in the auxiliary opening AH. At the same time, the auxiliary electrode AE ​​can be connected to the driving circuit, and the driving circuit transmits the same signal to the auxiliary electrode AE ​​as the signal transmitted to the second electrode CAT by the peripheral circuit, so that the auxiliary electrode AE ​​can be used as a part of the second electrode CAT, so that the area of ​​the second electrode CAT can be increased by the auxiliary electrode AE, which is conducive to reducing the impedance; and if the isolation groove SC cuts off the second electrode CAT, the second electrode CAT can be connected through the auxiliary electrode AE ​​to ensure the integrity of the second electrode CAT and the uniformity of the signal, thereby reducing the impedance.

[0102] like Figure 6As shown, the auxiliary electrode AE ​​can be arranged between two adjacent opening groups HG, while the auxiliary electrode AE ​​is not arranged between adjacent pixel openings PH in the same opening group HG, that is, the auxiliary electrode AE ​​can be arranged between two adjacent pixels, while the auxiliary electrode AE ​​is not arranged between the light emitting devices LD of the same pixel. Correspondingly, the auxiliary opening AH can be arranged between two adjacent pixels, while the auxiliary opening AH is not arranged between the light emitting devices LD of the same pixel.

[0103] Of course, the present disclosure does not exclude the provision of auxiliary electrodes AE between adjacent pixel openings PH in the same opening group HG.

[0104] In some embodiments, an auxiliary electrode AE ​​may be disposed between two adjacent opening groups HG. Figure 6 As shown, an auxiliary opening AH is provided between two adjacent opening groups HG. The auxiliary opening AH may include a first auxiliary opening AH1 extending along the second direction X and a second auxiliary opening AH2 extending along the first direction Y, wherein the first auxiliary opening AH1 is distributed between two adjacent opening groups HG in the first direction Y; and the second auxiliary opening AH2 is distributed between two adjacent opening groups HG in the second direction X. In addition, any two auxiliary openings AH are arranged at intervals, that is, any two auxiliary openings AH are not connected.

[0105] Further, such as Figure 6 As shown, in some embodiments of the present disclosure, the length of the first auxiliary opening AH1 in the second direction X is greater than the length of the opening group HG in the second direction X; at the same time, the length of the second auxiliary opening AH2 in the first direction Y is greater than the length of the opening group HG in the first direction Y.

[0106] The embodiments of the present disclosure further provide a display device, which may include the display panel of any of the above embodiments. The specific structure and beneficial effects of the display panel can be referred to the embodiments of the display panel above, and will not be described in detail here.

[0107] Furthermore, for the display panel having the opening Ho, it may also include a camera device, which may be arranged on a side of the substrate SU away from the light-emitting device LD and overlap with the opening Ho, and can capture images through the opening Ho.

[0108] The display device disclosed in the present invention may be a tablet computer, a notebook computer, or may be used in a mobile phone or other electronic devices with display functions, which are not listed here one by one.

[0109] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel comprising a display area and a peripheral area outside the display area; characterized in that: The display panel comprises: substrate; A transistor layer, disposed on one side of the substrate; A connection layer is provided on a surface of the transistor layer away from the substrate; the connection layer is provided with a plurality of isolation grooves, the sidewalls of the isolation grooves are concave; the isolation grooves include inner isolation grooves located in the display area and outer isolation grooves located in the peripheral area; A plurality of first electrodes are distributed in an array on a surface of the connection layer away from the substrate and located in the display area; A pixel definition layer is disposed on the same surface of the connection layer as the first electrode and is provided with a pixel opening for exposing each of the first electrodes; the inner isolation groove is disposed between two adjacent pixel openings; a light-emitting layer, covering the pixel definition layer and the first electrode, wherein the light-emitting layer is disconnected at a side wall of the isolation groove; The second electrode covers the light-emitting layer.

2. The display panel according to claim 1, characterized in that: The pixel openings are divided into a plurality of opening groups, one of the opening groups includes a plurality of the pixel openings, and an inner isolation groove is disposed between two adjacent pixel openings in the same opening group.

3. The display panel according to claim 2, characterized in that: The pixel openings of the same opening group are distributed along the first direction, the inner isolation groove between two adjacent pixel openings extends along the second direction, and the length of the inner isolation groove in the second direction is not less than the length of the pixel opening in the second direction; The first direction is perpendicular to the second direction.

4. The display panel according to claim 1, characterized in that: The display panel further includes: An outer barrier dam is provided on a side of the connection layer away from the substrate and located in the peripheral area; the light emitting layer and the second electrode cover the outer barrier dam; and the outer isolation grooves are distributed on both sides of the outer barrier dam; The encapsulation layer includes a first inorganic layer, an organic layer and a second inorganic layer, wherein the first inorganic layer covers the second electrode and extends to the peripheral area, the organic layer is arranged on the surface of the first inorganic layer away from the substrate and is limited to a side of the outer blocking dam close to the display area, and the second inorganic layer covers the organic layer and the first inorganic layer.

5. The display panel according to claim 1, characterized in that: The isolation trench comprises a first section and a second section which are connected in sequence, the first section is located on a side of the second section away from the substrate, and a boundary of an orthographic projection of the second section on the substrate is located outside a boundary of an orthographic projection of the first section on the substrate.

6. The display panel according to claim 3, characterized in that: The display panel further includes: an auxiliary electrode, disposed on a surface of the connection layer away from the substrate and spaced apart from the first electrode; The pixel definition layer is provided with an auxiliary opening exposing the auxiliary electrode, the light emitting layer is disconnected at the auxiliary opening, and the second electrode is stacked with the auxiliary electrode in the auxiliary opening.

7. The display panel according to claim 6, characterized in that: The auxiliary opening is arranged between two adjacent opening groups.

8. The display panel according to claim 7, characterized in that: Each of the opening groups is distributed along the first direction and the second direction; The auxiliary openings include first auxiliary openings extending along the second direction and second auxiliary openings extending along the first direction, the first auxiliary openings are distributed between the adjacent opening groups in the first direction; the second auxiliary openings are distributed between the adjacent opening groups in the second direction.

9. The display panel according to claim 8, characterized in that: The length of the first auxiliary opening in the second direction is greater than the length of the opening group in the second direction; A length of the second auxiliary opening in the first direction is greater than a length of the opening group in the first direction.

10. The display panel according to claim 8, characterized in that: Any two of the auxiliary openings are arranged at intervals.

11. The display panel according to claim 1, characterized in that: The display panel is provided with an opening, and the display panel further comprises a transition area surrounding the opening, and the display area is located outside the transition area; The isolation trench further includes a transition isolation trench, the transition isolation trench is located in the transition region, and the light-emitting layer is disconnected at a side wall of the transition isolation trench.

12. The display panel according to any one of claims 1 to 10, characterized in that: The connection layer includes at least one source-drain layer and a planar layer covering the source-drain layer, and the isolation trench is located in the planar layer.

13. The display panel according to claim 12, characterized in that: The source-drain layer includes a first source-drain layer and a second source-drain layer, and the planar layer includes a first planar layer and a second planar layer; The first source-drain layer is provided on a surface of the transistor layer away from the substrate, and the first flat layer covers the first source-drain layer; the second source-drain layer is provided on a surface of the first flat layer away from the substrate, and the second flat layer covers the second source-drain layer; the isolation trench at least penetrates the second flat layer; The first electrode is disposed on a surface of the second planar layer away from the substrate.

14. A display device, characterized in that: A display panel comprising any one of claims 1-13.

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