Field effect transistor

Abstract

Insulation breakdown of a gate insulating film is suppressed when a current diffusion n-layer is provided. A field effect transistor has a semiconductor substrate having a trench in an upper surface, a gate insulating film, and a gate electrode. The semiconductor substrate has a p-type bulk layer and a lower n-layer disposed on the lower side of the bulk layer. The lower n-layer has: a current diffusion n-layer which is in contact with the bulk layer from the lower side; and a low-concentration n-layer which is in contact with the current diffusion n-layer from below and which has a lower n-type impurity concentration than the current diffusion n-layer. The inner surface of the trench has: a side surface comprising a surface having a radius of curvature of 0.7 [mu] m or more; and a bottom connection surface which connects the side surface and the lower end of the trench and which is composed of a concave curved surface having a radius of curvature of less than 0.7 [mu] m. A peak portion of the current diffusion n layer is in contact with the gate insulating film at the side surface.

Description

Technical Field

[0001] (Cross-reference of related applications)

[0002] This application is a related application of Japanese patent application No. 2022-135237 filed on August 26, 2022, and claims the priority based on the Japanese patent application. All the contents described in the Japanese patent application are cited as the contents constituting the present specification.

[0003] The technology disclosed in this specification relates to a field effect transistor. Background Art

[0004] The field effect transistor disclosed in Japanese Patent Publication No. 2008-235546 has a trench-type gate electrode. In addition, the field effect transistor has an n-type source layer, a p-type body layer, and a lower n-layer arranged on the lower side of the body layer in the range connected to the gate insulating film. If a predetermined potential is applied to the gate electrode, a channel is formed in the body layer, and the source layer is connected to the lower n-layer in the channel. As a result, the field effect transistor is turned on. Summary of the invention

[0005] There is a case where a current diffusion n layer with a high n-type impurity concentration is provided in a range adjacent to the body layer in the lower n layer. According to this structure, electrons flowing from the channel into the lower n layer diffuse in the lateral direction in the current diffusion n layer. Therefore, the current easily diffuses and flows in the region (so-called drift layer) below the current diffusion n layer in the lower n layer, and the on-resistance of the field effect transistor is reduced. However, if a current diffusion n layer is provided, a high electric field is easily generated in the gate insulating film in the range adjacent to the current diffusion n layer. In this specification, a technology for suppressing insulation breakdown of the gate insulating film when a current diffusion n layer is provided is proposed.

[0006] The field effect transistor disclosed in this specification comprises: a semiconductor substrate having a groove on the upper surface; a gate insulating film covering the inner surface of the groove; and a gate electrode arranged in the groove and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate comprises: an n-type source layer in contact with the gate insulating film; a p-type body layer in contact with the gate insulating film on the lower side of the source layer; and a lower n-layer arranged on the lower side of the body layer. The lower n-layer comprises: a current diffusion n-layer in contact with the body layer from the lower side; and a low-concentration n-layer in contact with the current diffusion n-layer from the lower side and having a lower n-type impurity concentration than that of the current diffusion n-layer. The n-type impurity concentration distribution in the current diffusion n-layer in the depth direction of the semiconductor substrate is distributed in a manner having a peak. The inner surface of the groove has a side surface, which is a surface having a curvature radius of 0.7 μm or more, and a bottom connection surface, which is a concave curved surface connecting the side surface to the lower end of the groove and having a curvature radius of less than 0.7 μm. The portion of the current diffusion n layer having the peak value is in contact with the gate insulating film at the side surface.

[0007] The gate insulating film in the range covered by the bottom connection surface is easily applied with a higher electric field. Therefore, if the high-concentration n-layer is in contact with the gate insulating film in the range covered by the bottom connection surface, the gate insulating film in this range is easily applied with an excessively high electric field, and the gate insulating film is easily dielectrically broken down. In contrast, in the field effect transistor disclosed in this specification, the portion with a peak value of the current diffusion n-layer is in contact with the gate insulating film at the side of the groove. The side of the groove is composed of a relatively flat surface with a curvature radius of more than 0.7μm. Therefore, even if the portion with a peak value of the current diffusion n-layer is in contact with the gate insulating film at the side of the groove, the electric field applied to the gate insulating film can be prevented from being too high. Therefore, in this field effect transistor, the gate insulating film is not easy to be dielectrically broken down. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a cross-sectional perspective view of the MOSFET of Example 1.

[0009] Figure 2 This is an enlarged cross-sectional view of the upper portion of the MOSFET of Example 1.

[0010] Figure 3 This is an enlarged cross-sectional view of the upper portion of the MOSFET of Example 2.

[0011] Figure 4 This is an enlarged cross-sectional view of the upper portion of the MOSFET of Example 3.

[0012] Figure 5 This is an enlarged cross-sectional view of the upper portion of the MOSFET of Example 4.

[0013] Figure 6 This is an enlarged cross-sectional view of the upper portion of the MOSFET of Example 5. DETAILED DESCRIPTION

[0014] In the above-mentioned field effect transistor, the current diffusion n-layer may not be in contact with the gate insulating film at the bottom connection surface.

[0015] According to this structure, insulation breakdown of the gate insulating film can be suppressed more effectively.

[0016] The field effect transistor may further include a bottom p-layer in contact with the gate insulating film at the lower end of the trench.

[0017] According to this structure, the electric field acting on the gate insulating film in the vicinity of the lower end of the trench can be suppressed.

[0018] In the field effect transistor, the bottom p layer may be in contact with the current diffusion n layer in a range in contact with the gate insulating film. The current diffusion n layer between the body layer and the bottom p layer may have a thickness of 0.1 μm or more.

[0019] According to this structure, the body layer and the bottom p layer can be reliably separated by the current diffusion n layer.

[0020] Example 1

[0021] Figure 1 , Figure 2 The MOSFET (metal-oxide-semiconductor field effect transistor) 10 shown in the figure has a semiconductor substrate 12. Figure 1 , Figure 2In the figure, the x direction is a direction parallel to the upper surface 12a of the semiconductor substrate 12, and the y direction is a direction parallel to the upper surface 12a and orthogonal to the x direction. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may also be made of other semiconductors such as Si and GaN. A plurality of grooves 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each groove 14 extends in the y direction in the upper surface 12a. The grooves 14 are arranged at intervals in the x direction. The inner surface of each groove 14 is covered by a gate insulating film 16. A gate electrode 18 is arranged in each groove 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is covered by an interlayer insulating film 20. A source electrode 22 is arranged on the upper part of the semiconductor substrate 12. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. The gate electrode 18 is insulated from the source electrode 22 by the interlayer insulating film 20. The lower surface 12 b of the semiconductor substrate 12 is covered with a drain electrode 24 .

[0022] like Figure 2 As shown, the groove 14 has a side surface 14a, a bottom connection surface 14b and a bottom surface 14c. The side surface 14a is a flat surface extending along the depth direction (i.e., thickness direction) of the semiconductor substrate 12 (more specifically, a surface having a curvature radius of 0.7 μm or more in a cross section). The bottom surface 14c is a surface extending substantially parallel to the upper surface 12a of the semiconductor substrate 12, and constitutes the lower end of the groove 14. The bottom connection surface 14b is a concave curved surface connecting the lower end of the side surface 14a and the bottom surface 14c. In the cross section, the curvature radius of the bottom connection surface 14b is less than 0.7 μm.

[0023] The semiconductor substrate 12 has a source layer 30 , a body contact layer 32 , a body layer 34 , a bottom p layer 36 , a connecting p layer 38 , and a lower n layer 40 .

[0024] The source layer 30 is an n-type layer, and is in contact with the gate insulating film 16 at the upper end of the side surface 14a of the trench 14. The source layer 30 is in ohmic contact with the source electrode 22.

[0025] The body contact layer 32 is a p-type layer and is in ohmic contact with the source electrode 22 at a position adjacent to the source layer 30 .

[0026] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the body contact layer 32. The body layer 34 is in contact with the source layer 30 and the body contact layer 32 from the lower side. The body layer 34 is in contact with the gate insulating film 16 on the lower side of the source layer 30. The body layer 34 is in contact with the gate insulating film 16 in the side surface 14a of the trench 14.

[0027] The bottom p layer 36 is a p-type layer, and is in contact with the gate insulating film 16 at the bottom surface 14c of the trench 14. The bottom p layer 36 extends along the bottom surface 14c of the trench 14 in the y direction.

[0028] The connection p layer 38 is a p-type layer and protrudes downward from the body layer 34. When the semiconductor substrate 12 is viewed from above, the connection p layer 38 extends linearly along the x direction. The connection p layer 38 extends to the depth of the bottom p layer 36 in the depth direction. The connection p layer 38 connects the body layer 34 and the bottom p layer 36.

[0029] The lower n layer 40 is arranged on the lower side of the body layer 34. The lower n layer 40 is separated from the source layer 30 by the body layer 34. The lower n layer 40 is distributed from the lower end of the body layer 34 to the lower surface 12b of the semiconductor substrate 12. The lower n layer 40 includes a current diffusion n layer 40a, an electric field relaxation n layer 40b, a drift layer 40c, a buffer layer 40d and a drain layer 40e.

[0030] The current diffusion n-layer 40a is an n-type layer having a relatively high n-type impurity concentration. The current diffusion n-layer 40a is in contact with the body layer 34 from the bottom. The current diffusion n-layer 40a is in contact with the gate insulating film 16 on the bottom side of the body layer 34.

[0031] The electric field relaxation n-layer 40b is an n-type layer having a lower n-type impurity concentration than the current diffusion n-layer 40a. The electric field relaxation n-layer 40b is in contact with the current diffusion n-layer 40a from the bottom. The electric field relaxation n-layer 40b is distributed from the lower end of the current diffusion n-layer 40a to a position below the bottom p-layer 36. The electric field relaxation n-layer 40b is in contact with the gate insulating film 16 on the lower side of the current diffusion n-layer 40a. The electric field relaxation n-layer 40b is in contact with the side surface and the bottom surface of the bottom p-layer 36.

[0032] The drift layer 40c is an n-type layer having a lower n-type impurity concentration than the electric field relaxation n-layer 40b. The drift layer 40c is in contact with the electric field relaxation n-layer 40b from below.

[0033] The buffer layer 40d is an n-type layer having a higher n-type impurity concentration than the drift layer 40c. The buffer layer 40d is in contact with the drift layer 40c from the bottom.

[0034] The drain layer 40 e is an n-type layer having a higher n-type impurity concentration than the buffer layer 40 d . The drain layer 40 e is in contact with the buffer layer 40 d from below. The drain layer 40 e is in ohmic contact with the drain electrode 24 .

[0035] like Figure 2As shown, in the current diffusion n-layer 40a, the n-type impurity concentration is distributed in a normal distribution in the depth direction of the semiconductor substrate 12. In the current diffusion n-layer 40a, the n-type impurity concentration is distributed in a manner having a peak value nmax in the depth direction of the semiconductor substrate 12. In other words, the region where the n-type impurity concentration is distributed in a normal distribution in a manner having a peak value nmax is the current diffusion n-layer 40a. In the electric field relaxation n-layer 40b, the n-type impurity concentration is distributed at a substantially constant value at a value lower than that in the current diffusion n-layer 40a. In the drift layer 40c, the n-type impurity concentration is distributed at a substantially constant value at a value lower than that in the electric field relaxation n-layer 40b.

[0036] The portion of the current diffusion n-layer 40a having the peak value nmax is in contact with the gate insulating film 16 at the side surface 14a of the trench 14 (i.e., the surface having a curvature radius of 0.7 μm or more). In Embodiment 1, the entire current diffusion n-layer 40a is in contact with the gate insulating film 16 at the side surface 14a of the trench 14. That is, the current diffusion n-layer 40a is not in contact with the gate insulating film 16 at the bottom connection surface 14b of the trench 14. The electric field relaxation n-layer 40b is in contact with the gate insulating film 16 in the range between the current diffusion n-layer 40a and the bottom p-layer 36. The electric field relaxation n-layer 40b is in contact with the gate insulating film 16 at the bottom connection surface 14b.

[0037] When the MOSFET 10 is used, a higher potential than that of the source electrode 22 is applied to the drain electrode 24. In addition, the potential of the gate electrode 18 is controlled independently of the potentials of the drain electrode 24 and the source electrode 22. If a potential higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the range adjacent to the gate insulating film 16 in the body layer 34, and the source layer 30 is connected to the current diffusion n layer 40a through the channel. As a result, electrons flow from the source layer 30 to the drain layer 40e via the channel, the current diffusion n layer 40a, the electric field relaxation n layer 40b, the drift layer 40c, and the buffer layer 40d. As a result, the MOSFET 10 is turned on. The current diffusion n layer 40a has a relatively high n-type impurity concentration, so it has a low resistance. Therefore, the electrons flowing from the channel into the current diffusion n layer 40a are easy to flow along the x direction in the current diffusion n layer 40a. Therefore, in the drift layer 40c located below the current diffusion n layer 40a, electrons disperse in the x direction and flow toward the drain layer 40e. Since the electrons disperse and flow in the drift layer 40c, the on-resistance of the MOSFET 10 is low.

[0038] If the potential of the gate electrode 18 is reduced to a potential lower than the gate threshold, the channel disappears and the flow of electrons stops. That is, the MOSFET 10 is turned off. As a result, the depletion layer extends from the body layer 34 into the current diffusion n layer 40a, the electric field relaxation n layer 40b, and the drift layer 40c. The voltage between the drain electrode 24 and the source electrode 22 is maintained by the depletion layer extending into the current diffusion n layer 40a, the electric field relaxation n layer 40b, and the drift layer 40c. In addition, if the MOSFET 10 is turned off, the depletion layer also extends from the bottom p layer 36 to the electric field relaxation n layer 40b surrounding it. The electric field concentration near the lower end of the trench 14 is suppressed by the depletion layer extending from the bottom p layer 36.

[0039] When the current diffusion n-layer 40a and the electric field relaxation n-layer 40b are depleted, an electric field acts on the gate insulating film 16. The electric field is easily concentrated in the curved portion of the gate insulating film 16. That is, the electric field is more likely to be concentrated on the gate insulating film 16 covering the bottom connection surface 14b than on the gate insulating film 16 covering the side surface 14a. On the other hand, when the density of fixed charges existing in the depletion layer in contact with the gate insulating film 16 is high, the electric field acting on the gate insulating film 16 becomes high. That is, the higher the n-type impurity concentration of the n-type layer in contact with the gate insulating film 16, the higher the electric field acting on the gate insulating film 16. In this embodiment, the electric field relaxation n-layer 40b with a low n-type impurity concentration is in contact with the gate insulating film 16 at the bottom connection surface 14b where the electric field concentration is likely to occur. As a result, an excessively high electric field is prevented from acting on the gate insulating film 16 covering the bottom connection surface 14b, and insulation breakdown of the gate insulating film 16 is suppressed in this portion. In addition, the current diffusion n-layer 40a having a high n-type impurity concentration is connected to the gate insulating film 16 at the side surface 14a where electric field concentration is less likely to occur. Therefore, an excessively high electric field is prevented from acting on the gate insulating film 16 in the area where the current diffusion n-layer 40a is in contact, and insulation breakdown of the gate insulating film 16 is suppressed in this portion.

[0040] As described above, according to the MOSFET 10 of the present embodiment, it is possible to reduce the on-resistance of the MOSFET 10 by the current diffusion n-layer 40 a while suppressing the insulation breakdown of the gate insulating film 16 .

[0041] Example 2

[0042] exist Figure 3 In the MOSFET of the second embodiment shown, the thickness of the current diffusion n-layer 40a is thicker than that of the MOSFET 10 of the first embodiment. The other structures of the MOSFET of the second embodiment are equivalent to those of the MOSFET 10 of the first embodiment.

[0043] In the second embodiment, the lower end of the current diffusion n layer 40a is in contact with the gate insulating film 16 at the bottom connection surface 14b. However, the portion having the peak value nmax in the current diffusion n layer 40a is in contact with the gate insulating film 16 at the side surface 14a. That is, the portion having the peak value nmax is not in contact with the gate insulating film 16 at the bottom connection surface 14b, and the portion having a low n-type impurity concentration in the current diffusion n layer 40a is in contact with the gate insulating film 16 at the bottom connection surface 14b. Therefore, this structure can also suppress the electric field acting on the portion of the gate insulating film 16 covering the bottom connection surface 14b.

[0044] Example 3

[0045] The bottom p-layer 36 can be formed by ion implanting p-type impurities into the bottom of the trench 14 before forming the gate electrode 18. In this case, the bottom p-layer 36 can be formed as follows: Figure 4 The bottom p layer 36 is formed so that the bottom p layer 36 is in contact with the current diffusion n layer 40a from the lower side in the range in contact with the gate insulating film 16. In this structure, the bottom p layer 36 is in contact with the gate insulating film 16 in the entire bottom connection surface 14b. This structure can also reduce the electric field acting on the gate insulating film 16 covering the bottom connection surface 14b.

[0046] In addition, Figure 4 In the embodiment of the present invention, if the thickness T of the current diffusion n-layer 40a is too thin, the separation between the body layer 34 and the bottom p-layer 36 is insufficient, and the characteristics of the MOSFET deteriorate. In order to reliably separate the body layer 34 from the bottom p-layer 36, the thickness T of the current diffusion n-layer 40a between the body layer 34 and the bottom p-layer 36 can be made thicker than the width W of the depletion layer generated in the current diffusion n-layer 40a when no voltage is applied to the MOSFET. In addition, the width W of the depletion layer can be calculated by the following formula.

[0047] W=(2εVbi / qNd) -1 / 2

[0048] In the above formula, ε is the dielectric constant of the semiconductor substrate 12, Vbi is the built-in potential, q is the basic charge, and Nd is the n-type impurity concentration of the current diffusion n-layer 40a. The built-in potential Vbi can be calculated by the following formula.

[0049] Vbi=(kT / q)×ln(NaNd / ni 2 )

[0050] In the above formula, k is the Boltzmann constant, T is the temperature, Na is the p-type impurity concentration of the body layer 34 , and ni is the intrinsic carrier density.

[0051] More specifically, in Na=4×1017 cm -3 , Nd = 3 × 10 17 cm -3 , ni = 1 × 10 -8 cm -3 In the case of , the thickness T can be made 0.1 μm or more.

[0052] Example 4

[0053] exist Figure 5 In the MOSFET of the fourth embodiment shown, there is no electric field relaxation n-layer 40b, and the drift layer 40c is in contact with the current diffusion n-layer 40a from the bottom. The other structures of the MOSFET of the fourth embodiment are the same as the MOSFET 10 of the first embodiment. In the fourth embodiment, the drift layer 40c having a lower n-type impurity concentration than the electric field relaxation n-layer 40b is in contact with the gate insulating film 16 at the bottom connection surface 14b. Therefore, the electric field acting on the gate insulating film 16 covering the bottom connection surface 14b can be more effectively suppressed.

[0054] Example 5

[0055] exist Figure 6 In the MOSFET of the fifth embodiment shown, the bottom p layer 36 does not exist. In this case, the connection p layer 38 may not be provided. The other structures of the MOSFET of the fifth embodiment are the same as those of the MOSFET of the fourth embodiment. This structure can also suppress the electric field acting on the gate insulating film 16 covering the bottom connection surface 14b. In addition, in the first and second embodiments, the bottom p layer 36 may not be provided.

[0056] The electric field relaxation n-layer 40 b of Examples 1 to 3 and the drift layer 40 c of Examples 4 and 5 are examples of low-concentration n-layers.

[0057] The above detailed description of the implementation methods is provided, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various forms of deformation and modification of the specific examples illustrated above. The technical elements described in this specification or the drawings are technically useful alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings achieves multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims

1. A field effect transistor, characterized in that: have: A semiconductor substrate having a groove on an upper surface; A gate insulating film covers the inner surface of the trench; as well as a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; The semiconductor substrate has: An n-type source layer is in contact with the gate insulating film; A p-type body layer in contact with the gate insulating film below the source layer; and A lower n layer, arranged on the lower side of the body layer; The above lower n layers have: a current diffusion n layer connected to the body layer from the bottom side; and a low concentration n layer, which is in contact with the current diffusion n layer from below and has a lower n-type impurity concentration than that of the current diffusion n layer; The n-type impurity concentration distribution in the current diffusion n layer in the depth direction of the semiconductor substrate is distributed in a manner having a peak value; The inner surface of the groove has: The side surface is composed of a surface having a curvature radius of 0.7 μm or more; and A bottom connecting surface, connecting the side surface with the lower end of the groove, and composed of a concave curved surface with a curvature radius of less than 0.7 μm; The portion of the current diffusion n-layer having the peak value is in contact with the gate insulating film at the side surface.

2. The field effect transistor according to claim 1, characterized in that The current diffusion n-layer is not in contact with the gate insulating film at the bottom connection surface.

3. The field effect transistor according to claim 1 or 2, characterized in that: It also includes a bottom p-layer in contact with the gate insulating film at the lower end of the trench.

4. The field effect transistor according to claim 3, characterized in that The bottom p-layer is in contact with the current diffusion n-layer in a range in contact with the gate insulating film; The thickness of the current diffusion n layer between the body layer and the bottom p layer is 0.1 μm or more.

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