SOT-MRAM circuit unit based on 2T2M differential structure and storage array circuit thereof

Abstract

The invention relates to the field of nonvolatile memories, in particular to an SOT-MRAM circuit unit based on a 2T2M differential structure and a storage array circuit of the SOT-MRAM circuit unit. The SOT-MRAM unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first phase inverter, a second phase inverter, a write line, a read line, an input line and an output line which have a specific connection relation. According to the SOT-MRAM circuit unit, through the special 2T2M differential structure design and in combination with the excellent performance of a spin-orbit moment magnetic tunnel junction, the storage and operation performance and efficiency of a 2T2MSOT-MRAM differential circuit unit array are integrally improved, the dependence on the performance of the MTJ is reduced, the SOT-MRAM circuit unit has the better energy efficiency ratio and the more stable read-write speed and precision, and the SOT-MRAM circuit unit has the advantages of being simple in structure, low in cost and high in reliability. And the reliability and the stability are excellent.

Description

Technical Field

[0001] The present invention relates to the field of non-volatile memory, and in particular to a SOT-MRAM circuit unit based on a 2T2M differential structure and a storage and calculation array circuit thereof. Background Art

[0002] Artificial intelligence has developed rapidly and has been widely used and successful in many fields such as natural language processing, computer vision, and intelligent recommendation, which has promoted social progress. The development of artificial intelligence is mainly based on the development of neural networks, such as convolutional neural networks (CNNs), whose operation principle is multiplication and addition operations, and requires the use of multi-bit input (IN), weight (W), and output (OUT) for multiplication and accumulation (MAC) operations. Therefore, a large amount of weight information needs to be stored, and the transmission speed of weight information limits the performance of the system.

[0003] In the traditional von Neumann computer architecture, the storage unit is separated from the computing unit. The flow of data between the storage unit and the computing unit not only limits the computing speed of the system itself, but also accounts for 90% of the system's power consumption, greatly limiting the performance of the system. The current mainstream optimization method is to shorten the physical distance between the computing unit and the storage unit, but this solution cannot fundamentally solve the problem. Another solution is to use transistors combined with various new non-volatile memories, such as memristors, ferroelectric memories, phase change memories, and magnetic memories to achieve a storage-computing integrated design. In this type of storage-computing integrated design, the selection of non-volatile storage units and the structural design between them and transistors are very important, which will greatly affect the reliability, stability, computing speed, and computing density of the storage-computing integrated design.

[0004] For storage-computing integrated design, common structures include a 1T1R structure consisting of a transistor and a memristor (T stands for transistor, R stands for memristor), a 1T1M structure consisting of a transistor and a magnetic memory (M stands for magnetic memory), a 1T2M structure consisting of a transistor and two magnetic memories, and a 2T2M structure consisting of two transistors and two spin transfer magnetic memories (STT-MRAM). These structures can realize storage-computing integrated design to a certain extent, but the above structures all have certain shortcomings, such as slow reading and writing speed, low calculation precision and accuracy, difficult to ensure calculation reliability, high power consumption, low storage density, poor reliability and durability, etc., and the above problems need to be solved. Summary of the invention

[0005] The purpose of the present invention is to overcome the problems existing in the above-mentioned prior art and to provide a SOT-MRAM circuit unit based on a 2T2M differential structure and a storage and calculation array circuit thereof.

[0006] In order to achieve the above-mentioned object, the present invention provides a SOT-MRAM circuit unit based on a 2T2M differential structure on one hand, the circuit unit includes a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first inverter, a second inverter, a write line, a read line, an input line and an output line; the read line is respectively connected to the top electrodes of the first magnetic tunnel junction and the second magnetic tunnel junction; the write line is respectively connected to the input ends of the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction through the first inverter, and the first inverter is used to keep the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite at all times; the output end of the heavy metal layer of the first magnetic tunnel junction is connected to the source of the first field effect transistor, and the output end of the heavy metal layer of the second magnetic tunnel junction is connected to the source of the second field effect transistor; the output line is respectively connected to the drains of the first field effect transistor and the second field effect transistor; the input line is respectively connected to the gates of the first field effect transistor and the second field effect transistor through the second inverter, and the second inverter is used to switch the first field effect transistor or the second field effect transistor to be in a conducting state.

[0007] A second aspect of the present invention provides a SOT-MRAM storage and computing array circuit, which includes a plurality of the above-mentioned SOT-MRAM circuit units, wherein the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of the lowest-level SOT-MRAM circuit unit are either not connected to the ground line through a ground switch, or are connected to the ground line through a ground switch. When connected to the ground line through a ground switch, the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units are connected to the ground line through the ground switch.

[0008] A third aspect of the present invention provides a data operation method for the above-mentioned SOT-MRAM circuit unit, which includes: writing the first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; after the first data is written, pulling down the write line, and inputting a selection signal generated based on the second data through the input line, and the selection signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, inputting a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction through the read line, so that the output line outputs a calculated current signal based on the voltage signal; based on the current signal, extracting the operation result of the first data and the second data.

[0009] A fourth aspect of the present invention provides a data operation method for the above-mentioned SOT-MRAM storage and calculation array circuit, the data operation method comprising: by pulling up the write line of each level, writing the corresponding first data into the first magnetic tunnel junction and the second magnetic tunnel junction of each level; and controlling the corresponding ground switch to be in a conductive state to prevent the write current of the upper level SOT-MRAM circuit unit from flowing into the next level SOT-MRAM circuit unit, and controlling the remaining ground switches to be in a conductive state to prevent data from being written into SOT-MRAM circuit units of different columns at the same time; after the first data is written, pulling down the write line of each level, and inputting a selection signal generated based on the corresponding second data through the input line of each level, the selection signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each level to be turned on; at the same time, inputting a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each level through the read line of the highest level, so that each column completes the operation step by step based on the voltage signal, and then the corresponding lowest level output line outputs the final circuit signal; based on the final circuit signal of each column, respectively extracting the operation results of the first data and the second data of each column.

[0010] A fifth aspect of the present invention provides a data operation device based on the above-mentioned SOT-MRAM circuit unit, and the data operation device includes: a first write module, used to write the first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; a first operation module, used to pull down the write line after the first data is written, and input a selection signal generated based on the second data through the input line, and the selection signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the read line, so that the output line outputs a calculated current signal based on the voltage signal; a first extraction module, used to extract the operation results of the first data and the second data based on the current signal.

[0011] A sixth aspect of the present invention provides a data operation device based on the above-mentioned SOT-MRAM storage and calculation array circuit, the data operation device comprising: a second writing module, used to write the corresponding first data into the first magnetic tunnel junction and the second magnetic tunnel junction of each level by pulling up the write line of each level; and controlling the corresponding ground switch to be in a conducting state to prevent the write current of the upper level SOT-MRAM circuit unit from flowing into the next level SOT-MRAM circuit unit, and at the same time controlling the remaining ground switches to be in a conducting state to prevent data from being written into SOT-MRAM circuit units of different columns at the same time; a second operation module, used to pull down the write line of each level after the first data is written A write line, inputting a selection signal generated based on the corresponding second data through the input line of each level, the selection signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each level to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each level is input through the read line of the highest level, so that each column completes the operation step by step based on the voltage signal and then outputs the final circuit signal through the corresponding output line of the lowest level; a second extraction module is used to extract the operation results of the first data and the second data of each column respectively based on the final circuit signal of each column.

[0012] The SOT-MRAM circuit unit of the present invention integrates the storage unit and the calculation unit in a small structure, achieving a high degree of integration and compactness. The first inverter can be used to simultaneously write opposite storage information into two magnetic tunnel junctions, and the input line and the second inverter are used to select the operation channel. At the same time, the read line and the write line are separated, which reduces the influence of the voltage signal on the magnetic tunnel junction during the operation process, thereby improving the stability and reliability of the magnetic tunnel junction. The SOT-MRAM circuit unit of the present invention improves the storage and computing performance and efficiency of the 2T2M SOT-MRAM differential circuit unit array as a whole through a special 2T2M differential structure design and in combination with the excellent performance of the spin-orbit moment magnetic tunnel junction (SOT-MTJ). Compared with the traditional design, the energy consumption is reduced by 20% to 30%, and the optimized current path reduces the leakage current. In addition, the structural design reduces the dependence on the performance of the MTJ itself, and has a tolerance of 10% to 20% for the variation of its resistance value, thereby reducing the demand for the stability of the MTJ. At the same time, the anti-interference ability of the MTJ itself is utilized, so that it can still show a certain stability under high temperature and high pressure, and can usually withstand up to 1.5 times the rated voltage, showing excellent reliability and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of a SOT-MRAM circuit unit according to an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of a SOT-MRAM storage and computing array circuit (3×3) according to an embodiment of the present invention;

[0015] Figure 3 Schematic diagram of the spin-orbit moment magnetic tunnel junction of the present invention;

[0016] Figure 4 Schematic diagram of a testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article.

[0018] In the present invention, the terms "first", "second", etc. are used to distinguish similar objects for the convenience of description and understanding, rather than to describe a specific order or sequence.

[0019] The SOT-MRAM circuit unit and the read-write method thereof proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The accompanying drawings are in a very simplified form and in an inaccurate scale, and are only used to conveniently and clearly assist in explaining the purpose of the technical solution of the present invention, and the accompanying drawings show only one specific solution within the protection scope of the present invention.

[0020] On one hand, the present invention provides a SOT-MRAM circuit unit based on a 2T2M differential structure, the circuit unit includes a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first inverter, a second inverter, a write line, a read line, an input line and an output line; the read line is respectively connected to the top electrodes of the first magnetic tunnel junction and the second magnetic tunnel junction; the write line is respectively connected to the input ends of the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction through the first inverter, and the first inverter is used to keep the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite at all times; the output end of the heavy metal layer of the first magnetic tunnel junction is connected to the source of the first field effect transistor, and the output end of the heavy metal layer of the second magnetic tunnel junction is connected to the source of the second field effect transistor; the output line is respectively connected to the drains of the first field effect transistor and the second field effect transistor; the input line is respectively connected to the gates of the first field effect transistor and the second field effect transistor through the second inverter, and the second inverter is used to switch the first field effect transistor or the second field effect transistor to be in a conducting state.

[0021] According to the present invention, the first magnetic tunnel junction and the second magnetic tunnel junction can be selected from conventional spin-orbit moment magnetic tunnel junctions (SOT-MTJs) in the art, and the structure of the spin-orbit moment magnetic tunnel junction can also be a conventional known structure in the art, and can also be expanded to any non-volatile unit. In the present invention, the magnetic tunnel junction mentioned refers to the spin-orbit moment magnetic tunnel junction.

[0022] According to the present invention, the structure of the first magnetic tunnel junction and the second magnetic tunnel junction in the present invention includes the top electrode, the reference layer, the insulating layer, the free layer and the heavy metal layer in order from top to bottom, such as Figure 3 As shown. Among them, the thickness of the top electrode, reference layer, insulating layer, free layer and heavy metal layer and the materials used for each can be selected within a wide range, as long as the function of the spin-transfer torque magnetic tunnel junction can be realized. In order to further improve the stability and energy consumption ratio of the magnetic tunnel junction, preferably, the material of the reference layer can be selected from one or more of NiO, CoO, FeMn alloy, MnIr alloy and MnPt alloy, with a thickness of 5-15nm. The material of the insulating layer is selected from one or more of MgO, AlN, Al2O3 and HfO2, with a thickness of 1-3nm. The material of the free layer is selected from one or more of NiO, CoO, FeMn alloy, MnIr alloy and MnPt alloy, with a thickness of 10-25nm. The material of the heavy metal layer is selected from one or more of Ta, Pt and W, with a thickness of 5-30nm.

[0023] According to the present invention, the reference layer has a fixed magnetization direction, and the magnetization direction of the free layer can be switched between two opposite magnetization directions. When the magnetization directions of the reference layer and the free layer are the same, the magnetic tunnel junction presents a low resistance state, recorded as -1; when the magnetization directions of the reference layer and the free layer are opposite, the magnetic tunnel junction presents a high resistance state, recorded as +1. In addition, the principle of reading and writing data by the magnetic tunnel junction is as follows: after the state of the magnetic tunnel junction is initialized, when the current flows through the heavy metal layer of the magnetic tunnel junction, it can trigger the magnetic polarization reversal of the free layer, and the resistance state of the magnetic tunnel junction also changes accordingly, thereby writing the stored data. Afterwards, by inputting a current from the top electrode through the entire magnetic tunnel junction, the output current information is different according to the different resistance states of the magnetic tunnel junction, so that the corresponding stored data can be extracted.

[0024] According to the present invention, in order to prevent logic disorder during the operation of the SOT-MRAM circuit unit, preferably, the input end of the first inverter is connected to the input end of the heavy metal layer of the first magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the first field effect transistor. Alternatively, the input end of the first inverter is connected to the input end of the heavy metal layer of the second magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the second field effect transistor.

[0025] According to the present invention, the first inverter and the second inverter can be selected in a wide range, as long as the input voltage signal can be opposite to the output voltage signal, and can be used to control the reading and writing of the magnetic tunnel junction and the conduction of the field effect transistor. Preferably, the first inverter and the second inverter are both inverters composed of an operational amplifier, which are used to provide two voltage information with opposite polarities. Among them, the function of the first inverter is to make the voltage information of the heavy metal layer input to the first magnetic tunnel junction and the second magnetic tunnel junction opposite, so that the two magnetic tunnel junctions always maintain opposite resistance states, thereby recording opposite storage data on the two magnetic tunnel junctions. The function of the second inverter is to control the conduction state of the first field effect transistor and the second field effect transistor, so that one of them can be selected as the operation channel when reading data for operation.

[0026] According to the present invention, the first field effect transistor and the second field effect transistor can be selected in a wide range, as long as they can be turned on or off as a switch. Preferably, the first field effect transistor and the second field effect transistor are NMOS transistors.

[0027] A second aspect of the present invention provides a SOT-MRAM storage and computing array circuit, which includes a plurality of the above-mentioned SOT-MRAM circuit units, wherein the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of the lowest-level SOT-MRAM circuit unit are either not connected to the ground line through a ground switch, or are connected to the ground line through a ground switch. When connected to the ground line through a ground switch, the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units are connected to the ground line through the ground switch.

[0028] According to the present invention, the terms "lowest level", "highest level", "levels", etc. refer to the relative relationship of the SOT-MRAM circuit units in the vertical direction after a plurality of the SOT-MRAM circuit units form a SOT-MRAM storage and computing array circuit. "Highest level" refers to the topmost one or a row of the SOT-MRAM circuit units, and the read line of the topmost SOT-MRAM circuit unit is directly connected to the external circuit. "Lowest level" refers to the bottommost one or a row of the SOT-MRAM circuit units, and the output line of the lowest level SOT-MRAM circuit unit is directly connected to the external circuit.

[0029] According to the present invention, the SOT-MRAM storage and computing array circuit is formed by a plurality of the SOT-MRAM circuit units through longitudinal and / or lateral expansion.

[0030] Preferably, the longitudinal expansion method is: at least two of the SOT-MRAM circuit units are longitudinally connected in series, and the output line of the upper SOT-MRAM circuit unit in the two adjacent SOT-MRAM circuit units is connected to the read line of the lower SOT-MRAM circuit unit. Preferably, the grounding switch connected to each of the SOT-MRAM circuit units in longitudinal series is the same. Preferably, the grounding switch is an NMOS tube.

[0031] Preferably, the lateral expansion method is: at least two of the SOT-MRAM circuit units are laterally connected by sharing the write line and the input line. The specific connection relationship of each of the SOT-MRAM circuit units in the SOT-MRAM storage and computing array circuit can be referred to Figure 2 .

[0032] According to the present invention, in the SOT-MRAM storage and computing array circuit, the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of the SOT-MRAM circuit unit are connected to the ground line through a ground switch in order to avoid the loss or damage of the magnetic tunnel junction caused by the large current of the SOT-MRAM circuit unit of the previous level flowing through the transistor to the magnetic tunnel junction of the SOT-MRAM circuit unit of the next level when performing a write operation of a multi-bit operation.

[0033] A third aspect of the present invention provides a data operation method for the above-mentioned SOT-MRAM circuit unit, which includes: writing the first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; after the first data is written, pulling down the write line, and inputting a selection signal generated based on the second data through the input line, and the selection signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, inputting a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction through the read line, so that the output line outputs a calculated current signal based on the voltage signal; based on the current signal, extracting the operation result of the first data and the second data.

[0034] According to the present invention, the step of extracting the calculation result of the first data and the second data based on the current signal includes: performing a capacitor integration operation on the current signal to obtain the time length for the capacitor voltage to reach a threshold voltage; based on the time length, determining the calculation result of the first data and the second data.

[0035] A fourth aspect of the present invention provides a data operation method for the above-mentioned SOT-MRAM storage and calculation array circuit, the data operation method comprising: by pulling up the write line of each level, writing the corresponding first data into the first magnetic tunnel junction and the second magnetic tunnel junction of each level; and controlling the corresponding ground switch to be in a conductive state to prevent the write current of the upper level SOT-MRAM circuit unit from flowing into the next level SOT-MRAM circuit unit, and controlling the remaining ground switches to be in a conductive state to prevent data from being written into SOT-MRAM circuit units of different columns at the same time; after the first data is written, pulling down the write line of each level, and inputting a selection signal generated based on the corresponding second data through the input line of each level, the selection signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each level to be turned on; at the same time, inputting a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each level through the read line of the highest level, so that each column completes the operation step by step based on the voltage signal, and then the corresponding lowest level output line outputs the final circuit signal; based on the final circuit signal of each column, respectively extracting the operation results of the first data and the second data of each column.

[0036] According to the present invention, the step of extracting the calculation results of the first data and the second data of each column based on the final circuit signal of each column, includes: performing a capacitor integration operation on the final current signal of each column to obtain the time length for the capacitor voltage to reach a threshold voltage; based on the time length, dividing the time length interval to determine the calculation results of the first data and the second data of each column.

[0037] A fifth aspect of the present invention provides a data operation device based on the above-mentioned SOT-MRAM circuit unit, and the data operation device includes: a first write module, used to write the first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; a first operation module, used to pull down the write line after the first data is written, and input a selection signal generated based on the second data through the input line, and the selection signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the read line, so that the output line outputs a calculated current signal based on the voltage signal; a first extraction module, used to extract the operation results of the first data and the second data based on the current signal.

[0038] A sixth aspect of the present invention provides a data operation device based on the above-mentioned SOT-MRAM storage and calculation array circuit, the data operation device comprising: a second writing module, used to write the corresponding first data into the first magnetic tunnel junction and the second magnetic tunnel junction of each level by pulling up the write line of each level; and controlling the corresponding ground switch to be in a conducting state to prevent the write current of the upper level SOT-MRAM circuit unit from flowing into the next level SOT-MRAM circuit unit, and at the same time controlling the remaining ground switches to be in a conducting state to prevent data from being written into SOT-MRAM circuit units of different columns at the same time; a second operation module, used to pull down the write line of each level after the first data is written A write line, inputting a selection signal generated based on the corresponding second data through the input line of each level, the selection signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each level to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each level is input through the read line of the highest level, so that each column completes the operation step by step based on the voltage signal and then outputs the final circuit signal through the corresponding output line of the lowest level; a second extraction module is used to extract the operation results of the first data and the second data of each column respectively based on the final circuit signal of each column.

[0039] The SOT-MRAM circuit unit of the present invention improves the reliability, stability and computing density of the traditional storage-computation integrated architecture, and proposes a 2T2M differential structure design based on the spin-orbit moment magnetic tunnel junction. The read-write operation characteristics of the self-selected orbit moment magnetic tunnel junction are used to separate the read-write signal lines, reduce the influence of the voltage signal on the magnetic tunnel junction during the operation, and improve the system operation speed, energy consumption ratio, computing density and life without affecting the operation efficiency. At the same time, the specific 2T2M architecture of the present invention has high flexibility and programmability, can be customized and optimized according to different application requirements, supports highly parallel computing power, can simultaneously process the computing tasks of multiple neural network nodes, and accelerate the training and reasoning process of the neural network. Compared with the traditional computing architecture, this parallel computing power can reduce the energy consumption ratio of the system, without refreshing the weights of the neural network at all times, so that the static energy consumption of the system approaches 0, and the smaller read voltage and switching mechanism also reduce the dynamic power consumption of the system by 30-50%, and the increase in switching speed reduces the response time by 20-30%, which can accelerate the training and derivation process of the model.

[0040] The present invention will be described in detail below through embodiments in conjunction with the accompanying drawings.

[0041] The SOT-MRAM circuit unit of this embodiment is as follows Figure 1As shown. The read line IN is connected to the top electrodes of the first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 respectively. The write line WEN is connected to the input ends of the heavy metal layers of the first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 respectively through the first inverter N1, wherein the input end of the first inverter N1 is connected to the input end of the heavy metal layer of the second magnetic tunnel junction MTJ_2, and the output end of the first inverter N1 is connected to the input end of the heavy metal layer of the first magnetic tunnel junction MTJ_1. The output end of the heavy metal layer of the first magnetic tunnel junction MTJ_1 is connected to the source of the first field effect transistor NP1, and the output end of the heavy metal layer of the second magnetic tunnel junction MTJ_2 is connected to the source of the second field effect transistor NP2. The output line OUT is connected to the drains of the first field effect transistor NP1 and the second field effect transistor NP2 respectively. The input line W is connected to the gates of the first field effect transistor NP1 and the second field effect transistor NP2 respectively through the second inverter N2, wherein the input end of the second inverter N2 is connected to the gate of the second field effect transistor NP2, and the output end of the second inverter N2 is connected to the gate of the first field effect transistor NP1. The first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 are spin-orbit moment magnetic tunnel junctions, wherein the material of the reference layer is selected from FeMn alloy and has a thickness of 10nm. The material of the insulating layer is selected from MgO and has a thickness of 2nm. The material of the free layer is selected from FeMn alloy and has a thickness of 20nm. The material of the heavy metal layer is selected from Ta / Pt and has a thickness of 5 / 25nm. The first inverter N1 and the second inverter N2 are both inverters composed of an operational amplifier. The first field effect transistor NP1 and the second field effect transistor NP2 are both NMOS transistors.

[0042] The SOT-MRAM circuit unit is operated with data: first, a write operation is performed, by pulling up the write line WEN, a voltage signal of +10V is input to the write line WEN, at which time the first field effect transistor NP1 and the second field effect transistor NP2 are turned on, the voltage of the second magnetic tunnel junction MTJ_2 is +10V, and the voltage of the first magnetic tunnel junction MTJ_1 is -10V under the action of the first inverter N1, so that the resistance states of the first magnetic tunnel junction MTJ_1 and the second magnetic tunnel junction MTJ_2 are opposite. After the write operation is completed, the write line WEN is pulled down to make the voltage of the write line WEN 0V. Start reading and calculating again, input a voltage signal of +1.8V to the reading line IN, and input a voltage signal of +1.8V to the input line W at the same time. At this time, the second field effect transistor NP2 is turned on, and the first field effect transistor NP1 is turned off under the action of the second inverter N2. After the current flows through the entire second magnetic tunnel junction MTJ_2, a current signal is output on the output line OUT. A capacitor is used to integrate the current signal, and the time length for the capacitor voltage to reach the threshold voltage is obtained, thereby obtaining the calculation result.

[0043] The magnetic tunnel junction of the SOT-MRAM circuit unit is tested, and the testing method is as follows: Figure 4 As shown, DC and RF power are applied to the three-terminal device, mainly for testing after the high-resistance state. The RF power is used to inject pulses for current sensing switching and time-resolved measurement. The pulse generator generates two matching and opposite pulse voltages with a rise time of 0.2ns and a voltage of 10V and injects them into the heavy metal layer. The two inputs V1 and V2 have the same amplitude and opposite signs to ensure that the voltage in the vertical direction of the magnetic tunnel junction can be ignored. After each pulse read and write, a small current (100uA~5mA) is injected in the vertical direction of the magnetic tunnel junction for resistance measurement. The resistance state change can be judged based on the resistance measurement results. The magnetic tunnel junction of the SOT-MRAM unit was tested after tens of thousands of read and write operations. The results showed that it still has a stable read and write voltage, and the resistance error of the magnetic tunnel junction in the low-resistance and high-resistance states does not exceed 0.5KΩ.

[0044] By expanding the nine SOT-MRAM circuit units mentioned above horizontally and vertically, the following can be obtained: Figure 2 The SOT-MRAM storage and calculation array circuit (3×3) shown in the figure. Among them, the read line IN is directly connected to the top electrode of the highest-level SOT-MRAM circuit unit. The highest-level SOT-MRAM circuit unit shares a write line WEN1 and a common input line W1. The intermediate-level SOT-MRAM circuit units share a write line WEN2 and a common input line W2. The lowest-level SOT-MRAM circuit units share a write line WEN3 and a common input line W3. The cascade operation data of each column of SOT-MRAM circuit units are output by output line OUT1, output line OUT2 and output line OUT3 respectively. The heavy metal layer of the magnetic tunnel junction of each column of SOT-MRAM circuit units is connected to the ground line and is controlled by ground switch NG1, ground switch NG2 and ground switch NG3 respectively.

[0045] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A SOT-MRAM circuit unit based on a 2T2M differential structure, characterized in that: The circuit unit includes a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first inverter, a second inverter, a write line, a read line, an input line and an output line; The readout line is respectively connected to the top electrodes of the first magnetic tunnel junction and the second magnetic tunnel junction; The write line is connected to the input ends of the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction respectively through the first inverter, and the first inverter is used to keep the resistance states of the first magnetic tunnel junction and the second magnetic tunnel junction opposite at all times; The output end of the heavy metal layer of the first magnetic tunnel junction is connected to the source of the first field effect transistor, and the output end of the heavy metal layer of the second magnetic tunnel junction is connected to the source of the second field effect transistor; The output line is connected to the drain of the first field effect transistor and the drain of the second field effect transistor respectively; The input line is connected to the gates of the first field effect transistor and the second field effect transistor respectively through the second inverter, and the second inverter is used to switch the first field effect transistor or the second field effect transistor to be in a conducting state.

2. The SOT-MRAM circuit unit according to claim 1, wherein: The input end of the first inverter is connected to the input end of the heavy metal layer of the first magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the first field effect transistor; And / or, the input end of the first inverter is connected to the input end of the heavy metal layer of the second magnetic tunnel junction, and the input end of the second inverter is connected to the gate of the second field effect transistor; And / or, the first inverter and the second inverter are both inverters formed by an operational amplifier, used for providing two voltage information with opposite polarities.

3. A SOT-MRAM storage and computing array circuit, characterized in that: The SOT-MRAM storage and computing array circuit includes multiple SOT-MRAM circuit units as described in claim 1 or 2, wherein the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of the lowest-level SOT-MRAM circuit unit are either not connected to the ground line through a ground switch, or are connected to the ground line through a ground switch. When connected to the ground line through a ground switch, the heavy metal layers of the first magnetic tunnel junction and the second magnetic tunnel junction of all the SOT-MRAM circuit units are connected to the ground line through the ground switch.

4. The SOT-MRAM storage and computing array circuit according to claim 3, wherein: At least two of the SOT-MRAM circuit units are connected in series vertically, and the output line of the upper SOT-MRAM circuit unit of two adjacent SOT-MRAM circuit units is connected to the read line of the lower SOT-MRAM circuit unit.

5. The SOT-MRAM storage and computing array circuit according to claim 4, wherein: The grounding switch connected to each of the SOT-MRAM circuit units connected in series vertically is the same; And / or, the ground switch is an NMOS tube.

6. The SOT-MRAM storage and computing array circuit according to any one of claims 3 to 5, wherein: At least two of the SOT-MRAM circuit units are laterally connected by sharing the write line and the input line.

7. A data operation method based on the SOT-MRAM circuit unit according to claim 1 or 2, the data operation method comprising: Writing first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the write line; After the first data is written, the write line is pulled low, and a selection signal generated based on the second data is input through the input line, the selection signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction is input through the read line, so that the output line outputs the calculated current signal based on the voltage signal; Based on the current signal, a calculation result of the first data and the second data is extracted.

8. The data operation method of the SOT-MRAM circuit unit according to claim 7, wherein: The step of extracting the operation result of the first data and the second data based on the current signal includes: Performing a capacitance integration operation on the current signal to obtain a time duration for the voltage of the capacitor to reach a threshold voltage; Based on the duration, a calculation result of the first data and the second data is determined.

9. A data operation method based on the SOT-MRAM storage and computing array circuit according to any one of claims 3 to 6, the data operation method comprising: By pulling up the write lines at each level, the corresponding first data is written into the first magnetic tunnel junctions and the second magnetic tunnel junctions at each level; and controlling the corresponding grounding switch to be in an on state to prevent the write current of the previous-level SOT-MRAM circuit unit from flowing into the next-level SOT-MRAM circuit unit, and controlling the remaining grounding switches to be in an on state to prevent data from being written into SOT-MRAM circuit units in different columns at the same time; After the first data is written, the write line of each level is pulled down, and a selection signal generated based on the corresponding second data is input through the input line of each level, and the selection signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each level to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each level is input through the read line of the highest level, so that each column completes the operation step by step based on the voltage signal, and the final circuit signal is output by the corresponding output line of the lowest level; Based on the final circuit signal of each column, operation results of the first data and the second data of each column are respectively extracted.

10. The data operation method of the SOT-MRAM storage and operation array circuit according to claim 9, wherein: The step of respectively extracting the operation results of the first data and the second data of each column based on the final circuit signal of each column comprises: Performing a capacitance integration operation on the final current signal of each column to obtain the time length for the voltage of the capacitor to reach a threshold voltage; Based on the duration, the duration intervals are divided, and the calculation results of the first data and the second data in each column are determined.

11. A data operation device based on the SOT-MRAM circuit unit according to claim 1 or 2, the data operation device comprising: A first writing module, used for writing first data into the first magnetic tunnel junction and the second magnetic tunnel junction by pulling up the writing line; A first operation module is used for pulling down the write line after the first data is written, inputting a selection signal generated based on the second data through the input line, the selection signal is used to select the first field effect transistor or the second field effect transistor to be turned on; at the same time, inputting a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction through the read line, so that the output line outputs the calculated current signal based on the voltage signal; The first extraction module is used to extract a calculation result of the first data and the second data based on the current signal.

12. A data operation device based on the SOT-MRAM storage and operation array circuit according to any one of claims 3 to 6, the data operation device comprising: A second writing module, used for writing the corresponding first data into the first magnetic tunnel junctions and the second magnetic tunnel junctions at each level by pulling up the writing lines at each level; and controlling the corresponding grounding switch to be in an on state to prevent the write current of the previous-level SOT-MRAM circuit unit from flowing into the next-level SOT-MRAM circuit unit, and controlling the remaining grounding switches to be in an on state to prevent data from being written into SOT-MRAM circuit units in different columns at the same time; A second operation module is used to pull down the write line of each level after the first data is written, and input a selection signal generated based on the corresponding second data through the input line of each level, wherein the selection signal is used to select the first field effect transistor or the second field effect transistor of each SOT-MRAM circuit unit of each level to be turned on; at the same time, a voltage signal that does not change the current resistance state of the first magnetic tunnel junction and the second magnetic tunnel junction of each level is input through the read line of the highest level, so that each column completes the operation step by step based on the voltage signal, and then the corresponding output line of the lowest level outputs the final circuit signal; The second extraction module is used to extract the operation results of the first data and the second data of each column respectively based on the final circuit signal of each column.

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