High power supply rejection ratio low dropout linear regulator with level conversion function

Abstract

The invention discloses a high-power-supply-rejection-ratio low-dropout linear voltage regulator with a level conversion function. The high-power-supply-rejection-ratio low-dropout linear voltage regulator comprises an error amplifier EA, a super source follower, a frequency compensation module, a power tube, a feedback loop, an output load and a level conversion module. According to the low dropout linear regulator, a dynamic frequency compensation mode is adopted, a dynamic frequency compensation module is added to the output end of the error amplifier EA, dynamic frequency compensation can be achieved, and the stability of a system loop under different load currents is guaranteed. Meanwhile, a level conversion module is integrated in the low-dropout linear regulator, so that bidirectional voltage conversion between two levels can be realized. The level shifter can provide power for portable equipment, smart phones, industrial and medical equipment and the like, and can be used in I2C bus interface equipment application.

Description

Technical Field

[0001] The invention relates to a high power supply rejection ratio low voltage drop linear voltage stabilizer with a level conversion function, belonging to the technical field of linear voltage stabilizers. Background Art

[0002] Low Dropout regulator (LDO) is usually used as the power supply end of the chip. It has the advantages of small area, few peripheral devices, simple structure, no ripple and low noise.

[0003] Level converters are usually used as independent chips to bridge two different voltage nodes to successfully connect the logic gate levels in electronic systems. It can be used in point-to-point topology to connect devices or systems running at different interface voltages. It mainly uses open-drain mode to connect data with I / O ports, such as I2C bus interface devices, where data is transmitted bidirectionally and no control signals are required.

[0004] Independent level converter chips need to provide two power supply voltages, which increases the complexity of board-level circuit design. However, low-dropout linear regulators require a power supply as input, and after conversion, they output a voltage to power other modules. Therefore, LDO can be used to provide power for the level converter, realizing power supply and level conversion functions at the same time. Summary of the invention

[0005] In order to solve the above problems in the prior art, the present invention provides a low voltage drop linear regulator with a high power supply rejection ratio and a level conversion function, which can provide a wide input voltage range of 0.8 to 5.5V and withstand a load current of 1mA to 500mA, and achieve a voltage output range of 0.8 to 3.6V by changing the feedback resistance value. And the level conversion between the signals in the two voltage domains of input IN and output OUT can be achieved through the internal integrated level conversion module.

[0006] The present invention provides a high power supply rejection ratio low voltage drop linear regulator with a level conversion function, comprising an error amplifier EA, a super source follower, a frequency compensation module, a power tube, a feedback loop, an output load and a level conversion module. The output end of the error amplifier EA is connected to the super source follower and the frequency compensation module, the frequency compensation module is used for loop adaptive frequency compensation, the gate of the power tube is connected to the output end of the super source follower, the drain is connected to the input voltage IN, the feedback loop is connected to the source of the power tube in parallel with the output load, and the level conversion module comprises a power supply VCCA, a power supply VCCB, input ports A1 and A2, and output ports B1 and B2, wherein the power supply VCCA is connected to the input voltage IN, and the power supply VCCB is connected to the output OUT.

[0007] Furthermore, the error amplifier EA includes a transistor M11 and a transistor M12 providing a tail current source, wherein the gate of the transistor M11 is connected to the gate of the transistor M12 and inputs a bias voltage Vbias1, the drain is connected to the source of the transistor M12, and the source is connected to the power supply BIAS.

[0008] Furthermore, the error amplifier EA also includes an input tube M1, an input tube M2, an input tube M3 and an input tube M4, wherein the gate of the input tube M1 inputs a reference voltage Vref1, the drain is connected to the source of the input tube M3, and the source is connected to the drain of the transistor M12; the gate of the input tube M2 inputs a feedback voltage Vfb, the drain is connected to the source of the input tube M4, and the source is connected to the drain of the transistor M12; the gate of the input tube M3 inputs a bias voltage Vbias2, and the source is connected to the drain of the input tube M1; the gate of the input tube M4 inputs a bias voltage Vbias2, and the source is connected to the drain of the input tube M2.

[0009] Furthermore, the error amplifier EA also includes current mirror loads M5, M6, M7, and M8, and resistor loads R1 and R2. The gate and drain of the current mirror load M5 are connected to the gates of the current mirror loads M6, M7, and M8, and the source is connected to the drain of the current mirror load M7; the gate of the current mirror load M6 is connected to the gates of the current mirror loads M5, M7, and M8, and the source is connected to the drain of the current mirror load M8; the gate of the current mirror load M7 is connected to the gates of the current mirror loads M5, M6, and M8 and the drain of the current mirror load M5, and the drains are respectively connected to the The source of the current mirror load M5 and the drain of the input tube M3, the source is connected to the first port of the load resistor R1; the gate of the current mirror load M8 is connected to the gates of the current mirror loads M5, M6, and M7 and the drain of the current mirror load M5, the drain is respectively connected to the source of the current mirror load M6 and the drain of the input tube M4, and the source is connected to the first port of the load resistor R2; the first port of the resistance load R1 is connected to the source of the current mirror load M7, and the second port is grounded; the first port of the resistance load R2 is connected to the source of the current mirror load M8, and the second port is grounded.

[0010] Further, the error amplifier EA also includes MOS tubes M13, M14, M15, and M16. The gate of the MOS tube M13 is connected to the gates of the MOS tubes M14, M15, and M16 respectively, the drain is connected to the source of the MOS tube M14, and the source is connected to the power supply BIAS. The gate of the MOS tube M15 is connected to the gates of the MOS tubes M13, M14, and M16 respectively, the drain is connected to the source of the MOS tube M16, and the source is connected to the power supply BIAS. The gate of the MOS tube M14 is connected to the gates of the MOS tubes M13, M15, and M16 respectively, the drain is connected to the gates of the current mirror loads M5, M6, M7, and M8 and the drain of the current mirror load M5 respectively, and the source is connected to the drain of the MOS tube M13. The gate of the MOS tube M16 is connected to the gates of the MOS tubes M13, M14, and M15 respectively, the drain is connected to the drain of the current mirror load M6, and the source is connected to the drain of the MOS tube M15. The gates of the MOS transistors M13, M14, M15, and M16 are all input with a bias voltage Vbias1.

[0011] Furthermore, the drain of the current mirror load M6 and the drain of the MOS tube M16 are both connected to the output end of the error amplifier EA, and the output end of the error amplifier EA is connected to the gate of the input tube M9 of the super source follower.

[0012] Furthermore, the super source follower includes an input tube M9, MOS tubes M10, M17, M18, and a resistor R3. The gate of the input tube M9 is connected to the output end of the error amplifier EA, the source is connected to the drain of the MOS tube M18, and the drain is respectively connected to the gate of the MOS tube M10 and the first port of the resistor R3; the gate of the MOS tube M10 is respectively connected to the drain of the input tube M9 and the first port of the resistor R3, the drain is connected to the source of the input tube M9 and the drain of the MOS tube M18, and the source is grounded; the first port of the resistor R3 is respectively connected to the drain of the input tube M9 and the gate of the MOS tube M10, and the second port is grounded; the gate of the MOS tube M17 is connected to the gate of the MOS tube M18, the drain is connected to the source of the MOS tube M18, and the source is connected to the power supply BIAS; the gate of the MOS tube M18 is connected to the gate of the MOS tube M17, the source is connected to the drain of the MOS tube M17, and the drain is respectively connected to the source of the input tube M9 and the drain of the MOS tube M10. The gates of the MOS tubes M17 and M18 are both input with the bias voltage Vbias1.

[0013] Furthermore, the source of the input tube M9, the drain of the MOS tube M18 and the drain of the MOS tube M10 are all connected to the output end of the super source follower, and the output end of the super source follower is connected to the gate of the power tube MP.

[0014] Further, the frequency compensation module includes MOS tubes M19, M20, M21, M22, M23, M24, M25, MP1, compensation resistors Rc1, Rc2, Rc3, and compensation capacitors Cc1, Cc2, Cc3. The gate of the MOS tube MP1 is connected to the gate of the power tube MP and the output end of the super source follower, the drain is connected to the power supply IN, and the source is connected to the source of the MOS tube M19 and the source of the MOS tube M23. The drain of the MOS tube M19 is respectively connected to the gate of the MOS tube M19, the gate of the MOS tube M20, and the drain of the MOS tube M21, and the source is respectively connected to the source of the MOS tube MP1 and the source of the MOS tube M23. The gate of the MOS tube M20 is connected to the gate of the MOS tube M19, the source is connected to the source of the power tube MP, and the drain is respectively connected to the drain of the MOS tube M22 and the gate of the MOS tube M23. The gate of the MOS tube M21 is connected to the gate of the MOS tube M22, and the bias voltage Vbias3 is input at the same time. The drain is connected to the drain of the MOS tube M19, the gate of M19, and the gate of M20, and the source is grounded. The gate of the MOS tube M22 is connected to the gate of the MOS tube M21, and the bias voltage Vbias3 is input at the same time. The drain is connected to the drain of the MOS tube M20 and the gate of M23, and the source is grounded. The drain of the MOS tube M23 is connected to the gate of the MOS tube M24, the drain of M24, and the gate of M25, and the source of the MOS tube M24 is grounded. The gate of the MOS tube M25 is connected to the gate and drain of the MOS tube M24, the source is grounded, and the drain is connected to the second port of the compensation capacitor Cc2. The second port of the compensation resistor Rc1 is connected to the first port of the compensation capacitor Cc1, the second port of the compensation resistor Rc2 is connected to the first port of the compensation capacitor Cc2, and the first ports of the compensation resistor Rc1 and the compensation resistor Rc2 are both connected to the output port of the error amplifier EA. The second port of the compensation capacitor Cc1 is grounded, and the second port of the compensation capacitor Cc2 is connected to the drain of the MOS tube M25. The compensation resistor Rc3 is connected in series with the compensation capacitor Cc3, and the non-common end of the compensation resistor Rc3 and the compensation capacitor Cc3 is connected to the output end OUT of the low voltage difference linear regulator, and the non-common end of the compensation capacitor Cc3 and the compensation resistor Rc3 is connected to the feedback voltage Vfb.

[0015] Furthermore, the gate of the power tube MP is respectively connected to the output end of the super source follower and the gate of the MOS tube MP1, the drain is connected to the power supply IN, and the source is connected to the output end OUT of the low voltage difference linear regulator.

[0016] Furthermore, the feedback loop includes a feedback resistor Rf1 and a feedback resistor Rf2 connected in series. A common end of the feedback resistor Rf1 and the feedback resistor Rf2 outputs the feedback voltage Vfb.

[0017] Furthermore, the output load includes a load capacitor and a load resistor, and the load capacitor and the load resistor are arranged in parallel.

[0018] Furthermore, the level conversion module includes a power port VCCA, a power port VCCB, an input port A0, an input port A1, an output port B0, and an output port B1. The power port VCCA is connected to a voltage regulator input voltage IN, and the power port VCCB is connected to a voltage regulator output voltage OUT. Through the level conversion module, the level conversion between the digital signal under the voltage domain IN and the digital signal under the voltage domain OUT can be realized. The digital signal under the voltage domain IN is input through ports A0 and A1, and the digital signal under the voltage domain OUT is input through ports B0 and B1, and bidirectional conversion can be realized between the two signals.

[0019] The present invention adopts a dynamic frequency compensation method, and adds a dynamic frequency compensation module at the output end of the error amplifier EA, which can realize that the compensation resistor and the compensation capacitor change with the load current, thereby ensuring the stability of the system loop under different load currents. The circuit adopts a self-biased folded common source and common gate amplifier as the error amplifier EA, which can simplify the circuit and improve the power supply rejection ratio under the premise of meeting the DC gain. Using an NMOS tube as a power tube can improve the power supply rejection ratio while improving the load transient response performance of the system. At the same time, a level conversion module is integrated in the low-voltage difference linear regulator, which can realize the level conversion of the signal in the voltage domain where the input and output voltages are located while providing a stable power supply voltage, simplifying the off-chip circuit and meeting the requirements of circuit simplification and miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of a low voltage drop linear regulator with a high power supply rejection ratio and a level conversion function according to the present invention;

[0021] Figure 2 It is a circuit principle diagram of a linear voltage regulator part of a low voltage drop linear voltage regulator with a high power supply rejection ratio and a level conversion function according to the present invention;

[0022] Figure 3 yes Figure 2 A graph showing the change of internal node voltage with output load current during the operation of the medium frequency compensation module;

[0023] Figure 4 It is the frequency characteristic curve of the low dropout linear regulator loop;

[0024] Figure 5 It is the IN power supply rejection ratio curve of the low dropout linear regulator under various process angles;

[0025] Figure 6It is the BIAS power supply rejection ratio curve of the low dropout linear regulator under various process angles;

[0026] Figure 7 It is an input-output curve diagram of the level conversion module when it is working in a certain embodiment. DETAILED DESCRIPTION

[0027] The preferred embodiments of the present invention are given below in conjunction with the accompanying drawings and described in detail.

[0028] like Figure 1 As shown, according to the present invention, the low-voltage dropout linear regulator with high power supply rejection ratio and level conversion function includes a low-voltage dropout linear regulator and a level conversion module. The low-voltage dropout linear regulator includes an error amplifier EA, a super source follower, a frequency compensation module, a power tube MP, a feedback loop, and an output load. The output end EA_out of the error amplifier EA is connected to the super source follower and the frequency compensation module, and the frequency compensation module is used for loop adaptive frequency compensation; the gate of the power tube MP is connected to the output end of the super source follower, the drain is connected to the input voltage IN, and the feedback loop is connected to the source of the power tube MP in parallel with the output load. The level conversion module includes a power port VCCA, a power port VCCB, input ports A1 and A2, and output ports B1 and B2, wherein the power supply VCCA is connected to the input power supply IN of the low-voltage dropout linear regulator, and the power supply VCCB is connected to the output OUT of the low-voltage dropout linear regulator.

[0029] like Figure 2 The figure shows the schematic diagram of a low voltage dropout linear regulator, including an error amplifier EA, a super source follower, a frequency compensation module, a power tube MP, a feedback loop and an output load.

[0030] The error amplifier EA includes a transistor M11 and a transistor M12 for providing a tail current source, wherein the gate of the transistor M11 is connected to the gate of the transistor M12 and inputs a bias voltage Vbias1 , the drain is connected to the source of the transistor M12 , and the source is connected to the power supply BIAS.

[0031] The error amplifier EA also includes input tubes M1, M2, M3 and M4, wherein the gate of the input tube M1 inputs a reference voltage Vref1, the drain is connected to the source of the input tube M3, and the source is connected to the drain of the transistor M12; the gate of the input tube M2 inputs a feedback voltage Vfb, the drain is connected to the source of the input tube M4, and the source is connected to the drain of the transistor M12; the gate of the input tube M3 inputs a bias voltage Vbias2, and the source is connected to the drain of the input tube M1; the gate of the input tube M4 inputs a bias voltage Vbias2, and the source is connected to the drain of the input tube M2.

[0032] The error amplifier EA also includes current mirror loads M5, M6, M7, and M8, and resistor loads R1 and R2. The gate and drain of the current mirror load M5 are connected to the gates of the current mirror loads M6, M7, and M8, and the source is connected to the drain of the current mirror load M7; the gate of the current mirror load M6 is connected to the gates of the current mirror loads M5, M7, and M8, and the source is connected to the drain of the current mirror load M8; the gate of the current mirror load M7 is connected to the gates of the current mirror loads M5, M6, and M8 and the drain of the current mirror load M5, and the drains are connected to the current The source of the mirror load M5 and the drain of the input tube M3, the source is connected to the first port of the load resistor R1; the gate of the current mirror load M8 is connected to the gates of the current mirror loads M5, M6, and M7 and the drain of the current mirror load M5, the drain is respectively connected to the source of the current mirror load M6 and the drain of the input tube M4, and the source is connected to the first port of the load resistor R2; the first port of the resistance load R1 is connected to the source of the current mirror load M7, and the second port is grounded; the first port of the resistance load R2 is connected to the source of the current mirror load M8, and the second port is grounded.

[0033] The error amplifier EA also includes MOS tubes M13, M14, M15, and M16. The gate of the MOS tube M13 is connected to the gates of the MOS tubes M14, M15, and M16 respectively, the drain is connected to the source of the MOS tube M14, and the source is connected to the power supply BIAS. The gate of the MOS tube M15 is connected to the gates of the MOS tubes M13, M14, and M16 respectively, the drain is connected to the source of the MOS tube M16, and the source is connected to the power supply BIAS. The gate of the MOS tube M14 is connected to the gates of the MOS tubes M13, M15, and M16 respectively, the drain is connected to the gates of the current mirror loads M5, M6, M7, and M8 and the drain of the current mirror load M5 respectively, and the source is connected to the drain of the MOS tube M13. The gate of the MOS tube M16 is connected to the gates of the MOS tubes M13, M14, and M15 respectively, the drain is connected to the drain of the current mirror load M6, and the source is connected to the drain of the MOS tube M15. The gates of the MOS tubes M13, M14, M15, and M16 are all input with a bias voltage Vbias1.

[0034] The drain of the current mirror load M6 and the drain of the MOS tube M16 are both connected to the output end of the error amplifier EA, and the output end of the error amplifier EA is connected to the gate of the input tube M9 of the super source follower.

[0035] The error amplifier EA is a self-biased folded common source and common gate amplifier, which can meet the DC gain required by the circuit and has good anti-power supply interference capability. The output impedance of the error amplifier EA is:

[0036] R EA_out =[g m6 r o6 (g m3 r o3 r o1 / / gm8 r o8 R2)] / / g m16 r o16 r o15

[0037] where r o1 、r o3 、r o8 、r o15 、r o16 is the output impedance of the corresponding transistors M1, M3, M8, M15, and M16, g m3 , g m6 , g m8 , g m16 is the transconductance of the corresponding transistors M3, M6, M8, and M16, and R2 is the resistance value of the resistor R2.

[0038] like Figure 2 As shown, the super source follower includes an input tube M9, MOS tubes M10, M17, M18, and a resistor R3. The gate of the input tube M9 is connected to the output end of the error amplifier EA, the source is connected to the drain of the MOS tube M18, and the drain is respectively connected to the gate of the MOS tube M10 and the first port of the resistor R3; the gate of the MOS tube M10 is respectively connected to the drain of the input tube M9 and the first port of the resistor R3, the drain is connected to the source of the input tube M9 and the drain of the MOS tube M18, and the source is grounded; the first port of the resistor R3 is respectively connected to the drain of the input tube M9 and the gate of the MOS tube, and the second port is grounded; the gate of the MOS tube M17 is connected to the gate of the MOS tube M18, the drain is connected to the source of the MOS tube M18, and the source is connected to the power supply BIAS; the gate of the MOS tube M18 is connected to the gate of the MOS tube M17, the source is connected to the drain of the MOS tube M17, and the drain is respectively connected to the source of the input tube M9 and the drain of the MOS tube M10. The gates of the MOS tubes M17 and M18 are both input with a bias voltage Vbias1.

[0039] The source of the input tube M9 of the super source follower, the drain of the MOS tube M18 and the drain of the MOS tube M10 are all connected to the output end of the super source follower, and the output end of the super source follower is connected to the gate of the power tube MP.

[0040] Through the super source follower, a buffer can be formed between the output of the error amplifier EA and the power gate, reducing the impedance of the power tube gate, pushing the pole of the power tube gate to high frequency, and improving the stability of the loop.

[0041] like Figure 2As shown, the frequency compensation module includes MOS tubes M19, M20, M21, M22, M23, M24, M25, MP1, compensation resistors Rc1, Rc2, Rc3, and compensation capacitors Cc1, Cc2, Cc3. The gate of the MOS tube MP1 is connected to the gate of the power tube MP and the output end of the super source follower, the drain is connected to the power supply IN, and the source is connected to the source of the MOS tube M19 and the source of the MOS tube M23. The drain of the MOS tube M19 is respectively connected to the gate of the MOS tube M19, the gate of the MOS tube M20, and the drain of the MOS tube M21, and the source is respectively connected to the source of the MOS tube MP1 and the source of the MOS tube M23. The gate of the MOS tube M20 is connected to the gate of the MOS tube M19, the source is connected to the source of the power tube MP, and the drain is respectively connected to the drain of the MOS tube M22 and the gate of the MOS tube M23. The gate of MOS tube M21 is connected to the gate of MOS tube M22, and bias voltage Vbias3 is input at the same time. The drain is connected to the drain of MOS tube M19, the gate of M19, and the gate of M20, and the source is grounded. The gate of MOS tube M22 is connected to the gate of MOS tube M21, and bias voltage Vbias3 is input at the same time. The drain is connected to the drain of MOS tube M20 and the gate of M23, and the source is grounded. The drain of MOS tube M23 is connected to the gate of MOS tube M24, the drain of M24, and the gate of M25, and the source of MOS tube M24 is grounded. The gate of MOS tube M25 is connected to the gate and drain of MOS tube M24, the source is grounded, and the drain is connected to the second port of compensation capacitor Cc2. The second port of compensation resistor Rc1 is connected to the first port of compensation capacitor Cc1, the second port of compensation resistor Rc2 is connected to the first port of compensation capacitor Cc2, and the first ports of compensation resistor Rc1 and compensation resistor Rc2 are both connected to the output port of error amplifier EA. The second port of the compensation capacitor Cc1 is grounded, and the second port of the compensation capacitor Cc2 is connected to the drain of the MOS tube M25. The compensation resistor Rc3 is connected in series with the compensation capacitor Cc3, and the non-common end of the compensation resistor Rc3 and the compensation capacitor Cc3 is connected to the output end OUT of the low voltage difference linear regulator, and the non-common end of the compensation capacitor Cc3 and the compensation resistor Rc3 is connected to the feedback voltage Vfb.

[0042] The frequency compensation module is mainly used to change the zero-pole position of the output end of the error amplifier EA, and realize dynamic zero-pole compensation according to the size of the load current. In the frequency compensation module, the MOS tube MP1 is connected to the power tube MP in the form of a current mirror to copy the current flowing through the power tube at a certain ratio. When the load current is large, the output impedance is small, and the pole at the output end is at a high-frequency position. As the load current decreases, the output impedance gradually increases, and the pole at the output end moves from high frequency to low frequency, which affects the stability of the system. Through the fixed compensation resistors Rc1 and Rc2, compensation capacitors Cc1 and Cc2 in the frequency compensation module, and the output impedance R0 of the MOS tube M25 increases as the load current decreases, the position of the low-frequency band pole can be changed, and redundant zeros can be generated to offset the poles, thereby improving the frequency characteristics. The compensation resistor Rc3 and the compensation capacitor Cc3 form a feedforward compensation, generating a zero point between the output end and the feedback end to improve stability.

[0043] Under the action of the frequency compensation module, the zero poles at the output of the error amplifier EA are:

[0044]

[0045]

[0046]

[0047]

[0048]

[0049] Among them, R c1 is the resistance value of the compensation resistor Rc1, R eq is the equivalent resistance in series of the compensation resistor Rc2 and the output impedance of the MOS tube M25, R EA is the output impedance of the error amplifier EA, C c1 is the capacitance value of compensation capacitor Cc1, C c2 is the capacitance value of compensation capacitor Cc2, C EA is the equivalent capacitance at the output of the error amplifier EA.

[0050] The frequency compensation module is used to separate the output pole of the error amplifier EA, and two zero points are generated to offset the output pole of the linear regulator, thereby ensuring the phase margin and stabilizing the system.

[0051] The MOS tubes M19, M20, M21, and M22 in the frequency compensation module are equivalent to a voltage comparator. Due to the existence of the negative feedback loop, the source of the MOS tube M20, that is, the output terminal OUT of the linear regulator, changes very little with the load current, and the gate-source voltage Vgsp1 of the MOS tube MP1 decreases with the decrease of the load current. Under the action of the stable voltage provided by Vbias3, the drain current flowing through the MOS tube M19 remains unchanged, and the gate voltage of M19 decreases with the decrease of the load current, thereby increasing the gate-source voltage Vgs20 of the MOS tube M20, and the drain current of M20 will also increase accordingly, and the drain-source voltage increases, ensuring that the gate voltage of M23 increases with the decrease of the output load current, and the MOS tube M23 is gradually turned off. The gate voltage of the MOS tube M25 decreases as the output load current decreases, and its output impedance increases accordingly. When M25 is in the cut-off state, the output impedance is equivalent to infinity.

[0052] It can be seen that the zero point z2 generated by the frequency compensation module will tend to be low frequency as the load current decreases, which can just offset the pole at the output end. By selecting appropriate device parameters, the system can be kept stable when the load current changes.

[0053] like Figure 2 As shown, the gate of the power tube MP is respectively connected to the output end of the super source follower and the gate of the MOS tube MP1, the drain is connected to the power supply IN, and the source is connected to the output end OUT of the low voltage difference linear regulator.

[0054] The feedback loop includes a feedback resistor Rf1 and a feedback resistor Rf2 connected in series. A common end of the feedback resistor Rf1 and the feedback resistor Rf2 outputs a feedback voltage Vfb.

[0055] Furthermore, the output load includes a load capacitor CL and a load resistor RL, and the load capacitor CL and the load resistor RL are arranged in parallel.

[0056] like Figure 1 As shown, the level conversion module includes a power port VCCA, a power port VCCB, an input port A0, an input port A1, an output port B0, and an output port B1. The power port VCCA is connected to a voltage regulator input voltage IN, and the power port VCCB is connected to a voltage regulator output voltage OUT. Through the level conversion module, the level conversion between the digital signal under the voltage domain IN and the digital signal under the voltage domain OUT can be realized. The digital signal under the voltage domain IN is input through ports A0 and A1, and the digital signal under the voltage domain OUT is input through ports B0 and B1, and bidirectional conversion can be realized between the two signals.

[0057] During the operation of the linear regulator, the voltage input by the power supply IN will be converted into a stable low-disturbance output voltage OUT, which can provide power for the next-level circuit. Connecting the power port VCCA of the level conversion module to the voltage IN and the power port VCCB to the voltage OUT can convert the level signal sent (or received) by the host (or slave) working in the voltage domain IN with the level signal sent (or received) by the host (or slave) working in the voltage domain OUT, so as to achieve level signal matching in the two voltage domains.

[0058] Figure 3 The graph is a graph showing the change of the node voltage inside the frequency compensation module circuit with the output load current during the operation of the low voltage drop linear regulator. The graph also shows the change of the output resistance of the transistor M25 with the load current. Its resistance value increases with the decrease of the output load current. This resistance can generate a zero point with the compensation capacitor Cc2, which is used to offset the output terminal pole to achieve the purpose of frequency compensation.

[0059] Figure 4 The frequency characteristic curve diagram of the low voltage difference linear regulator system with and without the frequency compensation module is shown in the figure. It can be seen from the figure that under the action of the frequency compensation module, the phase margin of the loop is significantly improved, thereby improving the stability of the system.

[0060] Figure 5 This is the power supply rejection ratio curve under power supply IN, which can reach more than 90dB at low frequency.

[0061] Figure 6 This is the power supply rejection ratio curve under power supply BIAS, which can reach more than 100dB at low frequency.

[0062] Figure 7 The input and output curve diagram of the level conversion module in a certain embodiment when it is working. Data signals can be input through ports A0, A1, B0, and B1. Under the action of the internal level conversion module, the high-level signal with voltage IN input at ports A0 and A1 can be converted into a high-level signal with voltage OUT output from ports B0 and B1; the high-level signal with voltage OUT input at ports B0 and B1 can also be converted into a high-level signal with voltage IN output from ports A0 and A1.

[0063] In the present invention, the low-dropout linear regulator adopts a dynamic frequency compensation method, and a dynamic frequency compensation module is added to the output end of the error amplifier EA, so that the compensation resistor and the compensation capacitor can change with the load current, thereby ensuring the stability of the system loop under different load currents. The circuit adopts a self-biased folded common source and common gate amplifier as the error amplifier EA, which can simplify the circuit and improve the power supply rejection ratio under the premise of meeting the DC gain. Using the NMOS tube as a power tube can improve the power supply rejection ratio while improving the load transient response performance of the system. At the same time, a level conversion module is integrated in the low-dropout linear regulator, which can realize the level conversion of the signal in the voltage domain where the input and output voltages are located while providing a stable power supply voltage, simplifying the off-chip circuit and meeting the requirements of circuit simplification and miniaturization. The invention can provide power for portable devices, smart phones, industrial and medical equipment, etc., and can be used for level converters in I2C bus interface device applications, and the input and output voltage levels are compatible with the voltage levels of the I2C device specifications. The design of the invention allows the A port to track the IN level and the B port to track the OUT level. Allows bidirectional AB port voltage translation between any two levels in the range of IN voltage 0.8V to 5.5V and OUT voltage 0.8V to 3.6V.

[0064] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention. The contents not described in detail in the present invention are all conventional technical contents.

Claims

1. A high power supply rejection ratio low voltage drop linear regulator with level conversion function, characterized in that: It includes an error amplifier EA, a super source follower, a frequency compensation module, a power tube, a feedback loop, an output load and a level conversion module. The output end of the error amplifier EA is connected to the super source follower and the frequency compensation module, the gate of the power tube is connected to the output of the super source follower, the drain is connected to the input voltage IN, the feedback loop is connected to the output load in parallel and then connected to the source of the power tube, and the level conversion module includes a power supply VCCA, a power supply VCCB, input ports A1 and A2, and output ports B1 and B2, wherein the power supply VCCA is connected to the input voltage IN, and the power supply VCCB is connected to the output OUT. The error amplifier EA includes a first transistor and a second transistor for providing a tail current source. The gate of the first transistor is connected to the gate of the second transistor and inputs a bias voltage. The drain of the first transistor is connected to the source of the second transistor, and the source is connected to a power supply. The error amplifier EA also includes a first input tube, a second input tube, a third input tube and a fourth input tube, wherein the gate of the first input tube inputs a reference voltage, the drain is connected to the source of the third input tube, and the source is connected to the drain of the second transistor; the gate of the second input tube inputs a feedback voltage, the drain is connected to the source of the fourth input tube, and the source is connected to the drain of the second transistor; the gate of the third input tube inputs a bias voltage, and the source is connected to the drain of the first input tube; the gate of the fourth input tube inputs a bias voltage, and the source is connected to the drain of the second input tube. The error amplifier EA also includes a fifth current mirror load, a sixth current mirror load, a seventh current mirror load, an eighth current mirror load, a first resistor load, and a second resistor load. The gate and drain of the fifth current mirror load are connected to the gates of the sixth current mirror load, the seventh current mirror load, and the eighth current mirror load, and the source is connected to the drain of the seventh current mirror load; the gate of the sixth current mirror load is connected to the gates of the fifth current mirror load, the seventh current mirror load, and the eighth current mirror load, and the source is connected to the drain of the eighth current mirror load; the gate of the seventh current mirror load is connected to the gates of the fifth current mirror load, the sixth current mirror load, the eighth current mirror load, and the fifth current mirror load. The drain of the current mirror load is respectively connected to the source of the fifth current mirror load and the drain of the third input tube, and the source is connected to the first port of the first resistance load; the gate of the eighth current mirror load is connected to the gates of the fifth current mirror load, the sixth current mirror load, the seventh current mirror load and the drain of the fifth current mirror load, the drain is respectively connected to the source of the sixth current mirror load and the drain of the fourth input tube, and the source is connected to the first port of the second resistance load; the first port of the first resistance load is connected to the source of the seventh current mirror load, and the second port is grounded; the first port of the second resistance load is connected to the source of the eighth current mirror load, and the second port is grounded. The error amplifier EA also includes a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, and a sixteenth MOS tube. The gate of the thirteenth MOS tube is respectively connected to the gates of the fourteenth MOS tube, the fifteenth MOS tube, and the sixteenth MOS tube, the drain is connected to the source of the fourteenth MOS tube, and the source is connected to the power supply BIAS. The gate of the fifteenth MOS tube is respectively connected to the gates of the thirteenth MOS tube, the fourteenth MOS tube, and the sixteenth MOS tube, the drain is connected to the source of the sixteenth MOS tube, and the source is connected to the power supply BIAS. The gate of the fourteenth MOS tube is respectively connected to the gates of the thirteenth MOS tube, the fifteenth MOS tube, and the sixteenth MOS tube, the drain is respectively connected to the gates of the fifth current mirror load, the sixth current mirror load, the seventh current mirror load, the eighth current mirror load, and the drain of the fifth current mirror load, and the source is connected to the drain of the thirteenth MOS tube. The gate of the sixteenth MOS tube is respectively connected to the gates of the thirteenth MOS tube, the fourteenth MOS tube, and the fifteenth MOS tube, the drain is connected to the drain of the sixth current mirror load, and the source is connected to the drain of the fifteenth MOS tube. The gates of the thirteenth MOS tube, the fourteenth MOS tube, the fifteenth MOS tube and the sixteenth MOS tube are all input with a bias voltage. The drain of the sixth current mirror load and the drain of the sixteenth MOS tube are both connected to the output end of the error amplifier EA, and the output end of the error amplifier EA is connected to the gate of the ninth input tube of the super source follower.

2. The high power supply rejection ratio low voltage drop linear regulator with level conversion function according to claim 1, characterized in that: The super source follower includes a ninth input tube, a tenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube and a third resistor. The gate of the ninth input tube is connected to the output end of the error amplifier EA, the source is connected to the drain of the eighteenth MOS tube, and the drain is respectively connected to the gate of the tenth MOS tube and the first port of the third resistor; the gate of the tenth MOS tube is respectively connected to the drain of the ninth input tube and the first port of the third resistor, the drain is connected to the source of the ninth input tube and the drain of the eighteenth MOS tube, and the source is grounded; the first port of the third resistor is respectively connected to the drain of the ninth input tube and the gate of the tenth MOS tube, and the second port is grounded; the gate of the seventeenth MOS tube is connected to the gate of the eighteenth MOS tube, the drain is connected to the source of the eighteenth MOS tube, and the source is connected to the power supply; the gate of the eighteenth MOS tube is connected to the gate of the seventeenth MOS tube, the source is connected to the drain of the seventeenth MOS tube, and the drain is respectively connected to the source of the ninth input tube and the drain of the tenth MOS tube. The gates of the seventeenth MOS tube and the eighteenth MOS tube are both input with bias voltage. The source of the ninth input tube, the drain of the eighteenth MOS tube and the drain of the tenth MOS tube are all connected to the output end of the super source follower, and the output end of the super source follower is connected to the gate of the power tube.

3. The high power supply rejection ratio low voltage drop linear regulator with level conversion function according to claim 1, characterized in that: The frequency compensation module includes a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a first mirror tube, a first compensation resistor, a second compensation resistor, a third compensation resistor, a first compensation capacitor, a second compensation capacitor, and a third compensation capacitor. The gate of the first mirror tube is connected to the gate of the power tube and the output end of the super source follower, the drain is connected to the power supply IN, and the source is connected to the source of the nineteenth MOS tube and the source of the twenty-third MOS tube. The drain of the nineteenth MOS tube is respectively connected to the gate of the nineteenth MOS tube, the gate of the twentieth MOS tube, and the drain of the twenty-first MOS tube, and the source is respectively connected to the source of the first mirror tube and the source of the twenty-third MOS tube. The gate of the 20th MOS tube is connected to the gate of the nineteenth MOS tube, the source is connected to the source of the power tube, and the drain is respectively connected to the drain of the twenty-second MOS tube and the gate of the twenty-third MOS tube. The gate of the twenty-first MOS tube is connected to the gate of the twenty-second MOS tube, and the third bias voltage is input at the same time. The drain is connected to the drain of the nineteenth MOS tube, the gate of the nineteenth MOS tube, and the gate of the twentieth MOS tube, and the source is grounded. The gate of the twenty-second MOS tube is connected to the gate of the twenty-first MOS tube, and the third bias voltage is input at the same time. The drain is connected to the drain of the twentieth MOS tube and the gate of the twenty-third MOS tube, and the source is grounded. The drain of the twenty-third MOS tube is connected to the gate of the twenty-fourth MOS tube, the drain of the twenty-fourth MOS tube, and the gate of the twenty-fifth MOS tube, and the source of the twenty-fourth MOS tube is grounded. The gate of the twenty-fifth MOS tube is connected to the gate and drain of the twenty-fourth MOS tube, the source is grounded, and the drain is connected to the second port of the second compensation capacitor. The second port of the first compensation resistor is connected to the first port of the first compensation capacitor, the second port of the second compensation resistor is connected to the first port of the second compensation capacitor, and the first ports of the first compensation resistor and the second compensation resistor are both connected to the output port of the error amplifier EA. The second port of the first compensation capacitor is grounded, and the second port of the second compensation capacitor is connected to the drain of the twenty-fifth MOS tube. The third compensation resistor is connected in series with the third compensation capacitor, the non-common end of the third compensation resistor and the third compensation capacitor is connected to the output end of the low voltage difference linear regulator, and the non-common end of the third compensation capacitor and the third compensation resistor is connected to the feedback voltage.

4. The high power supply rejection ratio low voltage drop linear regulator with level conversion function according to claim 1, characterized in that: The gate of the power tube is respectively connected to the output end of the super source follower and the gate of the first mirror tube, the drain is connected to the power supply IN, and the source is connected to the output end of the low voltage difference linear regulator.

5. The high power supply rejection ratio low voltage drop linear regulator with level conversion function according to claim 1, characterized in that: The feedback loop includes a first feedback resistor and a second feedback resistor connected in series, and a common end of the first feedback resistor and the second feedback resistor outputs a feedback voltage.

6. The high power supply rejection ratio low voltage drop linear regulator with level conversion function according to claim 1, characterized in that: The output load includes a load capacitor and a load resistor, and the load capacitor and the load resistor are arranged in parallel.

7. The high power supply rejection ratio low voltage drop linear regulator with level conversion function according to claim 1, characterized in that: The level conversion module includes a power port VCCA, a power port VCCB, an input port A0, an input port A1, an output port B0, and an output port B1. The power port VCCA is connected to a voltage regulator input voltage IN, and the power port VCCB is connected to a voltage regulator output voltage OUT.

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