Method and device for realizing virtual flash based on SIU interface and display module
The display module integrates a bridge chip with a display chip and KRAM areas to provide virtual flash functionality, reducing costs and improving debugging efficiency by eliminating the need for a separate flash chip.
Patent Information
- Application Number
- CN202411275816.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-01-03
Smart Images
Figure CN119248212A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of display modules, and in particular to a method, a device and a display module for realizing virtual flash based on a system interface unit (SIU) interface. Background Art
[0002] The existing display module is composed of a bridge chip and a display chip. The bridge chip needs to have a flash memory protocol interaction firmware, and the display chip needs a flash memory touch recognition processing firmware. In this case, two flash chips are required, such as Figure 1 The figure shows a conventional hardware connection diagram. This method will cause the overall cost of the display module to be too high, and it is inconvenient to debug and maintain. It is also very inconvenient when burning the flash of the display chip.
[0003] In summary, there is an urgent need for a display module with low flash cost, convenient burning and upgrading program, and shortened debugging cycle. Summary of the invention
[0004] The present invention provides a method, device and display module for realizing virtual flash based on SIU interface, so as to solve the defects of the prior art that the overall cost of the display module is too high and it is inconvenient to debug and maintain, and realizes a display module with low flash cost, convenient burning and upgrading program and shortened debugging cycle.
[0005] The present invention provides a display module, comprising a bridge chip connected to an MCU unit and a display chip connected to a display screen, wherein the bridge chip is connected to a flash, the bridge chip is connected to the display chip via an IIC bus, and the flash interface of the display chip is also connected to the spi_slave interface of the bridge chip.
[0006] According to a display module provided by the present invention, the flash burns the firmware of the display chip and the firmware of the bridge chip.
[0007] The present invention provides a method for realizing virtual flash based on a system integration unit (SIU) interface, which is applicable to the above-mentioned display module. The method comprises:
[0008] After power-on, the display chip sends data read commands to the bridge chip through the spi_slave interface;
[0009] The bridge chip receives and parses the data read command, obtains the read address, and loads the read data from the fourth area of the KRAM according to the read address. The fourth area is an area where part of the data is pre-loaded, and the start address of the KRAM points to the end position of the second area.
[0010] The bridge chip determines whether the read data length is greater than NkB, where N is a positive integer;
[0011] If the read data length is less than or equal to NkB, the bridge chip sequentially loads the read data into the fourth area, the second area, and the third area of the KRAM;
[0012] If the read data length is greater than NkB, the bridge chip continues to load the read data in the first area after the fourth area, the second area and the third area of the KRAM are loaded in sequence;
[0013] The bridge chip returns the read data to the display chip through the spi_slave interface.
[0014] According to a method for implementing virtual flash based on a system interface unit interface provided by the present invention, after continuing to load the read data in the first area, the method further includes:
[0015] The bridge chip continues to alternately load the remaining read data into the second area and the first area.
[0016] According to a method for implementing virtual flash based on a system interface unit interface provided by the present invention, the bridge chip continues to alternately load the remaining read data in the second area and the first area specifically:
[0017] When returning the read data of the first area, the bridge chip loads the remaining read data from the flash to the second area in the rising edge interrupt processing function of the CS signal pin;
[0018] When returning the read data of the second area, the bridge chip loads the remaining read data from the flash to the first area in the rising edge interrupt processing function of the CS signal pin, and executes this cycle until all the read data are loaded.
[0019] According to a method for implementing virtual flash based on a system interface unit interface provided by the present invention, N is equal to 4.
[0020] According to a method for implementing virtual flash based on a system interface unit interface provided by the present invention, the data read command includes a read instruction and a read address.
[0021] The present invention also provides a device for implementing virtual flash based on a system interface unit interface, the device comprising:
[0022] The command sending unit is used for the display chip to send data read commands to the bridge chip through the spi_slave interface after power-on;
[0023] An instruction receiving unit, used for the bridge chip to receive and parse the data read command, obtain a read address, and load the read data from the fourth area of the KRAM according to the read address, the fourth area is an area where part of the data is pre-loaded, and the start address of the KRAM points to the end position of the second area;
[0024] A data judgment unit, used for the bridge chip to judge whether the length of the read data is greater than NkB, where N is a positive integer;
[0025] A first reading unit, configured to load the read data in the fourth area, the second area, and the third area of the KRAM in sequence by the bridge chip if the read data length is less than or equal to NkB;
[0026] A second reading unit, configured to, if the length of the read data is greater than NkB, cause the bridge chip to continue loading the read data into the first area after the fourth area, the second area and the third area of the KRAM are loaded in sequence;
[0027] A data returning unit is used for the bridge chip to return the read data to the display chip through the spi_slave interface.
[0028] According to a device for implementing virtual flash based on a system interface unit interface provided by the present invention, the device further includes:
[0029] The alternate loading unit is used for the bridge chip to continue to alternately load the remaining read data into the second area and the first area.
[0030] Specifically, the alternating loading unit is specifically used for, when the read data of the first area is returned, the bridge chip loads the remaining read data from the flash to the second area in the rising edge interrupt processing function of the CS signal pin; when the read data of the second area is returned, the bridge chip loads the remaining read data from the flash to the first area in the rising edge interrupt processing function of the CS signal pin, and the cycle is executed until all the read data are loaded.
[0031] According to a device for implementing virtual flash based on a system interface unit interface provided by the present invention, N is equal to 4.
[0032] According to a device for implementing virtual flash based on a system interface unit interface provided by the present invention, the data read command includes a read instruction and a read address.
[0033] The present invention also provides a chip, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for realizing virtual flash based on the system interface unit interface as described in any one of the above is implemented.
[0034] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for realizing virtual flash based on a system interface unit interface as described in any one of the above is implemented.
[0035] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method for realizing a virtual flash based on a system interface unit interface as described in any one of the above is implemented.
[0036] The method, device and display module for realizing virtual flash based on SIU interface provided by the present invention reduce the cost by reducing one flash by connecting the flash interface of the display chip to the spi_slave interface of the bridge chip, and at the same time facilitate the burning of upgrade programs and shorten the debugging cycle. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0038] Figure 1 It is a structural schematic diagram of an existing display module provided by the background technology.
[0039] Figure 2 It is a structural schematic diagram of the display module provided by the present invention.
[0040] Figure 3 It is a schematic diagram of the structure of the KRAM provided by the present invention.
[0041] Figure 4 It is a flow chart of a method for realizing virtual flash based on SIU interface provided by the present invention.
[0042] Figure 5 It is a structural schematic diagram of the data reading command provided by the present invention.
[0043] Figure 6 It is a schematic diagram of the structure of the chip provided by the present invention. DETAILED DESCRIPTION
[0044] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0045] In the embodiments of the present invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. In the textual description of the present invention, the character " / " generally indicates that the previous and next associated objects are in an "or" relationship. In addition, it should be noted that the serial numbers themselves, such as "first", "second", etc., used to distinguish the objects described in the present invention are only used to distinguish the objects described, and do not have any order or technical meaning.
[0046] Figure 2 is one of the structural schematic diagrams of the display module provided by the present invention, such as Figure 1 As shown, the display module includes a bridge chip connected to the MCU unit and a display chip connected to the display screen, wherein the bridge chip is connected to a flash, and the bridge chip is connected to the display chip via an IIC (Inter-Integrated Circuit) bus, and the flash interface of the display chip is also connected to the spi_slave interface of the bridge chip. The flash burns the firmware of the display chip and the firmware of the bridge chip. After power-on, the display chip sends a data read command to the bridge chip via the SPI interface, and the data read command includes a read instruction and a read address; the bridge chip receives and parses the data read command, obtains the read address, and at the same time loads the read data from the fourth area of the KRAM according to the read address. The KRAM is a random access memory marked as K inside the chip, and the starting address of the KRAM points to the end position of the second area, as shown Figure 3As shown, the KRAM is divided into a first area, a second area, a third area and a fourth area in sequence, and the length of the KRAM is 4096 bytes, wherein the fourth area is a pre-loaded data area to ensure timely return of data; the bridge chip determines whether the read data length is greater than NkB, wherein N is a positive integer, and N is equal to 4; if the read data length is less than or equal to NkB, the bridge chip loads the read data in the fourth area, the second area and the third area of the KRAM in sequence; if the read data length is greater than NkB, the bridge chip continues to load the read data in the first area after the fourth area, the second area and the third area of the KRAM are loaded in sequence; the bridge chip returns the read data to the display chip through the SPI interface.
[0047] The display module provided by the embodiment of the present invention reduces the cost by reducing one flash by connecting the flash interface of the display chip to the spi_slave interface of the bridge chip, and at the same time facilitates burning of upgrade programs and shortens the debugging cycle.
[0048] Figure 4 This is one of the flow charts of the method for implementing virtual flash based on the system integration unit (SIU) interface provided by the present invention, such as Figure 4 As shown, the method includes the following:
[0049] Step 401: After power-on, the display chip sends a data read command to the bridge chip via the SPI interface. The data read command includes a read instruction and a read address. Figure 5 As shown, it includes command (1 byte), 24-bit address (3 bytes), dummy (1 byte), a total of 5 bytes; after receiving the first 4 bytes of data, the bridge chip can parse the read command and read address.
[0050] Step 402, the bridge chip receives and parses the data read command, obtains the read address, and loads the read data from the fourth area of the KRAM according to the read address. The fourth area is an area where some data is pre-loaded. The starting address of the KRAM points to the end position of the second area, that is, Figure 3 The position of 1 in the figure is determined according to the data reading protocol and the bridge chip analysis time.
[0051] Step 403: The bridge chip determines whether the read data length is greater than NkB, where N is a positive integer. Preferably, N is equal to 4.
[0052] Step 404: If the read data length is less than or equal to NkB, the bridge chip sequentially loads the read data into the fourth area, the second area, and the third area of the KRAM.
[0053] Step 405: If the length of the read data is greater than NkB, the bridge chip continues to load the read data in the first area after loading the fourth area, the second area and the third area of the KRAM in sequence.
[0054] Preferably, after continuing to load the read data in the first area, the method further includes:
[0055] The bridge chip continues to alternately load the remaining read data into the second area and the first area.
[0056] Specifically, when returning the read data of the first area, the bridge chip loads the remaining read data from the flash to the second area in the rising edge interrupt processing function of the CS signal pin;
[0057] When returning the read data of the second area, the bridge chip loads the remaining read data from the flash to the first area in the rising edge interrupt processing function of the CS signal pin, and repeats this cycle until all the read data are loaded. Since the speed of loading flash is faster than the speed of returning data from the spi_slave interface, the data in Kram is prevented from being overwritten by dividing different address spaces.
[0058] Step 406: The bridge chip returns the read data to the display chip through the spi_slave interface.
[0059] The method for realizing virtual flash based on SIU interface provided by the embodiment of the present invention is as follows: after power-on, the display chip sends a data read command to the bridge chip through the spi_slave interface; the bridge chip receives and parses the data read command, obtains the read address, and loads the read data from the fourth area of KRAM according to the read address, the fourth area is an area for pre-loading part of the data, and the start address of the KRAM refers to the end position of the second area; the bridge chip determines whether the read data length is greater than NkB, and N is a positive integer; if the read data length is less than or equal to NkB, the bridge chip sequentially loads the read data in the fourth area, the second area and the third area of the KRAM; if the read data length is greater than NkB, the bridge chip sequentially loads the read data in the first area after the fourth area, the second area and the third area of the KRAM are loaded; the bridge chip returns the read data to the display chip through the spi_slave interface, so that the firmware in the flash is loaded through the bridge chip while reducing one flash, which can reduce the cost of the display module and make firmware burning more convenient.
[0060] The following is a description of a device for implementing a virtual flash based on a system interface unit interface provided by the present invention. The device for implementing a virtual flash based on a system interface unit interface described below and the method for implementing a virtual flash based on a system interface unit interface described above can be referred to each other. The device includes:
[0061] The command sending unit is used for the display chip to send data read commands to the bridge chip through the spi_slave interface after power-on;
[0062] An instruction receiving unit, used for the bridge chip to receive and parse the data read command, obtain a read address, and load the read data from the fourth area of the KRAM according to the read address, the fourth area is an area where part of the data is pre-loaded, and the start address of the KRAM points to the end position of the second area;
[0063] A data judgment unit, used for the bridge chip to judge whether the length of the read data is greater than NkB, where N is a positive integer;
[0064] A first reading unit, configured to load the read data in the fourth area, the second area, and the third area of the KRAM in sequence by the bridge chip if the read data length is less than or equal to NkB;
[0065] A second reading unit, configured to, if the length of the read data is greater than NkB, cause the bridge chip to continue loading the read data into the first area after the fourth area, the second area and the third area of the KRAM are loaded in sequence;
[0066] A data returning unit is used for the bridge chip to return the read data to the display chip through the spi_slave interface.
[0067] Further, after continuing to load the read data in the first area, the device further includes:
[0068] The alternate loading unit is used for the bridge chip to continue to alternately load the remaining read data into the second area and the first area.
[0069] Specifically, the alternating loading unit is specifically used for, when the read data of the first area is returned, the bridge chip loads the remaining read data from the flash to the second area in the rising edge interrupt processing function of the CS signal pin; when the read data of the second area is returned, the bridge chip loads the remaining read data from the flash to the first area in the rising edge interrupt processing function of the CS signal pin, and the cycle is executed until all the read data are loaded.
[0070] Furthermore, N is equal to 4.
[0071] Furthermore, the data read command includes a read instruction and a read address.
[0072] Figure 6 The schematic diagram of the physical structure of a chip is shown as an example. Figure 6As shown, the chip may include: a processor (processor) 810, a communication interface (Communications Interface) 820, a memory (memory) 830 and a communication bus 840, wherein the processor 810, the communication interface 820, and the memory 830 communicate with each other through the communication bus 840. The processor 810 can call the logic instructions in the memory 830 to execute the method for realizing virtual flash based on the system interface unit interface, the method comprising: after power-on, the display chip sends a data read command to the bridge chip through the spi_slave interface; the bridge chip receives and parses the data read command, obtains the read address, and loads the read data from the fourth area of the KRAM according to the read address, the fourth area is an area for pre-loading part of the data, and the start address of the KRAM points to the end position of the second area; the bridge chip determines whether the read data length is greater than NkB, where N is a positive integer; if the read data length is less than or equal to NkB, the bridge chip sequentially loads the read data in the fourth area, the second area and the third area of the KRAM; if the read data length is greater than NkB, the bridge chip sequentially loads the read data in the first area after the fourth area, the second area and the third area of the KRAM are loaded; the bridge chip returns the read data to the display chip through the spi_slave interface.
[0073] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.
[0074] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the method for realizing virtual flash based on the system interface unit interface provided by the above methods, and the method includes: after power-on, the display chip sends a data read command to the bridge chip through the spi_slave interface; the bridge chip receives and parses the data read command, obtains the read address, and loads the read data from the fourth area of the KRAM according to the read address, and the fourth area is a pre-loaded part of the data area, the starting address of the KRAM points to the end position of the second area; the bridge chip determines whether the read data length is greater than NkB, and N is a positive integer; if the read data length is less than or equal to NkB, the bridge chip loads the read data in the fourth area, the second area and the third area of the KRAM in sequence; if the read data length is greater than NkB, the bridge chip continues to load the read data in the first area after the fourth area, the second area and the third area of the KRAM are loaded in sequence; the bridge chip returns the read data to the display chip through the spi_slave interface.
[0075] On the other hand, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method for realizing virtual flash based on the system interface unit interface provided by the above methods is implemented, and the method includes: after power-on, the display chip sends a data read command to the bridge chip through the spi_slave interface; the bridge chip receives and parses the data read command, obtains the read address, and loads the read data from the fourth area of the KRAM according to the read address, the fourth area is an area where part of the data is pre-loaded, and the start address of the KRAM points to the end position of the second area; the bridge chip determines whether the length of the read data is greater than NkB, and N is a positive integer; if the length of the read data is less than or equal to NkB, the bridge chip loads the read data in the fourth area, the second area and the third area of the KRAM in sequence; if the length of the read data is greater than NkB, the bridge chip continues to load the read data in the first area after the fourth area, the second area and the third area of the KRAM are loaded in sequence; the bridge chip returns the read data to the display chip through the spi_slave interface.
[0076] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0077] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.
[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A display module, comprising a bridge chip connected to an MCU unit and a display chip connected to a display screen, wherein: The bridge chip is connected to a flash, and the bridge chip is connected to the display chip via an IIC bus. It is characterized in that the flash interface of the display chip is also connected to the spi_slave interface of the bridge chip.
2. The display module according to claim 1, characterized in that: The flash burns the firmware of the display chip and the firmware of the bridge chip.
3. A method for implementing virtual flash based on a system integration unit (SIU) interface, characterized in that: Applicable to the above display module, the method includes: After power-on, the display chip sends data read commands to the bridge chip through the spi_slave interface; The bridge chip receives and parses the data read command, obtains the read address, and loads the read data from the fourth area of the KRAM according to the read address. The fourth area is an area where part of the data is pre-loaded, and the start address of the KRAM points to the end position of the second area. The bridge chip determines whether the read data length is greater than NkB, where N is a positive integer; If the read data length is less than or equal to NkB, the bridge chip sequentially loads the read data into the fourth area, the second area, and the third area of the KRAM; If the read data length is greater than NkB, the bridge chip continues to load the read data in the first area after the fourth area, the second area and the third area of the KRAM are loaded in sequence; The bridge chip returns the read data to the display chip through the spi_slave interface.
4. The method according to claim 3, characterized in that After continuing to load the read data into the first area, the method further includes: The bridge chip continues to alternately load the remaining read data into the second area and the first area.
5. The method according to claim 4, characterized in that The bridge chip continues to alternately load the remaining read data in the second area and the first area. Specifically: When returning the read data of the first area, the bridge chip loads the remaining read data from the flash to the second area in the rising edge interrupt processing function of the CS signal pin; When returning the read data of the second area, the bridge chip loads the remaining read data from the flash to the first area in the rising edge interrupt processing function of the CS signal pin, and executes this cycle until all the read data are loaded.
6. The method according to claim 3, characterized in that: The N is equal to 4.
7. The method according to claim 3, characterized in that The data read command includes a read instruction and a read address.
8. A chip comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method for realizing virtual flash based on the system interface unit interface as described in any one of claims 3 to 7 is implemented.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for realizing virtual flash based on a system interface unit interface as claimed in any one of claims 3 to 7 is implemented.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method for realizing virtual flash based on a system interface unit interface as claimed in any one of claims 3 to 7 is implemented.