Adaptive analysis method and system for key instruction sequence fusion strategy

Abstract

The invention belongs to the technical field of computer architecture and instruction set optimization, and particularly relates to a self-adaptive analysis method and system for a key instruction sequence fusion strategy. The method comprises the following steps: according to an input program code, deeply mining a key instruction sequence with fusion potential to obtain a candidate key instruction sequence; formulating a scientific and effective fusion strategy for the candidate key instruction sequence, and selecting an optimal fusion strategy; selecting fusion parameters of the micro-system structure according to the optimal fusion strategy; and evaluating the performance and overhead of the fusion strategy. According to the method, self-adaptive analysis of the fusion strategy can be carried out according to customization requirements of different application scenes, simulation verification and continuous iteration are carried out by utilizing an existing simulator, an optimal micro-system structure implementation scheme is selected, and the problem that the current fusion strategy lacks generalization ability to cope with continuously expanded instruction sets can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer architecture and instruction set optimization, and in particular relates to an adaptive analysis method and system for a key instruction sequence fusion strategy. Background Art

[0002] In today's digital wave, with the rapid progress in machine learning, deep learning, and artificial intelligence, the complexity and scale of large-scale models are showing a trend of continuous growth. In order to adapt to the increasingly diverse and complex application scenarios, the instruction set is also constantly expanding and optimizing to meet more extensive and in-depth needs. Instruction fusion technology is of great significance in microarchitecture design and will play a more important role in future processor design.

[0003] Instruction fusion technology is a key technology to improve performance and reduce power consumption. This technology combines multiple instructions into a composite instruction for execution, reducing the waiting time between instructions within the composite instruction due to dependencies, thereby improving the execution efficiency and overall performance of the instructions. In addition, instruction fusion technology reduces the number of instructions required when the processor performs the same task, improves the utilization of the processor's internal renaming history table, physical registers, reordering cache and other micro-architectures, makes full use of existing execution units, and reduces dynamic power consumption.

[0004] Due to the complexity and variability of upper-level applications, the design requirements for micro-architectures are also different. The corresponding fusion strategy selection also changes due to application requirements. Existing instruction fusion solutions propose specific fusion solutions for specific instruction sets based on different performance requirements. Fusion instruction types include floating-point instructions, memory access instructions, operation instructions, branch instructions, conditional transfer instructions, encryption instructions, heterogeneous computing instructions, etc. The selection of instruction fusion stages includes the pre-fetch stage, decoding stage, and dispatch stage of instructions. Existing instruction fusion technology selects sequentially adjacent continuous instructions for fusion, and designers fuse instructions based on the performance requirements of different application fields.

[0005] Typical instruction set architectures have been continuously expanding to adapt to complex and changing application requirements. For example, in order to meet the growing computing needs and accelerate computing-intensive tasks in machine learning, graphics analysis, data-driven and other fields, x86, Arm, and RISC-V are constantly expanding their respective instruction sets. With the widespread application of design methods for application-specific architectures, the demand for customization of dedicated hardware accelerators is also growing explosively. Fusion, as a necessary technology for performance improvement, also needs to determine new fusion solutions and microarchitecture implementations as the instruction set expands.

[0006] The future instruction set architecture needs to be more flexible and scalable to support more customized hardware accelerators. At the same time, the microarchitecture also needs to be continuously optimized and innovated to adapt to new fusion solutions and performance improvement requirements. However, the design, performance improvement, and verification of existing fusion strategies all require manual participation, which has the following shortcomings.

[0007] 1) Different application scenarios and micro-architectures have different requirements for instruction fusion. The fusion strategy with manual participation lacks generalization ability when facing diverse application scenarios, is difficult to adapt to various scenarios, and lacks flexibility.

[0008] 2) The complex dependency relationship of instructions requires detailed analysis of the dependency relationship of each instruction during the fusion strategy formulation process. This complex dependency analysis is not only time-consuming but also prone to errors, which increases the difficulty of fusion strategy design.

[0009] 3) Different fusion strategies and corresponding microarchitecture implementations require a lot of correctness verification to ensure that the fused instructions can be executed correctly. Summary of the invention

[0010] The formulation of existing instruction fusion strategies often relies on manual analysis and experience. This method is not only inefficient but also prone to errors. The present invention is used to solve the dilemma of the current fusion strategy's lack of generalization ability to cope with the ever-expanding instruction set. According to application requirements, a verification-friendly fusion strategy and microarchitecture implementation are formulated.

[0011] The technical solution adopted by the present invention is as follows:

[0012] An adaptive analysis method for a key instruction sequence fusion strategy comprises the following steps:

[0013] According to the input program code, the key instruction sequences with fusion potential are deeply mined to obtain candidate key instruction sequences;

[0014] Formulate scientific and effective fusion strategies for candidate key instruction sequences and select the optimal fusion strategy;

[0015] Selecting fusion parameters of the microarchitecture according to the optimal fusion strategy;

[0016] Evaluate the performance and overhead of fusion strategies.

[0017] Furthermore, the in-depth mining of key instruction sequences with fusion potential includes:

[0018] Input standard test program slices or customized code snippets;

[0019] The instruction-level simulator generates a trace log file corresponding to the input;

[0020] By processing the trace log files, the candidate key instruction sequences are extracted using word vector models and sequential pattern mining techniques.

[0021] Furthermore, the extracting of candidate key instruction sequences by using a word vector model and a sequence pattern mining technique includes:

[0022] Obtain hot segments of the application load program and classify the hot segments;

[0023] Filter data, remove comments and extra blank lines, and ensure that each instruction has a consistent format;

[0024] Perform text preprocessing, split each instruction into instruction name and operand, and unify the representation of instructions;

[0025] Use the Word2Vec model to build word vectors;

[0026] Extract the vector representation of each instruction from the Word2Vec model, cluster the instruction vectors using the K-means algorithm, and determine the cluster to which each instruction belongs;

[0027] According to the clustering results, the PrefixSpan algorithm is used to mine sequence patterns and obtain the pattern vectors of key instruction sequences.

[0028] Furthermore, the selection of the optimal fusion strategy is to find a key instruction sequence with the minimum number of instructions after fusion from the input candidate key instruction sequences, including using a user-defined fusion strategy or using a machine learning model to automatically generate a fusion strategy.

[0029] Furthermore, the selecting the optimal fusion strategy includes:

[0030] First, the priority is set, including: calculating the sequence vector and category vector of the candidate key instruction sequence, measuring the cosine similarity between the sequence vector and each category vector, the value of the cosine similarity ranges from -1 to 1, and then mapping it to a value [0,1] aligned with the priority, and sorting all the candidate key instruction sequences by priority;

[0031] Then perform fusion detection, including:

[0032] a) Define two sets: strategy set A = {}, initially empty; candidate set B = {candidate fusion instruction sequences};

[0033] b) Use an instruction-level simulator to measure the number of instructions in the workload, denoted as K;

[0034] c) According to the descending priority order of the candidate fused instruction sequences in set B, they are added to set A one by one. Each time set A is updated, the number of instructions after fusion is measured and recorded as K1, K2...K n ;

[0035] d) Repeat the previous step and continue to optimize until the convergence threshold is reached: ((K i -K i-1 ) / K i-1 )*100%<0.1%.

[0036] Furthermore, the method of selecting fusion parameters of the microarchitecture according to the optimal fusion strategy includes: building a microarchitecture simulation simulator on a cycle-level simulator, selecting the most appropriate microarchitecture parameters during the dynamic optimization process, including the fusion stage, the emission width, whether to support fusion across data caches, and the fusion window size, using a microarchitecture simulation model to check the dependencies between instructions and apply the fusion strategy.

[0037] Furthermore, the fusion parameters of the microarchitecture are selected according to the optimal fusion strategy, and the following functions are supported: customization of fusion window width, customization of fusion conditions, and setting of fusion switches separately for each fusion pair; the customization of fusion conditions is used to perform correctness detection on the fused instructions to ensure that the instruction dependencies are not destroyed, including register dependency checks, specific instruction type matching, no branch or storage instruction restrictions, instruction order and register matching checks.

[0038] Furthermore, the performance and overhead of the fusion strategy are evaluated, including: using an instruction fusion simulation simulator, re-entering the benchmark program or customized code snippet, performing a performance simulation test, calculating and comparing the evaluation parameters before and after the fusion, as a reference factor for whether feedback is needed to iterate the microarchitecture design; by comparing the execution efficiency before and after the fusion, the performance improvement and area overhead of the processor caused by the fusion strategy are evaluated, thereby verifying the effectiveness of the fusion strategy and providing an important reference basis for subsequent optimization.

[0039] An adaptive analysis system for a key instruction sequence fusion strategy, comprising:

[0040] A fusion instruction determination module is used to deeply mine key instruction sequences with fusion potential based on the input program code to obtain candidate key instruction sequences;

[0041] The fusion strategy formulation module is used to formulate scientific and effective fusion strategies for candidate key instruction sequences and select the optimal fusion strategy;

[0042] A micro-architecture performance evaluation module, used to select the fusion parameters of the micro-architecture according to the optimal fusion strategy;

[0043] The fusion performance evaluation module is used to evaluate the performance and overhead of the fusion strategy.

[0044] The beneficial effects of the present invention are as follows:

[0045] The present invention aims to cope with the ever-expanding instruction set and proposes an adaptive analysis method and system, focusing on the optimization of key instruction sequence fusion strategy. The scheme is highly flexible and can perform adaptive analysis and adjustment of fusion strategy according to the specific needs of different application scenarios. The present invention uses instruction-level simulators and cycle-level simulators to automatically simulate the fusion strategy, and selects the best micro-architecture implementation scheme through iterative optimization.

[0046] The advantages of the present invention include: reducing manual involvement and improving the adaptive ability of the fusion strategy; verification-friendly; quantifying the selection process of the optimal instruction fusion sequence strategy; integrating the mainstream implementation methods of instruction fusion technology in micro-architecture BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a flow chart of the overall steps of the method of the present invention.

[0048] Figure 2 This is a flow chart of generating a trace log file through an instruction-level simulator.

[0049] Figure 3 It is a flowchart of hotspot fragment generation.

[0050] Figure 4 It is a flowchart of the classification of hot snippets of assembly type.

[0051] Figure 5 It is a flowchart for extracting candidate key instruction sequences.

[0052] Figure 6 It is a flow chart for developing a fusion strategy.

[0053] Figure 7 is a flow chart for selecting fusion parameters for the microarchitecture. DETAILED DESCRIPTION

[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below through specific embodiments and drawings.

[0055] This solution proposes an adaptive analysis method and system for the fusion strategy of key instruction sequences for the ever-expanding instruction set. The solution can perform adaptive analysis of the fusion strategy based on the customized requirements of different application scenarios, and use the existing simulator for simulation verification, and continuously iterate to select the optimal micro-architecture implementation solution. The system includes the following key steps: mining key instruction sequences that can be fused, formulating fusion strategies, selecting micro-architecture fusion parameters, and evaluating the performance and overhead of the fusion strategy.

[0056] The overall process of the present invention is as follows Figure 1 As shown in the figure, this method mainly includes the following key links:

[0057] 1. Identify fusion instructions: Deeply explore key instruction sequences with fusion potential.

[0058] The input of this step is a benchmark program slice or a customized optimized code snippet provided by the user. The compilation parameters of the code snippet must be indicated, and it must represent the key execution path of the entire program. Then the instruction-level simulator (Spike) generates a trace log file (trace.log) corresponding to the input, such as Figure 2 shown.

[0059] At this stage, the system needs to input typical assembly code snippets to be optimized and the microarchitecture parameters of the processor. Through the instruction-level simulator, the system can generate corresponding trace log files, which record in detail the behavior and data flow of the processor when executing instructions. By processing the log files, the word vector model and sequence pattern mining technology are used to extract candidate key instruction sequences. The purpose of this step is to identify candidate fusion-enabled key instruction sequences. The input does not limit the type of programming language, and the processing method during the processing is not limited to a specific machine learning model.

[0060] 1.1) Classification of hotspot segments of application load programs

[0061] 1.1.1) Input: This stage supports two types of input, namely:

[0062] a) Application load program (high-level programming language);

[0063] b) Application load program and standard instruction set documentation.

[0064] The application load program can be written in either high-level programming language or assembly language. If the load program is in assembly language, the recommended format for the load program is to have one single statement per line.

[0065] 1.1.2) Output: This step outputs the category label of the workload, and the identified key instruction sequence and its category label. The labels preset in the system include but are not limited to the following 8 categories:

[0066] Continuous memory-intensive tasks: Continuous read and write operations in memory, usually accessing a large continuous memory area.

[0067] Hash-type memory-intensive tasks: involve non-contiguous memory access patterns, usually used for operations on data structures such as hash tables, linked lists, or tree structures.

[0068] Computationally intensive tasks: The CPU's arithmetic logic unit (ALU) is highly loaded, and memory accesses are relatively rare.

[0069] Control flow sensitive tasks: highly dependent on the control flow of the program (such as conditional branches and loops), and the performance is greatly affected by branch prediction and instruction pipeline.

[0070] Computational precision-sensitive tasks: These tasks require very high precision in the calculation results, usually involving floating-point operations.

[0071] Linear dependency tasks: The result of the current operation directly depends on the result of the previous operation, usually expressed as a sequentially executed algorithm.

[0072] Non-linear dependency tasks: The dependency relationship is more complex, and the data processing order is not necessarily linear, which may involve parallel computing or graph algorithms.

[0073] Reduction-intensive tasks: involve reducing a large amount of data into a smaller amount of data, commonly seen in data aggregation operations such as summation, statistics, and maximum / minimum calculations.

[0074] 1.1.3) Execution process: In this step, the execution platform for operating the application load program is an instruction-level simulator.

[0075] 1.1.3.1) Hotspot fragment generation:

[0076] The process of generating hotspot fragments is as follows Figure 3 As shown, the following steps are included:

[0077] a) Configure the instruction-level simulator: Configure the instruction-level simulator to accurately simulate the specific processor architecture, ensuring that the simulator can simulate all key instructions and processor features.

[0078] b) Generate instruction trace file: Integrate the instruction trace information in the log into an instruction trace file, which contains all the instructions executed during the simulation and their context information.

[0079] c) Script processing and hot spot analysis: Use the script provided by this system to analyze the instruction tracking file. The script parses the execution frequency of each instruction and identifies the instruction sequence with the most execution times.

[0080] 1.1.3.2) Classification of hot snippets of assembly type: using clustering algorithm

[0081] The process of categorizing hotspot fragments of compilation type is as follows: Figure 4 As shown, the following steps are included:

[0082] a) Input: assembly source code (x86, RISC-V, ARM, etc.)

[0083] b) Instruction statistics: Statistics on the usage frequency of different types of instructions (such as arithmetic, memory access, and control flow instructions).

[0084] c) Feature extraction - analyzing memory access patterns: analyzing the pattern c of memory access instructions.

[0085] Continuous memory-intensive tasks: a large number of sequential memory access instructions, such as MOV, LOAD, and STORE, and the memory addresses are continuous.

[0086] Hash-based memory-intensive tasks: Memory access instructions access random memory addresses, and these access patterns have no obvious sequential order.

[0087] Computation-intensive tasks: A large number of arithmetic instructions such as ADD, MUL, DIV, etc., and fewer memory access instructions.

[0088] Control flow sensitive tasks: contain a large number of jump instructions such as JMP, JNZ, JZ, etc., and are classified by analyzing control flow structures such as conditional statements and loops in the program.

[0089] Precision-sensitive tasks: A large number of floating-point instructions such as FADD and FMUL can be distinguished by checking the precision of floating-point operations in the program.

[0090] Linear dependency tasks: There is a strong dependency between instructions, and the execution of the current instruction needs to wait for the completion of the previous instruction.

[0091] Non-linear dependency tasks: The dependency relationship between instructions is complex and irregular.

[0092] Reduction-intensive tasks: A large number of reduction operation instructions and loop operations are used to reduce data by traversing the data.

[0093] d) Data preprocessing:

[0094] Standardization: Standardize the feature data to eliminate the impact of dimension.

[0095] Dimensionality reduction: Use principal component analysis to reduce the dimensionality of high-dimensional feature (PAC) data.

[0096] e) Set clustering parameters:

[0097] Determine the number of clusters K: The K value is preset to 8 (continuous memory access intensive tasks, hash memory access intensive tasks, computation intensive tasks, control flow sensitive tasks, calculation precision sensitive tasks, linear dependency tasks, nonlinear dependency tasks, reduction intensive tasks)

[0098] f) Feature selection and preprocessing: Instruction statistics, memory access patterns, and branch density are selected as features. The features are standardized to ensure that each task feature contributes equally to the hotspot segment clustering results.

[0099] g) Initialize cluster centers: randomly select K points in the hotspot segment set as the initial cluster centers

[0100] h) Assign data points to the nearest cluster center: For each point in the dataset, calculate its distance to all cluster centers and assign it to the nearest cluster center.

[0101] i) Update cluster centers: For each cluster, calculate the mean of all points assigned to that cluster and set it as the new cluster center.

[0102] j) Iterate until convergence: Repeat steps h) and i) until the change in cluster center is less than a predetermined threshold.

[0103] k) Evaluate clustering results: Use the silhouette coefficient to evaluate the quality of the clustering and analyze the clustering results to associate each cluster with a task type based on the features. A small amount of data can be manually labeled to help interpret the clustering results.

[0104] l) Output: The output corresponding to each hotspot segment is represented by the data structure shown in Table 1:

[0105] Table 1

[0106]

[0107] 1.1.3.3) Classification of high-level programming language type hotspot fragments. The other steps are the same as those in the above-mentioned “classification of assembly type hotspot fragments”, only the feature extraction method is slightly different.

[0108] Continuous memory-access intensive tasks: When the program is running, record the address sequence of memory accesses to check whether there are continuous memory address accesses or whether there are continuous memory-access intensive tasks that are usually manifested as operations on large arrays or matrices, such as large-scale vector addition or matrix multiplication.

[0109] Hash-based memory-intensive tasks: When the program is running, record the address sequence of memory accesses and check whether there is a random memory access pattern.

[0110] Computation-intensive tasks: When the program is running, record the execution frequency of arithmetic instructions.

[0111] Control flow sensitive tasks: When the program is running, record the execution frequency of jump instructions, such as if-else, switch-case, for, while and other loop structures.

[0112] Computational precision-sensitive tasks: When the program is running, record the execution frequency and precision requirements of floating-point operation instructions (such as double, long double).

[0113] Linear dependency task: When the program is running, record the execution order and dependencies of instructions.

[0114] Non-linear dependency tasks: When the program is running, irregular instruction dependencies are recorded, which are usually manifested as parallel algorithms and graph traversal algorithms.

[0115] Reduction-intensive tasks: You can see a large number of reduction operations (such as sum, reduce, aggregate). In the assembly code, there will be a large number of reduction operation instructions and loop operations, which perform reduction by traversing the data.

[0116] In summary, a comprehensive algorithm can be designed to classify different types of applications by analyzing the program's memory access pattern, control flow structure, floating-point operation precision, data dependencies, and reduction operations.

[0117] 1.2) Extraction of candidate key instruction sequences: Train a Word2Vec model to capture the semantic relationship between instructions.

[0118] 1.2.1) Input: The hotspot program fragment extracted in the previous step.

[0119] 1.2.2) Output: The pattern of the key instruction sequence, represented by a vector of instruction names. The format is as follows<load,load,add,add,store> .

[0120] 1.2.3) The execution process is as follows Figure 5 As shown, the following steps are included:

[0121] a) Data filtering: remove comments and extra blank lines to ensure that each instruction has a consistent format.

[0122] b) Text preprocessing: Split each instruction into instruction name and operand (for example, split mov r1,#5 into ['mov','r1','#5']), unify the representation of instructions, for example, convert all register names to the same format.

[0123] c) Build word vectors: Select the Skip-gram model in Word2Vec. Some preset training parameters are as follows:

[0124] Define the context window: The default value is 5, which means that the model will consider the 5 instructions before and after each instruction as context.

[0125] vector_size: The dimension of the word vector, select 100.

[0126] d) Cluster analysis: Extract the vector representation of each instruction from the Word2Vec model trained in the previous step, cluster the instruction vectors using the K-means algorithm, and determine the cluster to which each instruction belongs.

[0127] e) Sequential pattern mining: Select PrefixSpan, an effective sequential pattern mining algorithm suitable for longer sequences and larger data sets. The steps of sequential pattern mining include:

[0128] e1) Determine the minimum support threshold, that is, the minimum number of occurrences required for a pattern to be considered a frequent pattern. The support threshold determines the quantity and quality of the mining results. It is preset to the frequency of execution of the hot fragment to which the pattern belongs in the workload obtained in the "Hot Fragment Generation" section above.

[0129] e2) Mining Mode:

[0130] Starting from a pattern of length 1, the pattern is gradually expanded. The support of each pattern is calculated, and if the support is greater than or equal to the defined threshold, the pattern is retained.

[0131] Example: Consider the following assembly instruction sequence:

[0132] Assembly language

[0133] mov r1,#5

[0134] add r1,r2

[0135] sub r3,r1

[0136] mov r1,r3

[0137] add r1,#10

[0138] mov r2,r1

[0139] add r2,#1

[0140] a) Use these instruction sequences to train a Word2Vec model with a window size of 5 and a vector dimension of 100.

[0141] b) After training, each instruction will have a 100-dimensional vector representation.

[0142] c) Use the PrefixSpan algorithm and set the minimum support to 2.

[0143] d) Mining out frequent instruction patterns, such as ['mov r1,#5','add r1,r2'] and ['mov r1,r3','addr1,#10'].

[0144] Through the above detailed steps, it is explained how to use word vector model and sequence pattern mining technology to extract candidate key instruction sequences.

[0145] 2. Formulate integration strategies: Formulate scientific and effective integration strategies.

[0146] The hot segment classification and candidate fusion-capable key instruction sequence obtained in the previous step are preprocessed and used as the input of this step. If there is a user-defined fusion strategy, it can be directly used as the output, or the tracking log can be used as the input of the machine learning model including but not limited to natural language processing to automatically discover possible fusion strategies as the output of this step.

[0147] like Figure 6 As shown in the figure, at this stage, the system first preprocesses the trace log (trace.log) to extract key information and features. Then, using the machine learning model, the system can automatically discover possible fusion strategies. These strategies include which instructions can be fused, the timing of fusion, and the effect after fusion. The system also supports user-defined fusion strategies to meet the needs of specific application scenarios. In addition, mathematical equations based on priority or weight are used to formalize the decision-making process of the fusion strategy, while considering the priority of the instruction sequence, the constraints of the fusion, and the optimization goal of the fusion effect.

[0148] Input: the classification of hotspot segments of the application load program obtained in the previous step + candidate fusible key instruction sequences.

[0149] Output: The optimal fusion strategy combination.

[0150] Optimization goal: the minimum number of instructions after fusion.

[0151] Method: The complete solution space of this problem is the full permutation of each key instruction sequence in the previous step, and the complexity is factorial. In order to avoid searching for the optimal fusion strategy in such a huge solution space, the present invention chooses to use a heuristic method to find the solution to the problem.

[0152] Formulate experience: According to the "Application Type-Fusion Instruction Mapping Relationship" shown in Table 2, assign a priority value between 0 and 1 to each candidate key instruction fragment, which represents the degree of fusion benefit that this candidate key instruction fragment may bring to the system. The higher the priority of the instruction fragment, the more priority it will be added to the strategy for performance evaluation.

[0153] Table 2

[0154] Task Type Fusion Instructions Continuous memory-intensive tasks LW, SW, ADDI, BEQ, BNE Hash-based memory-intensive tasks LW,SW,MUL,DIV Computationally intensive tasks ADD,SUB,MUL,DIV,AND,OR,XOR,NOT Control flow sensitive tasks JAL,JALR,BEQ,BNE,BLT,BGE Precision-sensitive tasks FADD.S,FSUB.S,FMUL.S,FDIV.S Linearly dependent tasks ADD,SUB,MUL,DIV Non-linear dependent tasks FENCE Reduction-intensive tasks LW,SW,ADD,SUB,BEQ,BNE

[0155] Fusion constraints: used to describe the additional contextual relationships that need to be satisfied when actually performing instruction fusion (additional means that they are in addition to the characteristics of the key instruction sequence itself). It is allowed to use system preset or user-defined fusion constraints. This system uses a triple to describe each fusion constraint relationship: <fusion instruction 1 category, fusion instruction 2 category, instruction category that cannot appear between instruction 1 and instruction 2>, for example:<Load,Load,Store> This constraint is made to avoid the complexity caused by inconsistent memory access.

[0156] Fusion strategy: Select the optimal fusion strategy, that is, find those key instruction sequences that can have the minimum number of instructions after fusion from the input candidate fusionable key instruction sequences.

[0157] 1) Priority setting: Analyze each hotspot segment of each load program in turn, and perform weighted summation of the embeddings of all instructions in the instruction sequence.

[0158] 1.1) Convert the candidate instruction sequence into a vector: weighted sum of the embedding values ​​of all instructions in this instruction sequence.

[0159]

[0160] Where S is the instruction sequence and embed(i) is the embedding vector of instruction i.

[0161] 1.2) Calculate the category vector: Take the weighted sum of all typical instructions in this category to construct a vector representing the entire category.

[0162]

[0163] Among them, C is a typical instruction set of a certain category.

[0164] 1.3) Calculate cosine similarity: measure the cosine similarity between the sequence vector and each category vector. The value of cosine similarity ranges from -1 (completely different) to 1 (exactly the same), and then maps it to a value [0,1] aligned with the priority. The calculation formula of the priority is:

[0165]

[0166] 1.4) Obtaining the priority: that is, calculating the cosine similarity between each candidate fusible instruction sequence and the program fragment category, and using the above formula to calculate the priority, and sorting all fusible instruction sequences by priority.

[0167] 2) Fusion detection:

[0168] a) Define two sets: strategy set A = {}, initially empty; candidate set B = {candidate fusible instruction sequences}.

[0169] b) Use an instruction-level simulator to measure the number of instructions in the workload, denoted as K.

[0170] c) According to the descending priority order of the candidate fused instruction sequences in set B, they are added to set A one by one. Each time set A is updated, the number of fused instructions is measured once, which are recorded as K1, K2...K n .

[0171] d) Repeat the previous step and continue to optimize until the convergence threshold is reached: ((K i -K i-1 ) / K i-1 )*100%<0.1%.

[0172] Optimize the strategic decision-making process:

[0173] K i =minimize(K|S∈B,A=A∪{S},priority(S,C)is maximized)

[0174] Among them, K i represents the number of instructions after fusion, S represents the candidate fusion instruction sequence, B is the candidate set, A is the strategy set, and K is the initial number of instructions. This process is repeated until the convergence condition ((K i -K i-1 ) / K i-1 )*100%<0.1%.

[0175] Example: Assume that the workload of a sequential memory-intensive task is as shown in Table 3.

[0176] Table 3

[0177]

[0178] There are five fusion schemes shown in Table 4. The five fusion schemes are added to the strategy set in turn, and the fusion effect is iteratively examined.

[0179] Table 4

[0180]

[0181]

[0182] 3. Select the fusion parameters of the microarchitecture.

[0183] This process needs to comprehensively consider factors such as the fusion search width and fusion stage determined by the user. A micro-architecture simulation simulator is built on the cycle-level simulator, and a micro-architecture simulation model (or micro-architecture simulation scheme instance) is built using the micro-architecture simulation simulator and the method of the present invention to check the dependencies between instructions and apply fusion strategies, such as Figure 7 Through this step, the system can more accurately evaluate the effectiveness and feasibility of the fusion strategy.

[0184] Input: The optimal fusion strategy obtained in the second step.

[0185] Output: Fusion parameters of the optimal microarchitecture.

[0186] Optimization goal: Minimum execution delay of code sequence.

[0187] Optional microarchitecture fusion parameters: a) fusion stage; b) issue width; c) whether to support fusion across data cache (DataCache); d) fusion window size.

[0188] Specific implementation method: The instruction fusion module is a part of the processor's value fetching module. In the value fetching stage of the cycle-level simulator, the value fetching component will fetch the instructions according to the maximum value fetching width and the instruction sequence, and place the fetched instructions in the value fetching queue (fetchQueue) after processing, thereby realizing the transfer of instructions from the value fetching module to the decoding module. A new component is added in the value fetching process: each time an instruction is fetched, check whether there are other instructions in the current instruction queue that can be fused with it. If so, delete the original instruction and put the fused instruction into the instruction queue fetchQueue. Try to fuse two instructions. If the fusion is successful, set its context data for the fused instruction.

[0189] The following features are supported:

[0190] 1) Customize the fusion window width: The fusion window width refers to the maximum number of instructions between two fused instructions in the value queue during a fusion. This width can be set in the fusion module.

[0191] 2) Customization of fusion conditions: On the one hand, fusion restrictions are required to ensure the correctness of the cross-instruction fusion program. On the other hand, specific programs may have specific fusion restrictions. The present invention provides a minimum subset of fusion restrictions:

[0192] a) Register dependency check: Among the two instructions to be fused, the subsequent instruction cannot depend on the destination register (i.e., output register) of the previous instruction. During the fusion process, check other instructions in the current queue to ensure that these instructions do not have dependencies on the instructions to be fused. For example, if the intermediate instruction uses the destination register of the instruction to be fused as the source register, it cannot be fused. In the specific implementation, the register usage of each intermediate instruction is checked by traversing the queue to determine whether there is a dependency.

[0193] b) Specific instruction type: The types of two instructions need to meet specific conditions, for example, one instruction is an addition and subtraction instruction, and the other is a mask operation instruction. These instructions need to meet a certain order, which can be addition and subtraction first, mask operation later, or vice versa.

[0194] c) No branch or storage instructions: There should be no branch instructions (such as jump instructions) or storage instructions between the instructions to be fused. This is to ensure the continuity of the instruction flow and the execution order after the fusion of instructions is not disrupted. The code determines whether the fusion can be performed by checking whether the instruction belongs to the branch instruction set or the storage instruction set.

[0195] d) Instruction order and register matching: Some conditions require that instructions be fused if they are adjacent in timing and the destination and source registers match. For example, if the destination register of the first instruction is the same as the source register of the second instruction, fusion can be performed.

[0196] e) In some cases, more register matching conditions need to be checked, such as the destination register of the first operation instruction is the same as the register of the first source operand of the second operation instruction.

[0197] 3) Set the fusion switch for each fusion pair separately to facilitate correctness debugging and performance analysis.

[0198] 4. Evaluate the performance and overhead of fusion strategies.

[0199] In this phase, the system uses a simulator to perform performance simulation tests on benchmark programs or custom code snippets. By comparing the execution efficiency before and after fusion, the system can evaluate the performance improvement and area overhead of the fusion strategy on the processor. This process not only helps to verify the effectiveness of the fusion strategy, but also provides an important reference for subsequent optimization.

[0200] Use the instruction fusion simulation simulator obtained in the previous module to re-enter the benchmark program or customized code snippet to perform performance simulation testing, calculate and compare evaluation parameters such as IPC and running time before and after fusion, and use them as a reference factor for whether feedback is needed to iterate the microarchitecture design.

[0201] In summary, the present invention designs an automated analysis system and method based on instruction fusion technology, which is implemented through the following steps: 1) First, generate input from standard test program slices or code snippets provided by users; 2) formulate possible fusion strategies through preprocessing and automated machine learning models; 3) build a microstructure simulation model on the simulator in combination with the search width and fusion stage determined by the user; 4) finally use the simulator to perform performance testing to evaluate the execution efficiency before and after fusion. This automated analysis system aims to solve the problem of insufficient adaptability to diversified scenarios and high-complexity instruction dependency analysis, and improve the efficiency of formulating and verifying instruction fusion strategies through automated means. Through the automated analysis system, the efficiency of formulating and verifying instruction fusion strategies can be improved, adapting to diversified business scenarios and processor architectures, and ultimately improving the performance and energy efficiency of the processor.

[0202] The key link of the present invention is:

[0203] 1) Fusion instruction determination: Input the standard test program slices or the code snippets provided by the user into the system to generate a trace log file. This file is the basis for the subsequent fusion strategy formulation. Use an instruction-level simulator to generate a trace log file.

[0204] 2) Fusion strategy formulation: Preprocess the tracking log files and combine them with user-defined fusion strategies, or use machine learning models to automatically generate fusion strategies. The key to this step is to use machine learning technology to automatically discover fusion strategies to improve the automation and generalization capabilities of rule formulation.

[0205] 3) Determine fusion parameters: Input the search width and fusion stage of the instruction fusion determined by the user, and build a micro-architecture simulation model on the cycle-level simulator. In the implementation method, the instruction fetch module will add a component to check and fuse instructions to ensure the accuracy and feasibility of instruction fusion.

[0206] 4) Rule correctness check: Check the correctness of the fused instructions to ensure that the instruction dependencies are not destroyed, including register dependency check, specific instruction type matching, no branch or storage instruction restrictions, instruction sequence and register matching check, etc.

[0207] 5) Performance effect analysis: Use the fusion simulator to re-enter the benchmark program or customized code snippet for performance testing. Analyze the fusion effect by comparing evaluation parameters such as IPC (instructions per clock cycle) and running time before and after fusion.

[0208] The main ideas and technical points of the present invention include: using artificial intelligence means (such as NLP word vector model) to discover the process of fusionable instructions; realizing the process of automatic assembly of fusion instructions in a cycle-level simulator; and realizing the automatic iteration process of test-performance optimization in a cycle-level simulator.

[0209] The method of discovering fusible instructions in the present invention can be considered to be implemented with the help of a large model in the future. The present invention is not limited to cycle-level simulators, and simulators such as nemu can be considered. The present invention uses the PrefixSpan algorithm of Word2Vec when mining key instruction sequences, and can also use the FP-growth algorithm.

[0210] The explanations of the technical terms mentioned above are shown in Table 5.

[0211] Table 5

[0212]

[0213]

[0214] Another embodiment of the present invention provides an adaptive analysis system for a key instruction sequence fusion strategy, which includes:

[0215] A fusion instruction determination module is used to deeply mine key instruction sequences with fusion potential based on the input program code to obtain candidate key instruction sequences;

[0216] The fusion strategy formulation module is used to formulate scientific and effective fusion strategies for candidate key instruction sequences and select the optimal fusion strategy;

[0217] A micro-architecture performance evaluation module, used to select the fusion parameters of the micro-architecture according to the optimal fusion strategy;

[0218] The fusion performance evaluation module is used to evaluate the performance and overhead of the fusion strategy.

[0219] The specific implementation process of each module refers to the above description of the method of the present invention.

[0220] Another embodiment of the present invention provides a computer device (computer, server, smart phone, etc.), which includes a memory and a processor, the memory stores a computer program, the computer program is configured to be executed by the processor, and the computer program includes instructions for executing each step in the method of the present invention.

[0221] Another embodiment of the present invention provides a computer-readable storage medium (such as ROM / RAM, magnetic disk, optical disk), wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a computer, the steps of the method of the present invention are implemented.

[0222] The specific embodiments of the present invention disclosed above are intended to help understand the content of the present invention and implement it accordingly. It can be understood by those skilled in the art that various replacements, changes and modifications are possible without departing from the spirit and scope of the present invention. The present invention should not be limited to the contents disclosed in the embodiments of this specification, and the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. An adaptive analysis method for a key instruction sequence fusion strategy, characterized in that: The following steps are involved: According to the input program code, the key instruction sequences with fusion potential are deeply mined to obtain candidate key instruction sequences; Formulate scientific and effective fusion strategies for candidate key instruction sequences and select the optimal fusion strategy; Selecting fusion parameters of the microarchitecture according to the optimal fusion strategy; Evaluate the performance and overhead of fusion strategies.

2. The method according to claim 1, characterized in that: The in-depth exploration of key instruction sequences with fusion potential includes: Input standard test program slices or customized code snippets; The instruction-level simulator generates a trace log file corresponding to the input; By processing the trace log files, the candidate key instruction sequences are extracted using the word vector model and sequence pattern mining technology; The method of extracting candidate key instruction sequences by using a word vector model and a sequence pattern mining technology includes: Obtain hot segments of the application load program and classify the hot segments; Filter data, remove comments and extra blank lines, and ensure that each instruction has a consistent format; Perform text preprocessing, split each instruction into instruction name and operand, and unify the representation of instructions; Use the Word2Vec model to build word vectors; Extract the vector representation of each instruction from the Word2Vec model, cluster the instruction vectors using the K-means algorithm, and determine the cluster to which each instruction belongs; According to the clustering results, the PrefixSpan algorithm is used to mine sequence patterns and obtain the pattern vectors of key instruction sequences.

3. The method according to claim 1, characterized in that The selection of the optimal fusion strategy is to find a key instruction sequence with the minimum number of instructions after fusion from the input candidate key instruction sequence, including using a user-defined fusion strategy or using a machine learning model to automatically generate a fusion strategy.

4. The method according to claim 3, characterized in that The selecting of the optimal fusion strategy comprises: First, the priority is set, including: calculating the sequence vector and category vector of the candidate key instruction sequence, measuring the cosine similarity between the sequence vector and each category vector, the value of the cosine similarity ranges from -1 to 1, and then mapping it to a value [0,1] aligned with the priority, and sorting all the candidate key instruction sequences by priority; Then perform fusion detection, including: a) Define two sets: strategy set A = {}, initially empty; candidate set B = {candidate fusion instruction sequences}; b) Use an instruction-level simulator to measure the number of instructions in the workload, denoted as K; c) According to the descending priority order of the candidate fused instruction sequences in set B, they are added to set A one by one. Each time set A is updated, the number of instructions after fusion is measured and recorded as K1, K2...K n ; d) Repeat the previous step and continue to optimize until the convergence threshold is reached: ((K i -K i-1 ) / K i-1 )*100%<0.1%.

5. The method according to claim 1, characterized in that: The method of selecting fusion parameters of the microarchitecture according to the optimal fusion strategy includes: building a microarchitecture simulation simulator on a cycle-level simulator, selecting the most appropriate microarchitecture parameters during the dynamic optimization process, including the fusion stage, the emission width, whether to support fusion across data caches, and the fusion window size, using a microarchitecture simulation model to check the dependencies between instructions and apply the fusion strategy.

6. The method according to claim 5, characterized in that The fusion parameters of the microarchitecture are selected according to the optimal fusion strategy, and the following functions are supported: customization of the fusion window width, customization of the fusion conditions, and setting of a fusion switch for each fusion pair; the customization of the fusion conditions is used to perform correctness detection on the fused instructions to ensure that the instruction dependencies are not destroyed, including register dependency checks, specific instruction type matching, no branch or storage instruction restrictions, and instruction order and register matching checks.

7. The method according to claim 1, characterized in that The performance and overhead of the fusion strategy are evaluated, including: using an instruction fusion simulation simulator, re-entering a benchmark program or a customized code snippet, performing a performance simulation test, and calculating and comparing evaluation parameters before and after fusion as a reference factor for whether feedback is needed to iterate the microarchitecture design; by comparing the execution efficiency before and after fusion, the performance improvement and area overhead of the processor by the fusion strategy are evaluated, thereby verifying the effectiveness of the fusion strategy and providing an important reference basis for subsequent optimization.

8. An adaptive analysis system for key instruction sequence fusion strategy, characterized in that: include: A fusion instruction determination module is used to deeply mine key instruction sequences with fusion potential based on the input program code to obtain candidate key instruction sequences; The fusion strategy formulation module is used to formulate scientific and effective fusion strategies for candidate key instruction sequences and select the optimal fusion strategy; A micro-architecture performance evaluation module, used to select the fusion parameters of the micro-architecture according to the optimal fusion strategy; The fusion performance evaluation module is used to evaluate the performance and overhead of the fusion strategy.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, the computer program is configured to be executed by the processor, and the computer program comprises instructions for executing the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a computer, the method according to any one of claims 1 to 7 is implemented.

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