Power-on method, power-off method, logic device, server, and readable storage medium

Abstract

The application discloses a startup method, a shutdown method, a logic device, a server and a readable storage medium. The logic device is located in the server, and the logic device is in communication connection with a field programmable gate array of the server. After the server is powered on, the logic device is triggered to reload firmware. After the reloading of the firmware is completed, standby components of the server are powered on, and the state of the standby components is monitored. After the field programmable gate array is monitored to start, level information is transmitted to the field programmable gate array. After standby timing control is completed, in the case that a startup signal is received, power-on timing interaction is performed with the field programmable gate array, and a processor is subjected to startup processing. The application has the technical effect that only standby timing and power-on timing of the logic device and the field programmable logic gate array are needed to realize startup action, the decoupling of server startup and shutdown and the baseboard management controller is realized, and therefore the server startup and shutdown are accelerated.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to power-on methods, power-off methods, logic devices, servers, and readable storage media. Background Technology

[0002] Currently, to meet the diverse computing acceleration needs of global data centers, the MGX server architecture has been proposed. This specification provides a modular reference architecture for the rapid, economical, and efficient manufacture of various server models.

[0003] The NV C2 is the first CPU (processor) model on the ARM platform of the MGX (an acceleration platform) architecture, and this processor plays a crucial role in the development of the MGX architecture. When designing servers with the NV C2, the design of the HPM (Host Processor Module) board is of paramount importance to server manufacturers.

[0004] The standard power-on topology on the HPM board relies on the BMC (Baseboard Management Controller, a controller on the server motherboard used for server management, i.e., the baseboard management controller) for power-on and power-off timing control.

[0005] Because the server relies on the BMC for power on / off, a BMC failure will prevent the server from functioning properly. Furthermore, due to the BMC's need to initialize the system and peripherals, the server must wait for the BMC to complete initialization before powering on for the first time, resulting in a relatively long boot time.

[0006] In conclusion, how to effectively solve problems such as server power on / off is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] The purpose of this application is to provide a power-on method, a power-off method, a logic device, a server, and a readable storage medium to decouple the server power-on / off process from the BMC, thereby accelerating the server power-on / off process.

[0008] To solve the above-mentioned technical problems, this application provides the following technical solution:

[0009] A power-on method is applied to a logic device located in a server, the logic device having a communicative connection with the server's field-programmable gate array (FPGA), the method comprising:

[0010] After the server powers on, a firmware reload is triggered;

[0011] After the firmware reload is completed, the standby components of the server are powered on, and the status of the standby components is monitored.

[0012] After detecting that the field-programmable gate array (FPGA) has started, level information is transmitted to the FPGA so that the FPGA can complete the standby timing based on the level information.

[0013] After the standby timing control is completed, upon receiving a power-on signal, the system interacts with the field-programmable gate array (FPGA) to enable the FPGA control processor to power on and start.

[0014] Preferably, the logic unit has a communication connection with the baseboard management controller in the server; correspondingly, after monitoring the status of the standby component, it further includes:

[0015] The status of the standby component is sent to the baseboard management controller.

[0016] Preferably, receiving a power-on signal includes:

[0017] If the power-on command sent by the baseboard management controller after initialization is received is received, it is determined that the power-on signal has been received;

[0018] Alternatively, if the power button is detected to be pressed, the power-on signal is determined to have been received.

[0019] Preferably, it further includes:

[0020] Receive polling requests from the baseboard management controller;

[0021] The register information is fed back to the baseboard management controller; the register information includes at least one of status information and alarm information.

[0022] Preferably, the logic unit has a parallel communication connection with the field-programmable gate array of the server;

[0023] Accordingly, transmitting level information to the field-programmable gate array includes:

[0024] Through the parallel communication connection, a level matching the level information is output to the field-programmable gate array.

[0025] A shutdown method is applied to a logic device located in a server, the logic device having a communicative connection with the server's field-programmable gate array, the method comprising:

[0026] Receive power-off signal;

[0027] The power-off signal is transmitted to the field-programmable gate array (FPGA) so that the FPGA can power off the processor.

[0028] The processor receives the current power-off state from the field-programmable gate array (FPGA) via its input / output interface; wherein the current power-off state corresponds to the processor.

[0029] Based on the current power-off state, determine whether the processor has been powered off;

[0030] If not, output the next-level shutdown signal corresponding to the current shutdown state to the field programmable gate array;

[0031] If so, the shutdown operation is complete.

[0032] Preferably, based on the current power-off state, it is determined whether the processor has been powered off; if not, a lower-level power-off signal corresponding to the current power-off state is output to the field-programmable gate array; if yes, the power-off operation is completed, including:

[0033] The power-off signal is transmitted to the field-programmable gate array (FPGA) so that the FPGA can power off the processor.

[0034] The processor receives the current power-off state from the field-programmable gate array (FPGA) via its input / output interface; wherein the current power-off state corresponds to the processor.

[0035] Based on the current power-off state, transition to the power-off state of the machine;

[0036] After the state transition is completed, determine whether the state of the power-off state machine is in the power-off state;

[0037] If not, then through the input / output interface, output the shutdown signal of the next state of the shutdown state machine to the field programmable gate array;

[0038] If so, the shutdown operation is complete;

[0039] After confirming that the power-off operation is complete, the standby component is kept powered on.

[0040] After receiving the power-on signal, the power-on signal is sent to the field-programmable gate array so that the field-programmable gate array can power on the processor.

[0041] The current power-on status is received from the field-programmable gate array via the input / output interface; wherein the current power-on status corresponds to the processor.

[0042] Based on the current power-on state, jump to the power-on state machine state;

[0043] After the state transition is completed, determine whether the state of the power-on state machine is in the power-on state;

[0044] If not, then through the input / output interface, output the power-on signal of the next state of the power-off state machine to the field programmable gate array;

[0045] If so, then the power-on process is complete.

[0046] A logic device, located in a server, having a communicative connection with a field-programmable gate array (FPGA) of the server, the logic device comprising:

[0047] The firmware loading module is used to trigger firmware reloading after the server is powered on.

[0048] The standby power-on module is used to power on the standby components of the server after firmware reloading is completed, and to monitor the status of the standby components.

[0049] The standby timing control module is used to transmit level information to the field programmable gate array after detecting that the field programmable gate array has started, so that the field programmable gate array can complete the standby timing based on the level information;

[0050] The power-on timing control module is used to perform power-on timing interaction with the field-programmable gate array (FPGA) after the standby timing control is completed and a power-on signal is received, so that the FPGA controls the processor to power on and start; after the power-on timing interaction is completed, it is determined that the processor has been powered on.

[0051] A server, comprising:

[0052] Field-programmable gate array, board management controller, processor, and logic device as described in claim 7;

[0053] The thread-programmable gate array is connected to the logic device, the thread-programmable gate array is connected to the processor, and the baseboard management controller is connected to the logic device;

[0054] The steps of the power-on method described above are performed in the logic device, and / or the steps of the power-on method described above are performed in the logic device.

[0055] A readable storage medium storing a computer program that, when executed by a processor, performs the steps of the power-on method described above, and / or, when executed by a processor, performs the steps of the power-off method described above.

[0056] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the above-described power-on method and / or the steps of the above-described power-off method.

[0057] The method provided in the embodiments of this application is applied in a logic device located in a server. The logic device has a communication connection with the server's field-programmable gate array (FPGA). The method includes: triggering firmware reloading after the server is powered on; after the firmware reloading is completed, powering on the server's standby components and monitoring the status of the standby components; after detecting that the FPGA is powered on, transmitting level information to the FPGA so that the FPGA can complete the standby timing based on the level information; after the standby timing control is completed, upon receiving a power-on signal, performing power-on timing interaction with the FPGA so that the FPGA can control the processor to power on and start.

[0058] In this application, after the server powers on, the firmware reloading of the logic unit is initiated first. After the logic unit completes the firmware loading, the standby components of the server are powered on, and their status is detected. Upon detecting the startup of the field-programmable gate array (FPGA), a communication connection is provided to transmit level information to the FPGA, thereby enabling the FPGA to complete its standby timing and meet the power-on conditions. After confirming that the standby timing control has ended, upon receiving the power-on signal, a power-on timing interaction can be performed with the FPGA so that the FPGA can control the processor to power on and start. After completing the power-on timing interaction, it can be determined that the processor has been powered on.

[0059] The technical effect of this application is that during the power-on process of the server, the power-on action can be achieved by the logic unit and the field-programmable gate array performing standby timing and power-on timing without the participation of the baseboard management controller. This decouples the server power-on and power-off from the baseboard management controller, thereby accelerating the server power-on and power-off process.

[0060] Accordingly, embodiments of this application also provide a shutdown method, logic device, server, readable storage medium, and computer program product corresponding to the above-described power-on method, which have the above-described technical effects, and will not be repeated here. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1This is a flowchart illustrating the implementation of a power-on method in an embodiment of this application;

[0063] Figure 2 This is a schematic diagram of the structure of a logic device in an embodiment of this application;

[0064] Figure 3 This is a schematic diagram of the structure of a server according to an embodiment of this application;

[0065] Figure 4 This is a schematic diagram of the internal structure of a server;

[0066] Figure 5 This is a schematic diagram of the internal structure of a server in one embodiment of this application;

[0067] Figure 6 This is a schematic diagram illustrating a specific implementation of a power-on method in an embodiment of this application. Detailed Implementation

[0068] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0069] Please refer to Figure 1 , Figure 1 This is a flowchart of a power-on method according to an embodiment of this application, applied to a logic device (such as a CPLD, Complex Programmable Logic Device). The logic device is located in a server and has a communication connection with the server's Field Programmable Gate Array (FPGA). The method includes the following steps:

[0070] S101. After the server is powered on, firmware reloading is triggered.

[0071] Among them, the CPLD performs firmware reloading. The firmware to be loaded is stored in the CPLD, so the CPLD can complete the loading quickly.

[0072] After the server powers on, it initially supplies power only to the BMC and CPLD, causing the BMC to initialize and the CPLD to reload its firmware. Because the BMC initialization takes a relatively long time, the CPLD will quickly complete loading during the BMC initialization process and begin performing logical function control, i.e., executing the operation in step S102. This firmware corresponds to the server's power-on control logic.

[0073] S102. After completing the firmware reload, power on the server's standby components and monitor their status.

[0074] After completing the firmware reload, the CPLD can power on the server's standby components, including standby components such as FPGAs, network ports, and other devices or chips.

[0075] The CPLD continuously monitors and obtains the status of standby components through GPIO (General-purpose input / output).

[0076] In one specific embodiment of this application, the logic unit has a communication connection with the baseboard management controller in the server; correspondingly, after monitoring the status of the standby component, it further includes:

[0077] Send the status of standby components to the baseboard management controller.

[0078] That is, after the BMC is initialized, it can receive the status of the standby components sent by the CPLD, which makes it easier for the BMC to monitor the standby components.

[0079] S103. After detecting the startup of the field programmable gate array (FPGA), transmit level information to the FPGA so that the FPGA can complete the standby timing based on the level information.

[0080] After detecting FPGA startup, the corresponding level information for standby timing can be transmitted to the FPGA. Based on this level information, the FPGA can complete its own standby timing (STBY timing, or STBY electrical timing).

[0081] In one specific embodiment of this application, the logic unit and the server's field-programmable gate array have a parallel communication connection;

[0082] Accordingly, level information is transmitted to the field-programmable gate array, including:

[0083] Through parallel communication connection, a level matching the level information is output to the field programmable gate array.

[0084] That is, the CPLD and FPGA signals are directly connected, and after signal quality optimization, there is no risk of bit errors or erroneous frames.

[0085] In practical applications, considering that standby timing requires confirmation that the previous state has been completed before entering the next state, the CPLD can be configured with a standby state machine. That is, after the FPGA starts, the CPLD uses the standby state machine in its logic code to interact with the FPGA via GPIO level control. The FPGA completes its own STBY timing based on the received GPIO level changes, and once completed, the FPGA is ready to power on.

[0086] S104 After the standby timing control is completed, upon receiving the power-on signal, the system interacts with the field-programmable gate array (FPGA) to enable the FPGA to control the processor to power on and start.

[0087] After the standby timing control is completed, it indicates that the FPGA is ready to be powered on. At this point, it can wait to receive the power-on signal.

[0088] After receiving the power-on signal, it can perform power-on timing interaction with the FPGA to power on and start the processor.

[0089] For ease of control, a power-on state machine can be set up, and the power-on timing output can be based on this state machine. That is, after the CPLD receives the power-on action, it starts to interact with the FPGA through GPIO and begins the CORE power-on timing part. At this time, the FPGA will control the CPU to power on and start up, and feed back the startup status information to the CPLD. The CPLD will then perform state machine transitions based on the signals fed back by the FPGA, and output the signals required by the lower-level FPGA to control the CPU to power on.

[0090] Specifically, the CPU can be a processor with the model number NVIDIA MGX C2.

[0091] In one specific embodiment of this application, receiving a power-on signal includes:

[0092] If the power-on command sent after the initialization of the baseboard management controller is completed is received, it is confirmed that a power-on signal has been received;

[0093] Alternatively, if the physical power button is detected to be pressed, a power-on signal can be determined.

[0094] In other words, after the STBY timing control is completed, the CPLD can be notified to perform the power-on action in two ways: by pressing the physical power button or by waiting for the BMC to complete initialization and then sending a power-on I2C command.

[0095] In one specific embodiment of this application, it further includes:

[0096] Receive polling requests from the baseboard management controller;

[0097] Feedback of register information to the board management controller; the register information includes at least one of status information and alarm information.

[0098] For ease of description, the above steps will be combined below.

[0099] Because CPLD has abundant pin resources, it can directly monitor the signals of other chip devices on the board through GPIO and perform status judgment through logic code. After further integration, it can report to BMC through I2C (Inter-Integrated Circuit, a serial communication bus), so that BMC can obtain the operating status of devices on the board, power operating status, power on / off status, etc. with only a few command frames, which improves the out-of-band management efficiency of BMC.

[0100] In other words, during the power-on process, the CPLD monitors the voltage and network connection status on the HPM board through GPIO. After initialization, the BMC polls the internal registers of the CPLD through I2C to obtain status and alarm information, which is used to record web logs and out-of-band management.

[0101] After completing the power-on timing interaction, it is confirmed that the processor has been powered on.

[0102] The method provided in the embodiments of this application is applied in a logic device located in a server. The logic device has a communication connection with the server's field-programmable gate array (FPGA). The method includes: triggering firmware reloading after the server is powered on; after the firmware reloading is completed, powering on the server's standby components and monitoring the status of the standby components; after detecting that the FPGA is powered on, transmitting level information to the FPGA so that the FPGA can complete the standby timing based on the level information; after the standby timing control is completed, upon receiving a power-on signal, performing power-on timing interaction with the FPGA so that the FPGA can control the processor to power on and start.

[0103] In this application, after the server powers on, the firmware reloading of the logic unit is initiated first. After the logic unit completes the firmware loading, the standby components of the server are powered on, and their status is detected. Upon detecting the startup of the field-programmable gate array (FPGA), a communication connection is provided to transmit level information to the FPGA, thereby enabling the FPGA to complete its standby timing and meet the power-on conditions. After confirming that the standby timing control has ended, upon receiving the power-on signal, a power-on timing interaction can be performed with the FPGA so that the FPGA can control the processor to power on and start. After completing the power-on timing interaction, it can be determined that the processor has been powered on.

[0104] The technical effect of this application is that during the power-on process of the server, the power-on action can be achieved by the logic unit and the field-programmable gate array performing standby timing and power-on timing without the participation of the baseboard management controller. This decouples the server power-on and power-off from the baseboard management controller, thereby accelerating the server power-on and power-off process.

[0105] This application also provides a shutdown method applied to a logic device (such as a CPLD, Complex Programmable Logic Device), the logic device being located in a server, and the logic device having a communication connection with the server's Field Programmable Gate Array (FPGA). The method includes the following steps:

[0106] Receive power-off signal;

[0107] The power-off signal is transmitted to the field programmable gate array (FPGA) so that the FPGA can power off the processor.

[0108] By connecting to the input / output interface of the field-programmable gate array (FPGA), the current power-off state fed back by the FPGA is received; wherein, the current power-off state corresponds to the processor.

[0109] Determine whether the processor has been shut down based on the current shutdown status;

[0110] If not, output the next-level shutdown signal corresponding to the current shutdown state to the field programmable gate array;

[0111] If so, then confirm that the shutdown operation is complete.

[0112] For ease of description, the above steps will be combined below.

[0113] When the server is shut down, the CPLD performs operations similar to those during startup. A shutdown command is sent to the CPLD via physical buttons or I2C by the BMC, at which point the CPLD receives the shutdown signal.

[0114] The CPLD transmits the power-off signal to the FPGA via GPIO. The FPGA performs a power-off operation on the processor and informs the CPLD of the power-off status via GPIO. The CPLD determines whether the processor has been powered off based on the signal fed back by the FPGA. If it has, the process ends; otherwise, it outputs the next-level power-off signal corresponding to that signal, and finally works with the FPGA to complete the power-off operation on the server.

[0115] In one specific embodiment of this application, the shutdown process may further include the following steps:

[0116] Receive power-off signal;

[0117] The power-off signal is transmitted to the field programmable gate array (FPGA) so that the FPGA can power off the processor.

[0118] By connecting to the input / output interface of the field-programmable gate array (FPGA), the current power-off state fed back by the FPGA is received; wherein, the current power-off state corresponds to the processor.

[0119] Based on the current shutdown state, jump to the shutdown state of the machine;

[0120] After completing the state transition, determine whether the power-off state machine is in the power-off state;

[0121] If not, then output the shutdown signal of the next state of the shutdown state machine to the field programmable gate array through the input / output interface;

[0122] If so, confirm that the shutdown operation is complete;

[0123] After confirming that the shutdown operation is complete, maintain standby power supply to the standby components;

[0124] After receiving the power-on signal, the system sends a power-on signal to the field programmable gate array (FPGA) so that the FPGA can power on the processor.

[0125] The current power-on status is received from the field-programmable gate array via the input / output interface; the current power-on status corresponds to the processor.

[0126] Based on the current power-on status, jump to the power-on state machine state;

[0127] After completing the state transition, determine whether the power-on state machine is in the power-on state;

[0128] If not, then through the input / output interface, output the power-on signal of the next state of the power-off state machine to the field programmable gate array;

[0129] If so, then the power-on process is complete.

[0130] For ease of description, the above steps will be combined below.

[0131] When the server is shut down, the control logic is similar. A shutdown command is sent to the CPLD via physical buttons or I2C by the BMC. The CPLD transmits the shutdown signal to the FPGA via GPIO. The FPGA performs a shutdown operation on the CPU and informs the CPLD of the shutdown status via GPIO. The CPLD performs a shutdown state machine transition based on the signal fed back by the FPGA and outputs the next-level shutdown signal. Finally, it works with the FPGA to complete the shutdown operation of the server.

[0132] After power-off, the CPLD maintains the STBY power supply on the HPM. When power-on next time, the previous STBY timing can be skipped for control.

[0133] In other words, after confirming the completion of the shutdown operation, standby power continues to be supplied to the standby components. When a power-on signal is received again, firmware reloading and standby timing control for FPGA power-on preparation can be omitted; a power-on signal can be directly sent to the FPGA so that the FPGA can power on the processor. The CPLD receives the current power-on status from the FPGA through the input / output interface; the current power-on status corresponds to the processor.

[0134] Then, based on the current power-on state, the system transitions to the power-on state machine. After the state transition is complete, it first checks whether the power-on state machine is in the power-on state; if not, it outputs the power-on signal for the next state of the power-off state machine to the FPGA through the input / output interface; if so, it confirms that the power-on operation is complete.

[0135] Corresponding to the above method embodiments, this application also provides a logic device. The logic device described below can be referred to in correspondence with the power-on method and power-off method described above.

[0136] See Figure 2 As shown, the logic unit 100 is located in the server and has a communication connection with the server's field-programmable gate array 200. The logic unit includes the following modules:

[0137] Firmware loading module 101 is used to trigger firmware reloading after the server is powered on;

[0138] The standby power-on module 102 is used to power on the standby components of the server after the firmware reload is completed, and to monitor the status of the standby components.

[0139] The standby timing control module 103 is used to transmit level information to the field programmable gate array after detecting that the field programmable gate array has started, so that the field programmable gate array can complete the standby timing based on the level information;

[0140] The power-on timing control module 104 is used to perform power-on timing interaction with the field programmable gate array (FPGA) after the standby timing control is completed and a power-on signal is received, so that the FPGA can control the processor to power on and start.

[0141] The logic device provided in this application embodiment is located in a server and has a communication connection with the server's field-programmable gate array (FPGA). The method includes: triggering firmware reloading after the server is powered on; after the firmware reloading is completed, powering on the server's standby components and monitoring the status of the standby components; after detecting that the FPGA is started, transmitting level information to the FPGA so that the FPGA can complete the standby timing based on the level information; after the standby timing control is completed, upon receiving a power-on signal, performing power-on timing interaction with the FPGA so that the FPGA can control the processor to power on and start.

[0142] In this application, after the server powers on, the firmware reloading of the logic unit is initiated first. After the logic unit completes the firmware loading, the standby components of the server are powered on, and their status is detected. Upon detecting the startup of the field-programmable gate array (FPGA), a communication connection is provided to transmit level information to the FPGA, thereby enabling the FPGA to complete its standby timing and meet the power-on conditions. After confirming that the standby timing control has ended, upon receiving the power-on signal, a power-on timing interaction can be performed with the FPGA so that the FPGA can control the processor to power on and start. After completing the power-on timing interaction, it can be determined that the processor has been powered on.

[0143] The technical effect of this application is that during the power-on process of the server, the power-on action can be achieved by the logic unit and the field-programmable gate array performing standby timing and power-on timing without the participation of the baseboard management controller. This decouples the server power-on and power-off from the baseboard management controller, thereby accelerating the server power-on and power-off process.

[0144] In one specific embodiment of this application, the logic unit has a communication connection with the baseboard management controller in the server; correspondingly, it also includes a status feedback module for monitoring the status of the standby component and then sending the status of the standby component to the baseboard management controller.

[0145] In one specific embodiment of this application, the power-on timing control module is specifically used to determine that a power-on signal has been received when a power-on command is sent after the initialization of the baseboard management controller is completed.

[0146] Alternatively, if the physical power button is detected to be pressed, a power-on signal can be determined.

[0147] In one specific embodiment of this application, it further includes:

[0148] The information feedback module is used to receive polling requests from the baseboard management controller and to feed back register information to the baseboard management controller; the register information includes at least one of status information and alarm information.

[0149] In one specific embodiment of this application, the logic unit may include:

[0150] The power-off processing module is used to receive power-off signals;

[0151] The power-off signal is transmitted to the field programmable gate array (FPGA) so that the FPGA can power off the processor.

[0152] By connecting to the input / output interface of the field-programmable gate array (FPGA), the current power-off state fed back by the FPGA is received; wherein, the current power-off state corresponds to the processor.

[0153] Determine whether the processor has been shut down based on the current shutdown status;

[0154] If not, output the next-level shutdown signal corresponding to the current shutdown state to the field programmable gate array;

[0155] If so, then confirm that the shutdown operation is complete.

[0156] In one specific embodiment of this application, it further includes:

[0157] The power-off processing module is used to receive power-off signals;

[0158] The power-off signal is transmitted to the field programmable gate array (FPGA) so that the FPGA can power off the processor.

[0159] By connecting to the input / output interface of the field-programmable gate array (FPGA), the current power-off state fed back by the FPGA is received; wherein, the current power-off state corresponds to the processor.

[0160] Based on the current shutdown state, jump to the shutdown state of the machine;

[0161] After completing the state transition, determine whether the power-off state machine is in the power-off state;

[0162] If not, then output the shutdown signal of the next state of the shutdown state machine to the field programmable gate array through the input / output interface;

[0163] If so, confirm that the shutdown operation is complete;

[0164] After confirming that the shutdown operation is complete, maintain standby power supply to the standby components;

[0165] Correspondingly, it also includes:

[0166] The restart module is used to receive a power-on signal and then send a power-on signal to the field-programmable gate array (FPGA) so that the FPGA can power on the processor.

[0167] The current power-on status is received from the field-programmable gate array via the input / output interface; the current power-on status corresponds to the processor.

[0168] Based on the current power-on status, jump to the power-on state machine state;

[0169] After completing the state transition, determine whether the power-on state machine is in the power-on state;

[0170] If not, then through the input / output interface, output the power-on signal of the next state of the power-off state machine to the field programmable gate array;

[0171] If so, then the power-on process is complete.

[0172] In one specific embodiment of this application, the logic unit and the server's field-programmable gate array have a parallel communication connection;

[0173] Correspondingly, the standby power-on module is specifically used to output a level that matches the level information to the field programmable gate array via a parallel communication connection.

[0174] Corresponding to the above method embodiments, this application also provides a server. The server described below can be referred to in correspondence with the power-on method, power-off method, and logic device described above.

[0175] Please refer to Figure 3 The server includes:

[0176] Field-programmable gate array 200, baseboard management controller 300, processor 400 and logic device 100 as described above;

[0177] The thread-programmable gate array (LPG) is connected to the logic unit, the LPG is connected to the processor, and the baseboard management controller is connected to the logic unit.

[0178] Perform the steps of the power-on method as described in the above embodiments and / or the steps of the power-off method as described in the above embodiments in the logic unit. And / or indicates at least one of the two.

[0179] To facilitate those skilled in the art to better understand and implement the technical solutions provided in the embodiments of this application, the following description is provided in conjunction with specific application scenarios and in comparison with related technologies.

[0180] Please refer to Figure 4On the HPM board, the BMC (Baseboard Management Controller) needs to be initialized first. After initialization, the BMC controls the PCA9555 (Input / Output Extender) via the I2C bus to control the I / O (Input / Output Interface) level changes, thereby controlling the timing of the FPGA (Field Programmable Gate Array). Based on this timing control, the FPGA interacts with the VR (Power Controller) to control the server's power-on / off timing, and also interacts with the NVC2 module to obtain its power-on / off status. Finally, the FPGA feeds back the NVC2 power-on / off status to the PCA9555's I / O, and the BMC then obtains the status via I2C (a data bus).

[0181] The aforementioned power-on / off scheme relies on the BMC's activity state. During operation, the BMC, influenced by its own operating system, has a probability of freezing, causing it to malfunction. The reference design's power-on / off sequence involves the BMC controlling the PCA9555's voltage level via I2C; therefore, when the BMC is frozen, power-on / off operations are impossible. In conventional server designs, power-on / off behavior is permitted even when the BMC is frozen.

[0182] Because the BMC needs to initialize the system and peripherals, the server must wait for the BMC initialization to complete before it can be powered on for the first time. Since FPGAs start up much faster than BMCs, there is also a waiting period during the initial power-on phase.

[0183] The BMC controls the I / O pins on the PCA9555 via I2C. The I2C communication of the BMC requires polling to control / read the pin status, which has low interaction efficiency. In addition, I2C communication is a low-speed signal and there is a risk of bit error.

[0184] As can be seen from the above embodiments, power-on / off timing control and BMC decoupling can be achieved for the NV C2 platform server motherboard. Specifically, by adding a CPLD device to the reference design, the power-on / off timing and sequence are controlled by logic code. This improves the timeliness and stability of timing control, ultimately achieving decoupling of the NV C2 module's power-on / off timing control from the BMC.

[0185] In other words, this application abandons the timing control method of using BMC to control the PCA9555 port in the public version, and adds direct interaction between CPLD and FPGA, realizing no power-on / power-off signal association between BMC and FPGA. Utilizing the stability of CPLD, it is less prone to hangs, effectively avoiding the problem of not being able to power on / off when BMC hangs in the public version design. Moreover, the direct connection between CPLD and FPGA signals eliminates the risk of bit errors and erroneous frames after signal quality optimization. Simultaneously, CPLD performs parallel logic processing, eliminating the need for polling operations, and can quickly make logical judgments and feedback on input signals, improving the efficiency of timing signal interaction.

[0186] Please refer to Figure 5 The PCA9555 chip between the BMC and FPGA on the board is removed and replaced with a CPLD chip. Only non-timing-dependent signals are retained between the BMC and FPGA; all timing-dependent signals are replaced with a direct connection between the CPLD and FPGA. An I2C bus is added between the CPLD and BMC. After the BMC is initialized, timing status information can be read from the CPLD via the I2C bus, achieving the same functionality as obtaining timing status from the PCA9555 in the reference design. This application does not affect its server management functions. The interaction between the FPGA back-end and the NVC2 module and VR remains unchanged, maximizing the use of the reference design and reducing development difficulty.

[0187] In addition, the CPLD has abundant pin resources, which can directly monitor the signals of other chip devices on the board through GPIO and perform status judgment through logic code. After further integration, it can report to the BMC through I2C, so that the BMC can obtain the operating status of the devices on the board, the power supply status, the power on / off status, etc. with only a few command frames, which improves the out-of-band management efficiency of the BMC.

[0188] The following reference Figure 5 Decoupling power-on / off schemes and Figure 6 The power-on process is decoupled, and the technical solution provided in this application is further explained through the specific backplane operation mode.

[0189] First, after the server powers on, power is initially supplied only to the BMC and CPLD chips, allowing the BMC to initialize and the CPLD to reload its firmware. Because BMC initialization takes a relatively long time, the CPLD will quickly complete loading during this process and begin logic function control.

[0190] After the CPLD is loaded, it begins controlling the STBY power supply on the HPM board to power on the FPGA, network ports, and other devices or chips. The CPLD continuously monitors the status of the chip devices on the board via GPIO. Once the BMC initialization is complete, the BMC can immediately obtain management information. After the FPGA starts up, the CPLD uses a state machine in its logic code to interact with the FPGA via GPIO level control. The FPGA completes its own STBY timing based on the received GPIO level changes (once completed, the FPGA is ready to power on).

[0191] After STBY timing control is completed, the CPLD can be notified to perform the power-on action in two ways: by pressing the physical power button or by waiting for the BMC to complete initialization and then sending a power-on I2C command.

[0192] After receiving the power-on command, the CPLD begins interacting with the FPGA via GPIO, initiating the CORE electrical timing section. At this time, the FPGA controls the CPU to power on and starts up, feeding back the startup status information to the CPLD. Based on the signals from the FPGA, the CPLD performs state machine transitions and outputs the signals required by the lower-level FPGA to control the CPU's power-on. Finally, after the timing sequence is completed, the CPU completes the power-on process.

[0193] During startup and operation, the CPLD monitors the voltage and network connection status on the HPM board through GPIO. After initialization, the BMC polls the CPLD's internal registers via I2C to obtain status and alarm information for recording web logs and out-of-band management.

[0194] When the server is shut down, the control logic is similar. A shutdown command is sent to the CPLD via physical buttons or I2C by the BMC. The CPLD transmits the shutdown signal to the FPGA via GPIO. The FPGA performs a shutdown operation on the CPU and informs the CPLD of the shutdown status via GPIO. The CPLD performs state machine transitions based on the signals fed back by the FPGA and outputs the next-level shutdown signal. Finally, it works with the FPGA to complete the shutdown operation of the server.

[0195] After power-off, the CPLD maintains the STBY power supply on the HPM. When power-on next time, the previous STBY timing can be skipped for control.

[0196] Because the boot sequence is entirely controlled by the CPLD without the need for the BMC, this application achieves decoupling between booting and the BMC. The NV C2 boot sequence can be completed without waiting for the BMC initialization to finish. Of course, in practical applications of servers using this design, even in unattended data centers, the server can still be remotely powered on / off after the BMC initialization is complete.

[0197] Specifically, after the remotely controllable server is powered on, the logic unit can enter the power-on timing after the standby timing control ends, and then interact with the field programmable gate array for power-on timing after the timing ends.

[0198] After completing the power-on timing interaction, it is confirmed that the processor has been powered on.

[0199] In other words, in practical applications, power-on timing control for the processor can be executed automatically without waiting for external triggering. Alternatively, a power-on signal can be sent remotely to the logic unit.

[0200] In summary, this application effectively improves the issue of power-on / off and power-on / off depending on the BMC startup status in the NV C2 reference design by adding a CPLD as the timing control master, avoiding the inability to perform server power-on / off operations when the BMC is suspended. Simultaneously, using the CPLD's GPIO directly connected to the FPGA for control eliminates the need for GPIO expansion chips like the PCA9555, preventing I2C communication frame transmission errors and improving the stability of timing control. Ultimately, this decouples the BMC from the NV C2 platform's power-on / off and power-on / off processes, improving system stability and optimizing the BMC's polling management process, thus increasing management efficiency.

[0201] Corresponding to the above method embodiments, this application also provides a readable storage medium. The readable storage medium described below can be referred to in conjunction with the power-on method and power-off method described above.

[0202] A readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the power-on method of the above method embodiments, and / or when the computer program is executed by a processor, it implements the steps of the power-off method of the above method embodiments.

[0203] The readable storage medium can specifically be a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, or any other readable storage medium capable of storing program code.

[0204] Corresponding to the above method embodiments, this application also provides a computer program product. The computer program product described below can be referred to in correspondence with the power-on method and power-off method described above.

[0205] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the above-described power-on method and / or the steps of the above-described power-off method.

[0206] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the logic devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0207] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0208] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0209] Finally, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "include," "contain," or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0210] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power-on method, characterized in that, Applied to a logic device located in a server, the logic device having a communicative connection with the server's field-programmable gate array, the method includes: After the server powers on, a firmware reload is triggered; After the firmware reload is completed, the standby components of the server are powered on, and the status of the standby components is monitored. After detecting that the field-programmable gate array (FPGA) has started, level information is transmitted to the FPGA so that the FPGA can complete the standby timing based on the level information. After the standby timing control is completed, upon receiving a power-on signal, the system interacts with the field-programmable gate array (FPGA) to enable the FPGA control processor to power on and start.

2. The method according to claim 1, characterized in that, The logic unit has a communication connection with the baseboard management controller in the server; correspondingly, after monitoring the status of the standby component, it further includes: The status of the standby component is sent to the baseboard management controller.

3. The method according to claim 2, characterized in that, Upon receiving the power-on signal, including: If the power-on command sent by the baseboard management controller after initialization is received is received, it is determined that the power-on signal has been received; Alternatively, if the power button is detected to be pressed, the power-on signal is determined to have been received.

4. The method according to claim 2, characterized in that, Also includes: Receive polling requests from the baseboard management controller; The register information is fed back to the baseboard management controller; the register information includes at least one of status information and alarm information.

5. The method according to any one of claims 1 to 4, characterized in that, The logic unit has a parallel communication connection with the field-programmable gate array of the server; Accordingly, transmitting level information to the field-programmable gate array includes: Through the parallel communication connection, a level matching the level information is output to the field-programmable gate array.

6. A method for shutting down a device, characterized in that, Applied to a logic device located in a server, the logic device having a communicative connection with the server's field-programmable gate array, the method includes: Receive power-off signal; The power-off signal is transmitted to the field-programmable gate array (FPGA) so that the FPGA can power off the processor. The processor receives the current power-off state from the field-programmable gate array (FPGA) via its input / output interface; wherein the current power-off state corresponds to the processor. Based on the current power-off state, determine whether the processor has been powered off; If not, output the next-level shutdown signal corresponding to the current shutdown state to the field programmable gate array; If so, the shutdown operation is complete.

7. The method according to claim 6, characterized in that, Based on the current power-off state, determine whether the processor has been powered off; if not, output a lower-level power-off signal corresponding to the current power-off state to the field-programmable gate array. If so, complete the shutdown process, including: The power-off signal is transmitted to the field-programmable gate array (FPGA) so that the FPGA can power off the processor. The processor receives the current power-off state from the field-programmable gate array (FPGA) via its input / output interface; wherein the current power-off state corresponds to the processor. Based on the current power-off state, transition to the power-off state of the machine; After the state transition is completed, determine whether the state of the power-off state machine is in the power-off state; If not, then through the input / output interface, output the shutdown signal of the next state of the shutdown state machine to the field programmable gate array; If so, the shutdown operation is complete; After confirming that the power-off operation is complete, the standby component is kept powered on. After receiving the power-on signal, the power-on signal is sent to the field-programmable gate array so that the field-programmable gate array can power on the processor. The current power-on status is received from the field-programmable gate array via the input / output interface; wherein the current power-on status corresponds to the processor. Based on the current power-on state, jump to the power-on state machine state; After the state transition is completed, determine whether the state of the power-on state machine is in the power-on state; If not, then through the input / output interface, output the power-on signal of the next state of the power-off state machine to the field programmable gate array; If so, then the power-on process is complete.

8. A logic device, characterized in that, The logic device is located in the server and has a communication connection with the server's field-programmable gate array. The logic device includes: The firmware loading module is used to trigger firmware reloading after the server is powered on. The standby power-on module is used to power on the standby components of the server after firmware reloading is completed, and to monitor the status of the standby components. The standby timing control module is used to transmit level information to the field programmable gate array after detecting that the field programmable gate array has started, so that the field programmable gate array can complete the standby timing based on the level information; The power-on timing control module is used to perform power-on timing interaction with the field-programmable gate array (FPGA) after the standby timing control is completed and a power-on signal is received, so that the FPGA controls the processor to power on and start; after the power-on timing interaction is completed, it is determined that the processor has been powered on.

9. A server, characterized in that, include: Field-programmable gate array, board management controller, processor, and logic device as described in claim 7; The field-programmable gate array is connected to the logic device, the field-programmable gate array is connected to the processor, and the baseboard management controller is connected to the logic device; The power-on method as described in any one of claims 1 to 5 is performed in the logic unit, and / or the power-off method as described in claim 6 or 7 is performed in the logic unit.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the power-on method as described in any one of claims 1 to 5, and / or, when executed by a processor, implements the steps of the power-off method as described in claim 6 or 7.

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