Processor, processor failure detection method, device and electronic equipment

Abstract

The present application discloses a processor, a method for detecting processor faults, an apparatus, and an electronic device. It relates to the field of processors, and the processor includes: a main core for executing instruction processing operations; a redundant core for operating in parallel with the main core to execute the instruction processing operations executed by the main core, wherein the functional module in the redundant core is the same as the first functional module in the main core, the second functional module in the main core is shared by the main core and the redundant core, and the second functional module is the functional module in the main core other than the first functional module; and a fault detection unit for detecting whether the processor has a fault based on the external output signals of the main core and the redundant core in the process of executing the instruction processing operation. The present application solves the technical problem of the related art that the same main core and redundant core are set in the processor architecture that realizes the dual-core lockstep function, resulting in high power consumption of the processor.

Description

Technical Field

[0001] The present application relates to the field of processors, and more specifically, to a processor, a method and device for detecting processor failures, and an electronic device. Background Art

[0002] As chip applications continue to expand (e.g., Internet of Vehicles, in-vehicle Ethernet, radar, autonomous / assisted driving), the demand for chip reliability and fault tolerance is also growing. For example, in the field of autonomous vehicles, safety-critical applications such as anti-lock braking, vehicle stability, and drive-by-wire technology have very high safety requirements.

[0003] Dual-core Lockstep (DCLS), proposed in the 1980s, is one of the more widely used system-level hardening methods. Dual-core Lockstep refers to instantiating two processor cores in a processor chip, with both cores running the same application and producing the same results. If the results of the two cores are different, the system can take further measures, such as retrying the instruction or restarting the system, to improve chip reliability and fault tolerance. Currently, related technologies usually set up a main core and redundant core with the same structure in the processor architecture that implements the dual-core lockstep function, resulting in higher processor power consumption and area.

[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0005] Embodiments of the present application provide a processor, a method and apparatus for detecting processor failure, and an electronic device to at least address the technical problem in related arts of setting identical main cores and redundant cores in a processor architecture that implements a dual-core lockstep function, resulting in high processor power consumption.

[0006] According to one aspect of an embodiment of the present application, a processor is provided, which is implemented based on a RISC-V architecture and includes: a main core for executing instruction processing operations; a redundant core for operating in parallel with the main core to execute the instruction processing operations executed by the main core, wherein a functional module in the redundant core is the same as a first functional module in the main core, a second functional module in the main core is shared by the main core and the redundant core, and the second functional module is a functional module in the main core other than the first functional module; and a fault detection unit for detecting whether there is a fault in the processor based on external output signals of the main core and the redundant core during the execution of instruction processing operations.

[0007] Furthermore, the second functional module is at least one of the following: a storage module and a branch prediction module. The storage module includes at least one of the following: an instruction cache, a data cache, and a quick table for recording the mapping relationship between virtual addresses and physical addresses. The branch prediction module includes a branch predictor and a branch history table for recording the execution results of historical branch instructions.

[0008] Furthermore, the second functional module is used to receive an access signal sent by the main core to the second functional module, and feed back data to the main core and the redundant core based on the access signal, so as to realize sharing of the second functional module between the main core and the redundant core.

[0009] According to another aspect of an embodiment of the present application, a method for detecting a processor failure is also provided, which is applied to the above-mentioned processor, including: obtaining an external output signal of a main core during the execution of an instruction processing operation to obtain a first external output signal; obtaining an external output signal of a redundant core during the execution of an instruction processing operation to obtain a second external output signal; and detecting whether the processor has a failure based on the first external output signal and the second external output signal.

[0010] Furthermore, detecting whether the processor has a fault based on the first external output signal and the second external output signal includes: obtaining an access signal of the main core to the second functional module in the main core to obtain a first access signal, wherein the access signal of the main core is sent to the second functional module when the processor is working normally, and the second functional module feeds back data to the main core and the redundant core based on the access signal of the main core; obtaining an access signal of the redundant core to the second functional module to obtain a second access signal, wherein the access signal of the redundant core is not sent to the second functional module when the processor is working normally; detecting whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal.

[0011] Furthermore, in the case where the second functional module includes a storage module, and the storage module includes an instruction cache, a data cache, and a cache for recording the mapping relationship between virtual addresses and physical addresses, obtaining the access signal of the main core to the second functional module in the main core, and obtaining the first access signal includes: in the instruction acquisition stage of the processor pipeline, obtaining the access signal of the instruction acquisition module in the main core to the instruction cache, and obtaining the first access sub-signal; in the instruction execution stage of the processor pipeline, obtaining the access signal of the target instruction execution module in the main core to the data cache, and obtaining the second access sub-signal, and obtaining the access signal of the memory management module in the main core to the cache, and obtaining the third access sub-signal; obtaining the first access signal based on the first access sub-signal, the second access sub-signal, and the third access sub-signal.

[0012] Furthermore, in the case where the second functional module includes a branch prediction module, obtaining an access signal of the main core to the second functional module in the main core, and obtaining the first access signal includes: in the branch prediction stage of the processor pipeline, obtaining an access signal of the instruction acquisition module in the main core to the branch prediction module to obtain a fourth access sub-signal; and obtaining the first access signal based on the fourth access sub-signal.

[0013] Furthermore, obtaining the external output signal of the main core during the execution of the instruction processing operation to obtain the first external output signal includes: during the process of the main core executing the instruction processing operation, if the main core outputs the external output signal, then the external output signal output by the main core is delayed by the first clock cycle to obtain the first external output signal; obtaining the external output signal of the redundant core during the execution of the instruction processing operation to obtain the second external output signal includes: when there is an external input signal for the redundant core, the external input signal for the redundant core is delayed by the second clock cycle; during the process of the redundant core executing the instruction processing operation based on the external input signal after delay processing, if the redundant core outputs the external output signal, then the external output signal output by the redundant core is delayed by the third clock cycle to obtain the second external output signal, wherein the sum of the second clock cycle and the third clock cycle is the same as the first clock cycle.

[0014] Furthermore, obtaining an access signal of the main core for the second functional module in the main core, and obtaining a first access signal includes: when the main core outputs an access signal for the second functional module, delaying the access signal output by the main core by a first clock cycle to obtain the first access signal; obtaining an access signal of the redundant core for the second functional module, and obtaining a second access signal includes: when the redundant core outputs an access signal for the second functional module, delaying the access signal output by the redundant core by a third clock cycle to obtain the second access signal.

[0015] Furthermore, detecting whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal includes: determining that the processor has no fault when the first external output signal is the same as the second external output signal, and the first access signal is the same as the second access signal; and determining that the processor has a fault when the first external output signal is different from the second external output signal, or the first access signal is different from the second access signal.

[0016] According to another aspect of an embodiment of the present application, a processor fault detection device is also provided, which is applied to the above-mentioned processor and includes: a first acquisition unit, used to acquire the external output signal of the main core during the execution of the instruction processing operation, and obtain a first external output signal; a second acquisition unit, used to acquire the external output signal of the redundant core during the execution of the instruction processing operation, and obtain a second external output signal; and a detection unit, used to detect whether the processor has a fault based on the first external output signal and the second external output signal.

[0017] Furthermore, the detection unit includes: a first acquisition sub-unit, used to acquire an access signal of the main core to the second functional module in the main core, and obtain a first access signal, wherein the access signal of the main core is sent to the second functional module when the processor is operating normally, and the second functional module feeds back data to the main core and the redundant core based on the access signal of the main core; a second acquisition sub-unit, used to acquire an access signal of the redundant core to the second functional module, and obtain a second access signal, wherein the access signal of the redundant core is not sent to the second functional module when the processor is operating normally; a detection sub-unit, used to detect whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal.

[0018] Furthermore, in the case where the second functional module includes a storage module, and the storage module includes an instruction cache, a data cache, and a cache for recording the mapping relationship between virtual addresses and physical addresses, the first acquisition sub-unit includes: a first acquisition module, used to obtain an access signal of the instruction acquisition module in the main core to the instruction cache in the instruction acquisition stage of the processor pipeline, and obtain a first access sub-signal; a second acquisition module, used to obtain an access signal of the target instruction execution module in the main core to the data cache in the instruction execution stage of the processor pipeline, and obtain a second access sub-signal, and obtain an access signal of the memory management module in the main core to the cache, and obtain a third access sub-signal; and a first processing module, used to obtain a first access signal based on the first access sub-signal, the second access sub-signal, and the third access sub-signal.

[0019] Furthermore, in the case where the second functional module includes a branch prediction module, the first acquisition sub-unit includes: a third acquisition module, used to obtain the access signal of the instruction acquisition module in the main core for the branch prediction module in the branch prediction stage of the processor pipeline, and obtain a fourth access sub-signal; and a second processing module, used to obtain the first access signal based on the fourth access sub-signal.

[0020] Furthermore, the first acquisition unit includes: a first processing sub-unit, which is used to delay the external output signal output by the main core by the first clock cycle to obtain the first external output signal if the main core outputs an external output signal during the process of the main core executing the instruction processing operation; the second acquisition unit includes: a second processing sub-unit, which is used to delay the external input signal for the redundant core by the second clock cycle when there is an external input signal for the redundant core; and a third processing sub-unit, which is used to delay the external output signal output by the redundant core by the third clock cycle to obtain the second external output signal if the redundant core outputs an external output signal during the process of the redundant core executing the instruction processing operation based on the delayed external input signal, wherein the sum of the second clock cycle and the third clock cycle is the same as the first clock cycle.

[0021] Furthermore, the first acquisition sub-unit includes: a third processing module, which is used to delay the access signal output by the main core by the first clock cycle to obtain the first access signal when the main core outputs an access signal for the second functional module; the second acquisition sub-unit includes: a fourth processing module, which is used to delay the access signal output by the redundant core by the third clock cycle to obtain the second access signal when the redundant core outputs an access signal for the second functional module.

[0022] Furthermore, the detection subunit includes: a first determination module, used to determine that there is no fault in the processor when the first external output signal is the same as the second external output signal, and the first access signal is the same as the second access signal; a second determination module, used to determine that there is a fault in the processor when the first external output signal is different from the second external output signal, or the first access signal is different from the second access signal.

[0023] According to another aspect of an embodiment of the present invention, an electronic device is provided, including: a memory storing an executable program; and a processor for running the program, wherein any one of the above-mentioned methods for detecting a processor failure is executed when the program is running.

[0024] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program or instructions, which implements any one of the above-mentioned methods for detecting a processor failure when executed by a processor.

[0025] In an embodiment of the present application, a processor is implemented based on a RISC-V architecture and includes a main core for executing instruction processing operations; a redundant core for operating in parallel with the main core to execute the instruction processing operations executed by the main core, wherein a functional module in the redundant core is identical to a first functional module in the main core, a second functional module in the main core is shared by the main core and the redundant core, and the second functional module is a functional module in the main core other than the first functional module; and a fault detection unit for detecting whether a processor fault exists based on external output signals of the main core and the redundant core during the execution of the instruction processing operations. The main core executes the instruction processing operations, the redundant core operates in parallel with the main core to execute the instruction processing operations executed by the main core, and the fault detection unit detects whether a processor fault exists based on external output signals of the main core and the redundant core during the execution of the instruction processing operations, thereby implementing a dual-core lockstep function in the processor. By setting the functional module in the redundant core to be identical to the first functional module in the main core and the second functional module in the main core to be shared by the main core and the redundant core, the number of functional modules used in the redundant core is effectively reduced, thereby effectively reducing processor power consumption and reducing the area occupied by the redundant core. This achieves the goal of streamlining redundant cores in the processor and realizes the technical effect of reducing processor power consumption, thereby solving the technical problem of high processor power consumption caused by setting the same main core and redundant core in the processor architecture that realizes the dual-core lockstep function in the related technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0027] Figure 1 This is a schematic diagram of a processor provided according to embodiment 1 of the present application. Figure 1 ;

[0028] Figure 2 This is an architecture diagram of a main core provided according to the first embodiment of the present application;

[0029] Figure 3 This is a schematic diagram of a processor provided according to embodiment 1 of the present application. Figure 2 ;

[0030] Figure 4 is a schematic diagram of a computer terminal provided according to the second embodiment of the present application;

[0031] Figure 5 is a flowchart of a method for detecting a processor failure according to the second embodiment of the present application;

[0032] Figure 6is a schematic diagram of a target instruction fetch unit provided according to the second embodiment of the present application;

[0033] Figure 7 is a schematic diagram of a target load / store unit provided according to the second embodiment of the present application;

[0034] Figure 8 is a schematic diagram of a main processing unit provided according to the second embodiment of the present application;

[0035] Figure 9 This is a schematic diagram of determining a fault detection result according to the second embodiment of the present application;

[0036] Figure 10 is a schematic diagram of a processor failure detection device provided according to Embodiment 3 of the present application;

[0037] Figure 11 This is a structural block diagram of an electronic device provided according to Example 4 of the present application. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0041] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following interpretations:

[0042] RISC-V architecture: an open source instruction set architecture based on the reduced instruction set principle.

[0043] DCLS stands for Dual-core Lockstep. This refers to instantiating two processor cores within a single chip, running the same instructions and processing the same data simultaneously. The two cores operate in complete synchronization (i.e., in lockstep) and periodically compare their outputs.

[0044] CPU: Central Processing Unit, central processing unit.

[0045] CPU core: The basic processing unit in a CPU.

[0046] IFU: Instruction Fetch Unit. It takes instructions from the instruction cache and places them into the processor pipeline to begin completing the instruction function.

[0047] LSU: Load / Store Unit. A functional unit responsible for executing Load / Store instructions, i.e., retrieving data from or storing data in the data cache.

[0048] MMU: Memory Management Unit. Responsible for converting and mapping virtual addresses to physical addresses, and maintaining and managing the mapping table, also called the page table.

[0049] Example 1

[0050] As chip applications, such as in autonomous vehicles, continue to expand, the demand for chip reliability and fault tolerance is also growing. For example, in the autonomous vehicle sector, safety-critical applications such as anti-lock braking, vehicle stability, and drive-by-wire technology have very high safety requirements.

[0051] Dual-core Lockstep (DCLS), proposed in the 1980s, is one of the more widely used system-level hardening methods. Dual-core Lockstep refers to instantiating two processor cores in a processor chip, with both cores running the same application and producing the same results. If the results of the two cores are different, the system can take further measures, such as retrying the instruction or restarting the system, to improve chip reliability and fault tolerance. Currently, related technologies usually set up a main core and redundant core with the same structure in the processor architecture that implements the dual-core lockstep function, resulting in higher processor power consumption and area.

[0052] In the above technical background, the present application provides Figure 1 Processor shown. Figure 1 This is a schematic diagram of a processor provided according to embodiment 1 of the present application. Figure 1 ,like Figure 1 As shown, the processor is based on the RISC-V architecture and includes:

[0053] The main core is used to perform instruction processing operations;

[0054] a redundant core, configured to operate in parallel with the main core to execute instruction processing operations executed by the main core, wherein a functional module in the redundant core is the same as a first functional module in the main core, a second functional module in the main core is shared by the main core and the redundant core, and the second functional module is a functional module in the main core other than the first functional module;

[0055] The fault detection unit is used to detect whether the processor has a fault based on the external output signals of the main core and the redundant core during the execution of instruction processing operations.

[0056] Optionally, the above-mentioned processor is a processor implemented based on the RISC-V architecture and supporting a dual-core lockstep function, and the above-mentioned main core and redundant core are two processor cores implemented based on the dual-core lockstep architecture. The main core is used to perform instruction processing operations, and the redundant core is used to operate in parallel with the main core to perform the instruction processing operations performed by the main core. The main core and the redundant core are initialized (reset) in the same state and receive the same input. Therefore, when the processor is operating normally, the two cores always produce the same output. By comparing the outputs of the two cores, a logical fault in the output of one of the cores can be detected, that is, a fault in the processor is detected. After detecting a fault, the system where the processor is located can select various methods to handle it according to application requirements, such as retrying instructions, restarting the system, or other operations.

[0057] In an optional embodiment, in a processor supporting dual-core lockstep, the primary and redundant cores belong to a DCLS processing unit. When the processor is operating normally, the output of the DCLS processing unit is driven by the primary core, meaning that the primary core's output serves as the output of the DCLS processing unit. The redundant core is used to confirm the correctness of the primary core's output but does not enhance system performance because it receives the same instructions and data as the primary core. Logically, from a software and system architecture perspective, the DCLS processing unit can be considered equivalent to a single processor core because it provides a single processing function.

[0058] In an optional embodiment, the primary core and redundant cores execute instruction processing operations in a pipelined manner. Instruction processing operations include, but are not limited to, instruction processing operations from instruction fetch to data writeback after instruction execution. For example, the processor may have a nine-stage pipeline, with the names and functions of each stage as follows:

[0059] (1) IF (instruction fetch): fetch instructions from the instruction cache (I Cache) according to the program counter (PC);

[0060] (2) IP (instruction predecode): simple decoding of the fetched instructions;

[0061] (3) IB (instruction buffer): encapsulates and temporarily stores instructions preprocessed in the IP stage, and performs branch prediction;

[0062] (4) ID (instruction decode): disassembles the instruction and determines the instruction function and operand information;

[0063] (5) RF (register file): Gets instruction operands from the general register file and sends them to the lower level;

[0064] (6) EX1 (execute1): The first stage of instruction execution. Load and store instructions perform address calculations here and complete the conversion from virtual addresses to physical addresses. Branch instructions complete the jump condition judgment and target address calculation;

[0065] (7) EX2 (execute2): The second stage of instruction execution. Load and store instructions access the data cache (D Cache) here, and branch instructions perform prediction checks;

[0066] (8) EX3 (execute3): The third stage of instruction execution. Load and store instructions are aligned here, and instructions such as multiplication instructions may also be processed.

[0067] (9) WB (writeback): The data write-back phase after the instruction is executed.

[0068] Optionally, Figure 2 This is an architecture diagram of a main core provided according to the first embodiment of the present application. The main core can be Figure 2 The architecture shown implements the pipeline described above to complete instruction processing operations. Figure 2 As shown, the main core includes an instruction fetch unit (IFU), a main processing unit (CORE), a load / store unit (LSU), and a memory management unit (MMU). The instruction fetch unit covers three pipeline stages: IF-IP-IB, and is used to complete instruction fetching and branch prediction, generating new instruction PCs. The main processing unit covers the ID-RF-EX1-EX2-EX3-WB pipeline stages, and is used to complete the instruction decoding, execution, write-back, and finally retirement. The load / store unit covers the EX1-EX2-EX3-WB pipeline stages, and is used to complete the execution and write-back of load and store instructions. The memory management unit covers the EX1-EX2-EX3 pipeline stages, and is used to complete the conversion from virtual addresses to physical addresses and obtain address attributes.

[0069] Optionally, based on Figure 2 The main core architecture shown in FIG illustrates the process of the main core executing instruction processing operations based on the above pipeline. Figure 2As shown, the instruction fetch unit includes an instruction cache (I CACHE), an instruction fetch module, a branch predictor, and a branch history table. In the IF stage, the instruction fetch module retrieves instructions from the instruction cache based on the instruction address in the program counter. Then, in the IP stage, the obtained instruction is pre-decoded to obtain a pre-decoded result. The pre-decoded result includes at least information characterizing the instruction type, which includes but is not limited to branch instructions, jump instructions, load instructions, store instructions, arithmetic instructions, etc. The pre-decoded result can be the instruction's opcode. In the IB stage, the instruction fetch module determines the instruction type based on the pre-decoded result. If the instruction is a branch instruction, the instruction and its pre-decoded result are sent to the branch predictor. The branch predictor then performs a branch prediction based on the instruction, its pre-decoded result, and the branch history table to obtain a branch prediction result. The branch prediction result includes the address of the next instruction predicted to follow the branch instruction. The branch prediction result is then fed back to the instruction fetch module, and the current branch instruction and its pre-decoded result are packaged and temporarily stored for transmission to the next level. Optionally, the instruction acquisition module can obtain the predicted instruction based on the branch prediction result fed back by the branch predictor, and when it is subsequently determined that the instruction prediction is successful, the address in the PC can be updated to the address of the predicted instruction, so that in the next cycle the PC can correctly obtain the next instruction corresponding to the predicted instruction. Optionally, the branch predictor can be a multi-level, hybrid branch predictor combination, such as TAGE (Tagged GEometric history length branch preditor, tagged geometric history length branch predictor), bimodal predictor, etc. The branch history table is used to record the execution results of historical branch instructions, and the execution results of historical branch instructions may include the instruction address of the next instruction corresponding to the historical branch instruction. Optionally, after the instruction acquisition module determines the instruction type of the instruction based on the pre-decoding result, if the instruction is not a branch instruction, the instruction acquisition module can encapsulate and temporarily store the instruction and its pre-decoding result for sending to the next level.

[0070] like Figure 2As shown, the main processing unit includes an instruction decoding module and various instruction execution modules: an arithmetic logic unit (ALU), a branch instruction calculation module (Branch), a multiplication module (Mult), etc. The load / store unit includes a data cache, a load module, a store module, etc. The memory management unit includes a memory management module and a cache table for recording the mapping relationship between virtual addresses and physical addresses, which can also be called a TLB (Translation Lookaside Buffer). The instruction fetch module can send the temporarily stored instructions to the instruction decoding module, which decodes the instructions in the ID stage to obtain a decoding result. Optionally, the decoding result includes at least the instruction's opcode and operand information. The operand information can be the operand itself, the operand type, or the operand address. Subsequently, the instruction decoding module can obtain the operand based on the operand information in the RF stage. Optionally, after obtaining the opcode and operand, the instruction decoding module can determine the instruction type based on the opcode and then send the instruction decoding result, operand, and other information to the corresponding instruction execution module based on the instruction type. For example, if it is an arithmetic instruction, the instruction decoding result, operand and other information are sent to Figure 2 If it is a branch instruction, the arithmetic logic module 0 or arithmetic logic module 1 in the instruction sends the instruction decoding result, operand and other information to Figure 2 If it is a load instruction, the branch instruction calculation module sends the instruction decoding result, operand and other information to Figure 2 If it is a store instruction, the load module in the load / store unit sends the instruction decoding result, operand and other information to Figure 2 The storage module in the load / store unit in.

[0071] Alternatively, as Figure 2As shown, after receiving the decoding result, operand and other information of the instruction, the branch instruction calculation module can perform jump condition judgment and target address calculation in EX1, where the target address is the instruction address of the next instruction corresponding to the branch instruction. After calculating the target address, the target address can be fed back to the branch predictor in the EX2 stage, and then the branch predictor saves the branch instruction and the target address corresponding to the branch instruction into the branch history table for learning. Optionally, after calculating the target address, the prediction checker in the branch instruction calculation module will also compare the target address and the branch prediction result corresponding to the branch instruction, and determine whether to flush the pipeline based on the comparison result. For example, if the target address and the branch prediction result are consistent, there is no need to flush the pipeline. If the target address and the branch prediction result are inconsistent, the pipeline needs to be flushed. The flushing process includes but is not limited to deleting the instruction address represented by the branch prediction result, rolling back the instruction processing operations of the instruction matched by the branch prediction result, etc.

[0072] Alternatively, as Figure 2 As shown, after receiving the decoding result of the instruction, operand and other information, the load module (or storage module) can calculate the address for accessing the data cache according to the received information in the EX1 stage, and then send the calculated access address to Figure 2 The memory management module in the memory management unit in the memory management module, and then the memory management module searches in the above-mentioned cache according to the received access address, thereby converting the received access address from the virtual address to the physical address, obtaining the target access address, and feeding the target access address back to the loading module (or storage module). Optionally, if the target access address cannot be found in the cache, the target access address can be searched in the page table. Afterwards, the loading module (or storage module) can access the data cache according to the target access address in the EX2 stage, and perform data alignment and data loading (or storage) in the EX3 stage.

[0073] It should be noted that, depending on actual application requirements, different processors may have different numbers of pipeline stages and functional units / modules. Therefore, in this embodiment, the architecture of the processor pipeline and the main core is not specifically limited.

[0074] In an optional embodiment, the functional module in the redundant core is the same as the first functional module in the main core, and the second functional module in the main core is shared by the main core and the redundant core.

[0075] In an optional embodiment, the second functional module can be at least one of the following: a storage module, a branch prediction module, the storage module includes at least one of the following: an instruction cache, a data cache, a quick table for recording the mapping relationship between virtual addresses and physical addresses, and the branch prediction module includes a branch predictor and a branch history table for recording the execution results of historical branch instructions.

[0076] In an optional embodiment, the second functional module includes at least the above-mentioned storage module and may further include a branch prediction module.

[0077] In an optional embodiment, the functional modules in the primary core and the redundant core each send an access signal to the second functional module in the primary core, and the second functional module feeds back data to the primary core and the redundant core based on the received access signal, thereby enabling the second functional module to be shared between the primary core and the redundant core. The aforementioned functional module is either the first functional module or the second functional module.

[0078] In an optional embodiment, only the functional module in the main core sends an access signal to the second functional module in the main core, and the second functional module feeds back data to the main core and the redundant core respectively based on the received access signal, so as to realize sharing of the second functional module between the main core and the redundant core.

[0079] In an optional embodiment, the fault detection unit is part of the aforementioned DCLS processing unit. The fault detection unit can obtain external output signals from the primary core and the redundant core while each is executing instruction processing operations, and compare the external output signals from the primary core and the redundant core during the execution of instruction processing operations to detect whether the processor is faulty based on the comparison results. For example, if the external output signals output by the primary core and the redundant core are identical during the same clock cycle, it is determined that the processor is not faulty. If the external output signals output by the primary core and the redundant core are different during the same clock cycle, it is determined that the processor is faulty, i.e., the DCLS processing unit is faulty.

[0080] In an optional embodiment, the fault detection unit may be instantiated twice, that is, two fault detection units are used to respectively detect whether the processor has a fault, so as to prevent a single stuck-at-fault in the fault detection unit from causing the fault detection function to fail.

[0081] In an optional embodiment, the output objects of the external output signals of the main core (or redundant core) include but are not limited to various buses, external storage (such as memory), and operating peripherals, and the external output signals include but are not limited to exception and interrupt signals, memory access signals, access signals for operating peripherals, status signals representing the working status of the main core (or redundant core), etc.

[0082] In an optional embodiment, the fault detection unit can also obtain the access signals of the main core and the redundant core to the second functional module during the execution of instruction processing operations, thereby detecting whether the processor has a fault based on the access signals of the main core and the redundant core to the second functional module and the external output signals of the main core and the redundant core.

[0083] In an optional embodiment, the primary core and the redundant core in the DCLS processing unit share a clock domain.

[0084] In an optional embodiment, to prevent clock interference caused by radiation from affecting both the primary and redundant cores and to reduce the probability of common mode failures (CMFs) occurring in the primary and redundant cores, the DCLS processing unit may further include a delay register to allow for a time difference in instruction processing operations between the primary and redundant cores. Optionally, in addition to the clock source signal, the external input signal to the redundant core is directly input to the redundant core after passing through the redundant core input delay register. Before comparing the outputs of the primary and redundant cores, the external output signal of the primary core may be delayed using the primary core output delay register, and the external output signal of the redundant core may be delayed using the redundant core output delay register, so that the cycles of the external output signals of the two cores are synchronized, thereby ensuring the accuracy of detection by the fault detection unit.

[0085] Alternatively, the RISC-V architecture is currently primarily used in embedded-level control applications. As vehicles become software-defined, reliability requirements increase due to trends such as electrification, connectivity, and autonomous driving. The industry is demanding standardization and ecosystem compatibility, with CPUs being key. Processor chips based on the RISC-V instruction set architecture are currently being applied to areas such as the Internet of Vehicles, in-vehicle Ethernet, radar, autonomous / assisted driving, and ECUs (Electronic Control Units).

[0086] It should be noted that by setting the second functional module shared by the main core and the redundant core in the main core, the original processor code hierarchy in the single core is retained. As a result, during the production process of the processor, the processor containing the main core can be directly used as a processor that does not support the dual-core lock-step function. Alternatively, the logic unit corresponding to the redundant core and the related signal comparison logic can be added to the processor containing the main core to obtain a processor that supports the dual-core lock-step function, thereby avoiding major modifications to the code in the processor and improving its applicability.

[0087] In this solution, the main core executes instruction processing operations, and the redundant core operates in parallel with the main core to execute the instruction processing operations executed by the main core. The fault detection unit detects whether there is a fault in the processor based on the external output signals of the main core and the redundant core in the process of executing the instruction processing operations, thereby realizing a dual-core lock-step function in the processor. By setting the functional module in the redundant core to be the same as the first functional module in the main core, the second functional module in the main core is shared by the main core and the redundant core, which effectively reduces the number of functional modules used in the redundant core, thereby effectively reducing the power consumption of the processor and reducing the area occupied by the redundant core.

[0088] In order to reduce the power consumption of the processor, in the processor provided in Example 1 of the present application, the second functional module is at least one of the following: a storage module and a branch prediction module. The storage module includes at least one of the following: an instruction cache, a data cache, and a quick table for recording the mapping relationship between virtual addresses and physical addresses. The branch prediction module includes a branch predictor and a branch history table for recording the execution results of historical branch instructions.

[0089] For complex processors, speculative execution is a key technology for improving processor performance. A branch predictor is a form of speculative execution. When a processor executes a branch instruction, it cannot determine the address of the next instruction during the instruction fetch phase. The processor must wait until the instruction completes, obtains the address of the next instruction, and then resumes execution. Alternatively, the processor can predict the outcome of the instruction based on past behavior and fetch instructions directly from the predicted destination address. If the prediction is correct, the processor continues execution, saving time. If the prediction is incorrect, the instructions already fetched and executed on the wrong path must be flushed, and execution must resume from the correct address.

[0090] Therefore, speculative execution is achieved through a branch predictor and a prediction checker. The branch predictor is responsible for predicting addresses, while the prediction checker is responsible for correcting incorrect predictions. Furthermore, speculatively executed instructions do not necessarily affect or alter the architectural state of the instruction or resources external to the processor. Therefore, the impact of branch mispredictions is limited, detectable, and reversible.

[0091] In the conventional implementation, the main core and the redundant core each instantiate a branch predictor and a prediction checker. Although this implementation is correct, the two instantiated branch predictors are redundant. Even if the result of a branch predictor is interfered with by the environment and causes a logical error, it only causes the instruction address it predicts to be wrong. The instructions fetched and executed according to the wrong instruction address can be detected in the prediction checker and flushed, returning to the state before the wrong instruction was executed. Therefore, it will not affect the correctness of the dual-core lock-step execution and can still ensure the reliability of the processor core.

[0092] Therefore, in an optional embodiment, the second functional module can be a branch prediction module, which includes a branch predictor and a branch history table for recording the execution results of historical branch instructions. Optionally, both the primary core and the redundant core include a prediction checker to determine whether the branch prediction result is correct and initiate corrective measures if the branch prediction result is inaccurate. By sharing the branch predictor, significant area and power savings can be achieved without affecting the processor's ability to detect faults.

[0093] In an optional embodiment, the second functional module may be a storage module, which includes at least one of the following: an instruction cache, a data cache, and a cache for recording a mapping relationship between a virtual address and a physical address.

[0094] In an optional embodiment, when the second functional module is a storage module and a branch prediction module, and the storage module includes an instruction cache, a data cache, and a cache for recording a mapping relationship between a virtual address and a physical address, according to Figure 3 The working process of the main core and redundant core in the processor executing instruction processing operations is described. Figure 3 This is a schematic diagram of a processor provided according to embodiment 1 of the present application. Figure 2 ,like Figure 3 As shown, Figure 3 The processor shown in FIG maintains the original single-core components and architecture unchanged, and adds the logic required for DCLS in each unit. Figure 3 The dotted box is the original processor component design, which is used as the main core in the DCLS processing unit. Its pipeline process is the same as Figure 2 The pipeline process performed by the architecture shown in the figure is the same, so it will not be repeated here. The redundant core is also divided into four parts: IFU, CORE, LSU, and MMU. There is no need to reorganize and rearrange the storage modules. Instead, the storage modules are still located in the original main core. For example, Figure 3 The instruction cache, data cache, cache table, and branch history table in the redundant core are only present in the primary core and are not set up in the redundant core. The redundant core's pipeline is basically the same as the primary core, except for the branch prediction stage (also known as the instruction cache stage) and the second stage of instruction execution (EX2).

[0095] Optionally, the difference from the aforementioned branch prediction stage is that the branch predictor and branch history table are directly removed from the redundant core in this stage, and the pre-decoding results generated by the redundant core are not used for branch prediction, but are used to compare with the branch prediction results of the main core.

[0096] Optionally, in the second stage of the aforementioned instruction execution, the cache and data cache are deleted in the redundant core, so that the original access behavior becomes a comparison behavior with the main core.

[0097] It should be noted that by integrating the aforementioned first-level caches, including the instruction cache, data cache, cache table, and branch history table, into the processor, the bus is prevented from being occupied for every data access operation by the processor core, thereby providing fast data storage and loading and achieving shorter data access latency. By adding redundant logic (i.e., the logic units corresponding to the redundant cores) to the contents of each pipeline module according to the modular concept, while the comparison portion (i.e., the execution content of the fault detection unit) is also performed within the DCLS processing unit, there is no need to reorganize the processor design hierarchy due to redundant logic, and there is no need to move the original storage and branch speculation execution logic. This protects the original hardware design code hierarchy and provides flexible hardware control through modular redundancy.

[0098] In order to further reduce the power consumption of the processor, in the processor provided in Example 1 of the present application, the second functional module is used to receive an access signal sent by the main core to the second functional module, and to feedback data to the main core and the redundant core based on the access signal, so as to realize sharing of the second functional module between the main core and the redundant core.

[0099] That is, when the processor is working normally, the redundant core does not need to access the second functional module. The main core only needs to access the second functional module, so that both the main core and the redundant core can obtain the data fed back by the second functional module, thereby avoiding the interaction process between the redundant core and the second functional module, and further reducing the power consumption of the processor.

[0100] In an optional embodiment, where the second functional module is a storage module and the storage module includes an instruction cache, the access signal from the primary core to the instruction cache is an access signal from the instruction fetch module in the primary core to the instruction cache. This access signal is used by the instruction fetch module to fetch instructions from the instruction cache. The access signal from the instruction fetch module to the instruction cache includes at least an address signal of the instruction to be fetched by the instruction fetch module and may also include signals such as a chip select signal and a read signal. The data fed back by the instruction cache to the instruction fetch modules of the primary core and the redundant core based on the access signal includes at least instructions.

[0101] In an optional embodiment, when the second functional module is a storage module and the storage module includes a data cache, the access signal of the main core to the data cache is an access signal of the target instruction execution module in the main core to the data cache. The access signal is used for the target instruction execution module to read data from the data cache or write data to the data cache. The target instruction execution module can be a loading module or a storage module. The access signal of the target instruction execution module to the data cache includes at least an address signal and a read signal of the data to be read, or an address signal and a write signal of the data to be written, and may also include a chip select signal and other signals. When the data cache includes a write signal in the received access signal, it may not feedback data to the target instruction execution module of each of the main core and the redundant core, or it may feedback the execution result of the access signal (such as execution success or execution failure) to the target instruction execution module of each of the main core and the redundant core. When the data cache includes a read signal in the received access signal, it feedbacks the data to be read to the target instruction execution module of each of the main core and the redundant core.

[0102] In an optional embodiment, where the second functional module is a storage module and the storage module includes a cache for recording the mapping relationship between virtual addresses and physical addresses, the access signal from the primary core to the cache is an access signal from the memory management module in the primary core to the cache, and the access signal is used by the memory management module to obtain the physical address from the cache. The access signal from the memory management module to the cache includes at least a virtual address to be mapped to a physical address. The virtual address can be an address provided by a load module or a storage module. The access signal can also include signals such as a chip select signal and a read signal. The data fed back by the cache to the memory management modules of the primary core and the redundant core based on the access signal includes at least the physical address.

[0103] In an optional embodiment, where the second functional module is a branch prediction module, the access signal from the primary core to the branch prediction module is an access signal from the instruction fetch module in the primary core to the branch predictor. This access signal is used by the instruction fetch module to obtain a branch prediction result for a target branch instruction from the branch predictor. The target branch instruction refers to a branch instruction sent by the instruction fetch module to the branch predictor, and can also be understood as the branch instruction currently being predicted by the branch predictor. The access signal from the instruction fetch module to the branch predictor includes at least instruction information for the target branch instruction (e.g., a pre-decoding result for the target branch instruction). The access signal may also include signals such as a chip select signal and a read signal. Based on the access signal, the data fed back by the branch predictor to the instruction fetch modules of the primary core and the redundant core includes at least the branch prediction result for the target branch instruction.

[0104] Optionally, upon receiving an access signal from the instruction fetch module, the branch predictor in the branch prediction module may generate an access signal for a branch history table. The access signal is used by the branch predictor to obtain the execution result of the historical branch instruction that matches the target branch instruction from the branch history table, so as to perform branch prediction on the target branch instruction. The access signal from the branch predictor to the branch history table includes at least instruction information of the target branch instruction (e.g., the pre-decoding result of the target branch instruction), and may also include a chip select signal, a read signal, and other signals. Based on the access signal, the branch history table may feed back the execution result of the historical branch instruction that matches the target branch instruction to the branch predictor of the main core.

[0105] In an optional embodiment, when the second functional module is a storage module and a branch prediction module, and the storage module includes an instruction cache, a data cache, and a cache for recording a mapping relationship between a virtual address and a physical address, according to Figure 3 The method of sharing the second functional module between the main core and the redundant core in the processor is described. Figure 3 As shown, the main core sends an access signal to the instruction cache in the IF stage to obtain instructions. The instruction cache feeds back instructions to the main core and the redundant core based on the received access signal. After obtaining the instructions, the main core and the redundant core each execute the instruction IP stage. Then, in the IB stage (also known as the instruction buffer stage), if the currently processed instruction is a branch instruction, the main core sends an access signal to the branch predictor in the branch prediction module. The branch predictor accesses the branch history table to perform branch prediction and feeds back the branch prediction results to the main core and the redundant core. If the currently processed instruction is an instruction other than a branch instruction, the main core and the redundant core each perform temporary storage processing.

[0106] Optionally, after the IB stage, the main core and the redundant core each execute the ID stage and the RF stage, and in the EX1 stage, if the instruction currently being processed is a load instruction or a store instruction, the main core accesses the cache to convert the virtual address to the physical address, and the cache feeds back the physical address to the main core and the redundant core. Afterwards, the main core and the redundant core execute the EX2 stage. In the EX2 stage, if the instruction currently being processed is a branch instruction, the main core and the redundant core each perform a prediction check based on the branch prediction result of the IB stage. If the instruction currently being processed is a load instruction or a store instruction, the main core accesses the data cache to load or store data, and the data cache, upon receiving an access signal, performs data alignment and feeds back data (e.g., data to be loaded) to the main core and the redundant core. Optionally, the main core and the redundant core can each execute the EX3 stage, and during the execution of the EX3 stage, since the data cache is shared, the redundant core may not execute the data alignment instruction.

[0107] It should be noted that by having the second functional module receive the access signal sent by the main core to the second functional module, and feeding back data to the main core and the redundant core based on the access signal, the number of accesses to the redundant core is effectively reduced while reducing the functional modules in the redundant core, thereby further reducing the power consumption of the processor.

[0108] In an embodiment of the present application, a processor is implemented based on a RISC-V architecture and includes a main core for executing instruction processing operations; a redundant core for operating in parallel with the main core to execute the instruction processing operations executed by the main core, wherein a functional module in the redundant core is identical to a first functional module in the main core, a second functional module in the main core is shared by the main core and the redundant core, and the second functional module is a functional module in the main core other than the first functional module; and a fault detection unit for detecting whether a processor fault exists based on external output signals of the main core and the redundant core during the execution of the instruction processing operations. The main core executes the instruction processing operations, the redundant core operates in parallel with the main core to execute the instruction processing operations executed by the main core, and the fault detection unit detects whether a processor fault exists based on external output signals of the main core and the redundant core during the execution of the instruction processing operations, thereby implementing a dual-core lockstep function in the processor. By setting the functional module in the redundant core to be identical to the first functional module in the main core and the second functional module in the main core to be shared by the main core and the redundant core, the number of functional modules used in the redundant core is effectively reduced, thereby effectively reducing processor power consumption and reducing the area occupied by the redundant core. This achieves the goal of streamlining redundant cores in the processor and realizes the technical effect of reducing processor power consumption, thereby solving the technical problem of high processor power consumption caused by setting the same main core and redundant core in the processor architecture that realizes the dual-core lockstep function in the related technology.

[0109] Example 2

[0110] According to an embodiment of the present application, a method for detecting a processor failure is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0111] The method embodiment provided in the second embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 4 The hardware structure block diagram of a computer terminal (or mobile device) for implementing a method for detecting a processor failure is shown. Figure 4As shown, the computer terminal (or mobile device) 10 may include a processor set 102 (the processor set 102 may include but is not limited to a processing device such as a microcontroller unit (MCU) or a programmable logic device (FPGA), and the processor set 102 may include a processor set, Figure 4 102a, 102b, ..., 102n are used to illustrate), a memory 104 for storing data, and a transmission device 106 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a Universal Serial Bus (USB) port (which can be included as one of the ports of the BUS), a network interface, a power supply and / or a camera. It will be understood by those skilled in the art that Figure 4 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 4 More or fewer components than shown, or with Figure 4 Different configurations shown.

[0112] It should be noted that the one or more processors 102 and / or other data processing circuits described above may generally be referred to herein as "data processing circuitry." The data processing circuitry may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuitry may be a single, independent processing module, or may be fully or partially integrated into any of the other components of the computer terminal 10 (or mobile device).

[0113] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the method for detecting processor failure in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-mentioned method for detecting processor failure. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0114] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by the communications provider of the computer terminal 10. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0115] The display may be a touch screen liquid crystal display that enables a user to interact with a user interface of the computer terminal 10 (or mobile device).

[0116] Figure 5 This is a flow chart of a method for detecting a processor failure according to the second embodiment of the present application. Figure 5 As shown, the method is applied to the processor in the above embodiment 1, and the method includes:

[0117] Step S501 : acquiring an external output signal generated by a main core in the process of executing an instruction processing operation, and obtaining a first external output signal.

[0118] In an optional embodiment, the output objects of the main core's external output signals include but are not limited to various buses, external storage (such as memory), and operating peripherals, and the external output signals include but are not limited to exception and interrupt signals, memory access signals, access signals for operating peripherals, status signals representing the working status of the main core, etc.

[0119] Optionally, the processor may obtain, through the fault detection unit, an external output signal of the main core during the execution of the instruction processing operation, to obtain a first external output signal.

[0120] Step S502 : acquiring an external output signal generated by the redundant core during the execution of the instruction processing operation to obtain a second external output signal.

[0121] In an optional embodiment, the output objects of the redundant core's external output signals include but are not limited to various buses, external storage (such as memory), and operating peripherals, and the external output signals include but are not limited to exception and interrupt signals, memory access signals, access signals for operating peripherals, status signals representing the working status of the redundant core, etc.

[0122] Optionally, the processor may obtain, through the fault detection unit, an external output signal of the redundant core during execution of the instruction processing operation to obtain a second external output signal.

[0123] Step S503: Detect whether the processor has a fault according to the first external output signal and the second external output signal.

[0124] Optionally, the fault detection unit in the processor may include at least one comparator and a logic processing module. The processor may compare the first external output signal and the second external output signal through the comparator to obtain a first comparison result, and the logic processing module may determine whether the processor has a fault based on the first comparison result.

[0125] For example, when the aforementioned first comparison result indicates that the first external output signal and the second external output signal are the same, it is determined that the processor has no fault; when the aforementioned first comparison result indicates that the first external output signal and the second external output signal are different, it is determined that the processor has a fault.

[0126] It should be noted that by comparing the outputs of the main core and the redundant core, errors generated within the circuit are detected, thereby prompting the system to perform error processing or restart, thereby enhancing security and stability, so that the processor provided in this application can be used in chip modules with higher functional safety certification scenarios.

[0127] In this solution, the main core executes instruction processing operations, and the redundant core operates in parallel with the main core to execute the instruction processing operations executed by the main core. The fault detection unit detects whether there is a fault in the processor based on the external output signals of the main core and the redundant core in the process of executing the instruction processing operations, thereby realizing a dual-core lock-step function in the processor. By setting the functional module in the redundant core to be the same as the first functional module in the main core, the second functional module in the main core is shared by the main core and the redundant core, which effectively reduces the number of functional modules used in the redundant core, thereby effectively reducing the power consumption of the processor and reducing the occupied area of ​​the redundant core. At the same time, it can also effectively reduce the power consumption of the processor during fault detection.

[0128] How to accurately detect whether the processor has a fault is crucial. Therefore, in the processor fault detection method provided in Example 2 of the present application, detecting whether the processor has a fault based on the first external output signal and the second external output signal includes: obtaining an access signal of the main core to the second functional module in the main core to obtain a first access signal, wherein the access signal of the main core is sent to the second functional module when the processor is working normally, and the second functional module feeds back data to the main core and the redundant core based on the access signal of the main core; obtaining an access signal of the redundant core to the second functional module to obtain a second access signal, wherein the access signal of the redundant core is not sent to the second functional module when the processor is working normally; detecting whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal.

[0129] Optionally, in order to improve the accuracy of processor fault detection, the access behavior in the main core can be compared so that errors generated by the main core in the process of generating access signal logic can be effectively detected. Therefore, in addition to comparing the external output signals of the main core and the redundant core, the processor can also additionally detect whether the access signals of the main core and the redundant core to the second functional module are the same. For example, Figure 3 As shown, check the access signals of the main core and redundant core to the instruction cache, check the access signals of the main core and redundant core to the branch predictor in the branch prediction module, check the access signals of the main core and redundant core to the data cache, and check the access signals of the main core and redundant core to the fast table.

[0130] Optionally, although the second functional module is shared by the main core and the redundant core, in order to detect whether the access signal of the main core to the second functional module is accurate, the redundant core is set to generate an access signal to the second functional module in the main core. However, when the processor is working normally, the access signal generated by the redundant core to the second functional module is not sent to the second functional module, but is sent to the fault detection unit so that the fault detection unit can compare the access signals of the main core and the redundant core.

[0131] In an optional embodiment, the first access signal includes at least one access sub-signal, and different access sub-signals in the first access signal refer to access signals of the main core for different second functional modules.

[0132] In an optional example, the second access signal includes at least one access sub-signal, and different access sub-signals in the second access signal refer to access signals of the redundant core for different second functional modules.

[0133] In an optional embodiment, the processor can compare the first external output signal and the second external output signal through a comparator in the fault detection unit to obtain a first comparison result, and compare the first access signal and the second access signal through a comparator in the fault detection unit to obtain a second comparison result, so that the logic processing module in the fault detection unit determines whether the processor has a fault based on the first comparison result and the second comparison result.

[0134] For example, when the first comparison result indicates that the first external output signal and the second external output signal are the same, and the second comparison result indicates that the first access signal and the second access signal are the same, it is determined that the processor has no fault; when the first comparison result indicates that the first external output signal and the second external output signal are different, or when the second comparison result indicates that the first access signal and the second access signal are different, it is determined that the processor has a fault.

[0135] In an optional embodiment, when a processor fault is detected, the logic processing module may generate a target signal and send the target signal to a target control unit in the system where the processor is located, so that the target control unit can decide how to handle the fault.

[0136] In an optional embodiment, the first external output signal and the second external output signal, the first access signal and the second access signal can be compared by the same comparator, or they can be compared by different comparators.

[0137] In an optional embodiment, the second comparison result includes at least one comparison sub-result, with different comparison sub-results corresponding to different second functional modules. Optionally, if both comparison sub-results in the second comparison result indicate that the access sub-signals of the primary core and the redundant core are identical, the second comparison result may be determined to indicate that the first access signal and the second access signal are identical; if the second comparison result indicates that the access sub-signals of the primary core and the redundant core are different, the second comparison result may be determined to indicate that the first access signal and the second access signal are different.

[0138] In an optional embodiment, the access sub-signal in the first access signal and the access sub-signal in the second access signal can be compared by the same comparator to obtain a comparison sub-result, or the access sub-signal in the first access signal and the access sub-signal in the second access signal can be compared by different comparators to obtain a comparison sub-result.

[0139] For example, the above-mentioned IFU, LSU, and MMU all have corresponding comparators. The processor can compare the access sub-signals matched by the IFU (i.e., the access signals of the main core and the redundant core for the instruction cache and the access signals of the main core and the redundant core for the branch predictor in the branch prediction module) through the comparator corresponding to the IFU, compare the access sub-signals matched by the LSU (i.e., the access signals of the main core and the redundant core for the data cache) through the comparator corresponding to the LSU, and compare the access sub-signals matched by the MMU (i.e., the access signals of the main core and the redundant core for the cache) through the comparator corresponding to the MMU.

[0140] It should be noted that by combining the main core and the redundant core to perform fault detection on the access signal of the second functional module, a comparison of the access behavior in the main core is achieved, so that the errors generated by the main core in the process of generating the access signal logic can be effectively detected, thereby effectively improving the accuracy of fault detection.

[0141] In order to accurately obtain the first access signal, in the processor failure detection method provided in Example 2 of the present application, when the second functional module includes a storage module, and the storage module includes an instruction cache, a data cache, and a cache for recording the mapping relationship between virtual addresses and physical addresses, the access signal of the main core to the second functional module in the main core is obtained, and the first access signal is obtained, including: in the instruction acquisition stage of the processor pipeline, obtaining the access signal of the instruction acquisition module in the main core to the instruction cache to obtain a first access sub-signal; in the instruction execution stage of the processor pipeline, obtaining the access signal of the target instruction execution module in the main core to the data cache to obtain a second access sub-signal, and obtaining the access signal of the memory management module in the main core to the cache to obtain a third access sub-signal; and obtaining the first access signal based on the first access sub-signal, the second access sub-signal, and the third access sub-signal.

[0142] Optionally, the access signal from the instruction acquisition module to the instruction cache is used for the instruction acquisition module to acquire instructions from the instruction cache. The access signal from the instruction acquisition module to the instruction cache includes at least the address signal of the instruction to be acquired by the instruction acquisition module, and may also include a chip select signal, a read signal, and other signals.

[0143] Optionally, the instruction execution phase includes the aforementioned first, second, and third instruction execution phases. The target instruction execution module's access signal to the data cache is used by the target instruction execution module to read data from or write data to the data cache. The target instruction execution module may be a load module or a storage module. The target instruction execution module's access signal to the data cache includes at least an address signal and a read signal for the data to be read, or an address signal and a write signal for the data to be written, and may also include signals such as a chip select signal.

[0144] Optionally, the memory management module's access signal to the cache is used by the memory management module to obtain a physical address from the cache. The memory management module's access signal to the cache includes at least a virtual address to be mapped to a physical address. The virtual address may be an address provided by a load module or a storage module. The access signal may also include a chip select signal, a read signal, and other signals.

[0145] In an optional embodiment, the DCLS processing unit may include a target IFU (ie, a target instruction fetch unit), and the target IFU includes at least an IFU in the main core and an IFU in the redundant core. Figure 6 The schematic diagram shown in FIG. 4 realizes sharing the instruction cache between the main core and the redundant core. Figure 6 is a schematic diagram of a target instruction fetch unit provided according to the second embodiment of the present application, such as Figure 6As shown, the IFU in the main core and redundant core receives the input signal (which can be the instruction address in the PC), generates an access signal for the instruction cache and sends it to the instruction cache through the corresponding data access signal line. The instruction cache feeds back data to the IFU in the main core and redundant core based on the received access signal, for example, to the instruction acquisition module in the IFU. In this process, Figure 6 As shown, the fault detection unit can obtain the first access sub-signal.

[0146] In an optional embodiment, the DCLS processing unit may include a target LSU (ie, a target load / store unit), and the target LSU includes at least an LSU in the primary core and an LSU in the redundant core. Figure 7 The schematic diagram shown in FIG. 4 realizes sharing data cache between the main core and the redundant core. Figure 7 is a schematic diagram of a target load / store unit provided according to the second embodiment of the present application, such as Figure 7 As shown, the LSU in the main core and redundant core receives an input signal (which may be a load instruction or a store instruction), generates an access signal for the data cache, and sends it to the data cache through the corresponding data access signal line. The data cache feeds back data to the LSU in the main core and redundant core based on the received access signal, for example, to the storage module in the LSU. In this process, Figure 7 As shown, the fault detection unit can obtain the second access sub-signal. Optionally, the data cache may include multiple cache lines, and the cache line includes two parts: a tag (TAG) and data (DATA).

[0147] Optionally, the process of the processor obtaining the third access sub-signal is similar to the process of obtaining the second access sub-signal and the first access sub-signal, and thus will not be described in detail here.

[0148] In an optional embodiment, the DCLS processing unit may include a target MMU (ie, a target memory management unit), and the target MMU includes at least an MMU in the primary core and an MMU in the redundant core.

[0149] In an optional embodiment, the DCLS processing unit may include a target CORE (ie, a target main processing unit), and the target CORE includes at least a CORE in the main core and a CORE in the redundant core. Figure 8 is a schematic diagram of a main processing unit provided according to the second embodiment of the present application, such as Figure 8As shown, because the CORE in the primary core is a pure logic module with no data access signal lines, the CORE in the redundant core is identical to the CORE in the primary core and does not involve information exchange, so the two do not interfere with each other. The input data of the CORE in the redundant core comes from the IFU in the redundant core. This data can be instructions to be decoded. Its output data can be sent to the LSU. The output data can be decoded store instructions or decoded load instructions.

[0150] In an optional embodiment, after the first access sub-signal, the second access sub-signal, and the third access sub-signal are obtained, the first access sub-signal, the second access sub-signal, and the third access sub-signal are used to form a first access signal.

[0151] In an optional embodiment, when the second functional module includes a storage module, and the storage module includes at most two of an instruction cache, a data cache, and a cache for recording the mapping relationship between virtual addresses and physical addresses, the method for obtaining the first access signal is the same as the above-mentioned method for obtaining the first access signal, so it will not be repeated here.

[0152] In an optional embodiment, the process of the processor obtaining the second access signal is the same as the process of obtaining the first access signal described above, and therefore will not be described in detail.

[0153] It should be noted that by acquiring the first access sub-signal, the second access sub-signal and the third access sub-signal from specific modules in each stage of the processor pipeline, and then obtaining the first access signal, the first access signal is accurately acquired.

[0154] In order to accurately obtain the first access signal, in the processor fault detection method provided in Example 2 of the present application, when the second functional module includes a branch prediction module, the access signal of the main core to the second functional module in the main core is obtained, and obtaining the first access signal includes: in the branch prediction stage of the processor pipeline, obtaining the access signal of the instruction acquisition module in the main core to the branch prediction module to obtain a fourth access sub-signal; and obtaining the first access signal based on the fourth access sub-signal.

[0155] Optionally, the instruction fetch module's access signal to the branch prediction module is used to enable the instruction fetch module to obtain a branch prediction result for a target branch instruction from the branch predictor. The target branch instruction refers to a branch instruction sent by the instruction fetch module to the branch predictor, and can also be understood as the branch instruction currently being predicted by the branch predictor. The instruction fetch module's access signal to the branch prediction module includes at least instruction information for the target branch instruction (e.g., a pre-decoding result of the target branch instruction). The access signal may also include signals such as a chip select signal and a read signal.

[0156] like Figure 6As shown, the IFU in the main core and redundant core receives the input signal (which can be the instruction address in the PC), generates an access signal for the branch prediction module and sends it to the branch predictor through the corresponding data access signal line. The branch predictor interacts with the branch history table based on the received access signal to implement branch prediction and feeds back the data to the IFU in the main core and redundant core, for example, to the instruction fetch module in the IFU. In this process, Figure 6 As shown, the fault detection unit can obtain the fourth access sub-signal.

[0157] In an optional embodiment, after the fourth access sub-signal, the first access signal is composed of the fourth access sub-signal.

[0158] In an optional embodiment, when the second functional module includes a storage module and a branch prediction module, and the storage module includes an instruction cache, a data cache, and a cache for recording a mapping relationship between virtual addresses and physical addresses, the first access signal is obtained based on the above-mentioned first access sub-signal, second access sub-signal, third access sub-signal, and fourth access sub-signal.

[0159] In an optional embodiment, the process of obtaining the second access signal is the same as the process of obtaining the first access signal described above, and therefore will not be described in detail.

[0160] It should be noted that, by acquiring the fourth access sub-signal from the instruction fetch module in the branch prediction stage of the processor pipeline, and then obtaining the first access signal, accurate acquisition of the first access signal is achieved.

[0161] In order to reduce the probability of common mode failure of the main core and the redundant core, in the processor fault detection method provided in the second embodiment of the present application, the external output signal of the main core in the process of executing the instruction processing operation is obtained, and the first external output signal is obtained, which includes: in the process of the main core executing the instruction processing operation, if the main core outputs the external output signal, then the external output signal output by the main core is delayed by the first clock cycle to obtain the first external output signal; the external output signal of the redundant core in the process of executing the instruction processing operation is obtained, and the second external output signal is obtained, which includes: when there is an external input signal for the redundant core, the external input signal for the redundant core is delayed by the second clock cycle; in the process of the redundant core executing the instruction processing operation based on the external input signal after delay processing, if the redundant core outputs the external output signal, then the external output signal output by the redundant core is delayed by the third clock cycle to obtain the second external output signal, wherein the sum of the second clock cycle and the third clock cycle is the same as the first clock cycle.

[0162] In order to prevent clock interference caused by radiation from affecting both cores simultaneously, a delay module may optionally be introduced into the processor to perform clock cycle delay processing so that there is a time difference in instruction processing operations between the primary core and the redundant core.

[0163] Optionally, the DCLS processing unit may include a delay register to allow for a time difference in instruction processing operations between the primary and redundant cores. Optionally, in addition to the clock source signal, external input signals to the redundant core are directly input to the redundant core after passing through the redundant core input delay register. Before comparing the outputs of the primary and redundant cores, the primary core's external output signal may be delayed using the primary core output delay register, and the redundant core's external output signal may be delayed using the redundant core output delay register. This allows the cycles of the external output signals of the two cores to be synchronized, thereby ensuring the accuracy of detection by the fault detection unit.

[0164] For example, the redundant core's input delay register can be used to delay the redundant core's external input signal by two clock cycles (i.e., the second clock cycle mentioned above), and the redundant core's output delay register can be used to delay the redundant core's external output signal by one clock cycle (i.e., the third clock cycle mentioned above), for a total of three clock cycles. For comparison, the external output signals of the primary and redundant cores can be resynchronized. Specifically, the primary core's output delay register can be used to delay the primary core's output by three clock cycles, so that the cycles of the external output signals of the two cores are synchronized.

[0165] In an optional embodiment, the content of the external input signal to the redundant core is the same as the external input signal to the primary core. For performance reasons, delaying the external input signal to the primary core is avoided. Optionally, the input objects for sending external input signals to the primary core or redundant core include, but are not limited to, various buses, external storage (e.g., memory), and operating peripherals. The external input signals include, but are not limited to, instruction addresses in the PC, exception and interrupt signals, signals fed back by memory access to the core, signals fed back by operating peripherals to the core access, and status signals of operating peripherals.

[0166] It should be noted that by delaying the clock cycle of the output of the main core and the input and output of the redundant core, there is a time difference in the instruction processing operations between the main core and the redundant core, which can effectively reduce the probability of common mode failure of the main core and the redundant core and improve the stability of the processor operation.

[0167] In order to improve the accuracy of fault detection, in the processor fault detection method provided in Example 2 of the present application, obtaining the access signal of the main core to the second functional module in the main core, and obtaining the first access signal includes: when the main core outputs the access signal to the second functional module, delaying the access signal output by the main core by the first clock cycle to obtain the first access signal; obtaining the access signal of the redundant core to the second functional module, and obtaining the second access signal includes: when the redundant core outputs the access signal to the second functional module, delaying the access signal output by the redundant core by the third clock cycle to obtain the second access signal.

[0168] Because delay processing of the redundant core's external input signals causes a time difference in instruction processing between the primary and redundant cores, there will also be a time difference in the access signals to the second functional module between the primary and redundant cores. In this case, the processor can delay the access signals output by the primary and redundant cores to synchronize the access signal cycles of the primary and redundant cores.

[0169] Optionally, because the access signals output by the primary core and the access signals output by the redundant core each include access signals for different second functional modules, a first delay register and a third delay register may be respectively set in the target IFU, the target LSU, and the target MMU to delay the access signals of the primary core and the redundant core for different second functional modules. The first delay register is used to delay the access signal by a first clock cycle, and the third delay register is used to delay the access signal by a third clock cycle.

[0170] For example, Figure 6 As shown, in the target IFU, the access signal of the instruction acquisition module in the main core for the instruction cache and the access signal of the instruction acquisition module in the main core for the branch prediction module pass through the first delay register to obtain the first access sub-signal and the fourth access sub-signal, and the first access sub-signal and the fourth access sub-signal are input to the comparator, and the access signal of the instruction acquisition module in the redundant core for the instruction cache and the access signal of the instruction acquisition module in the main core for the branch prediction module pass through the third delay register to obtain the corresponding access sub-signals, and the corresponding access sub-signals are input to the comparator.

[0171] For example, Figure 7 As shown, in the target LSU, the target instruction execution module in the main core obtains the second access sub-signal for the access signal of the data cache through the first delay register, and inputs the corresponding second access sub-signal to the comparator, and the target instruction execution module in the redundant core obtains the corresponding access sub-signal for the access signal of the data cache through the third delay register, and inputs the corresponding access sub-signal to the comparator.

[0172] In an optional embodiment, the method of obtaining the third access sub-signal based on the delay processing is the same as the method of obtaining the second access sub-signal based on the delay processing described above, and therefore will not be described in detail here.

[0173] In an optional embodiment, if Figure 8 As shown, since the COREs of the main core and the redundant core do not involve data access in the target CORE, it is not necessary to set a delay register in the target CORE.

[0174] To ensure a time difference between instruction processing operations between the primary core and the redundant core, a time difference must also exist between the data fed back by the second functional module to the primary core and the redundant core. Therefore, in an optional embodiment, a second delay register can be provided in each of the target IFU, target LSU, and target MMU to delay processing of data fed back by the second functional module in the primary core for the redundant core. The second delay register is used to delay the access signal by a second clock cycle.

[0175] For example, Figure 6 As shown, in the target IFU, the data fed back by the instruction cache in the main core is fed back to the IFU in the redundant core through the second delay register.

[0176] For example, Figure 7 As shown, in the target LSU, the data fed back by the data cache in the main core is fed back to the LSU in the redundant core through the second delay register.

[0177] In an optional embodiment, the method of delaying the data fed back by the cache is the same as the above-mentioned method of delaying the data fed back by the instruction cache and the data cache, so it is not repeated here.

[0178] It should be noted that by delaying the access signals of the main core and the redundant core, the periodic synchronization of the access signals in the main core and the redundant core is achieved, thereby avoiding erroneous fault detection caused by access signal asynchrony and effectively improving the accuracy of fault detection.

[0179] In order to improve the accuracy of fault detection, in the processor fault detection method provided in Example 2 of the present application, detecting whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal includes: when the first external output signal is the same as the second external output signal, and the first access signal is the same as the second access signal, determining that the processor has no fault; when the first external output signal is different from the second external output signal, or the first access signal is different from the second access signal, determining that the processor has a fault.

[0180] In an optional embodiment, the second comparison result includes at least one comparison sub-result, with different comparison sub-results corresponding to different second functional modules. Optionally, if all comparison sub-results in the second comparison result indicate that the access sub-signals of the primary core and the redundant core are identical, the second comparison result may be determined to indicate that the first access signal and the second access signal are identical; if one of the second comparison results indicates that the access sub-signals of the primary core and the redundant core are different, the second comparison result may be determined to indicate that the first access signal and the second access signal are different.

[0181] In an optional embodiment, different comparators can be used to compare the first external output signal and the second external output signal, the first access signal and the second access signal, and different comparators can be used to compare the access sub-signal in the first access signal and the access sub-signal in the second access signal to obtain comparison sub-results. For example, Figure 9 The schematic diagram shown is used to determine the fault detection result. Figure 9 is a schematic diagram of determining the fault detection result according to the second embodiment of the present application, such as Figure 9 As shown, the processor can determine the comparison sub-result corresponding to the access sub-signal in the IFU through a comparator in the target IFU, determine the comparison sub-result corresponding to the access sub-signal in the LSU through a comparator in the target LSU, determine the comparison sub-result corresponding to the access sub-signal in the MMU through a comparator in the target MMU, and determine the comparison result corresponding to the first external output signal and the second external output signal through the target comparator. Optionally, the target comparator can be a comparator other than the comparators in the target IFU, target LSU, and target MMU.

[0182] Alternatively, as Figure 9 As shown, after obtaining the first comparison result and each comparison sub-result, the logic processing module in the fault detection unit can use an OR operation to determine a second comparison result based on each comparison sub-result, and use an OR operation to determine whether the processor is faulty based on the first comparison result and the second comparison result, that is, to determine whether the processor is faulty. That is, if the first comparison result indicates that the first external output signal and the second external output signal are identical, and the second comparison result indicates that the first access signal and the second access signal are identical, it is determined that the processor is not faulty; if the first comparison result indicates that the first external output signal and the second external output signal are different, or if the second comparison result indicates that the first access signal and the second access signal are different, it is determined that the processor is faulty.

[0183] It should be noted that by adopting an OR operation to determine the fault detection result based on the comparison result of the output signal and the comparison result of the access signal, the accuracy of the fault detection can be effectively improved.

[0184] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0185] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0186] Example 3

[0187] According to an embodiment of the present application, a processor failure detection device for implementing the above-mentioned processor failure detection method is also provided. Figure 10 As shown, the device is applied to the processor in the above embodiment 1, including: a first acquisition unit 1001, a second acquisition unit 1002, and a detection unit 1003.

[0188] A first acquiring unit 1001 is configured to acquire an external output signal of the main core during the execution of an instruction processing operation, and obtain a first external output signal;

[0189] A second acquiring unit 1002 is configured to acquire an external output signal of the redundant core during the execution of the instruction processing operation to obtain a second external output signal;

[0190] The detection unit 1003 is configured to detect whether the processor has a fault according to the first external output signal and the second external output signal.

[0191] In the processor fault detection device provided in the third embodiment of the present application, a first acquisition unit 1001 acquires an external output signal of a main core during the execution of an instruction processing operation to obtain a first external output signal; a second acquisition unit 1002 acquires an external output signal of a redundant core during the execution of an instruction processing operation to obtain a second external output signal; and a detection unit 1003 detects whether a processor fault exists based on the first external output signal and the second external output signal. In this solution, the main core executes an instruction processing operation, and the redundant core operates in parallel with the main core to execute the instruction processing operation executed by the main core. The fault detection unit detects whether a processor fault exists based on the external output signals of the main core and the redundant core during the execution of the instruction processing operation, thereby realizing a dual-core lockstep function in the processor. By setting the functional module in the redundant core to be the same as the first functional module in the main core, and the second functional module in the main core being shared by the main core and the redundant core, the number of functional modules used in the redundant core is effectively reduced, thereby effectively reducing the power consumption of the processor and reducing the area occupied by the redundant core. This achieves the goal of streamlining redundant cores in the processor and realizes the technical effect of reducing processor power consumption, thereby solving the technical problem of high processor power consumption caused by setting the same main core and redundant core in the processor architecture that realizes the dual-core lockstep function in the related technology.

[0192] Optionally, in the processor failure detection device provided in Example 3 of the present application, the detection unit includes: a first acquisition sub-unit, used to acquire an access signal of the main core to the second functional module in the main core, and obtain a first access signal, wherein the access signal of the main core is sent to the second functional module when the processor is working normally, and the second functional module feeds back data to the main core and the redundant core based on the access signal of the main core; a second acquisition sub-unit, used to acquire an access signal of the redundant core to the second functional module, and obtain a second access signal, wherein the access signal of the redundant core is not sent to the second functional module when the processor is working normally; a detection sub-unit, used to detect whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal.

[0193] Optionally, in the processor fault detection device provided in Example 3 of the present application, when the second functional module includes a storage module, and the storage module includes an instruction cache, a data cache, and a cache for recording the mapping relationship between virtual addresses and physical addresses, the first acquisition sub-unit includes: a first acquisition module, used to obtain the access signal of the instruction acquisition module in the main core to the instruction cache in the instruction acquisition stage of the processor pipeline, and obtain a first access sub-signal; a second acquisition module, used to obtain the access signal of the target instruction execution module in the main core to the data cache in the instruction execution stage of the processor pipeline, and obtain a second access sub-signal, and obtain the access signal of the memory management module in the main core to the cache, and obtain a third access sub-signal; and a first processing module, used to obtain the first access signal based on the first access sub-signal, the second access sub-signal, and the third access sub-signal.

[0194] Optionally, in the processor fault detection device provided in Example 3 of the present application, when the second functional module includes a branch prediction module, the first acquisition sub-unit includes: a third acquisition module, used to obtain the access signal of the instruction acquisition module in the main core for the branch prediction module in the branch prediction stage of the processor pipeline to obtain a fourth access sub-signal; and a second processing module, used to obtain the first access signal based on the fourth access sub-signal.

[0195] Optionally, in the processor failure detection device provided in Example 3 of the present application, the first acquisition unit includes: a first processing sub-unit, which is used to delay the external output signal output by the main core by a first clock cycle to obtain the first external output signal if the main core outputs an external output signal during the process of the main core executing the instruction processing operation; the second acquisition unit includes: a second processing sub-unit, which is used to delay the external input signal for the redundant core by a second clock cycle when there is an external input signal for the redundant core; and a third processing sub-unit, which is used to delay the external output signal output by the redundant core by a third clock cycle to obtain the second external output signal if the redundant core outputs an external output signal during the process of the redundant core executing the instruction processing operation based on the delayed external input signal, wherein the sum of the second clock cycle and the third clock cycle is the same as the first clock cycle.

[0196] Optionally, in the processor failure detection device provided in Example 3 of the present application, the first acquisition sub-unit includes: a third processing module, which is used to delay the access signal output by the main core by the first clock cycle to obtain the first access signal when the main core outputs an access signal for the second functional module; the second acquisition sub-unit includes: a fourth processing module, which is used to delay the access signal output by the redundant core by the third clock cycle to obtain the second access signal when the redundant core outputs an access signal for the second functional module.

[0197] Optionally, in the processor fault detection device provided in Example 3 of the present application, the detection subunit includes: a first determination module, used to determine that there is no fault in the processor when the first external output signal is the same as the second external output signal, and the first access signal is the same as the second access signal; and a second determination module, used to determine that there is a fault in the processor when the first external output signal is different from the second external output signal, or the first access signal is different from the second access signal.

[0198] It should be noted that the first acquisition unit 1001, the second acquisition unit 1002, and the detection unit 1003 described above correspond to steps S501 to S503 in Example 2. The examples and application scenarios implemented by the above units and corresponding steps are the same, but are not limited to the contents disclosed in Example 2. It should be noted that the above modules, as part of the device, can be run in the computer terminal 10 provided in Example 2.

[0199] It should be noted that the preferred implementation scheme involved in the above embodiments of this application is the same as the scheme provided in Example 2, as well as the application scenario and implementation process, but is not limited to the scheme provided in Example 2.

[0200] Example 4

[0201] The embodiment of the present application may provide an electronic device, which may be any electronic device in a group of electronic devices. Optionally, in this embodiment, the electronic device may also be replaced by a terminal device such as a mobile terminal.

[0202] Optionally, in this embodiment, the electronic device may be located in at least one network device among a plurality of network devices of a computer network.

[0203] In this embodiment, the above-mentioned electronic device can execute the program code of the following steps in the method for detecting processor failure: obtaining the external output signal of the main core during the execution of the instruction processing operation to obtain a first external output signal; obtaining the external output signal of the redundant core during the execution of the instruction processing operation to obtain a second external output signal; and detecting whether the processor has a fault based on the first external output signal and the second external output signal.

[0204] The above-mentioned electronic device can also execute the program code of the following steps in the method for detecting processor failure: obtaining an access signal of the main core to the second functional module in the main core to obtain a first access signal, wherein the access signal of the main core is sent to the second functional module when the processor is working normally, and the second functional module feeds back data to the main core and the redundant core based on the access signal of the main core; obtaining an access signal of the redundant core to the second functional module to obtain a second access signal, wherein the access signal of the redundant core is not sent to the second functional module when the processor is working normally; and detecting whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal.

[0205] The above-mentioned electronic device can also execute the program code of the following steps in the method for detecting processor failure: in the instruction acquisition stage of the processor pipeline, obtain the access signal of the instruction acquisition module in the main core to the instruction cache to obtain a first access sub-signal; in the instruction execution stage of the processor pipeline, obtain the access signal of the target instruction execution module in the main core to the data cache to obtain a second access sub-signal, and obtain the access signal of the memory management module in the main core to the cache to obtain a third access sub-signal; obtain the first access signal based on the first access sub-signal, the second access sub-signal and the third access sub-signal.

[0206] The above-mentioned electronic device can also execute the program code of the following steps in the method for detecting processor failure: in the branch prediction stage of the processor pipeline, obtain the access signal of the instruction acquisition module in the main core to the branch prediction module to obtain a fourth access sub-signal; and obtain the first access signal based on the fourth access sub-signal.

[0207] The above-mentioned electronic device can also execute the program code of the following steps in the method for detecting processor failure: during the process of the main core executing the instruction processing operation, if the main core outputs an external output signal, the external output signal output by the main core is delayed by the first clock cycle to obtain the first external output signal; when there is an external input signal for the redundant core, the external input signal for the redundant core is delayed by the second clock cycle; during the process of the redundant core executing the instruction processing operation based on the external input signal after delay processing, if the redundant core outputs an external output signal, the external output signal output by the redundant core is delayed by the third clock cycle to obtain the second external output signal, wherein the sum of the second clock cycle and the third clock cycle is the same as the first clock cycle.

[0208] The above-mentioned electronic device can also execute the program code of the following steps in the method for detecting processor failure: when the main core outputs an access signal for the second functional module, the access signal output by the main core is delayed by the first clock cycle to obtain a first access signal; when the redundant core outputs an access signal for the second functional module, the access signal output by the redundant core is delayed by the third clock cycle to obtain a second access signal.

[0209] The above-mentioned electronic device can also execute the program code of the following steps in the method for detecting processor failure: when the first external output signal is the same as the second external output signal, and the first access signal is the same as the second access signal, determining that there is no fault in the processor; when the first external output signal is different from the second external output signal, or the first access signal is different from the second access signal, determining that there is a fault in the processor.

[0210] Optionally, Figure 11 This is a structural block diagram of an electronic device according to an embodiment of the present application. Figure 11 As shown, the electronic device 110 may include: one or more ( Figure 11 (only one is shown) processor 1102, memory 1104. The electronic device 110 may further include a memory controller to control and manage the memory 1104; the electronic device 110 may further include a peripheral interface to connect to a radio frequency module, an audio module, and a display screen, etc.

[0211] Among them, the memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the processor failure detection method and device in the embodiment of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, realizing the above-mentioned processor failure detection method. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely located relative to the processor, and these remote memories can be connected to the terminal 10 via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0212] The processor can call the information and application programs stored in the memory through the transmission device to perform the following steps: obtain the external output signal of the main core during the execution of the instruction processing operation to obtain a first external output signal; obtain the external output signal of the redundant core during the execution of the instruction processing operation to obtain a second external output signal; and detect whether the processor has a fault based on the first external output signal and the second external output signal.

[0213] Optionally, the above-mentioned processor can also execute the program code of the following steps: obtain the access signal of the main core to the second functional module in the main core to obtain a first access signal, wherein the access signal of the main core is sent to the second functional module when the processor is working normally, and the second functional module feeds back data to the main core and the redundant core based on the access signal of the main core; obtain the access signal of the redundant core to the second functional module to obtain a second access signal, wherein the access signal of the redundant core is not sent to the second functional module when the processor is working normally; detect whether the processor has a fault based on the first external output signal and the second external output signal, the first access signal and the second access signal.

[0214] Optionally, the above-mentioned processor can also execute the program code of the following steps: in the instruction acquisition stage of the processor pipeline, obtain the access signal of the instruction acquisition module in the main core to the instruction cache to obtain a first access sub-signal; in the instruction execution stage of the processor pipeline, obtain the access signal of the target instruction execution module in the main core to the data cache to obtain a second access sub-signal, and obtain the access signal of the memory management module in the main core to the cache to obtain a third access sub-signal; obtain the first access signal based on the first access sub-signal, the second access sub-signal and the third access sub-signal.

[0215] Optionally, the processor may also execute the following program code: in the branch prediction stage of the processor pipeline, obtain the access signal of the instruction acquisition module in the main core to the branch prediction module to obtain a fourth access sub-signal; and obtain the first access signal based on the fourth access sub-signal.

[0216] Optionally, the above-mentioned processor can also execute the program code of the following steps: in the process of the main core executing the instruction processing operation, if the main core outputs an external output signal, the external output signal output by the main core is delayed by the first clock cycle to obtain the first external output signal; when there is an external input signal for the redundant core, the external input signal for the redundant core is delayed by the second clock cycle; in the process of the redundant core executing the instruction processing operation based on the external input signal after delay processing, if the redundant core outputs an external output signal, the external output signal output by the redundant core is delayed by the third clock cycle to obtain the second external output signal, wherein the sum of the second clock cycle and the third clock cycle is the same as the first clock cycle.

[0217] Optionally, the above-mentioned processor can also execute the program code of the following steps: when the main core outputs an access signal for the second functional module, the access signal output by the main core is delayed by the first clock cycle to obtain a first access signal; when the redundant core outputs an access signal for the second functional module, the access signal output by the redundant core is delayed by the third clock cycle to obtain a second access signal.

[0218] Optionally, the above-mentioned processor can also execute the program code of the following steps: when the first external output signal is the same as the second external output signal, and the first access signal is the same as the second access signal, determine that there is no fault in the processor; when the first external output signal is different from the second external output signal, or the first access signal is different from the second access signal, determine that there is a fault in the processor.

[0219] It can be understood by those skilled in the art that Figure 11 The structure shown is for illustration only, and the electronic device may also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile Internet device (MID), a PAD, or other terminal devices. Figure 11 It does not limit the structure of the above electronic device. For example, the electronic device 110 may also include Figure 11 More or fewer components (such as network interfaces, display devices, etc.) shown in, or with Figure 11 Different configurations shown.

[0220] A person skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0221] Example 5

[0222] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program or instructions, which, when executed by a processor, implement the processor failure detection method provided in the second embodiment.

[0223] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0224] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0225] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0226] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0227] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0228] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program code.

[0229] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A processor, characterized in that: The processor is based on the RISC-V architecture and includes: The main core is used to perform instruction processing operations; a redundant core, configured to operate in parallel with the main core to execute instruction processing operations executed by the main core, wherein a functional module in the redundant core is the same as a first functional module in the main core, a second functional module in the main core is shared by the main core and the redundant core, and the second functional module is a functional module in the main core other than the first functional module; The fault detection unit is used to detect whether the processor has a fault based on the external output signals of the main core and the redundant core during the execution of instruction processing operations.

2. The processor according to claim 1, wherein: The second functional module is at least one of the following: a storage module, a branch prediction module, the storage module includes at least one of the following: an instruction cache, a data cache, a quick table for recording the mapping relationship between virtual addresses and physical addresses, and the branch prediction module includes a branch predictor and a branch history table for recording the execution results of historical branch instructions.

3. The processor according to claim 1, wherein: The second functional module is used to receive an access signal sent by the main core to the second functional module, and to feed back data to the main core and the redundant core based on the access signal, so as to realize sharing of the second functional module between the main core and the redundant core.

4. A method for detecting a processor failure, characterized in that: The processor according to any one of claims 1 to 3, comprising: Acquire an external output signal of the main core during the execution of the instruction processing operation to obtain a first external output signal; Acquiring an external output signal of the redundant core during the execution of the instruction processing operation to obtain a second external output signal; Whether the processor has a fault is detected according to the first external output signal and the second external output signal.

5. The method according to claim 4, characterized in that Detecting whether the processor has a fault according to the first external output signal and the second external output signal includes: acquiring an access signal from the main core to a second functional module in the main core to obtain a first access signal, wherein the access signal from the main core is sent to the second functional module when the processor is operating normally, and the second functional module feeds back data to the main core and the redundant core based on the access signal from the main core; Acquire an access signal of the redundant core to the second functional module to obtain a second access signal, wherein the access signal of the redundant core is not sent to the second functional module when the processor operates normally; Whether the processor has a fault is detected according to the first external output signal, the second external output signal, the first access signal, and the second access signal.

6. The method according to claim 5, characterized in that In a case where the second functional module includes a storage module, and the storage module includes an instruction cache, a data cache, and a cache for recording a mapping relationship between a virtual address and a physical address, obtaining an access signal from the main core to the second functional module in the main core to obtain the first access signal includes: In an instruction acquisition phase of a processor pipeline, acquiring an access signal of an instruction acquisition module in the main core to the instruction cache to obtain a first access sub-signal; During an instruction execution phase of the processor pipeline, obtaining an access signal from a target instruction execution module in the main core to the data cache to obtain a second access sub-signal, and obtaining an access signal from a memory management module in the main core to the cache to obtain a third access sub-signal; The first access signal is obtained according to the first access sub-signal, the second access sub-signal, and the third access sub-signal.

7. The method according to claim 5, characterized in that In a case where the second functional module includes a branch prediction module, obtaining an access signal of the main core to the second functional module in the main core to obtain the first access signal includes: In a branch prediction stage of the processor pipeline, obtaining an access signal of the instruction acquisition module in the main core to the branch prediction module to obtain a fourth access sub-signal; The first access signal is obtained according to the fourth access sub-signal.

8. The method according to claim 5, characterized in that Acquiring an external output signal of the main core during execution of the instruction processing operation to obtain the first external output signal includes: if the main core outputs the external output signal during the execution of the instruction processing operation by the main core, delaying the external output signal output by the main core by a first clock cycle to obtain the first external output signal; Obtaining an external output signal of a redundant core in the process of executing an instruction processing operation to obtain a second external output signal includes: when there is an external input signal for the redundant core, delaying the external input signal for the redundant core by a second clock cycle; in the process of the redundant core executing an instruction processing operation based on the delayed external input signal, if the redundant core outputs an external output signal, delaying the external output signal output by the redundant core by a third clock cycle to obtain the second external output signal, wherein the sum of the second clock cycle and the third clock cycle is the same as the first clock cycle.

9. The method according to claim 8, characterized in that Acquiring an access signal from the main core to the second functional module in the main core to obtain a first access signal includes: When the main core outputs an access signal for the second functional module, delaying the access signal output by the main core by the first clock cycle to obtain the first access signal; Obtaining an access signal from the redundant core to the second functional module, where obtaining the second access signal includes: In a case where the redundant core outputs an access signal for the second functional module, the access signal output by the redundant core is delayed by the third clock cycle to obtain the second access signal.

10. The method according to claim 5, characterized in that Detecting whether the processor has a fault according to the first external output signal, the second external output signal, the first access signal, and the second access signal includes: When the first external output signal is identical to the second external output signal, and the first access signal is identical to the second access signal, determining that the processor is not faulty; When the first external output signal is different from the second external output signal, or the first access signal is different from the second access signal, it is determined that the processor has a fault.

11. A processor failure detection device, characterized in that: The processor according to any one of claims 1 to 3, comprising: A first acquiring unit is configured to acquire an external output signal of the main core during the execution of an instruction processing operation, and obtain a first external output signal; A second acquiring unit is configured to acquire an external output signal of the redundant core during the execution of the instruction processing operation to obtain a second external output signal; A detection unit is used to detect whether the processor has a fault according to the first external output signal and the second external output signal.

12. An electronic device, characterized in that: include: a memory storing an executable program; A processor, configured to run the program, wherein the program, when running, executes the method for detecting processor failure according to any one of claims 4 to 10.

13. A computer program product, characterized in that The method comprises a computer program or instructions, which implement the method for detecting processor failure according to any one of claims 4 to 10 when executed by a processor.

Images