Controller and multiple control method

Abstract

The invention provides a controller and a multi-control method, and relates to the technical field of automation control, the controller comprises n channels, each channel comprises a processor, the processor in the ith channel is connected with the processor in the (i + 1) th channel through a coupling capacitor, and the processor in the (i + 1) th channel is connected with the processor in the (i + 1) th channel through a coupling capacitor. The processor in the nth channel is connected with the processor in the first channel through a coupling capacitor, and n is greater than or equal to 2; i is greater than or equal to 1 and less than or equal to n-1. A plurality of channels are arranged in the controller, the channels are connected through the coupling capacitors, data transmission and physical isolation are ensured at the same time, based on the arrangement of the channels, the reliability of the whole system is improved through physical isolation and coupling capacitor connection, and the safety of the system is improved through a control output mechanism.

Description

Technical Field

[0001] The present invention relates to the field of automation control technology, and in particular to a controller and a multiple control method. Background Art

[0002] With the development of industrial automation and intelligent manufacturing, the computing power and reliability requirements of controllers are getting higher and higher. Complex application scenarios have high requirements for controller performance. Since it is difficult to use high-frequency controllers, multiple low-frequency controllers are usually combined in the existing technology to meet the high-performance requirements in complex scenarios.

[0003] In the prior art, since a single-channel design is generally adopted when multiple controllers are used in combination, that is, multiple controllers are set in the same channel, once an abnormality occurs in a controller, it may cause the entire control system to work abnormally, thereby causing the reliability and safety of the control system to decrease. Summary of the invention

[0004] The problem solved by the present invention is how to ensure the stable operation of the controller, thereby improving the reliability and safety of the controller.

[0005] To solve the above problems, the present invention provides a controller and a multiple control method.

[0006] In a first aspect, the present invention provides a controller, comprising n channels, each of which comprises a processor, the processor in the i-th channel is connected to the processor in the i+1-th channel via a coupling capacitor, and the processor in the n-th channel is connected to the processor in the first channel via a coupling capacitor, wherein n is greater than or equal to 2; i is greater than or equal to 1, and less than or equal to n-1.

[0007] Optionally, each of the channels further includes a clock generator, and the clock generator in each channel is respectively connected to the corresponding processor, the clock generator in the i-th channel is also connected to the processor in the i+1-th channel, and the clock generator in the n-th channel is also connected to the processor in the first channel.

[0008] Optionally, a coupling capacitor is connected in series between the clock generator in the ith channel and the processor in the (i+1)th channel, and a coupling capacitor is connected in series between the clock generator in the nth channel and the processor in the first channel.

[0009] Optionally, each of the channels further includes a bus module, and the bus module in each of the channels is communicatively connected to the corresponding processor via a local bus of the corresponding processor.

[0010] Optionally, each of the channels further includes a buffer and a latch, the input end of the buffer is connected to the external address latch of the corresponding processor, the input end of the latch is respectively connected to the output end of the corresponding buffer and the data interface of the corresponding processor, and the output end of the latch is connected to the data interface of the corresponding bus module.

[0011] Optionally, each of the channels further includes a power supply module, and the power supply modules in each of the channels are electrically connected to the corresponding processors respectively.

[0012] The controller of the present invention forms a closed ring structure by arranging multiple channels in the controller, wherein the processor of each channel is connected to the processor of the next channel through a coupling capacitor, and the processor of the nth channel is connected to the processor of the first channel through a coupling capacitor. Based on the arrangement of the above channels, data and signals are allowed to be efficiently and safely transmitted between channels, while maintaining electrical isolation between channels to avoid mutual interference. Even if a channel fails, it will not affect the normal operation of other channels, thereby improving the reliability and safety of the entire system.

[0013] In a second aspect, the present invention provides a multiple control method, which is applied to any one of the controllers described above, and the multiple control method includes:

[0014] Processing the acquired bus data through the processor of each channel to obtain processing results corresponding to each of the channels;

[0015] For each of the channels, the processing results of other channels other than the channel are obtained, and the processing results of the channel are compared and analyzed with the processing results of other channels to determine whether the channel is abnormal.

[0016] Optionally, comparing and analyzing the processing result of the channel with the processing results of other channels to determine whether the channel is abnormal includes:

[0017] When the processing result of the channel is the same as the processing results of other channels, the channel is determined to be normal;

[0018] When the processing result of the channel is different from the processing results of other channels, and the number of other channels with processing results different from the channel is greater than or equal to a first preset number threshold, the channel is determined to be abnormal;

[0019] When the processing result of the channel is different from the processing results of other channels, and the number of other channels with processing results different from the channel is less than the first preset number threshold, the channel is determined to be normal;

[0020] The first preset quantity threshold is smaller than the total quantity of the channels.

[0021] Optionally, each of the channels further comprises a bus module, and the bus modules in each of the channels are respectively communicatively connected with the corresponding processor via a local bus of the corresponding processor; the multiple control method further comprises:

[0022] When the channel is abnormal, the processor controlling the channel does not output the processing result of the channel, or disconnects the power supply of the channel;

[0023] When the channel is normal, the processing result of the channel is output through the bus module.

[0024] Optionally, each of the channels further comprises a bus module, a buffer and a latch, the bus modules in each channel are respectively connected to the corresponding processor through the local bus of the corresponding processor, the input end of the buffer is connected to the external address latch of the corresponding processor, the input end of the latch is respectively connected to the output end of the corresponding buffer and the data interface of the corresponding processor, and the output end of the latch is connected to the data interface of the corresponding bus module; the multiple control method further comprises:

[0025] For each of the channels, when the processor in the channel communicates data with the bus module, the control signal of the external address latch of the processor is delayed by a preset time length through the buffer to obtain a delayed control signal;

[0026] The address part of the data signal between the processor and the bus module is latched by the latch according to the delayed control signal.

[0027] In the multiple control method of the present invention, the processor of each channel first analyzes and processes the received bus data to generate respective processing results. The processing result of the channel is compared with the processing results of other channels to determine whether the channel is abnormal. Based on the multi-channel design in the controller, in the case of a single channel abnormality, the normal operation of other channels can still be guaranteed. In this way, the controller can ensure that only correct and consistent data is output for further processing and execution, thereby improving the stability and safety of the entire system. Therefore, the present invention improves the reliability of the entire system through physical isolation and coupling capacitor connection, and improves the safety of the system through the control output mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of a multiple control system in one embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of inter-channel communication in another embodiment of the present invention;

[0030] Figure 3 A schematic diagram of clock distribution in another embodiment of the present invention;

[0031] Figure 4 It is a flowchart of a multiple control method in another embodiment of the present invention;

[0032] Figure 5 The figure is a schematic structural diagram of an electronic device in another embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0034] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0035] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to"; the term "based on" means "based at least in part on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments"; the term "optionally" means "optional embodiments". The relevant definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc. mentioned in the present invention are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0036] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0037] The names of the messages or information exchanged between multiple devices in the embodiments of the present invention are only used for illustrative purposes, and are not used to limit the scope of these messages or information.

[0038] In the related art, a single-channel design is usually adopted when multiple controllers are used in combination. This means that all data and control signals are transmitted through a single physical path, without redundancy or backup paths. Once this single channel fails, whether due to hardware damage, software errors or external interference, it will cause errors in the operation of the entire control system, resulting in the system's lack of fault tolerance, making the system very vulnerable to abnormal situations. At the same time, due to the single-channel design, once a controller has an abnormality, it is easy to spread to other controllers along a single communication path, thereby affecting the stability of the entire control system. In the field of automated control, especially in critical infrastructure and industrial production, this spread of faults may lead to serious production interruptions or even safety accidents.

[0039] In view of the problems existing in the above-mentioned related technologies, this embodiment provides a controller and a multiple control method.

[0040] Combination Figure 1 As shown, an embodiment of the present invention provides a controller, the controller includes n channels, each of the channels includes a processor, the processor in the i-th channel is connected to the processor in the i+1-th channel through a coupling capacitor, and the processor in the n-th channel is connected to the processor in the first channel through a coupling capacitor, wherein n is greater than or equal to 2; i is greater than or equal to 1, and less than or equal to n-1.

[0041] Specifically, the controller is composed of multiple channels, which are physically isolated from each other but can be connected for communication. This isolation is achieved through coupling capacitors. The coupling capacitors allow signals to be transmitted between channels without causing direct current flow, thereby achieving electrical isolation between channels. While allowing signals to be transmitted between channels, potential current loops are avoided, reducing mutual interference between channels. Each channel has independent processing capabilities. When a single channel fails, other channels can continue to operate. Each channel contains a processor. The processor of the i-th channel is connected to the processor of the i+1-th channel through a coupling capacitor, forming a closed ring structure, wherein the processor of the n-th channel is connected to the processor of the first channel through a coupling capacitor, ensuring the integrity of the ring structure. In a preferred embodiment of the present invention, combined with Figure 2As shown in the schematic diagram of inter-channel communication, the controller can set three channels, namely channel A, channel B and channel C. At the same time, in order to improve the processing performance of the controller, the processor uses the high-performance Feiteng E2000D chip with a main frequency of up to 1.5GHz to design the controller. Among them, E2000D-A, E2000D-B and E2000D-C are the processors of channel A, channel B and channel C respectively, so that the controller has higher computing power and can meet the use requirements of complex environments. The clock and SGMII signals are isolated through coupling capacitors, which not only ensures the normal communication of the processors between the three channels, but also realizes complete isolation between the channels. When any channel fails, it will not affect the other two channels.

[0042] The controller of the present invention provides multiple channels in the controller, wherein each channel is connected by a coupling capacitor, thereby ensuring data transmission and physical isolation. Based on the arrangement of the channels, even if a channel fails, it will not affect the normal operation of other channels, thereby improving the reliability of the entire system. Through the closed ring arrangement, a redundancy mechanism is provided. Even if the processor of a channel fails, data can still be transmitted and processed by the processors of other channels, thereby ensuring the continuous operation and high reliability of the controller.

[0043] Optionally, each of the channels further includes a clock generator, and the clock generator in each channel is respectively connected to the corresponding processor, the clock generator in the i-th channel is also connected to the processor in the i+1-th channel, and the clock generator in the n-th channel is also connected to the processor in the first channel.

[0044] Specifically, each channel also includes a clock generator. The clock generator in each channel is connected to the corresponding processor respectively. The clock generator in the ith channel is also connected to the processor in the i+1th channel, and the clock generator in the nth channel is also connected to the processor in the first channel. The clock generator of the ith channel is connected to the processor of the i+1th channel, forming a ring clock link. This design means that the clock signal can be transmitted between channels, thereby achieving clock synchronization of all processors in the entire controller. The clock generator of each channel can be independently configured and adjusted, providing the system with flexible clock management capabilities. In a preferred embodiment of the present invention, combined with Figure 3As shown, clock-A, clock-B and clock-C are the clock generators of channel A, channel B and channel C respectively. The clock generators provide 100MHz clocks for the two channels respectively. Among them, the clock generator of channel A provides clocks for the SGMII interfaces of channel A and channel B to achieve the homology function; the clock generator of channel B provides clocks for channel B and channel C; the clock generator of channel C provides clocks for channel C and channel A.

[0045] In this optional embodiment, through the ring clock link, even if the clock generator of a channel fails, the clock signals of other channels can continue to maintain the synchronization of the system, so it will not affect the operation of the entire system, thereby improving the stability and reliability of the system.

[0046] Optionally, a coupling capacitor is connected in series between the clock generator in the ith channel and the processor in the (i+1)th channel, and a coupling capacitor is connected in series between the clock generator in the nth channel and the processor in the first channel.

[0047] Specifically, the connection between the clock generator and the processor is realized through a coupling capacitor, and the above design is applied between the clock generator of the i-th channel and the processor of the i+1-th channel, and between the clock generator of the n-th channel and the processor of the first channel. The clock signal transmitted through the coupling capacitor maintains its integrity, ensuring that the processor can receive an accurate clock signal, thereby ensuring the synchronization of data processing.

[0048] In this optional embodiment, the clock generator of each channel is connected to the processor of the adjacent channel through a coupling capacitor, ensuring that data transmission is physically isolated at the same time, and the clock generator provides a clock for the channel and other adjacent channels to ensure that the data received by each channel is of the same source.

[0049] Optionally, each of the channels further includes a bus module, and the bus module in each of the channels is communicatively connected to the corresponding processor via a local bus of the corresponding processor.

[0050] Specifically, each channel integrates a bus module, which communicates with the processor through the local bus of each processor, thereby allowing each channel to independently process data from its bus module without going through the central processor or other channels, thereby improving the efficiency and speed of data processing.

[0051] In this optional embodiment, by providing a bus module in each channel, each channel can be independently upgraded or replaced without affecting the operation of other channels. This design improves the flexibility of the system.

[0052] Optionally, each of the channels further includes a buffer and a latch, the input end of the buffer is connected to the external address latch of the corresponding processor, the input end of the latch is respectively connected to the output end of the corresponding buffer and the data interface of the corresponding processor, and the output end of the latch is connected to the data interface of the corresponding bus module.

[0053] Specifically, each channel design includes a buffer and a latch, and this arrangement is to optimize the data communication between the processor and the bus module. Specifically, the input end of the buffer is connected to the external address latch of the processor, so that the address signal sent by the processor can be temporarily stored by the buffer, thereby providing a stable signal source for subsequent latching operations. The input end of the latch is simultaneously connected to the output end of the buffer and the data interface of the processor, which means that the latch can receive the address signal processed by the buffer and the data signal of the processor, and then latch these signals at the appropriate time. The output end of the latch is connected to the data interface of the bus module, ensuring that the latched data can be accurately transmitted to the bus module, completing the closed loop of data communication.

[0054] In this optional embodiment, by using a buffer and a latch, the data communication problem between the processor and the bus module caused by timing mismatch can be effectively solved, thereby improving the accuracy and reliability of data transmission.

[0055] Optionally, each of the channels further includes a power supply module, and the power supply modules in each of the channels are electrically connected to the corresponding processors respectively.

[0056] Specifically, each channel integrates independent power modules, which are electrically connected to the processors in their respective channels. The processors in each channel have their own dedicated power supply, which ensures the stable operation and performance of the processors. The power modules provide the processors with the necessary power to support them in performing data processing, logical operations, and control tasks. In addition, this independent power configuration also helps to improve the reliability and safety of the system. If there is a problem with the power module of a channel, it will not affect the operation of other channels because the power supply of each channel is isolated.

[0057] In this optional embodiment, by separately providing a power supply module in each channel, each channel can be controlled individually, thereby optimizing the operating energy efficiency of the entire controller. When an abnormality occurs in a channel, it can be shut down through the power supply module without affecting other channels.

[0058] Combination Figure 4 As shown, an embodiment of the present invention also provides a multiple control method, which is applied to any of the controllers described above, and the multiple control method includes:

[0059] The acquired bus data is processed by the processor of each channel to obtain processing results corresponding to each of the channels.

[0060] Specifically, when the processor receives the bus data acquired by the bus module, the processor processes the data according to a preset algorithm or program, wherein the processing steps include operations such as data analysis, calculation, and logical judgment.

[0061] For each of the channels, processing results of other channels other than the channel are obtained.

[0062] Specifically, when the processor of a channel completes data processing and obtains a result, it will not make a decision based on this result alone, but will actively obtain the processing results of other channels. This step reflects the redundancy and mutual inspection capability of the system design, and is an important link to ensure the stability of the entire control system. In a preferred embodiment of the present invention, in a three-channel system, the processor of channel A completes data processing, and at this time, the processors of channel B and channel C will be requested to send the processing results of their respective channels.

[0063] Compare and analyze the processing result of the channel with the processing results of other channels to determine whether the channel is abnormal.

[0064] Specifically, when the processor of a channel completes data processing and obtains a result, it will compare and analyze the result with the results of other channels to determine whether there is a channel abnormality. In a preferred embodiment of the present invention, in a three-channel system, the processor of channel A compares and analyzes these results to check whether there are significant differences or inconsistencies, so as to determine whether there is an abnormality in any channel. If it is found that the processing result of a channel is significantly different from that of other channels, the system can determine that the channel may have an abnormality, such as a hardware failure or a data processing error.

[0065] In the multiple control method of the present invention, the processor of each channel first analyzes and processes the received bus data to generate respective processing results. The processing result of the channel is compared with the processing results of other channels to determine whether the channel is abnormal. Based on the multi-channel design in the controller, in the case of a single channel abnormality, the normal operation of other channels can still be guaranteed. In this way, the controller can ensure that only correct and consistent data is output for further processing and execution, thereby improving the stability and safety of the entire system. Therefore, the present invention improves the reliability of the entire system through physical isolation and coupling capacitor connection, and improves the safety of the system through the control output mechanism.

[0066] Optionally, comparing and analyzing the processing result of the channel with the processing results of other channels to determine whether the channel is abnormal includes:

[0067] When the processing result of the channel is the same as the processing results of other channels, the channel is determined to be normal;

[0068] When the processing result of the channel is different from the processing results of other channels, and the number of other channels with processing results different from the channel is greater than or equal to a first preset number threshold, the channel is determined to be abnormal;

[0069] When the processing result of the channel is different from the processing results of other channels, and the number of other channels with processing results different from the channel is less than the first preset number threshold, the channel is determined to be normal;

[0070] The first preset quantity threshold is smaller than the total quantity of the channels.

[0071] Specifically, when the processor of a channel completes data processing and obtains a result, it will compare and analyze this result with the results of other channels to determine whether there is a channel abnormality. In a preferred embodiment of the present invention, the first preset quantity threshold is set to 1. In a three-channel system, if the processor of channel A finds that its processing result is inconsistent with the results of channels B and C, the processor of channel A will determine that channel A is abnormal. If the processor of channel A finds that its processing result is inconsistent with the results of channels B or C, the processor of channel A will determine that channel A is normal. This determination mechanism based on quantity threshold enables the system to accurately identify abnormal channels when most channels are consistent.

[0072] In this optional embodiment, by setting a preset quantity threshold, the system can accurately identify abnormal channels when most channels are consistent, thereby avoiding the performance of the entire system being affected by the abnormality of a single channel, which not only enhances the stability of the system, but also improves the efficiency of fault handling.

[0073] Optionally, each of the channels further comprises a bus module, and the bus modules in each of the channels are respectively communicatively connected with the corresponding processor via a local bus of the corresponding processor; the multiple control method further comprises:

[0074] When the channel is abnormal, the processor controlling the channel does not output the processing result of the channel, or disconnects the power supply of the channel;

[0075] When the channel is normal, the processing result of the channel is output through the bus module.

[0076] Specifically, each channel is equipped with an independent bus module, which communicates with the processor through the local bus of each processor. In the multi-control method, when a channel is detected to be abnormal, the system will take corresponding measures, such as controlling the processor of the channel not to output the processing result or directly disconnecting the power supply of the channel, thereby preventing the abnormal situation from spreading to the entire control system. At the same time, it can still continue to operate through other normally working channels, improving the robustness and reliability of the system.

[0077] In this optional embodiment, by independently controlling the processor and power supply of each channel, the system can respond quickly when an abnormality is detected, prevent the spread of faults, ensure the stable operation of the entire control system, reduce the risk of system downtime due to single channel failure, and improve production efficiency.

[0078] Optionally, each of the channels further comprises a bus module, a buffer and a latch, the bus modules in each channel are respectively connected to the corresponding processor through the local bus of the corresponding processor, the input end of the buffer is connected to the external address latch of the corresponding processor, the input end of the latch is respectively connected to the output end of the corresponding buffer and the data interface of the corresponding processor, and the output end of the latch is connected to the data interface of the corresponding bus module; the multiple control method further comprises:

[0079] For each of the channels, when the processor in the channel communicates data with the bus module, the control signal of the external address latch of the processor is delayed by a preset time length through the buffer to obtain a delayed control signal;

[0080] The address part of the data signal between the processor and the bus module is latched by the latch according to the delayed control signal.

[0081] Specifically, the design of each channel includes a bus module, a buffer, and a latch, which work together to achieve effective communication between the processor and the bus module. Among them, the processor in each channel communicates with the bus module through the local bus, ensuring the directness and efficiency of data transmission. In this process, the buffer delays the control signal of the processor's external address latch for a preset time to ensure that the timing of the control signal and the data signal can match and meet the working requirements of the latch. Subsequently, the latch uses this delayed control signal to latch the address part of the data signal transmitted between the processor and the bus module, ensuring the accuracy of data transmission.

[0082] In this optional embodiment, the control signal of the processor's external address latch is delayed by a buffer to ensure that the timing of the control signal matches the data signal, so that the latch can accurately latch the address information, reduce errors and conflicts during data transmission, and improve the stability and reliability of the entire system.

[0083] Combination Figure 5 As shown, an electronic device 500 provided by an embodiment of the present invention includes a memory 510 and a processor 520; the memory 510 is used to store a computer program; the processor 520 is used to implement the multiple control methods described above when executing the computer program.

[0084] In other words, an electronic device 500 includes a memory 510 and a processor 520 coupled to the memory 510; the memory 510 is configured to store a computer program; and the processor 520 is configured to perform the following operations when executing the computer program:

[0085] Processing the acquired bus data through the processor of each channel to obtain processing results corresponding to each of the channels;

[0086] For each of the channels, the processing results of other channels other than the channel are obtained, and the processing results of the channel are compared and analyzed with the processing results of other channels to determine whether the channel is abnormal.

[0087] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the multiple control method described above is implemented.

[0088] In other words, a non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor performs the following operations:

[0089] Processing the acquired bus data through the processor of each channel to obtain processing results corresponding to each of the channels;

[0090] For each of the channels, the processing results of other channels other than the channel are obtained, and the processing results of the channel are compared and analyzed with the processing results of other channels to determine whether the channel is abnormal.

[0091] An electronic device 500 that can be used as a server or client of the present invention will now be described, which is an example of a hardware device that can be applied to various aspects of the present invention. The electronic device 500 is intended to represent various forms of digital electronic computer equipment, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 500 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present invention described and / or required herein.

[0092] The electronic device 500 includes a computing unit, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) or a computer program loaded from a storage unit into a random access memory (RAM). In the RAM, various programs and data required for the operation of the device can also be stored. The computing unit, ROM, and RAM are connected to each other via a bus. An input / output (I / O) interface is also connected to the bus.

[0093] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. In the present application, the unit described as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or it may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment of the present invention. In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0094] Although the present invention is disclosed as above, the protection scope of the present invention is not limited thereto. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications will fall within the protection scope of the present invention.

Claims

1. A controller, characterized in that: The controller includes n channels, each of which includes a processor, the processor in the i-th channel is connected to the processor in the i+1-th channel via a coupling capacitor, and the processor in the n-th channel is connected to the processor in the first channel via a coupling capacitor, wherein n is greater than or equal to 2; i is greater than or equal to 1, and less than or equal to n-1.

2. The controller according to claim 1, characterized in that: Each of the channels also includes a clock generator. The clock generator in each channel is connected to the corresponding processor respectively. The clock generator in the i-th channel is also connected to the processor in the i+1-th channel, and the clock generator in the n-th channel is also connected to the processor in the first channel.

3. The controller according to claim 2, characterized in that: A coupling capacitor is connected in series between the clock generator in the ith channel and the processor in the (i+1)th channel, and a coupling capacitor is connected in series between the clock generator in the nth channel and the processor in the first channel.

4. The controller according to claim 1, characterized in that: Each of the channels further includes a bus module, and the bus module in each of the channels is communicatively connected to the corresponding processor via a local bus of the corresponding processor.

5. The controller according to claim 4, characterized in that: Each of the channels also includes a buffer and a latch, the input end of the buffer is connected to the external address latch of the corresponding processor, the input end of the latch is respectively connected to the output end of the corresponding buffer and the data interface of the corresponding processor, and the output end of the latch is connected to the data interface of the corresponding bus module.

6. The controller according to claim 1, characterized in that: Each of the channels further includes a power supply module, and the power supply modules in each of the channels are electrically connected to the corresponding processors respectively.

7. A multiple control method, characterized in that: Applied to the controller according to any one of claims 1 to 6, the multiple control method comprises: Processing the acquired bus data through the processor of each channel to obtain processing results corresponding to each of the channels; For each of the channels, the processing results of other channels other than the channel are obtained, and the processing results of the channel are compared and analyzed with the processing results of other channels to determine whether the channel is abnormal.

8. The multiple control method according to claim 7, characterized in that: The comparing and analyzing the processing result of the channel with the processing results of other channels to determine whether the channel is abnormal includes: When the processing result of the channel is the same as the processing results of other channels, the channel is determined to be normal; When the processing result of the channel is different from the processing results of other channels, and the number of other channels with processing results different from the channel is greater than or equal to a first preset number threshold, the channel is determined to be abnormal; When the processing result of the channel is different from the processing results of other channels, and the number of other channels with processing results different from the channel is less than the first preset number threshold, the channel is determined to be normal; The first preset quantity threshold is smaller than the total quantity of the channels.

9. The multiple control method according to claim 7, characterized in that: Each of the channels further comprises a bus module, and the bus module in each of the channels is communicatively connected with the corresponding processor via a local bus of the corresponding processor; The multiple control method further comprises: When the channel is abnormal, the processor controlling the channel does not output the processing result of the channel, or disconnects the power supply of the channel; When the channel is normal, the processing result of the channel is output through the bus module.

10. The multiple control method according to claim 7, characterized in that: Each of the channels further comprises a bus module, a buffer and a latch, wherein the bus module in each channel is respectively connected to the corresponding processor through the local bus of the corresponding processor, the input end of the buffer is connected to the external address latch of the corresponding processor, the input end of the latch is respectively connected to the output end of the corresponding buffer and the data interface of the corresponding processor, and the output end of the latch is connected to the data interface of the corresponding bus module; The multiple control method further comprises: For each of the channels, when the processor in the channel communicates data with the bus module, the control signal of the external address latch of the processor is delayed by a preset time length through the buffer to obtain a delayed control signal; The address part of the data signal between the processor and the bus module is latched by the latch according to the delayed control signal.

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