DMA processor and data processing system

Abstract

The invention provides a DMA processor and a data processing system. The DMA processor comprises an APB control module and a function module. The function module comprises a selection module and a sub-function module; the sub-function module comprises a data search module, a data XOR module, a data comparison module and an AXI read-write module; the APB control module receives a data processing task issued by the CPU, analyzes the data processing task, generates task parameters and sends the task parameters to the function module; the selection module is used for sending the task parameters to the corresponding sub-function modules according to task types in the task parameters; and the sub-function module receives AXI return data and returns an operation result to the CPU. The APB is used for controlling DMA operation, the memory is accessed through the AXI interface, the functions of data migration, data filling, data searching, data XOR and data comparison are achieved, the data processing speed of a CPU is increased, cost is low, and the functions are powerful.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a DMA processor and a data processing system. Background Art

[0002] In SOC system design, in order to save CPU resources, DMA direct memory access is usually used to achieve high-speed data transmission between external devices and memory or between memory and memory. The existing DMA technical solutions only involve data movement or filling, and the corresponding IP is expensive, which increases the difficulty of project implementation in terms of functionality and economy. Summary of the invention

[0003] The purpose of this application is to provide a DMA processor and a data processing system, which uses APB to control DMA operations and accesses memory through an AXI interface; the AXI read and write module supports parameterized configuration of the interface bit width on the master side and the slave side; in addition to the traditional data movement function, data search, data XOR, and data comparison functions are added, which further speeds up the data processing speed of the CPU, with low cost and powerful functions.

[0004] In the first aspect, the present application provides a DMA processor, which includes: an APB control module and a functional module; the functional module includes: a selection module and a sub-functional module; the sub-functional module includes: a data search module, a data XOR module, a data comparison module, an AXI read module, and an AXI write module; the selection module is respectively connected to the APB control module, the data search module, the data XOR module, and the data comparison module; each of the selection module, the APB control module, the data search module, the data XOR module, and the data comparison module is respectively connected to the AXI read module and the AXI write module; the APB control module receives the data processing task issued by the CPU, parses the data processing task, generates task parameters and sends them to the functional module; the selection module in the functional module sends the task parameters to the corresponding sub-functional module according to the task type in the task parameters; the sub-functional module receives the AXI return data, performs corresponding operations, and returns the operation results to the CPU.

[0005] Furthermore, the selection module in the above-mentioned functional module performs the following steps: if the task type is a data movement type, the task parameters are sent to the AXI read module and the AXI write module to access the external device through the AXI read module and the AXI write module; if the task type is a data filling type, the task parameters are sent to the AXI write module to write data; if the task type is a target type, the task parameters are sent to the target sub-module corresponding to the target type, so that the target sub-module splits the task parameters into multiple AXI task data packets and sends them to the AXI read module or the AXI write module; wherein the target type includes: a data search type, a data XOR type or a data comparison type; the target sub-modules corresponding to the target type include: a data search module, a data XOR module or a data comparison module.

[0006] Furthermore, if the task type is a data movement type, after the AXI read module processes the read data returned on the bus, it stores the read data in the read control queue, then reads the data in the read control queue and sends it to the external device, and after the external device returns the last burst write response signal, the AXI write module returns a task end signal to the CPU; if the task type is a data filling type, after the AXI write module writes the CPU-specified data to the specified address range, after the external device returns the last burst write response signal, the AXI write module returns a task end signal to the CPU; if the task type is a target type, after the AXI read module processes the read data returned on the bus, it stores the read data in the read control queue, and the target submodule corresponding to the target type reads the data in the read control queue and calculates, and feeds the calculation result back to the APB control module through the selection module, so as to be returned to the CPU through the APB interface.

[0007] Furthermore, the AXI read module includes: a read control module, a read data module and a read bit width conversion module; the read control module is used to receive the AXI task parameters carrying the starting access address, the access data volume, and the task start indication signal, generate an AXI read control channel signal to access the external device, and store the offset of the starting access address, the cross-4k boundary indication signal, and the last burst indication signal in the read control queue to achieve non-aligned access, cross-4k boundary processing, and generate a completion signal; the read data module is used to receive the AXI return data and read the control signal required for processing the burst data from the read control queue. The control information is obtained, the invalid data caused by the first address offset is removed, and the data to be converted with the same width as the slave side is generated and sent to the read bit width conversion module; the read bit width conversion module is used to split the data to be converted and store them in the cache when it is judged that the slave side width is greater than the master side width, so that the master side reads the master side width data in the cache as output each time until the cache is empty and then rewrites the data; if the slave side data is less than the master side width, multiple data to be converted are spliced ​​into one master side width data and stored in the cache to wait for the master side to read.

[0008] Furthermore, the above-mentioned AXI write module includes: a write control module, a write data module and a write bit width conversion module; the write bit width conversion module is used to receive the data to be written, and when it is determined that the master side bit width is greater than the slave side bit width, the data to be written is split and stored in the cache, and the write data module reads one slave side bit width data each time. If the master side bit width is less than the slave side bit width, multiple data to be written are spliced ​​into slave side bit width data and stored in the cache to wait for the write data module to read; the write data module is used to read the burst data, read the control information required for processing the burst data from the write control queue of the write control module, add the invalid signal of the first address offset, generate a byte indication signal, and access the memory or external device through the write data channel.

[0009] Furthermore, the above-mentioned APB control module is used to receive the data processing tasks issued by the CPU through the APB bus, decode the data processing tasks, obtain task parameters, and send the task parameters to the functional module; the APB control module is also used to receive the task result information returned by the functional module, decode the task result information, generate an APB signal and feed it back to the CPU; the task result information includes: task end signal, search result of the search function, calculation result of the comparison function, and AXI read and write error information.

[0010] Furthermore, the above functional module also includes: an interrupt control module; the interrupt control module is used to handle interrupts in the following two situations: the APB signal configuration interrupt register, the AXI protocol error indication signal and the data transmission error signal are valid.

[0011] Furthermore, when the interrupt register is valid, if the AXI read module or the AXI write module has not sent the control information at this time, it will be interrupted immediately; if the AXI read module or the AXI write module has sent the control information at this time, it will wait until the bus access is completed based on the control information before interrupting.

[0012] Furthermore, when the error indication signal and the data transmission error signal of the AXI protocol are valid, the interrupt control module generates an interrupt enable signal to interrupt the current task and report an error to the CPU through the APB bus.

[0013] In a second aspect, the present application further provides a data processing system, the system comprising: a CPU and the DMA processor described in the first aspect.

[0014] In the DMA processor and data processing system provided by the present application, the DMA processor includes: an APB control module and a functional module; the functional module includes: a selection module and a sub-functional module; the sub-functional module includes: a data search module, a data XOR module, a data comparison module, an AXI read module, and an AXI write module; the selection module is respectively connected to the APB control module, the data search module, the data XOR module, and the data comparison module; each module in the selection module, the APB control module, the data search module, the data XOR module, and the data comparison module is respectively connected to the AXI read module and the AXI write module; the APB control module receives the data processing task issued by the CPU, parses the data processing task, generates task parameters and sends them to the functional module; the selection module in the functional module sends the task parameters to the corresponding sub-functional module according to the task type in the task parameters; the sub-functional module receives the AXI return data, performs corresponding operations, and returns the operation results to the CPU. The above-mentioned DMA processor controls DMA operations through APB and accesses memory through the AXI interface; the AXI read and write module supports parameterized configuration of the interface bit width on the master side and the slave side; in addition to the traditional data movement function, it also adds data search, data XOR, and data comparison functions, further accelerating the CPU's data processing speed, with low cost and powerful functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 A schematic diagram of a DMA transmission principle provided in an embodiment of the present application;

[0017] Figure 2 A structural block diagram of a DMA processor provided in an embodiment of the present application;

[0018] Figure 3 A structural block diagram of an AXI read module in a DMA processor provided in an embodiment of the present application;

[0019] Figure 4 A structural block diagram of an AXI write module in a DMA processor provided in an embodiment of the present application;

[0020] Figure 5 A schematic diagram of a task start data processing process of a DMA processor provided in an embodiment of the present application;

[0021] Figure 6 A schematic diagram of a task end data processing process of a DMA processor provided in an embodiment of the present application;

[0022] Figure 7 A flowchart of three data processing processes provided in an embodiment of the present application;

[0023] Figure 8 A structural block diagram of a data processing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0025] DMA transmission principle is as follows Figure 1As shown in the figure, a complete DMA transfer includes four steps: DMA request, DMA response, DMA transfer and DMA end. First, the CPU sends a read / write request to the DMA controller through the bus; then, if the DMA controller is in an idle state, it will respond to the bus request and receive parameters such as the source address, target address, transfer data, and transfer data volume; then, the DMA controller starts the data transfer and accesses the I / O or memory through the bus; finally, when all the data has been transferred, it sends a DMA end signal to the CPU and returns the bus control. The existing DMA technical solutions only involve the movement or filling of data, and the corresponding IP is expensive, which will increase the difficulty of project implementation in terms of functionality and economy.

[0026] Based on this, an embodiment of the present application provides a DMA processor and a data processing system, which uses APB to control DMA operations and accesses memory through an AXI interface; the AXI read and write module supports parameterized configuration of the interface bit width on the master side and the slave side; in addition to the traditional data movement function, data search, data XOR, and data comparison functions are added, which further speeds up the data processing speed of the CPU, with low cost and powerful functions.

[0027] To facilitate understanding of this embodiment, a DMA processor disclosed in an embodiment of the present application is first introduced in detail.

[0028] Figure 2 A schematic diagram of a DMA processor provided for an embodiment of the present application, the DMA processor includes: an APB control module 1 and a functional module 2; the functional module 2 includes: a selection module 21 and a sub-functional module 22; the sub-functional module 22 includes: a data search module 221, a data XOR module 222, a data comparison module 223, an AXI read module 224, and an AXI write module 225; the selection module 21 is respectively connected to the APB control module 1, the data search module 221, the data XOR module 222, and the data comparison module 223; each of the selection module 21, the APB control module 1, the data search module 221, the data XOR module 222, and the data comparison module 223 is respectively connected to the AXI read module 224 and the AXI write module 225.

[0029] The above-mentioned APB control module 1 receives the data processing task issued by the CPU, parses the data processing task, generates task parameters and sends them to the functional module 2; the selection module 21 in the functional module 2 sends the task parameters to the corresponding sub-functional module 22 according to the task type in the task parameters; the sub-functional module 22 receives the AXI return data, performs corresponding operations, and returns the operation results to the CPU.

[0030] The specific implementation process of the above modules is described in detail below:

[0031] See also Figure 3 As shown, the AXI read module 224 includes: a read control module 2241 , a read data module 2242 and a read bit width conversion module 2243 .

[0032] The read control module 2241 is used to receive the AXI task parameters carrying the starting access address, the access data amount, and the task start indication signal, generate the AXI read control channel signal to access the external device, and store the offset of the starting access address, the cross-4k boundary indication signal, and the last burst indication signal in the read control queue to implement non-aligned access, cross-4k boundary processing, and generate a completion signal;

[0033] The above-mentioned cross-4k boundary indication signal: Because the AXI protocol stipulates that a burst cannot cross the 4k boundary address, when a burst crosses the 4k address boundary, the burst must be divided into two small bursts, one accessing the previous 4k memory block and the other accessing the next 4k memory block. The cross-4k boundary indication signal is used to indicate whether it crosses the 4k boundary.

[0034] The data reading module 2242 is used to receive the AXI return data, read the control information required for processing the burst data from the read control queue, remove the invalid data caused by the first address offset, generate the data to be converted with the same width as the slave side, and send it to the read bit width conversion module;

[0035] The read bit width conversion module 2243 is used to split the data to be converted and store it in the cache when it is determined that the bit width on the slave side is greater than the bit width on the master side, so that the master side reads the master side bit width data in the cache as output each time, and rewrites the data after the cache is empty; for example, if the slave side is 1024 bits and the master side bit width is 256 bits, the 1024-bit data processed by the slave side will be stored in the shift register first, and the master side reads 256 bits each time, and the register is shifted right by 256 bits. If the slave side data is smaller than the master side bit width, multiple data to be converted will be spliced ​​into one master side bit width data and stored in the cache to wait for the master side to read.

[0036] See also Figure 4 As shown, the AXI write module 225 includes: a write control module 2251 , a write data module 2252 and a write bit width conversion module 2253 .

[0037] The write bit width conversion module 2251 is used to receive the data to be written. When it is determined that the bit width on the master side is greater than the bit width on the slave side, the data to be written is split and stored in the cache. The write data module reads one bit width data on the slave side as output each time. For example, if the bit width on the master side is 1024 bits and the bit width on the slave side is 256 bits, the 1024 bits of data on the MST side will be stored in the shift register first. The slave side reads 256 bits each time and the register is shifted right by 256 bits. If the bit width on the master side is less than the bit width on the slave side, multiple data to be written are spliced ​​into the bit width data on the slave side and stored in the cache to wait for the write data module 2252 to read.

[0038] The write data module 2252 is used to read the control information required for processing the burst data from the write control queue of the write control module 2253 after reading the burst data, add the invalid signal of the first address offset, generate a byte indication signal, and access the memory or external device through the write data channel.

[0039] In this embodiment, the master side refers to the side of the AXI read / write module connected to the CPU, and the slave side refers to the side of the AXI read / write module connected to an external device (such as a memory).

[0040] Further, the working mode of the APB control module is described as follows:

[0041] The above-mentioned APB control module 1 is used to receive the data processing task sent by the CPU through the APB bus, decode the data processing task, obtain the task parameters, and send the task parameters to the functional module 2; the APB control module 1 is also used to receive the task result information returned by the functional module 2, and decode the task result information to generate an APB signal to feed back to the CPU; the task result information includes: task end signal, search result of the search function, calculation result of the comparison function, and AXI read and write error information.

[0042] See also Figure 5 As shown in the figure, the processing of APB signals is completed by the control module. When the task starts, the CPU sends the task parameters through the APB bus. After APB decoding, the task start address, task data volume, task type and other parameters are obtained, and then packaged and sent to the functional module. Figure 6 As shown, when the task is completed, the functional module returns the task completion signal, the search result of the search function, the calculation result of the comparison function, and the AXI read and write error information to the control module, and generates an APB signal through APB decoding to feed back to the CPU.

[0043] Combine the following Figure 5 and Figure 6Describe the overall DMA processor workflow:

[0044] The working order is:

[0045] ①. The CPU sends the task parameters through the APB interface. The control module receives the APB signal and parses it into a task parameter package, which contains information such as the task type, starting address, ending address, task data volume, task start signal, and specific value of the search function. Then it will determine whether the starting address, ending address, and task data volume exceed the upper and lower boundaries specified by the CPU. If they exceed the boundaries, an error will be reported to the CPU through the APB port, requesting the task parameters to be resent; otherwise, if the parameters meet the specifications, they will be passed to the functional module.

[0046] ②. The functional module receives the task data packet and sends it to the corresponding functional module through the parameter selection module.

[0047] Specifically, the selection module in the above functional modules performs the following steps:

[0048] If the task type is a data movement type, the task parameters are sent to the AXI read module and the AXI write module to access the external device through the AXI read module and the AXI write module;

[0049] If the task type is data filling type, the task parameters are sent to the AXI write module for data writing;

[0050] If the task type is a target type, the task parameters are sent to the target submodule corresponding to the target type, so that the target submodule splits the task parameters into multiple AXI task data packets and sends them to the AXI read module or the AXI write module; wherein the target type includes: data search type, data XOR type or data comparison type; the target submodules corresponding to the target type include: data search module, data XOR module or data comparison module.

[0051] That includes the following three situations:

[0052] A. For the data movement function, the task parameters are sent directly to the AXI read / write module, and then the DMA processor sends AXI read / write control commands to access the external device.

[0053] B. For the data filling function, send the task parameters to the AXI write module.

[0054] C. For data search, data comparison or data XOR functions, the task parameters will be sent to the data search module, data comparison module or data XOR module first, the task parameters will be split into multiple AXI task data packets, and then these AXI task data packets will be sent to the AXI read module or AXI write module.

[0055] The function module receives the AXI return data and performs the corresponding operations:

[0056] Specifically, if the task type is data movement type, after the AXI read module processes the read data returned on the bus, it stores the read data in the read control queue, then reads the data in the read control queue and sends it to the external device. After the external device returns the last burst write response signal, the AXI write module returns a task end signal to the CPU;

[0057] If the task type is data filling type, after the AXI write module writes the CPU specified data to the specified address range, the AXI write module returns a task end signal to the CPU after the external device returns the last burst write response signal;

[0058] If the task type is a target type, after the AXI read module processes the read data returned on the bus, it stores the read data in the read control queue. The target submodule corresponding to the target type reads the data in the read control queue and calculates, and feeds the calculation result back to the APB control module through the selection module, so as to be returned to the CPU through the APB interface.

[0059] That includes the following three situations:

[0060] A. For the data movement function, after the AXI read module processes the read data returned on the bus, it stores it in the read control queue and then sends it to the external device through the AXI write module. The task ends when the external device returns the last burst write response signal.

[0061] B. For the data filling function, the task ends after the external device returns the write response of the last burst.

[0062] C. For data search, data comparison or data XOR functions, after receiving the data processed by the AXI read module, the data search module, data comparison module or data XOR module calculates the read data, and then feeds back the calculation result to the control module through the result selection, and finally returns the result to the CPU through the APB interface.

[0063] The data calculation process is described below:

[0064] The operation of AXI read return data is implemented through the data search module, data XOR module, and data comparison module. The search module can search for specific values, maximum and minimum values, the first number greater than a specific value, and the first number less than a specific value within the specified address range, and can return the address of the number to the CPU; the XOR module can XOR two blocks of address space data of the same size, and then write the result to one of the addresses; the data comparison module can compare the number of data from bit1 to bit0, or bit0 to bit1 in two blocks of address space of the same size, and return the result to the CPU. The data flow from the APB port to the AXI port and the data flow from the AXI port to the APB port are as follows: Figure 5 and Figure 6 shown.

[0065] For the data movement and data filling functions, since only AXI reading and writing are involved, the task parameters are directly sent to the AXI read-write module, and the AXI read-write module continuously accesses external devices through AXI to realize data movement and filling.

[0066] For data search, XOR, and comparison functions, since the returned data will be calculated between AXI read and write accesses, the workflow is as follows: Figure 7 shown.

[0067] The interruption scheme is described below:

[0068] The above functional modules also include: an interrupt control module; an interrupt control module, which is used to handle interrupts in the following two situations: the APB signal configuration interrupt register, the error indication signal (AXI_rresp) of the AXI protocol, and the data transmission error signal (AXI_bresp) are valid. When the interrupt register is valid, if the AXI read module or the AXI write module has not sent the control information at this time, it will be interrupted immediately; if the AXI read module or the AXI write module has sent the control information at this time, it will wait until the bus access is completed based on the control information before interrupting. When the error indication signal and the data transmission error signal of the AXI protocol are valid, the interrupt control module generates an interrupt enable signal to interrupt the current task and report the error to the CPU through the APB bus.

[0069] The DMA processor provided in the embodiment of the present application mainly realizes the decoding and encoding of the master-side APB signal, the generation of the slave-side AXI signal, the operation and processing of the AXI return data, and the interrupt processing. The generation of the slave-side AXI signal is the basis of communication, which is mainly realized by the AXI read module and the AXI write module. Compared with the traditional solution, on the basis of data movement and filling, data search, data XOR and data comparison functions are added, and the bit width parameterization configuration of the master side and the slave side of the AXI module is supported.

[0070] Based on the above DMA processor, the present application embodiment also provides a data processing system, see Figure 8 As shown, the system includes: a CPU 82 and the DMA processor 84 described in the above embodiment, and the CPU 82 is connected to the APB control module 842 in the DMA processor 84.

[0071] The data processing system provided in the embodiment of the present application has the same implementation principle and technical effects as those of the aforementioned DMA processor embodiment. For the sake of brief description, for matters not mentioned in the embodiment of the data processing system, reference may be made to the corresponding contents in the aforementioned DMA processor embodiment.

[0072] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0073] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A DMA processor, characterized in that: The DMA processor comprises: an APB control module and a functional module; the functional module comprises: a selection module and a sub-functional module; the sub-functional module comprises: a data search module, a data XOR module, a data comparison module, an AXI read module, and an AXI write module; the selection module is respectively connected to the APB control module, the data search module, the data XOR module, and the data comparison module; each of the selection module, the APB control module, the data search module, the data XOR module, and the data comparison module is respectively connected to the AXI read module and the AXI write module; The APB control module receives the data processing task sent by the CPU, analyzes the data processing task, generates task parameters and sends them to the functional module; The selection module in the functional module sends the task parameters to the corresponding sub-functional module according to the task type in the task parameters; The sub-function module receives the AXI return data, performs corresponding operations, and returns the operation results to the CPU.

2. The DMA processor according to claim 1, characterized in that: The selection module in the functional module performs the following steps: If the task type is a data movement type, sending the task parameters to the AXI read module and the AXI write module, so as to access an external device through the AXI read module and the AXI write module; If the task type is a data filling type, sending the task parameters to the AXI write module to write data; If the task type is a target type, sending the task parameters to a target submodule corresponding to the target type, so that the target submodule splits the task parameters into multiple AXI task data packets and sends them to an AXI read module or an AXI write module; Among them, the target type includes: data search type, data XOR type or data comparison type; the target sub-module corresponding to the target type includes: the data search module, the data XOR module or the data comparison module.

3. The DMA processor according to claim 2, characterized in that: If the task type is a data movement type, after the AXI read module processes the read data returned on the bus, it stores the read data in a read control queue, then reads the data in the read control queue and sends it to the external device, and after the external device returns the last burst write response signal, the AXI write module returns a task end signal to the CPU; If the task type is a data filling type, after the AXI write module writes the CPU specified data into the specified address range, after the external device returns the last burst write response signal, the AXI write module returns a task end signal to the CPU; If the task type is a target type, after the AXI read module processes the read data returned on the bus, it stores the read data in a read control queue. The target submodule corresponding to the target type reads the data in the read control queue and calculates, and feeds the calculation result back to the APB control module through the selection module, so as to be returned to the CPU through the APB interface.

4. The DMA processor according to claim 1, characterized in that: The AXI read module includes: a read control module, a read data module and a read bit width conversion module; The read control module is used to receive AXI task parameters carrying a starting access address, access data volume, and a task start indication signal, generate an AXI read control channel signal to access an external device, and store the offset of the starting access address, the cross-4k boundary indication signal, and the last burst indication signal in the read control queue to implement non-aligned access, cross-4k boundary processing, and generate a completion signal; The data reading module is used to receive the AXI return data, read the control information required for processing the burst data from the read control queue, remove the invalid data caused by the first address offset, generate the data to be converted with the same width as the slave side, and send it to the read bit width conversion module; The read bit width conversion module is used to split the data to be converted and store them in the cache when it is determined that the slave side bit width is greater than the master side bit width, so that the master side reads the master side bit width data in the cache as output each time until the cache is empty and then rewrites the data; if the slave side data is less than the master side bit width, multiple data to be converted are spliced ​​into one master side bit width data and stored in the cache to wait for the master side to read.

5. The DMA processor according to claim 1, characterized in that: The AXI write module includes: a write control module, a write data module and a write bit width conversion module; The write bit width conversion module is used to receive the data to be written, and when it is determined that the master side bit width is greater than the slave side bit width, the data to be written is split and stored in the cache. The write data module reads one slave side bit width data each time. If the master side bit width is less than the slave side bit width, multiple data to be written are spliced ​​into slave side bit width data and stored in the cache to wait for the write data module to read; The write data module is used to read the burst data, read the control information required for processing the burst data from the write control queue of the write control module, add the invalid signal of the first address offset, generate a byte indication signal, and access the memory or external device through the write data channel.

6. The DMA processor according to claim 1, characterized in that: The APB control module is used to receive the data processing task sent by the CPU through the APB bus, decode the data processing task, obtain the task parameters, and send the task parameters to the function module; The APB control module is also used to receive the task result information returned by the functional module, decode the task result information, and generate an APB signal to feed back to the CPU; the task result information includes: task end signal, search result of the search function, calculation result of the comparison function, and AXI read and write error information.

7. The DMA processor according to claim 5, characterized in that: The functional module also includes: an interrupt control module; The interrupt control module is used to process interrupts in the following two situations: the APB signal configuration interrupt register, the AXI protocol error indication signal and the data transmission error signal are valid.

8. The DMA processor according to claim 7, characterized in that: When the interrupt register is valid, if the AXI read module or the AXI write module has not sent the control information at this time, it will be interrupted immediately; if the AXI read module or the AXI write module has sent the control information at this time, it will wait until the bus access is completed based on the control information before interrupting.

9. The DMA processor according to claim 7, characterized in that: When the error indication signal and the data transmission error signal of the AXI protocol are valid, the interrupt control module generates an interrupt enable signal to interrupt the current task and reports an error to the CPU through the APB bus.

10. A data processing system, characterized in that: The system comprises: a CPU and a DMA processor as described in any one of claims 1-9.

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