Multifunctional chip and electronic equipment

Abstract

The invention provides a multifunctional chip and electronic equipment, and relates to the technical field of research and development of basic hardware, design and research and development of chips and the like. According to the specific implementation scheme, the multifunctional chip is realized by adopting an IO Hub chip of a CPU, and the IO Hub chip of the CPU comprises a consistency cache control logic unit, a corresponding cache, a DDR controller and an interconnection bus; the consistency cache control logic unit and the DDR controller are respectively connected with the interconnection bus; the consistency cache control logic unit is used for recording the cache condition and the cache state of the data of the memory address responsible for management in the memory data state information table; the multifunctional chip is also provided with a CXL device controller which is connected with the interconnection bus. And the CXL equipment controller, the consistency cache control logic unit, the corresponding cache and the DDR controller jointly realize the function of a CXL controller chip. According to the technology disclosed by the invention, the research and development efficiency of the CXL controller chip can be effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, specifically to the technical fields of basic hardware research and development, chip design and research and development, and more particularly to a multifunctional chip and electronic device. Background Art

[0002] The input and output (IO) hub chip of the central processing unit (CPU) is a very important chip in the CPU.

[0003] The IO Hub chip is a chip (die) in the CPU chip that integrates functions such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Peripheral Component Interconnect express (PCIe), and Compute Express Link (CXL). It is connected to the computing chip (Die) through a die to die interface. Among them, DDR SDRAM is referred to as DDR. PCIe is a high-speed serial computer expansion bus standard. CXL is a new interconnect technology standard designed to provide high-speed and efficient interconnection between processors, memory expansion and accelerators. The IO Hub chip can also implement cache consistency protocol. Summary of the invention

[0004] The present disclosure provides a multifunctional chip and an electronic device.

[0005] According to one aspect of the present disclosure, a multifunctional chip is provided, wherein the multifunctional chip is implemented by an input / output hub chip of a central processing unit, and the input / output hub chip of the central processing unit includes a consistent cache control logic unit and a corresponding cache, a double-rate synchronous dynamic random access memory controller, and an interconnection bus; the consistent cache control logic unit is connected to the corresponding cache, and the consistent cache control logic unit and the double-rate synchronous dynamic random access memory controller are respectively connected to the interconnection bus; the consistent cache control logic unit is used to record the cache status and cache status of the data of the memory address responsible for management in a memory data status information table;

[0006] The multifunctional chip is also provided with a computing fast interconnect device controller connected to the interconnect bus; the computing fast interconnect device controller, the consistent cache control logic unit and the corresponding cache, and the double rate synchronous dynamic random access memory controller jointly realize the function of the computing fast interconnect controller chip.

[0007] According to another aspect of the present disclosure, an electronic device is provided, wherein the electronic device comprises the multifunctional chip according to the aspect described above; if the multifunctional chip is used as an input and output hub chip of a central processing unit, the function of calculating a fast interconnect controller chip is turned off;

[0008] If the multifunctional chip is used as a fast interconnection controller chip, the function of the input and output hub chip of the central processing unit is turned off.

[0009] According to the technology disclosed in the present invention, the research and development efficiency of CXL controller chips can be effectively improved.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0012] Figure 1 is a schematic diagram according to a first embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram according to a second embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram according to a third embodiment of the present disclosure;

[0015] Figure 4 is a schematic diagram according to a fourth embodiment of the present disclosure;

[0016] Figure 5 is a schematic diagram according to a fifth embodiment of the present disclosure;

[0017] Figure 6 is a schematic diagram according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0019] Obviously, the described embodiments are only part of the embodiments of the present disclosure, but not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0020] It should be noted that the terminal devices involved in the embodiments of the present disclosure may include but are not limited to mobile phones, personal digital assistants (PDAs), wireless handheld devices, tablet computers and other smart devices; display devices may include but are not limited to personal computers, televisions and other devices with display functions.

[0021] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0022] CXL is the core technology for achieving storage and computing separation, so the research and development of CXL controller chips is very important. Among them, the CXL pooling function is the most complex function in the CXL controller chip. Supporting the CXL pooling function requires the implementation of the cache consistency protocol in the CXL controller chip. In the existing technology, designing a CXL controller chip from scratch requires a large investment, a long cycle, and high risk.

[0023] Figure 1 is a schematic diagram according to the first embodiment of the present disclosure; Figure 1 As shown, this embodiment provides a multifunctional chip 100, which is implemented by an IO Hub chip of a CPU. Specifically, the IO Hub chip of the CPU includes a consistent cache control logic unit 101 and a corresponding cache 101C, a DDR controller 102, and an interconnection bus 103; the consistent cache control logic unit 101 and the DDR controller 102 are respectively connected to the interconnection bus 103; the consistent cache control logic unit 101 is used to record the cache status and cache status of the data of the memory address responsible for management in the memory data status information table;

[0024] Specifically, in the IO Hub chip of the CPU, multiple consistent cache control logic units 101 may be provided, and each unit is responsible for the management of a memory address. When the data of a memory address that is responsible for management is read by a CPU die, the memory address of the data being read, the identifier of the CPU die that reads the data, the operation state of the CPU die reading the data, and the state of the data in the corresponding local cache 101C may be recorded in the memory data status information. Among them, the operation state of the CPU die reading the data includes reading or reading and modifying. If the operation state is reading, it means that the CPU die that reads the data has not modified the data of the memory address. At this time, if the data of the memory address is stored in the corresponding local cache 101C, it is still in a valid state. If the operation state is reading and modifying, it means that the CPU die that reads the data has modified the data of the memory address after reading the data of the memory address. At this time, if the data of the memory address is stored in the corresponding local cache 101C, it is in an invalid state. That is to say, in this embodiment, the consistency cache control logic unit 101 and the corresponding cache 101C appear in pairs, each consistency cache control logic unit 101 corresponds to a cache 101C, and each consistency cache control logic unit 101 is responsible for the management of a segment of memory addresses. The data in the responsible memory addresses that have been recently accessed can be stored in the corresponding cache 101C to improve the response speed in subsequent accesses.

[0025] It should be noted that, in this embodiment, the coherent cache control logic unit 101 and the corresponding cache 101C are separately configured as an example. In actual applications, the two can also be configured as an integrated structure.

[0026] The multifunctional chip 100 is also provided with a CXL device controller 104, which is connected to the interconnection bus 103; the CXL device controller 104, the coherent cache control logic unit 101 and the corresponding cache 101C, and the DDR controller 102 jointly implement the functions of the CXL controller chip. For example, the main functions of the CXL controller chip may include the function of responding to the memory access request of the external CXL master device. Since the multifunctional chip 100 is implemented by the IO Hub chip of the CPU, it can also be considered that the CXL device controller 104 is set on the IO Hub chip of the CPU.

[0027] The interconnection bus 103 in the multifunctional chip 100 of this embodiment is a path for connecting various functional units and is used to realize data transmission between various functional units.

[0028] In this embodiment, the cache 101C corresponding to the consistent cache control logic unit 101 is used to cache the commonly used data in the chip memory, so as to reduce the latency of the CPU accessing the chip memory and improve the bandwidth of the CPU accessing the chip memory. In actual application scenarios, the consistent cache control logic unit 101 and the corresponding cache 101C may include N, where N may be a positive integer greater than or equal to 1. When N is greater than 1, a distributed implementation may be adopted, where N consistent cache control logic units 101 are responsible for managing the address space of the entire memory, and each unit is responsible for 1 / N of the address space.

[0029] In this embodiment, the DDR controller 102 includes not only a DDR controller, but also a corresponding physical layer (PHY). The DDR model supported by the DDR controller 102 is selected during chip design, including but not limited to DDR4, DDR5, etc. In this embodiment, the number of DDR controllers 102 included in the multifunctional chip 100 can be one, two or more, and the specific number can be adjusted according to the needs of the actual scenario.

[0030] In this embodiment, the CXL device controller 104 is an interface control logic for implementing the function of a CXL type 3 device. The number of CXL device controllers 104 included in the multifunctional chip 100 may be one, two or more, and the specific number is adjusted according to the requirements of the actual scenario.

[0031] The multifunctional chip 100 of this embodiment can realize the functions of the CXL controller chip together with the consistency cache control logic unit 101 and the corresponding cache 101C, and the DDR controller 102 by setting a CXL device controller 104 in the existing CPU IO Hub chip, thereby effectively reducing the research and development time and difficulty of the CXL controller chip and effectively improving the research and development efficiency of the CXL controller chip.

[0032] Figure 2 is a schematic diagram according to the second embodiment of the present disclosure; Figure 2 As shown, the multifunctional chip 200 of this embodiment, in the above Figure 1 Based on the technical solutions of the illustrated embodiments, the technical solutions of the present disclosure are further described in more detail.

[0033] like Figure 2 As shown, in the multifunctional chip 200 of this embodiment, in addition to the above Figure 1The cache control logic unit 201 with the same name and function and the corresponding cache 201C, DDR controller 202, interconnection bus 203, and CXL device controller 204 are also provided with a system management logic unit 205 of the CXL chip, which is used to implement the management of the CXL controller chip, including the startup process of the CXL controller chip and the initialization configuration of the CXL controller chip; it can be considered that the system management logic unit 205 of the CXL chip is a logic unit that implements the system management function of the system-on-chip (SOC) of the CXL controller chip. The system management logic unit 205 of the CXL chip is connected to the interconnection bus 203. The system management logic unit 205 of the CXL chip can configure and manage the CXL controller chip, effectively ensuring the realization of the functions of the CXL controller chip.

[0034] Further optionally, in one embodiment of the present disclosure, when the multi-function chip 200 is used as a CXL controller chip, the CXL device controller 204 is used to receive a memory read request sent by an external CXL master device, where the memory read request carries a memory address;

[0035] The CXL device controller 204 is also used to transmit the memory read request to the coherent cache control logic unit 201 via the interconnect bus 203;

[0036] The coherent cache control logic unit 201 is used to obtain data of the memory address based on the recorded memory data status information table, and transmit it to the CXL master device through the interconnect bus 203 and the CXL device controller 204 to respond to the memory read request sent by the CXL master device.

[0037] Further optionally, in an embodiment of the present disclosure, during specific implementation, the coherent cache control logic unit 201 is used to determine that when data of a memory address needs to be obtained from the corresponding cache 201C based on the recorded memory data status information table and the data stored in the corresponding cache 201C, obtain the data of the memory address from the corresponding cache 201C, and transmit the data to the CXL master device through the interconnection bus 203 and the CXL device controller 204.

[0038] For example, when the coherent cache control logic unit 201 obtains a memory read request, it first determines whether the data of the memory address requested to be read by the memory read request has been read by other CXL master devices according to the memory status information table; if not, it further detects whether the data of the memory address is stored in the corresponding cache 201C; if it is stored, it determines that the data of the memory address needs to be obtained from the corresponding cache 201C, and at this time, the data of the memory address is directly read from the corresponding cache unit 201C and returned to the interconnection bus 203. The interconnection bus 203 further returns the data of the memory address to the CXL device controller 204, and the CXL device controller 204 further returns the data of the memory address to the CXL master device that sent the memory read request to respond to the memory read request.

[0039] Further optionally, in one embodiment of the present disclosure, the coherent cache control logic unit 201 is further configured to, when it is determined based on the recorded memory data status information table that the data at the memory address is stored in the cache corresponding to the other CXL master device, send a listening instruction carrying the memory address to the other CXL device through the interconnection bus 203 and the other CXL device controllers corresponding to the other CXL master device, so as to obtain the data at the memory address from the cache corresponding to the other CXL device controller; and transmit the data to the CXL master device through the interconnection bus 203 and the CXL device controller 204.

[0040] In the scenario of this embodiment, there is only one CXL controller chip, and multiple CXL master devices can initiate memory read requests to the CXL controller chip. For example, in this embodiment, the CXL master device that sends the memory read request and other CXL master devices here can access the current CXL controller chip. When accessing, the CXL master device that sends the memory read request and other CXL master devices respectively initiate memory read requests through their corresponding CXL device controllers.

[0041] For example, the consistent cache control logic unit 201 determines, based on the memory status information table, that the data of the memory address requested to be read by the memory read request has been read and modified by other CXL master devices; at this time, the data of the memory address in the local corresponding cache 201C is invalid, and it is necessary to read the data of the memory address from the cache corresponding to the other CXL master device. Specifically, the consistent cache control logic unit 201 sends a listening instruction to the interconnection bus 203, and the listening instruction carries the memory address. The listening instruction can be sent by the interconnection bus 203 to other CXL device controllers corresponding to other CXL master devices. After receiving the listening instruction, the other CXL device controllers send the listening command to the corresponding other CXL master devices, so that the other CXL master devices can obtain the data of the memory address from the cache, and return it to the current consistent cache control logic unit 201 through other CXL device controllers and the interconnection bus 203.

[0042] Further optionally, in one embodiment of the present disclosure, the coherent cache control logic unit 201 is also used to determine that when it is necessary to obtain the data of the memory address from the DDR based on the recorded memory data status information table and the data stored in the corresponding cache 201C, send the memory read request to the corresponding DDR controller 202 through the interconnection bus 203, so that the corresponding DDR controller 202 obtains the data of the memory address from the corresponding DDR and returns it to the coherent cache control logic unit 201; and then transmit it to the CXL master device that sends the memory read request through the interconnection bus 203 and the CXL device controller 204 to respond to the memory read request.

[0043] Specifically, the consistent cache control logic unit 201 determines that the data of the memory address of the memory read request has not been read and modified by other CXL master devices based on the recorded memory data status information table, and according to the data stored in the local corresponding cache 201C, it is determined that the data of the memory address is not stored in the local corresponding cache 201C. At this time, it can be determined that the data of the memory address must be stored in the DDR, that is, the data of the memory address needs to be obtained from the DDR. Then, the consistent cache control logic unit 201 transmits a memory read request to the DDR controller 202 through the interconnection bus 203 to request to read the data of the memory address from the DDR. After the DDR controller 202 reads the data of the memory address, it returns it to the interconnection bus 203, and then the interconnection bus 203 returns it to the consistent cache control logic unit 201; then the consistent cache control logic unit 201 transmits it to the CXL master device that sent the memory read request through the interconnection bus 203 and the CXL device controller 204 to respond to the memory read request.

[0044] It should be noted that, based on the above embodiments, it can be known that the multifunctional chip 200 provided in the embodiments of the present disclosure can not only provide the functions of the IO Hub chip in the CPU, but also realize the functions of the CXL controller chip. However, these two functions cannot be used at the same time. When used as the IO Hub chip of the CPU, the function of the CXL controller chip needs to be turned off. When used as the CXL controller chip, the function of the IO Hub chip of the CPU needs to be turned off.

[0045] By adopting the above solution, the multifunctional chip 200 of this embodiment can be used to implement the data access function of the CXL controller chip, thereby realizing the functions of the CXL controller chip.

[0046] The multifunctional chip 200 of this embodiment can realize the functions of the CXL controller chip in the original CPU IO Hub chip by setting a CXL device controller 204 and a system management logic unit 205 of the CXL chip, and combining the consistent cache (cache) control logic unit 201 and the corresponding 201C, DDR controller 202 and interconnection bus 203 in the CPU IO Hub chip, thereby avoiding designing and developing the CXL controller chip from scratch, and can effectively reduce the research and development time and difficulty of the CXL controller chip, and effectively improve the research and development efficiency of the CXL chip.

[0047] Figure 3 is a schematic diagram according to the third embodiment of the present disclosure; Figure 3 As shown, the multifunctional chip 300 of this embodiment, in the above Figure 2 Based on the technical solution of the embodiment shown, in addition to the above Figure 2 The coherent cache control logic unit 301 and the corresponding cache 301C, DDR controller 302, interconnect bus 303, CXL device controller 304, and system management logic unit 305 of CXL chip with the same name and function also include: chip to chip (Die to Die) control logic unit 306, CXL main controller 307, multi-way interconnect controller 308, CPU chip system management logic unit 309, and Peripheral Component Interconnect express (PCIe) main controller 310. The die to die control logic unit 306, CXL main controller 307, multi-way interconnect controller 308, CPU chip system management logic unit 309, and PCIe main controller 310 are connected to the interconnect bus 303 respectively.

[0048] When the multifunctional chip 300 is used as the IO Hub chip of the CPU, multiple IO Hub chips of the CPU with the same structure can be cascaded; specifically, they are connected through the multi-way interconnection controller 308 in the IO Hub chip of each CPU, so the multi-way interconnection controller 308 can be used to achieve the consistent interconnection of the cache of the current CPU IO Hub chip and other CPU IO Hub chips.

[0049] The Die to Die control logic unit 306 includes a protocol switching logic module and a physical layer PHY, which is used to realize data transmission between the CPU Die and the IO Hub. In this embodiment, the Die to Die control logic unit 306 can also have one, two or more in the IO Hub chip of the CPU. The specific number is adjusted according to the needs of the actual scenario.

[0050] The CXL master controller 307 is used to implement the control logic of the CXL master control function and is implemented according to the CXL protocol standard. Similarly, there may be one, two or more CXL master controllers 307 in the IO Hub chip of the CPU. The specific number is adjusted according to the needs of the actual scenario.

[0051] The multi-way interconnection controller 308 is used to realize the cache consistency interconnection between the CPU chip and one or more CPU chips. Similarly, there can be one, two or more multi-way interconnection controllers 308 in the IO Hub chip of the CPU. The specific number is adjusted according to the needs of the actual scenario.

[0052] The CPU chip system management logic unit 309 is a logic unit that implements the system management function of the SOC of the CPU chip.

[0053] The PCIe host controller 310 is used to implement the control logic of the PCIeC root component (RC) function, which is implemented according to the PCIe protocol standard. There can also be one, two or more PCIe host controllers 310 in the CPU's IO Hub chip, and the specific number is adjusted according to the needs of the actual scenario.

[0054] In this embodiment, the CXL host controller 307 shares the physical layer PHY with the CXL device controller 304 , the PCIe host controller 310 and the multi-channel interconnect controller 308 .

[0055] Based on the above analysis, it can be known that the multifunctional chip 300 of this embodiment, when used as the IO Hub chip of the CPU and the CXL controller chip respectively, shares the following units: a coherent cache control logic unit 301 , a DDR controller 302 and an interconnect bus 303 .

[0056] When the multifunctional chip 300 is used as the IO Hub chip of the CPU, the unique units include: a Die to Die control logic unit 306 , a CXL main controller 307 , a multi-way interconnection controller 308 , a CPU chip system management logic unit 309 , and a PCIe main controller 310 .

[0057] When the multi-function chip 300 is used as a CXL controller chip, the specific units include: a CXL device controller 304 and a system management logic unit 305 of the CXL chip.

[0058] Therefore, when the multifunction chip 300 of this embodiment is used as a CXL controller chip, the chip-to-chip control logic unit 306, the CXL main controller 307, the multi-way interconnect controller 308, the CPU chip system management logic unit 309, and the PCI Express main controller 310 are turned off.

[0059] When used as an IO Hub chip of the CPU, the CXL device controller 304 and the system management logic unit 305 of the CXL chip are turned off.

[0060] When the multifunctional chip 300 of this embodiment is used as an IO Hub chip of a CPU, the specific memory read operation process may include the following steps:

[0061] 1. The external CPU Die issues a memory read request, which is received by the Die to Die control logic unit 306 in the multi-function chip 300 and reaches the coherent cache control logic unit 301 through the interconnection bus 303;

[0062] 2. The consistent cache control logic unit 301 checks the location of the latest data of the memory address to be accessed based on the recorded memory data status information table and the data stored in the local corresponding cache 301C; if the latest data of the memory address is in the cache of other CPU Dies, the consistent cache control logic unit 301 sends a snoop instruction, and the snoop instruction reaches the other CPU Die via the interconnection bus 303 and the Die to Die control logic unit 306 corresponding to the other CPU Die. The other CPU Die obtains the latest data of the memory address from the cache and sends it out, and reaches the consistent cache control logic unit 301 via the Dieto Die control logic unit 306 corresponding to the other CPU Die and the interconnection bus 303.

[0063] In the scenario of this solution of this embodiment, other CPU Dies and the CPU Die that issues a memory read request may not cross chips, that is, they are all connected to the IO Hub chip of the current CPU.

[0064] In actual applications, if other CPU Dies and the CPU Die that issues a memory read request are cross-chip, for example, the CPU Die that issues a memory read request is connected to the IO Hub chip of the current CPU, recorded as the IO Hub chip 0 of the CPU, and other CPU Dies are connected to the IO Hub chip 1 of the CPU, the IO Hub chip 0 of the CPU and the IO Hub chip 1 of the CPU are connected together through their respective multi-way interconnection controllers 308. At this time, after the consistent cache control logic unit 301 in the IO Hub chip 0 of the CPU sends a snoop instruction, the snoop instruction reaches the multi-way interconnection controller 308 via the interconnection bus 303, and then the multi-way interconnection controller 308 transmits the snoop command to the multi-way interconnection controller in the IO Hub chip 1 of the CPU at the opposite end; the multi-way interconnection controller in the IO Hub chip 1 of the CPU then reaches other CPU Dies through the interconnection bus in the IO Hub chip 1 of the CPU and the Die to Die control logic unit corresponding to other CPU Dies. Other CPU Dies obtain the latest data of the memory address from the Cache and return it through the Die to Die control logic unit, interconnection bus, and multi-way interconnection controller corresponding to other CPU Dies in the CPU's IO Hub chip 1 to reach the multi-way interconnection controller 308 in the CPU's IO Hub chip 0, and then further through the interconnection bus 303 to reach the consistency cache control logic unit 301.

[0065] If, based on the recorded memory data status information table, it is determined that no other CPU Die has read the data at the memory address, and the data at the memory address is stored in the local corresponding cache 301C, then it can be considered that the latest data of the memory address is in the local corresponding cache 301C, and the data can be read from the local corresponding cache 301C.

[0066] If, based on the recorded memory data status information table, it is determined that no other CPU Die has read the data at the memory address and the data at the memory address is not stored in the cache, it can be considered that the latest data at the memory address can only be stored in the DDR memory. The consistent cache control logic and unit 301 sends the memory read request to a DDR controller 302 via the interconnection bus 303. After the DDR controller 302 reads the data at the memory address from the DDR memory, it sends it back to the consistent cache control logic unit 301 via the interconnection bus 303.

[0067] Specifically, each DDR controller may also be responsible for processing access to a segment of the memory address space, and the interconnection bus 303 may determine to which DDR controller 302 the memory read request is transmitted according to the memory address carried in the memory read request.

[0068] 3. Finally, the coherent cache control logic unit 301 transmits the acquired data of the memory address to the CPU Die via the interconnect bus 303 and the Die to Die control logic unit 306.

[0069] The multifunctional chip 300 of this embodiment can enrich and improve the functions of the multifunctional chip 300 when used as the IO Hub chip of the CPU by further setting up a Die to Die control logic unit 306, a CXL main controller 307, a multi-way interconnection controller 308, a CPU chip system management logic unit 309, and a PCIe main controller 310; and according to the above processing method, the processing of memory access requests of the CPU's IO Hub chip can be accurately implemented.

[0070] Figure 4 is a schematic diagram according to a fourth embodiment of the present disclosure; Figure 4 As shown, in the above embodiment Figure 3 Based on the illustrated embodiment, the technical solution of the present disclosure is further described in more detail. Figure 4 As shown, in an embodiment, the multi-way interconnection controller 308 includes:

[0071] The first memory access request control logic unit 3081 is used to process the memory access request of the IO Hub chip of the local CPU and is responsible for interacting with the memory access request processing logic unit of the multi-way interconnection controller in the IO Hub chip of the CPU of the opposite end;

[0072] The multifunctional chip of this embodiment is used as the IO Hub chip of the CPU. Specifically, when the IO Hub chip of the CPU is used in an electronic device, there may be only one chip or more than two chips. If there are more than two chips, as described in the above embodiment, the IO Hub chips of the two CPUs may be connected together through their respective multi-way interconnection controllers 308 to achieve cascading.

[0073] The first memory access request processing logic unit 3082 is used to process the memory access request of the IO Hub chip of the opposite CPU, and is responsible for the interaction with the first memory access request control logic unit of the multi-way interconnected controller of the IO Hub chip of the opposite CPU; the first transport layer 3083 is used to pack the data transmitted by the first memory access request control logic unit or the first memory access request processing logic unit and transmit it to the physical layer; it is also used to unpack the data received from the physical layer and transmit it to the first memory access request control logic unit or the first memory access request processing logic unit.

[0074] In the scenario of this embodiment, the electronic device may include at least two cascaded CPU IO Hub chips, and the two cascaded CPU IO Hub chips are connected through respective multi-way interconnection controllers 308. The multi-way interconnection controllers 308 all adopt the above structure of this embodiment.

[0075] For example, in the scenario 1 provided in the embodiment of the present disclosure, the CPU Die sends a memory read request to the Die to Die control logic unit 306 in the current CPU IO Hub chip, and the memory read request carries a memory address. The Die to Die control logic unit 306 sends the memory read request to the interconnection bus 303. The interconnection bus 303 detects whether the memory address carried in the memory read request is responsible for the current CPU IO Hub chip. If not, the interconnection bus 303 transmits the memory read request to the multi-way interconnection controller 308, and the first memory access request control logic unit 3081 in the multi-way interconnection controller 308 receives the memory read request and transmits it to the first transport layer 3083, which is then processed by the first transport layer 3083 and transmitted to the first memory access request processing logic unit in the CPU IO Hub chip at the opposite end through the physical layer. The CPU IO Hub chip at the opposite end is symmetrically designed with the current CPU IO Hub chip through the multi-way interconnection controller, and the implementation method is the same as that in the current CPU IO Hub chip, and no further details are given.

[0076] Furthermore, the link for returning the data response corresponding to the memory read request is the reverse of the link of the above-mentioned memory read request, until the data corresponding to the memory read request is returned to the CPU Die that sent the memory read request, which will not be described in detail here.

[0077] For another example, in scenario 2 provided in the embodiment of the present disclosure, the CPU Die sends a memory read request to the Die to Die control logic unit 306 in the current CPU IO Hub chip, and the memory read request carries a memory address. The Die to Die control logic unit 306 sends the memory read request to the interconnection bus 303. The interconnection bus 303 detects and determines that the memory address carried in the memory read request is responsible for the current CPU IO Hub chip, and the interconnection bus 303 transmits the memory read request to the consistency cache control logic unit 301 responsible for the memory address. The consistency cache control logic unit 301 determines that the latest data of the memory address is stored in the cache of other CPU Dies across the CPU IO Hub chip based on the recorded memory data status information table. At this time, the consistency cache control logic unit 301 needs to send a snoop command to other CPU Dies across the CPU IO Hub chip, and the snoop command carries a memory address to request to snoop the data of the memory address. Specifically, the coherent cache control logic unit 301 first sends a snoop command to the interconnection bus 303, and the interconnection bus 303 sends the snoop command to the multi-way interconnection controller 308. The first memory access request control logic unit 3081 in the multi-way interconnection controller 308 receives the snoop command and transmits it to the first transport layer 3083. Then, the first transport layer 3083 processes it and transmits it to the first memory access request processing logic unit in the CPU IO Hub chip at the opposite end through the physical layer. The CPU IO Hub chip at the opposite end is symmetrically designed with the current CPU IO Hub chip through the multi-way interconnection controller, and the implementation method is the same as that in the current CPU IOHub chip, and no further details are given.

[0078] Furthermore, the link through which the data response corresponding to the listening command is returned is the reverse of the link for sending the listening command, until the listened data is returned to the consistency cache control logic unit 301, and then the consistency cache control logic unit 301 returns the data corresponding to the memory read request to CPUDie that sent the memory read request based on the reverse of the memory read request link, which will not be elaborated here.

[0079] The above scenarios 1 and 2 are both based on the current CPU IO Hub chip receiving the memory read request of CPU Die. In actual applications, there may also be a scenario in which the CPU IO Hub chip at the opposite end connected to the multi-way interconnection controller 308 of the current CPU IO Hub chip in scenarios 1 and 2 receives the memory read request of CPU Die.

[0080] For example, compared with scenario 1, the first transport layer 3083 in the multi-way interconnection controller 308 in the current CPU IO Hub chip is also used to unpack the data received from the physical layer and transmit it to the first memory access request processing logic unit 3082, that is, a memory read request is received, and the memory read request carries a memory address; the first memory access request processing logic unit 3082 sends the memory read request to the interconnection bus 303, and the interconnection bus 303 forwards the memory read request to the corresponding consistency cache control logic unit 301, and then the consistency cache control logic unit 301 obtains the data in the memory address in the memory read request based on the recorded memory data status information table and the data stored in the local corresponding cache 301C, and returns it by the original path. For details, please refer to the relevant records in the above embodiments, which will not be repeated here.

[0081] For example, compared with scenario 2, the first transport layer 3083 in the multi-way interconnection controller 308 in the current CPU IO Hub chip is also used to unpack the data received from the physical layer and transmit it to the first memory access request processing logic unit 3082, that is, a listening command is received, and the listening command carries the CPU Die identifier and the memory address; the first memory access request processing logic unit 3082 sends the listening command to the interconnection bus 303, and the interconnection bus 303 then forwards the listening command to the corresponding CPU Die through the Die to Die control logic unit 306 corresponding to the CPU Die identifier, so as to obtain the data corresponding to the memory address from the CPU Die cache; and the principle is returned. For details, please refer to the relevant records in the above embodiments, which will not be repeated here.

[0082] The embodiments of the above-mentioned multiple scenarios are that the multi-way interconnected controller 308 implements memory read requests and corresponding responses, the sending of listening commands and corresponding responses by adopting the first memory access request control logic unit 3081, the first memory access request processing logic unit 3082 and the first transport layer 3083; in actual application scenarios, there may also be other similar requests and responses, and the implementation process is similar, which will not be repeated here one by one.

[0083] When the multifunctional chip of this embodiment is used as an IO Hub chip of the CPU, the multi-way interconnection controller 308 can accurately and efficiently implement the processing flow of memory read requests of the IO Hub chip across the CPU by adopting the first memory access request control logic unit 3081, the first memory access request processing logic unit 3082 and the first transmission layer 3083.

[0084] Figure 5 is a schematic diagram according to the fifth embodiment of the present disclosure; Figure 5 As shown, in the above embodiment Figure 3Based on the illustrated embodiment, the technical solution of the present disclosure is further described in more detail. Figure 5 As shown, in an embodiment, the CXL master controller 307 includes:

[0085] The second memory access request control logic unit 3071 is used to process the memory access request of the local CPU IO Hub chip;

[0086] The CXL master control protocol conversion logic unit 3072 is used to implement the conversion between the cache coherence access protocol of the CPU IO Hub chip and the CXL master control protocol;

[0087] The second transport layer 3073 is used to implement data conversion between the CXL main control protocol conversion logic unit and the physical layer.

[0088] Specifically, in the scenario of this embodiment, the CXL master controller 307 can be connected to an external extended memory. According to the above embodiment, the CPU Die sends a memory read request to the Die to Die control logic unit 306 in the current CPU IO Hub chip, and the memory read request carries a memory address. The Die to Die control logic unit 306 sends the memory read request to the interconnection bus 303. The interconnection bus 303 detects and determines that the memory address carried in the memory read request belongs to the external extended memory of the CXL master controller 307. At this time, the interconnection bus 303 can send the memory read request to the CXL master controller 307. Specifically, the second memory access request control logic unit 3071 receives the memory read request sent by the interconnection bus 303, and the CXL master control protocol conversion logic unit 3072 performs protocol conversion on the memory read request, specifically, converting the local cache consistency memory access protocol to the CXL master control protocol. Then the memory read request after protocol conversion is sent to the second transport layer 3073. The second transport layer 3073 sends a memory read request after protocol conversion to the physical layer, which is transmitted to the external extended memory through the physical layer, and then the data of the memory address is obtained from the extended memory. The returned response process is the reverse of the memory read request sending link, which will not be repeated here.

[0089] In this embodiment, the second memory access request control logic unit 3071 can be implemented by reusing the first memory access request control logic unit 3081, which can effectively simplify the structure and improve the research and development efficiency of the multi-functional chip.

[0090] When the multifunctional chip of this embodiment is used as the IO Hub chip of the CPU, the CXL main controller 307 can accurately and efficiently implement the processing flow of reading data from the extended memory by adopting the second memory access request control logic unit 3071, the CXL main control protocol conversion logic unit 3072 and the second transport layer 3073.

[0091] Figure 6 is a schematic diagram according to the sixth embodiment of the present disclosure; Figure 6 As shown, in the above embodiment Figure 3 Based on the illustrated embodiment, the technical solution of the present disclosure is further described in more detail. Figure 6 As shown, in an embodiment, the CXL device controller 302 includes:

[0092] The second memory access request processing logic unit 3021 is used to process the memory access request of the CXL master device at the opposite end;

[0093] The CXL device control protocol conversion logic unit 3022 is used to implement the conversion between the cache coherence access protocol of the CPU IO Hub chip and the CXL device control protocol;

[0094] The third transport layer 3023 is used to implement data conversion between the CXL device control protocol conversion logic unit and the physical layer, and process control between the transport layer of the CXL device controller at the opposite end.

[0095] In this embodiment, the second memory access request processing logic unit 3021 can be implemented by reusing the first memory access request processing logic unit 3082, which can effectively simplify the structure and improve the research and development efficiency of the multifunctional chip.

[0096] Figure 6 In the scenario of the illustrated embodiment, the multifunctional chip is used as a CXL controller chip, and the CXL device controller 302 in the CXL controller chip is connected to a CXL master device at the opposite end. The CXL device controller 302 in the current CXL controller chip can receive a memory access request from the opposite CXL master device. Specifically, the third transport layer 3023 in the CXL device controller 302 first receives a data packet transmitted from the physical layer, that is, a data packet corresponding to the memory access request, and the memory access request can carry a memory address. And transmit it to the CXL device control protocol conversion logic unit 3022, which realizes the conversion between the CXL device control protocol of the memory access request and the cache consistency memory access protocol of the current multi-function chip, namely the CPU IO Hub chip; then forward the converted memory access request to the second memory access request processing logic unit 3021, and the second memory access request processing logic unit 3021 can forward the memory access request after the protocol conversion to the interconnection bus 303, and the interconnection bus 303 then forwards the memory access request to the corresponding consistency cache control logic unit 301 based on the memory address, and the consistency cache control logic unit 301 obtains the data of the memory address and returns the original path.

[0097] Specifically, the memory access request in this embodiment can also be considered as Figure 2 The memory read request in the embodiment shown. The technical solution in this embodiment can be considered as Figure 2 The technical solution of the illustrated embodiment is refined in the CXL device controller 302 , and the remaining implementation solutions are the same and will not be described in detail here.

[0098] When the multifunctional chip of this embodiment is used as a CXL control chip, the CXL device controller 302 can accurately and efficiently implement the processing flow of the memory access request of the CXL master control device by using the second memory access request processing logic unit 3021, the CXL device control protocol conversion logic unit 3022, and the third transport layer 3023.

[0099] It should be noted that the above Figure 4 The multi-way interconnection controller 308 of the embodiment shown, Figure 5 The CXL master controller 307 of the illustrated embodiment, Figure 6 The CXL device controller 302 of the illustrated embodiment shares the physical layer PHY, which further effectively simplifies the structure of the multi-function chip and improves the research and development efficiency.

[0100] The multifunctional chip of this embodiment can realize the functions of the CPU IO Hub chip and the CXL controller chip by adopting the above technical solution. Before use, the function to be realized can be selected and irrelevant functional units can be turned off, which is very flexible to use. Compared with the prior art, it can effectively reduce the R&D time and difficulty of the CXL controller chip and effectively improve the R&D efficiency of the CXL chip.

[0101] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device. The electronic device includes the above Figure 1-Figure 6 The multifunctional chip defined in any embodiment. If the multifunctional chip is used as the IO Hub chip of the CPU, the function of the CXL controller chip is turned off; for example, the CXL device controller in the multifunctional chip and the system management logic unit of the CXL chip are specifically turned off.

[0102] If the multi-function chip is used as a CXL controller chip, the function of the CPU's IO Hub chip is turned off. For example, the Die to Die control logic unit, the CXL main controller, the multi-way interconnection controller, the CPU's chip system management logic unit, and the PCIe controller can be turned off.

[0103] The method of closing the unit in this embodiment can be achieved by software or hardware. In short, no matter which method is used, the function of the corresponding unit can be disabled. For details, please refer to the relevant technology and will not be repeated here. It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders. As long as the expected results of the technical solution disclosed in this disclosure can be achieved, this document does not limit it here.

[0104] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A multifunctional chip, wherein: The multifunctional chip is implemented by an input / output hub chip of a central processing unit, and the input / output hub chip of the central processing unit includes a consistent cache control logic unit and a corresponding cache, a double-rate synchronous dynamic random access memory controller, and an interconnection bus; the consistent cache control logic unit is connected to the corresponding cache, and the consistent cache control logic unit and the double-rate synchronous dynamic random access memory controller are respectively connected to the interconnection bus; the consistent cache control logic unit is used to record the cache status and cache status of the data of the memory address responsible for management in the memory data status information table; The multifunctional chip is also provided with a computing fast interconnect device controller connected to the interconnect bus; the computing fast interconnect device controller, the consistent cache control logic unit and the corresponding cache, and the double rate synchronous dynamic random access memory controller jointly realize the function of the computing fast interconnect controller chip.

2. The multifunctional chip according to claim 1, wherein: The multifunctional chip is also provided with a system management logic unit of a computing fast interconnection chip, which is used to implement the management of the computing fast interconnection controller chip, including the management of the startup process of the computing fast interconnection controller chip and the initialization configuration of the computing fast interconnection controller chip; the system management logic unit of the computing fast interconnection chip is connected to the interconnection bus.

3. The multifunctional chip according to claim 1, wherein: The computing fast interconnect device controller is used to receive a memory read request sent by an external computing fast interconnect master control device, wherein the memory read request carries a memory address; The computing fast interconnect device controller is further used to transmit the memory read request to the consistent cache control logic unit via the interconnect bus; The coherent cache control logic unit is used to obtain the data of the memory address based on the recorded memory data status information table; and transmit the data to the computing fast interconnect master device through the interconnect bus and the computing fast interconnect device controller.

4. The multifunctional chip according to claim 3, wherein: The consistent cache control logic unit is used to determine, based on the recorded memory data status information table and the corresponding data stored in the cache, that the data of the memory address needs to be obtained from the cache, and to obtain the data of the memory address from the cache; and transmit the data to the computing fast interconnect master control device through the interconnect bus and the computing fast interconnect device controller.

5. The multifunctional chip according to claim 3, wherein: The consistent cache control logic unit is used to determine, based on the recorded memory data status information table, that the data of the memory address is stored in the cache corresponding to the other computing fast interconnection master device, and to send a listening instruction carrying the memory address to the other computing fast interconnection device controller through the interconnection bus and the other computing fast interconnection device controller corresponding to the other computing fast interconnection master device, so as to obtain the data of the memory address from the cache corresponding to the other computing fast interconnection device controller; and transmit the data to the computing fast interconnection master device through the interconnection bus and the computing fast interconnection device controller.

6. The multifunctional chip according to claim 3, wherein: The consistent cache control logic unit is used to determine that it is necessary to obtain the data of the memory address from the double-speed synchronous dynamic random access memory based on the recorded memory data status information table and the corresponding data stored in the cache, and to send the memory read request to the corresponding double-speed synchronous dynamic random access memory controller through the interconnection bus, so that the corresponding double-speed synchronous dynamic random access memory controller can obtain the data of the memory address from the double-speed synchronous dynamic random access memory and return it to the consistent cache control logic unit; and then transmit it to the computing fast interconnection master control device through the interconnection bus and the computing fast interconnection device controller.

7. The multifunctional chip according to any one of claims 1 to 6, wherein: The input and output hub chip of the central processing unit also includes: a chip-to-chip control logic unit, a computing fast interconnection main controller, a multi-way interconnection controller, a chip system management logic unit of the central processing unit, and a fast peripheral component interconnection main controller; the chip-to-chip control logic unit, the computing fast interconnection main controller, the multi-way interconnection controller, the chip system management logic unit of the central processing unit, and the fast peripheral component interconnection main controller are all connected to the interconnection bus respectively.

8. The multifunctional chip according to claim 7, wherein: When the multifunctional chip is used as a computing rapid interconnect controller chip, the chip-to-chip control logic unit, the computing rapid interconnect main controller, the multi-way interconnect controller, the chip system management logic unit of the central processing unit, and the rapid peripheral component interconnect main controller are turned off.

9. The multifunctional chip according to claim 7, wherein: The computing interconnect express device controller, the multi-way interconnect controller, the computing interconnect express master controller, and the peripheral component interconnect express master controller share a physical layer.

10. The multifunctional chip according to claim 7, wherein: The multi-channel interconnection controller comprises: The first memory access request control logic unit is used to process the memory access request of the input and output hub chip of the local central processing unit, and is responsible for the interaction with the first memory access request processing logic unit of the multi-way interconnection controller in the input and output hub chip of the central processing unit at the opposite end; The first memory access request processing logic unit is used to process the memory access request of the input and output hub chip of the central processing unit at the opposite end, and is responsible for the interaction with the first memory access request control logic unit of the multi-way interconnection controller of the input and output hub chip of the central processing unit at the opposite end; The first transport layer is used to pack the data transmitted by the first memory access request control logic unit or the first memory access request processing logic unit and transmit it to the physical layer; it is also used to unpack the data received from the physical layer and transmit it to the first memory access request control logic unit or the first memory access request processing logic unit.

11. The multifunctional chip according to claim 10, wherein: The computing fast interconnection main controller comprises: A second memory access request control logic unit, used for processing memory access requests of the input and output hub chip of the local central processing unit; A computing fast interconnect master control protocol conversion logic unit is used to implement the conversion between the local cache consistency access protocol of the input and output hub chip of the central processing unit and the computing fast interconnect master control protocol; The second transmission layer is used to realize the data conversion between the computing fast interconnection main control protocol conversion logic unit and the physical layer.

12. The multifunctional chip according to claim 10, wherein: The computing fast interconnection device controller comprises: A second memory access request processing logic unit is used to process a memory access request of a computing fast interconnection master control device at the opposite end; A computing fast interconnect device control protocol conversion logic unit is used to implement the conversion between the cache consistency access protocol of the input and output hub chip of the central processing unit and the computing fast interconnect device control protocol; The third transport layer is used to realize data conversion between the computing fast interconnection device control protocol conversion logic unit and the physical layer.

13. An electronic device, wherein: The electronic device comprises the multifunctional chip as described in any one of claims 1 to 12 above; if the multifunctional chip is used as an input and output hub chip of a central processing unit, the function of calculating a fast interconnection controller chip is turned off; If the multifunctional chip is used as a fast interconnection controller chip, the function of the input and output hub chip of the central processing unit is turned off.

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