Three-dimensional storage and calculation integrated system and calculation method thereof

Abstract

The invention belongs to the technical field of storage and calculation integration, and particularly discloses a three-dimensional storage and calculation integration system and an operation method thereof, and the system comprises an input module which has an input end connected to an output end of a main processor and is used for converting to-be-processed data into an analog voltage signal; the input end of the memristor array is connected to the output end of the input module, and the memristor array is used for carrying out matrix vector multiplication or matching operation on pre-stored operation data and the analog voltage signal and outputting a first operation result of the data to be processed; the input end of the sensing module is connected to the output end of the memristor array, and the sensing module is used for converting the first operation result into a corresponding digital signal based on the signal form of the first operation result; and the main processor is used for analyzing the digital signal and determining a second operation result of the data to be processed. According to the invention, the storage area and power consumption of the system can be effectively reduced, and the operation speed and efficiency of the system are improved.

Description

Technical Field

[0001] The present application belongs to the field of storage and computing integration technology, and more specifically, relates to a three-dimensional storage and computing integration system and its computing method. Background Art

[0002] Matrix multiplication and exact matching are both very important forms of calculation in machine learning. Matrix multiplication is mainly used to implement the convolutional layer and fully connected layer in the machine learning neural network, while exact matching is used to implement the machine learning decision tree and random forest algorithm. In machine learning algorithms, two machine learning algorithms are often combined to achieve higher prediction performance.

[0003] However, at present, the computing architecture adopted by the existing systems that implement the above two machine learning algorithms is the traditional von Neumann architecture. During the data calculation process, since the computing module and the storage module are separated, data will be continuously transmitted between the computing module and the storage module. The amount of data calculation is huge, resulting in large system storage area and power consumption overhead. At the same time, it also leads to slow system operation speed and low computing efficiency. Summary of the invention

[0004] In view of the defects of the prior art, the present application aims to solve the problems of large system storage area and resource overhead, slow system operation speed and low operation efficiency of the traditional fusion matrix multiplication and exact matching algorithm.

[0005] To achieve the above objectives, the present application provides a three-dimensional storage and computing integrated system, including:

[0006] An input module, whose input terminal is connected to the output terminal of the main processor and is used to convert the data to be processed into an analog voltage signal;

[0007] A memristor array, whose input end is connected to the output end of the input module, is used to perform a matrix-vector multiplication operation or a matching operation on the pre-stored operation data and the analog voltage signal, and output a first operation result of the data to be processed;

[0008] a sensing module, whose input end is connected to the output end of the memristor array, and is used to convert the first operation result into a corresponding digital signal based on the signal form of the first operation result;

[0009] And a main processor, whose first input end is used to receive the data to be processed, and whose second input end is connected to the output end of the perception module, is used to analyze the digital signal and determine the second operation result of the data to be processed.

[0010] Optionally, the memristor array comprises multiple layers of memristor sub-arrays, each column of memristors in each layer of the memristor sub-arrays is connected by a bit line, and each row of memristors in each layer of the memristor sub-arrays is connected by a word line;

[0011] The memristor sub-arrays of each layer are connected by the word lines; the number of the bit lines and the word lines are determined according to the size of the memristor sub-arrays;

[0012] The bit line is used to input the analog voltage signal; the word line is used to output the first operation result of the data to be processed.

[0013] Optionally, each of the word lines is connected to a discharge transistor; the discharge transistor is used to perform a data initialization operation before the memristor array performs a matrix-vector multiplication operation or a matching operation.

[0014] Optionally, the multi-layer memristor subarray includes a first memristor subarray and a second memristor subarray;

[0015] The first memristor subarray is used to store a multiplied data matrix so that the multiplied data matrix performs a matrix-vector multiplication operation with the analog voltage signal;

[0016] The second memristor subarray is used to store a data matrix to be searched, so that the data matrix to be searched is matched with the analog voltage signal; the operation data includes the multiplied data matrix and the data matrix to be searched.

[0017] Optionally, the data to be processed includes first data for performing a matrix-vector multiplication operation or second data for performing a matching operation; correspondingly, the analog voltage signal includes a first analog voltage signal corresponding to the first data or a second analog voltage signal corresponding to the second data;

[0018] The bit lines include a first bit line arranged in the first memristor subarray and a second bit line arranged in the second memristor subarray; the first bit line is used to input the first analog voltage signal, and the second bit line is used to input the second analog voltage signal;

[0019] The first memristor subarray is used to perform a matrix-vector multiplication operation on the first analog voltage signal and the multiplied data matrix; the second memristor subarray is used to perform a matching operation on the second analog voltage signal and the to-be-searched data matrix;

[0020] The word line is used to output a calculation result corresponding to the first data or a calculation result corresponding to the second data; the first calculation result includes a calculation result corresponding to the first data or a calculation result corresponding to the second data.

[0021] Optionally, each column of stored data in the multiplied data matrix is ​​represented by a column of memristors in the first memristor subarray, wherein a high resistance state of the memristor represents that the stored data is "0", and a low resistance state of the memristor represents that the stored data is "1";

[0022] When the data input to a column of memristors of the first memristor subarray is "0", the corresponding input analog voltage signal is defined as a signal GND; when the data input to a column of memristors is "1", the corresponding input analog voltage signal is defined as a signal Vs;

[0023] The signal Vs is used to indicate a voltage signal for reading the memristor, and the signal GND is used to indicate that the memristor is grounded.

[0024] Optionally, each column of stored data in the to-be-searched data matrix is ​​represented by two columns of memristors in the second memristor subarray, wherein, in the two columns of memristors, the high resistance state of any memristor and the low resistance state of its corresponding memristor represent that the stored data is "0", the low resistance state of any memristor and the high resistance state of its corresponding memristor represent that the stored data is "1", and the high resistance state of any memristor and the high resistance state of its corresponding memristor represent that the stored data is "X", and the stored data "X" is used to represent a don't care state;

[0025] When the data input to the two columns of memristors in the second memristor subarray is "0", the two corresponding input analog voltage signals are defined as a sequential combination of signal GND and signal Vs; when the data input to the two columns of memristors is "1", the two corresponding input analog voltage signals are defined as a sequential combination of signal Vs and signal GND; when the data input to the two columns of memristors is "X", the two corresponding input analog voltage signals are defined as a combination of signal GND and signal GND.

[0026] Optionally, the memristor array includes a resistive memory array, a ferroelectric memory array, a phase change memory array, a magnetic random access memory array or a non-volatile flash memory device array.

[0027] Optionally, the spatial arrangement structure of the memristor array includes a three-dimensional horizontal stacking structure or a three-dimensional vertical stacking structure.

[0028] The present application also provides a computing method applied to any one of the above-mentioned three-dimensional storage and computing integrated systems, including:

[0029] Convert the data to be processed into an analog voltage signal;

[0030] Performing a matrix-vector multiplication operation or a matching operation on the pre-stored operation data and the analog voltage signal, and outputting a first operation result of the data to be processed;

[0031] Based on the signal form of the first operation result, converting the first operation result into a corresponding digital signal;

[0032] The digital signal is analyzed to determine a second operation result of the data to be processed.

[0033] In general, the above technical solutions conceived by the present application have at least the following beneficial effects compared with the prior art:

[0034] The present application provides a three-dimensional storage and computing integrated system and its operation method. The system uses an input module to convert input data to be processed into an analog voltage signal, and a memristor array performs matrix-vector multiplication or matching operation on the stored operation data and the analog voltage signal. Combined with the processing and analysis of the operation results by the perception module and the main processor, the two operation functions of precise search and matrix multiplication can be realized in the same memristor array, which can effectively reduce the system's storage area and power consumption overhead, and improve the system's operation speed and efficiency. At the same time, the system can also be reconfigured without introducing additional arrays and circuits, adapting to the functional requirements of precise matching operations or matrix multiplication operations, and is conducive to improving the integration density and array size of the system circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is one of the structural schematic diagrams of the three-dimensional storage and computing integrated system provided in the embodiment of the present application;

[0036] Figure 2 This is the second structural diagram of the three-dimensional storage and computing integrated system provided in the embodiment of the present application;

[0037] Figure 3 It is one of the structural schematic diagrams of the three-dimensional self-rectifying memristor array provided in the embodiment of the present application;

[0038] Figure 4 This is the second structural schematic diagram of the three-dimensional self-rectifying memristor array provided in the embodiment of the present application;

[0039] Figure 5 It is a schematic diagram of a flow chart of a memristor array performing a matrix-vector multiplication operation provided in an embodiment of the present application;

[0040] Figure 6 It is a schematic diagram of a flow chart of a matching operation performed by a memristor array provided in an embodiment of the present application;

[0041] Figure 7 It is a schematic diagram of the result of realizing matrix-vector multiplication operation by the three-dimensional self-rectifying memristor array provided in an embodiment of the present application;

[0042] Figure 8This is a schematic diagram of the result of implementing precise matching operation using a three-dimensional self-rectifying memristor array provided in an embodiment of the present application;

[0043] Fig. 9 It is a flow chart of the operation method of the three-dimensional storage and computing system provided in the embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] The terms "first" and "second" and the like in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, the first operation result and the second operation result are used to distinguish different operation results rather than to describe a specific order of the operation results; the first memristor subarray and the second memristor subarray are used to distinguish memristor subarrays with different functions rather than to describe a specific order of the memristor subarrays.

[0046] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0047] In the description of the embodiments of the present application, unless otherwise specified, "multi-layer" means two layers or more layers. For example, a multi-layer memristor subarray refers to a memristor subarray with two or more layers.

[0048] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0049] Figure 1 is one of the structural diagrams of the three-dimensional storage and computing integrated system provided in the embodiment of the present application, such as Figure 1 As shown, the system includes:

[0050] An input module, whose input terminal is connected to the output terminal of the main processor and is used to convert the data to be processed into an analog voltage signal;

[0051] A memristor array, whose input end is connected to the output end of the input module, is used to perform a matrix-vector multiplication operation or a matching operation on the pre-stored operation data and the analog voltage signal, and output a first operation result of the data to be processed;

[0052] A sensing module, whose input end is connected to the output end of the memristor array, and is used to convert the first operation result into a corresponding digital signal based on the signal form of the first operation result;

[0053] And a main processor, whose first input end is used to receive the data to be processed, and whose second input end is connected to the output end of the perception module, is used to analyze the digital signal and determine the second operation result of the data to be processed.

[0054] Specifically, the operation data described in the embodiment of the present application is used to perform a matrix vector multiplication operation or a matching operation with the analog voltage signal, wherein the matching operation can be a fuzzy matching operation or an exact matching operation.

[0055] In the embodiment of the present application, the input module is used to convert the data to be processed forwarded by the main processor into an analog voltage signal, which can also be described as an "input voltage driving module". It can be specifically composed of multiple 1-bit digital-to-analog converters to use the converted analog voltage signal as the voltage input of the memristor array for operation.

[0056] In an embodiment of the present application, the memristor array can map each data in the operation data to a corresponding conductance value in advance for data storage. The memristor array can specifically adopt a three-dimensional self-rectifying memristor array, that is, a self-rectifying memristor array made by three-dimensional chip stacking technology. The self-rectifying memristor array can effectively suppress the array leakage current by utilizing the reverse rectification characteristics of the self-rectifying memristor.

[0057] It should be noted that the memristor array may also use other memristors that can implement matrix-vector multiplication and matching operation functions, and this application does not make specific limitations on this.

[0058] Due to the self-rectifying characteristics of the memristor device, when reading in the forward direction, the high and low resistance states of the device can be read, and when reading in the reverse direction, the read resistance is much higher than the high resistance of the device. This self-rectifying characteristic of forward conduction and reverse cutoff can further help the memristor array achieve precise matching and reconfigurable operations of matrix-vector multiplication.

[0059] The first operation result described in the embodiment of the present application refers to the original operation result obtained after the analog voltage signal corresponding to the data to be processed is processed by the memristor array, which may specifically include the memristor array processing result corresponding to the matrix-vector multiplication operation, or the memristor array processing result corresponding to the matching operation. The signal form of the first operation result may include two forms: the form of a current signal and the form of a voltage signal.

[0060] In an embodiment of the present application, the sensing module can be pre-configured with sensing modes, including voltage sensing mode and current sensing mode, so it can also be described as a "configurable current / voltage sensing module". The principle of using the configurable current / voltage sensing module to realize the two operation functions of matching and matrix-vector multiplication is as follows: the current sensing mode corresponds to the matrix-vector multiplication operation function, and the operation result is positively linearly correlated with the current. Through the first operation result output in the form of a current signal, the sensing module directly senses the corresponding current value, and then converts it into the corresponding multiplication result through the main processor; the voltage sensing mode corresponds to the matching operation function. Since the voltage difference between complete matching and mismatching is large and easy to distinguish, the reference voltage can be set between the two. Through the first operation result output in the form of a voltage signal, the sensing module compares the first operation result with the reference voltage to determine whether it is completely matched.

[0061] The second operation result described in the embodiment of the present application refers to the final matrix-vector multiplication operation result or matching result corresponding to the data to be processed. When the second operation result is the final matrix-vector multiplication operation result, it is specifically manifested as the data information obtained by performing matrix-vector multiplication calculation on the data to be processed; when the second operation result is the final matching operation result, it is specifically manifested as the data information of successful or unmatched matching obtained by performing search and matching calculation on the data to be processed.

[0062] Furthermore, in an embodiment of the present application, after the perception module converts the first operation result into a corresponding digital signal, it inputs it into the main processor, and the main processor analyzes the digital signal to ultimately determine the matrix-vector multiplication result or matching result corresponding to the data to be processed.

[0063] It should be noted that the main processor may be a processor commonly used in the art, such as a DSP chip or an FPGA chip, etc., and the embodiments of the present application do not impose any specific restrictions on this.

[0064] Figure 2 This is the second structural diagram of the three-dimensional storage and computing integrated system provided in the embodiment of the present application. Figure 2 As shown, in an embodiment of the present application, the memristor array 2 adopts a three-dimensional self-rectifying memristor array, and the input voltage driving module 1 converts the data to be processed input by the main processor 4 into an analog voltage signal and transmits it to the three-dimensional self-rectifying memristor array for matrix-vector multiplication or matching operation. The operation result is further output to the configurable current / voltage sensing module 3 for analog-to-digital conversion and converted into a corresponding digital signal. The main processor 4 performs digital signal analysis to obtain the final operation result of the data to be processed.

[0065] Among them, the configurable current / voltage sensing module may include multiple configurable current / voltage sensing units, each configurable current / voltage sensing unit is connected to a corresponding matching line, and each configurable current / voltage sensing unit includes a transimpedance amplifier, two two-or-one switches respectively arranged at both ends of the transimpedance amplifier and an analog-to-digital converter (ADC). The sensing mode of each configurable current / voltage sensing unit can be achieved by controlling the switching of the two two-or-one switches in the configurable current / voltage sensing module by the main processor.

[0066] When the main processor controls the switching of the two-to-one switch so that the first operation result is processed by the transimpedance amplifier and ADC, the sensing module is in the current sensing mode. The function of the transimpedance amplifier is to convert the current signal into a voltage signal during current sensing; when the two-to-one switch is controlled to switch so that the first operation result is only processed by the ADC, the sensing module is in the voltage sensing mode. The function of the ADC is to sense the voltage signal and output the corresponding digital signal.

[0067] The three-dimensional storage and computing integrated system of the embodiment of the present application utilizes an input module to convert input data to be processed into an analog voltage signal, and the memristor array performs matrix-vector multiplication or matching operation on the stored operation data and the analog voltage signal. Combined with the processing and analysis of the operation results by the perception module and the main processor, the two operation functions of precise search and matrix multiplication can be realized in the same memristor array, which can effectively reduce the storage area and power consumption of the system, and improve the operation speed and efficiency of the system. At the same time, the system can also be reconfigured without introducing additional arrays and circuits, adapting to the functional requirements of precise matching operation or matrix multiplication operation, and is conducive to improving the integration density and array size of the system circuit.

[0068] Based on the content of the above embodiment, as an optional embodiment, the memristor array includes multiple layers of memristor sub-arrays, each column of memristors in each layer of memristor sub-arrays is connected by a bit line, and each row of memristors in each layer of memristor sub-arrays is connected by a word line;

[0069] Each layer of memristor subarrays is connected by word lines; the number of bit lines and word lines is determined according to the size of the memristor subarray;

[0070] The bit line is used for inputting an analog voltage signal; the word line is used for outputting a first operation result of the data to be processed.

[0071] Specifically, in an embodiment of the present application, a memristor array can be manufactured using a three-dimensional chip stacking technology, including multiple layers of memristor subarrays, each column of memristors in each layer of memristor subarrays is connected by a bit line, and each row of memristors in each layer of memristor subarrays is connected by a word line. The bit lines can be divided into three categories according to the type of input data, respectively denoted as BL, SL, and SLb; the word lines can be denoted as WL.

[0072] In the embodiment of the present application, each layer of memristor subarrays is connected by word lines to form a large three-dimensional array. The number of bit lines and word lines is determined according to the size of the memristor subarray. For example, if the size of each layer of memristor subarray is 4×8, it can be determined that there are 8 bit lines and 4 word lines in each layer of memristor subarray.

[0073] The bit line is used to input an analog voltage signal corresponding to the data to be processed; and the word line is used to output a first operation result of the data to be processed.

[0074] The system of the embodiment of the present application adopts a layered array structure design, uses word lines and bit lines to connect each memristor device to form a multi-layer memristor sub-array, and uses word lines to connect the layers of memristor sub-arrays to perform three-dimensional stacking to form an entire three-dimensional memristor array. By controlling the input and output of data signals through bit lines and word lines, a matrix multiplication or matching array operation can be implemented in a parallel array read operation, so that the system has the advantages of low time complexity and high parallelism, and also has the characteristics of high integration density and large array scale.

[0075] Based on the content of the above embodiment, as an optional embodiment, each word line is connected to a discharge transistor; the discharge transistor is used to perform a data initialization operation before the memristor array performs a matrix-vector multiplication operation or a matching operation.

[0076] It should be noted that during the operation of the memristor array, a certain amount of charge may accumulate on the word line, and these residual charges may affect the normal operation of the entire array circuit or cause data reading errors.

[0077] Specifically, in the embodiment of the present application, in the memristor array structure, each word line is connected to a discharge transistor. By controlling the on and off of the discharge transistor, the residual charge accumulated on the word line can be easily cleared, thereby realizing data initialization operation before the memristor array performs matrix-vector multiplication operation or matching operation.

[0078] At the same time, the provided discharge transistor can also play the function of resetting the circuit, and restore the circuit to the initial state through the discharge operation.

[0079] In addition, when an abnormal situation occurs in the memristor array circuit (such as overcurrent, overvoltage, etc.), the discharge transistor can also be turned on quickly to divert the current or voltage to a safe path, thereby protecting other circuit components from damage.

[0080] The system of the embodiment of the present application connects a discharge transistor to each word line in the memristor array to initialize data before operation. The discharge transistor is used for discharge, which can effectively release the charge or current on the word line, thereby achieving the purpose of clearing residual charge, resetting circuit status or protecting other circuit elements, thereby ensuring the stable operation and high efficiency performance of the memristor array.

[0081] Based on the content of the above embodiment, as an optional embodiment, the multilayer memristor subarray includes a first memristor subarray and a second memristor subarray;

[0082] The first memristor subarray is used to store a multiplied data matrix so that the multiplied data matrix and the analog voltage signal perform a matrix-vector multiplication operation;

[0083] The second memristor subarray is used to store the data matrix to be searched, so that the data matrix to be searched can be matched with the analog voltage signal; the operation data includes the multiplied data matrix and the data matrix to be searched.

[0084] Specifically, the first memristor subarray described in the embodiment of the present application refers to a memristor array portion in the multilayer memristor subarray used to perform matrix-vector multiplication operations.

[0085] The second memristor sub-array described in the embodiment of the present application refers to the memristor array portion in the multi-layer memristor sub-array used to perform matching operations.

[0086] In an embodiment of the present application, the operation data may specifically include a multiplied data matrix and a to-be-searched data matrix. It is understandable that when performing a matrix-vector multiplication operation, the operation data is a multiplied data matrix; when performing a matching operation, the operation data is a to-be-searched data matrix. The multiplied data matrix is ​​pre-mapped and stored in the first memristor subarray, and the to-be-searched data matrix is ​​pre-mapped and stored in the second memristor subarray.

[0087] It should be noted that when the second operation result is the final matrix-vector multiplication operation result, it is specifically manifested as the data information calculated by the data to be processed and the multiplied data matrix; when the second operation result is the final matching operation result, it is specifically manifested as the data information of whether the data to be processed successfully matches or does not match the data matrix to be searched.

[0088] Based on the content of the above embodiment, as an optional embodiment, the data to be processed includes first data for performing a matrix-vector multiplication operation or second data for performing a matching operation; correspondingly, the analog voltage signal includes a first analog voltage signal corresponding to the first data or a second analog voltage signal corresponding to the second data;

[0089] The bit lines include a first bit line arranged in the first memristor subarray and a second bit line arranged in the second memristor subarray; the first bit line is used to input a first analog voltage signal, and the second bit line is used to input a second analog voltage signal;

[0090] The first memristor subarray is used to perform a matrix-vector multiplication operation on the first analog voltage signal and the multiplied data matrix; the second memristor subarray is used to perform a matching operation on the second analog voltage signal and the data matrix to be searched;

[0091] The word line is used to output a calculation result corresponding to the first data or a calculation result corresponding to the second data; the first calculation result includes a calculation result corresponding to the first data or a calculation result corresponding to the second data.

[0092] Specifically, in an embodiment of the present application, the data to be processed includes first data used to perform matrix-vector multiplication operations or second data used to perform matching operations. After the first data or the second data is processed by the input voltage driving module, the corresponding analog voltage signal obtained includes a first analog voltage signal corresponding to the first data, or a second analog voltage signal corresponding to the second data.

[0093] In an embodiment of the present application, the memristor array is controlled by bit lines (BL, SL, SLb) and word lines (WL). The bit lines include a first bit line (BL) arranged in a first memristor subarray, and a second bit line (SL, SLb) arranged in a second memristor subarray, wherein the first bit line (BL) is composed of one bit line for inputting a first analog voltage signal; the second bit line (SL, SLb) is composed of two bit lines for inputting a second analog voltage signal. In this way, the first memristor subarray can perform a matrix-vector multiplication operation on the first analog voltage signal and a multiplied data matrix stored in itself, and the second memristor subarray can perform a data matching operation on the second analog voltage signal and a data matrix to be searched stored in itself.

[0094] Figure 3 is one of the structural schematic diagrams of the three-dimensional self-rectifying memristor array provided in the embodiment of the present application, such as Figure 3As shown, in an embodiment of the present application, the memristor array adopts a three-dimensional self-rectifying memristor array, with a total of t layers of memristor sub-arrays, each layer of array size is m×n, and the solid black dots in the array represent a memristor device. Among them, the three-dimensional self-rectifying memristor array is directly interconnected through word lines WL to form a whole large array, and the array size is m×N, where N=n×t. There are N bit lines and m word lines. The device on each bit line can be arbitrarily defined as being used for matrix-vector multiplication operations, which corresponds to the first bit line (BL); or defined as being used for exact matching operations, which corresponds to the second bit line (SL, SLb).

[0095] The entire t-layer memristor subarray includes two functional arrays, namely, a first memristor subarray and a second memristor subarray. The first memristor subarray is used to perform an i-dimensional matrix-vector multiplication operation, and its array size is m×i. The first bit lines corresponding to the i-dimensional matrix-vector multiplication operation are i, respectively represented as BL[0], BL[1], ..., BL[i-1]. The second memristor subarray is used to perform a j-dimensional exact matching operation, and its array size is m×2j. The second bit lines corresponding to the j-dimensional exact matching operation are 2j, respectively represented as SL[0], SLb[0], SL[1], SLb[1], ..., SL[j-1], SLb[j-1]. In addition, there are m word lines for outputting the first operation result, respectively represented as WL[0], WL[1], ..., WL[m-1]. Wherein, i and j satisfy N=i+2j.

[0096] In an embodiment of the present application, the bit lines of the entire array are input with analog voltage signals by the input voltage driving module, wherein the first bit lines BL[0], BL[1], ..., BL[i-1] respectively input i-dimensional data corresponding to the first analog voltage signal, and the second bit lines SL[0], SLb[0], SL[1], SLb[1], ..., SL[j-1], SLb[j-1] respectively input j-dimensional data corresponding to the second analog voltage signal. The word lines WL[0], WL[1], ..., WL[m-1] are used to output the operation result corresponding to the first data in the form of current, or output the operation result corresponding to the second data in the form of voltage, and output it to the configurable current / voltage sensing module for analog-to-digital conversion.

[0097] The system of the embodiment of the present application can make the memristor subarray that implements the matrix-vector multiplication operation function and the memristor subarray that implements the matching operation function operate more efficiently by further subdividing the signal input of the memristor array and the allocation of bit lines and word lines, further improving the parallelism of the system operation, reducing the system time complexity, and improving the system operation speed and efficiency.

[0098] Figure 42 is a schematic diagram of the structure of the three-dimensional self-rectifying memristor array provided in the embodiment of the present application. Figure 4 As shown, the memristor array has t=2 layers of memristor subarrays, and the array size of each layer of memristor subarray is 4×8. The word lines of the two layers of arrays are connected together through vertical interconnection to form an array of size 4×16, including 4 word lines and 16 bit lines. Among them, the first memristor subarray stores a 6×4 multiplied data matrix, and the second memristor subarray stores a 5×4 to-be-searched data matrix.

[0099] Among them, the 6 bit lines BL[0], BL[1], ..., BL[5] are used to input the first analog voltage signal of the 6-dimensional multiplication vector, and the 10 bit lines SL[0], SLb[0], ..., SL[4], SLb[4] are used to input the second analog voltage signal of the 5-dimensional matching search vector.

[0100] The system of the embodiment of the present application, by splitting the multilayer memristor subarray into a memristor array part for matrix-vector multiplication operations and a memristor array part for matching operations, each array part is used to store the multiplied data matrix and the data matrix to be searched, respectively, and can efficiently implement both precise search and matrix-vector multiplication operations in the same memristor array, which is beneficial to further improve the efficiency and reliability of system operations.

[0101] Figure 5 is a schematic diagram of a flow chart of a memristor array performing a matrix-vector multiplication operation provided in an embodiment of the present application, such as Figure 5 As shown, each column of stored data in the multiplied data matrix is ​​represented by a column of memristors in the first memristor subarray, wherein the high resistance state of the memristor represents that the stored data is "0", and the low resistance state of the memristor represents that the stored data is "1";

[0102] When the data input to a column of memristors of the first memristor subarray is "0", the corresponding input analog voltage signal is defined as signal GND; when the data input to a column of memristors is "1", the corresponding input analog voltage signal is defined as signal Vs;

[0103] The signal Vs is used to indicate a voltage signal for reading the memristor, and the signal GND is used to indicate that the memristor is grounded.

[0104] Specifically, in the embodiments of the present application, only an example of a single device storing binary data is shown, and in actual situations, multiple values ​​may be stored. Figure 5 As shown, the input multiplication vector can be expressed as [a0, a1, ..., a i-1], the first analog voltage signal is inputted by the array bit lines of the first memristor subarray, that is, the first bit lines BL[0], BL[1], ..., BL[i-1], and the first analog voltage signal can be expressed as [V in[0] , V in[1] , …, V in[i-1] ]. Among them, the second bit lines SL[0], SLb[0], ..., SL[j-1], SLb[j-1] are all in a floating state.

[0105] When the first analog voltage signal is V S When , it represents that the data a in the input multiplication vector is "1"; when the input first analog voltage signal is the signal GND, it represents that the input data a is "0".

[0106] In an embodiment of the present application, the multiplied data matrix stored in the first memristor subarray can be expressed as: 0,0 , b 0,1 , …, b 0,i-1 ],[b 1,0 , b 1,1 , …, b 1,i-1 ],…,[b m-1,0 , b m-1,1 , …, b m-1,i-1 ]}, the i×m self-rectifying memristor array, i.e., the first memristor subarray, is mapped into a conductance value matrix, which can be expressed as: {[R 0,0 , R 0,1 , …, R 0,i-1 ],[R 1,0 , R 1,1 , …, R 1,i-1 ],…,[R m-1,0 , R m-1,1 , …, R m-1,i-1 ]}.

[0107] When the resistance state of the self-rectifying memristor is a high resistance state (HRS), the storage data b corresponding to the memristor is "0"; when the resistance state is a low resistance state (LRS), the storage data b corresponding to the memristor is "1"; the output result, i.e., the first operation result, can be expressed as [c0, c1, ..., c m-1 ], the array word line output current [I out[0] , I out[1] ,…,I out[m-1] ] indicates that the output current value is positively correlated with the matrix-vector multiplication result value c, which can be read out by the subsequent current sensing module.

[0108] The system of the embodiment of the present application can effectively implement the function of matrix-vector multiplication operation in the same memristor array by mapping the multiplied data matrix stored in the memristor array and the resistance state of the memristor, thereby improving the speed and efficiency of the system in performing matrix-vector multiplication operation.

[0109] Figure 6 is a schematic diagram of a flow chart of a memristor array performing a matching operation provided in an embodiment of the present application, such as Figure 6 As shown, each column of stored data in the data matrix to be searched is represented by two columns of memristors in the second memristor subarray, wherein, in the two columns of memristors, the high resistance state of any memristor and the low resistance state of its corresponding memristor represent that the stored data is "0", the low resistance state of any memristor and the high resistance state of its corresponding memristor represent that the stored data is "1", and the high resistance state of any memristor and the high resistance state of its corresponding memristor represent that the stored data is "X", and the stored data "X" is used to represent the don't care state;

[0110] When the data input to the two columns of memristors in the second memristor subarray is "0", the two corresponding input analog voltage signals are defined as a sequential combination of the signal GND and the signal Vs; when the data input to the two columns of memristors is "1", the two corresponding input analog voltage signals are defined as a sequential combination of the signal Vs and the signal GND; when the data input to the two columns of memristors is "X", the two corresponding input analog voltage signals are defined as a combination of the signal GND and the signal GND.

[0111] Specifically, in the embodiment of the present application, the process of the second memristor subarray implementing the matching operation is as follows: Figure 6 As shown, the binary input search vector can be expressed as [q0, q1, ..., q j-1 ], the second analog voltage signal is inputted by the array bit lines of the second memristor subarray, namely the second bit lines SL[0], SLb[0], ..., SL[j-1], SLb[j-1], and the voltage signal can be expressed as [V in[0] , V inb[0] , V in[1] , V inb[1] , …, V in[j-1] , V inb[j-1] ]. Among them, the first bit lines BL[0], BL[1], ..., BL[i-1] are all in a floating state.

[0112] Among them, the input voltage (V in , V inb ) represents the one-dimensional binary input data q. When the corresponding second analog voltage signal is a sequential combination of the signal Vs and the signal GND (V S , GND), it represents that the input data q is "1"; when the input second analog voltage signal is the signal GND and the signal V SThe sequence combination (GND, V S ), it represents that the input data q is "0"; when the second analog voltage signal of the input circuit is a combination of the signal GND and the signal GND (GND, GND), it represents that the input data q is "X", that is, the don't care state.

[0113] In an embodiment of the present application, the data matrix to be searched stored in the second memristor subarray can be expressed as {[d 0,0 , d 0,1 , …, d 0,j-1 ],[d 1,0 , d 1,1 , …, d 1,j-1 ],…,[d m-1,0 , d m-1,1 , …, d m-1,j-1 ]}, the second memristor subarray with an array size of 2j×m is mapped into a conductance value matrix, which can be expressed as: {[M 0,0 , Mb 0,0 , M 1,0 , Mb 0,1 , …, M 0,j-1 , Mb 0,j-1 ],[M 1,0 , Mb 1,0 , M 1,1 , Mb 1,1 , …, M 1,j-1 , Mb 1,j-1 ],…,[M m-1,0 , Mb m-1,0 , M m-1,1 , Mb m-1,1 , …, M m-1,j-1 , Mb m-1,j-1 ]}.

[0114] Among them, the storage memristor state (M, Mb) represents a binary storage data d. When it is (LRS, HRS), it means that the storage data d of the memristor is "0"; when it is (HRS, LRS), it means that the storage data d of the memristor is "1"; when it is (HRS, HRS), it means that the storage data d of the memristor is "X". At this time, the matching result, that is, the first operation result, can be expressed as [s0, s1, ..., s m-1 ], the array word line output voltage [V out[0] , V out[1] , …, V out[m-1] ] indicates that when the output voltage is high, it represents “mismatch”; when the output voltage is low, it represents “successful match”.

[0115] It should be noted that when performing voltage reading, due to the self-rectifying characteristics of the self-rectifying memristor, the device with input voltage GND is always in reverse reading resistance, which is much higher than the high impedance state of the device and is approximately equal to an open circuit. S The device on the V S All the devices on the word line are in high-impedance state, and are not charged at this time, so the word line voltage does not increase.

[0116] The system of the embodiment of the present application can effectively implement the function of matching operation in the same memristor array by mapping the to-be-searched data matrix stored in the memristor array with the resistance state of the memristor, thereby improving the speed and efficiency of the system in performing matching operations.

[0117] Figure 7 is a schematic diagram of the result of implementing a matrix-vector multiplication operation using a three-dimensional self-rectifying memristor array provided in an embodiment of the present application, such as Figure 7 As shown in the figure, the data stored in the 6×4 self-rectifying memristor array is [100110, 111010, 001110, 011011], where "1" corresponds to LRS with a resistance of 17.7MΩ; "0" corresponds to HRS with a resistance of 294MΩ. When performing matrix-vector multiplication, the input data of the word line is [011011], where "1" corresponds to the signal V S , which is 2V input voltage; "0" corresponds to signal GND, which is grounding. The output result is in the form of current, and the word line output end is equivalent to grounding. According to Ohm's law and Kirchhoff's current law, the currents output by the four word lines are 0.907μA, 2.705μA, 1.806μA, and 3.604μA respectively. According to the corresponding table of output current and multiplication result (MACV), the output MACVs are 1, 3, 2, and 4 respectively, and the results are consistent with expectations.

[0118] Figure 8 is a schematic diagram of the result of the three-dimensional self-rectifying memristor array provided in the embodiment of the present application realizing the precise matching operation, such as Figure 8 As shown in the figure, the 5×4 data stored in the 10×4 self-rectifying memristor array are [010X1, X0X10, 1X0X1, 10011], where each data is represented by two self-rectifying memristors, "1" corresponds to (HRS, LRS), "0" corresponds to (LRS, HRS), and "X" corresponds to (HRS, HRS). When performing a search, the input search data of the word line is [01X01], at which time "1" corresponds to (V S , GND), "0" corresponds to (GND, V S ), "X" corresponds to (GND, GND). The output result is output in the form of voltage, and the word line output terminal is equivalent to an open circuit.

[0119] Since the word line voltage is between 0-2V, the device connected to GND is equivalent to being in a reverse read state and has a very high resistance, so it is mainly composed of V S The word line is determined by the resistance state of the device at the end. When there are low-resistance devices, the word line is quickly charged to a high level; when all are high-resistance devices, the word line cannot be charged and the level is low. The word line charging levels at a certain moment are 0.01V, 1.98V, 1.87V, and 1.97V. At this time, the voltage comparison reference voltage can be set to 1V. When the word line voltage is higher than the reference voltage, the vector does not match the input vector; when it is lower than the reference voltage, it matches. According to the voltage results, the output results are "match", "mismatch", "mismatch", and "mismatch", which are in line with expectations.

[0120] Based on the contents of the above embodiments, as an optional embodiment, the memristor array includes a resistive memory array, a ferroelectric memory array, a phase change memory array, a magnetic random access memory array or a non-volatile flash memory device array.

[0121] Specifically, in the embodiments of the present application, the memristor array can be a resistive memory array, a ferroelectric memory array, a phase change memory array, a magnetic random access memory array, or a non-volatile flash memory device array. The non-volatile flash memory device array includes a NOR Flash device array or a NAND Flash device array.

[0122] Among them, the spatial arrangement structure of the memristor array includes a three-dimensional horizontal stacking structure similar to a 3D X-Point structure or a three-dimensional vertical stacking structure similar to a 3D V-NAND flash memory, which is not specifically limited in the present application.

[0123] The system of the embodiment of the present application can increase the diversity of methods for manufacturing memristor arrays by utilizing different types of memory arrays and arrangement structures to construct memristor arrays, which is beneficial to reducing the manufacturing cost of memristor arrays and thereby reducing the manufacturing cost of the entire storage-computing integrated circuit.

[0124] Fig. 9 is a flow chart of a computing method of a three-dimensional storage and computing integrated system provided in an embodiment of the present application, which can be applied to any of the aforementioned three-dimensional storage and computing integrated systems, such as Fig. 9 As shown, the method includes:

[0125] Step S1, converting the input data to be processed into an analog voltage signal;

[0126] Step S2, performing a matrix-vector multiplication operation or a matching operation on the pre-stored operation data and the analog voltage signal, and outputting a first operation result of the data to be processed;

[0127] Step S3, based on the signal form of the first operation result, converting the first operation result into a corresponding digital signal;

[0128] Step S4, analyzing the digital signal to determine a second operation result of the data to be processed.

[0129] It should be understood that the method in the above embodiment is applied to the aforementioned three-dimensional storage and computing integrated system, and its implementation principle and technical effect are similar to those described in the above system. The detailed process of the method can refer to the corresponding description process in the above system, and will not be repeated here.

[0130] The operation method of the three-dimensional storage and computing integrated system of the embodiment of the present application is that the system uses an input module to convert the input data to be processed into an analog voltage signal, and the memristor array performs matrix-vector multiplication or matching operation on the stored operation data and the analog voltage signal. Combined with the processing and analysis of the operation results by the perception module and the main processor, the two operation functions of precise search and matrix multiplication can be realized in the same memristor array, which can effectively reduce the storage area and power consumption overhead of the system, and improve the system operation speed and efficiency. At the same time, the system can also be reconfigured without introducing additional arrays and circuits, adapting to the functional requirements of precise matching operations or matrix multiplication operations, and is conducive to improving the integration density and array size of the system circuit.

[0131] In another specific embodiment of the present application, a parallel computing method of a three-dimensional storage and computing integrated system is also provided, in which the memristor array adopts a three-dimensional self-rectifying memristor array, and the specific steps include:

[0132] Step 110: determine which computing function the three-dimensional self-rectifying memristor array needs to implement, and configure a corresponding sensing mode of the configurable current / voltage sensing module.

[0133] Step 120: Initialization operation, turning on all discharge transistors to discharge each word line to ground; after the initialization is completed, turning off all discharge transistors.

[0134] Step 130: The data to be processed, including multiplication data (i.e., the first data) or search data (i.e., the second data), is input into the input voltage driving module through the main processor to convert it into a corresponding analog voltage signal and input it in parallel to each bit line of the three-dimensional self-rectifying memristor array, and the voltage or current signal is output in parallel according to the sensing mode to obtain the first operation result.

[0135] Step 140: The configurable current / voltage sensing module converts the current or voltage signal on the matching line into a corresponding digital signal result according to the sensing mode. When sensing voltage, the digital results "0" and "1" are output according to the voltage level, representing "matching success" and "no match" respectively; when sensing current, the digital result of the current value read is directly output.

[0136] Step 150: The main processor performs digital analysis based on the digital signal result output by the configurable current / voltage sensing module to obtain a second operation result, that is, ultimately obtains a matching result or a multiplication result corresponding to the data to be processed.

[0137] In general, the above technical solution provided by this application can achieve the following beneficial effects compared with the prior art:

[0138] (1) The three-dimensional storage and computing integrated system provided by the present application can realize one array operation in one array parallel reading operation, and has the advantages of low time complexity and high parallelism;

[0139] (2) The three-dimensional storage and computing system provided by the present application can realize two computing functions, matrix-vector multiplication or precise search, by switching the sensing mode of the configurable current / voltage sensing module according to computing requirements, thereby realizing the reconfigurability of the system without introducing additional arrays and circuits, reducing the area and power consumption of the system, and having universality;

[0140] (3) The three-dimensional storage and computing integrated system provided in this application adopts a three-dimensional stacking structure, which has the characteristics of high integration density and large array scale.

[0141] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0142] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0143] In addition, in the embodiments of the present application, the mathematical concepts mentioned are symmetry, equality, parallelism, verticality, etc. These limitations are all for the current state of the art, rather than being absolutely strict definitions in a mathematical sense, and allow a small amount of deviation, approximation to symmetry, approximation to equality, approximation to parallelism, approximation to verticality, etc. are all possible. For example, A and B are parallel, which means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. A and B are perpendicular, which means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A three-dimensional storage and computing system, characterized in that: include: An input module, whose input terminal is connected to the output terminal of the main processor and is used to convert the data to be processed into an analog voltage signal; A memristor array, whose input end is connected to the output end of the input module, is used to perform a matrix-vector multiplication operation or a matching operation on the pre-stored operation data and the analog voltage signal, and output a first operation result of the data to be processed; a sensing module, whose input end is connected to the output end of the memristor array, and is used to convert the first operation result into a corresponding digital signal based on the signal form of the first operation result; And a main processor, whose first input end is used to receive the data to be processed, and whose second input end is connected to the output end of the perception module, is used to analyze the digital signal and determine the second operation result of the data to be processed.

2. The three-dimensional storage and computing integrated system according to claim 1, characterized in that: The memristor array comprises multiple layers of memristor sub-arrays, each column of memristors in each layer of the memristor sub-arrays is connected by a bit line, and each row of memristors in each layer of the memristor sub-arrays is connected by a word line; The memristor sub-arrays of each layer are connected by the word lines; the number of the bit lines and the word lines are determined according to the size of the memristor sub-arrays; The bit line is used to input the analog voltage signal; the word line is used to output the first operation result of the data to be processed.

3. The three-dimensional storage and computing integrated system according to claim 2 is characterized in that: Each of the word lines is connected to a discharge transistor; the discharge transistor is used to perform a data initialization operation before the memristor array performs a matrix-vector multiplication operation or a matching operation.

4. The three-dimensional storage and computing integrated system according to claim 2, characterized in that: The multi-layer memristor sub-array comprises a first memristor sub-array and a second memristor sub-array; The first memristor subarray is used to store a multiplied data matrix so that the multiplied data matrix performs a matrix-vector multiplication operation with the analog voltage signal; The second memristor subarray is used to store a data matrix to be searched, so that the data matrix to be searched is matched with the analog voltage signal; the operation data includes the multiplied data matrix and the data matrix to be searched.

5. The three-dimensional storage and computing integrated system according to claim 4 is characterized in that: The data to be processed includes first data for performing a matrix-vector multiplication operation or second data for performing a matching operation; correspondingly, the analog voltage signal includes a first analog voltage signal corresponding to the first data or a second analog voltage signal corresponding to the second data; The bit lines include a first bit line arranged in the first memristor subarray and a second bit line arranged in the second memristor subarray; the first bit line is used to input the first analog voltage signal, and the second bit line is used to input the second analog voltage signal; The first memristor subarray is used to perform a matrix-vector multiplication operation on the first analog voltage signal and the multiplied data matrix; the second memristor subarray is used to perform a matching operation on the second analog voltage signal and the to-be-searched data matrix; The word line is used to output a calculation result corresponding to the first data or a calculation result corresponding to the second data; the first calculation result includes a calculation result corresponding to the first data or a calculation result corresponding to the second data.

6. The three-dimensional storage and computing integrated system according to claim 4, characterized in that: Each column of stored data in the multiplied data matrix is ​​represented by a column of memristors in the first memristor subarray, wherein a high resistance state of the memristor represents that the stored data is "0", and a low resistance state of the memristor represents that the stored data is "1"; When the data input to a column of memristors of the first memristor subarray is "0", the corresponding input analog voltage signal is defined as a signal GND; when the data input to a column of memristors is "1", the corresponding input analog voltage signal is defined as a signal Vs; The signal Vs is used to indicate a voltage signal for reading the memristor, and the signal GND is used to indicate that the memristor is grounded.

7. The three-dimensional storage and computing integrated system according to claim 6, characterized in that: Each column of stored data in the data matrix to be searched is represented by two columns of memristors in the second memristor subarray, wherein in the two columns of memristors, the high resistance state of any memristor and the low resistance state of its corresponding memristor represent that the stored data is "0", the low resistance state of any memristor and the high resistance state of its corresponding memristor represent that the stored data is "1", and the high resistance state of any memristor and the high resistance state of its corresponding memristor represent that the stored data is "X", and the stored data "X" is used to represent a don't care state; When the data input to the two columns of memristors in the second memristor subarray is "0", the two corresponding input analog voltage signals are defined as a sequential combination of the signal GND and the signal Vs; when the data input to the two columns of memristors is "1", the two corresponding input analog voltage signals are defined as a sequential combination of the signal Vs and the signal GND; when the data input to the two columns of memristors is "X", the two corresponding input analog voltage signals are defined as a combination of the signal GND and the signal GND.

8. The three-dimensional storage and computing integrated system according to any one of claims 1 to 7, characterized in that: The memristor array includes a resistive memory array, a ferroelectric memory array, a phase change memory array, a magnetic random access memory array or a non-volatile flash memory device array.

9. The three-dimensional storage and computing integrated system according to any one of claims 1 to 7, characterized in that: The spatial arrangement structure of the memristor array includes a three-dimensional horizontal stacking structure or a three-dimensional vertical stacking structure.

10. A computing method applied to the three-dimensional storage and computing integrated system as described in any one of claims 1 to 9, characterized in that: include: Convert the input data to be processed into an analog voltage signal; Performing a matrix-vector multiplication operation or a matching operation on the pre-stored operation data and the analog voltage signal, and outputting a first operation result of the data to be processed; Based on the signal form of the first operation result, converting the first operation result into a corresponding digital signal; The digital signal is analyzed to determine a second operation result of the data to be processed.

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