Nor-type memory device and method of manufacturing the same

Abstract

The invention relates to a NOR type memory device and a method of manufacturing the same. The NOR type memory device includes: at least two source / drain contact layers and at least one isolation layer alternately stacked in a vertical direction; a gate structure vertically extending through the source / drain contact layer and the isolation layer; the semiconductor layer is positioned on the periphery of the gate structure; wherein two source / drain contact layers, respectively, immediately above and below the isolation layer, are respectively connected to two bit lines / source lines, and form a memory transistor with the gate structure and the semiconductor layer. The invention provides a novel vertically stacked NOR type memory device structure, which improves the integration density of a memory array, and is simple in structure and simple and feasible in manufacturing process.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a NOR type memory device. Background Art

[0002] Currently, flash memory is divided into NOR type and NAND type, wherein the former arranges the memory cells in parallel and the latter arranges the memory cells in series. Due to the difference in the circuit structure of the memory cells, it is more difficult to increase the integration density of the memory devices in NOR type memory compared to NAND type memory.

[0003] Therefore, many new designs have been proposed to maximize the integration density of storage cells in NOR-type memories. Summary of the invention

[0004] A technical problem to be solved by the present disclosure is to provide a NOR memory device with a novel structure to improve its integration density, and the manufacturing process is simple and easy.

[0005] According to a first aspect of the present disclosure, a NOR-type memory device is provided, comprising: at least two source / drain contact layers and at least one isolation layer alternately stacked in a vertical direction; a gate structure vertically extending through the source / drain contact layers and the isolation layers; and a semiconductor layer located at the periphery of the gate structure; wherein two source / drain contact layers immediately above and below the isolation layer, respectively, are connected to two bit lines / source lines, respectively, and form a storage transistor with the gate structure and the semiconductor layer.

[0006] Optionally, the source / drain contact layers and isolation layers alternately stacked in the vertical direction include h+1 source / drain contact layers and h isolation layers, respectively, where h is a natural number greater than 1; a semiconductor layer is provided around the gate structure; each source / drain contact layer is connected to a respective different bit line / source line; and two source / drain contact layers immediately above and below each isolation layer, the gate structure, and a semiconductor layer located between the corresponding isolation layer and the gate structure form a corresponding storage transistor, thereby forming h storage transistors stacked vertically.

[0007] Optionally, the semiconductor layer is disposed between the gate structure and the source / drain contact layer and the isolation layer, and extends continuously in a vertical direction around the gate structure.

[0008] Optionally, the semiconductor layer includes semiconductor sub-layers that are spaced apart in a vertical direction and are arranged between each isolation layer and the gate structure.

[0009] Optionally, the gate structure contacts the sidewall of the source / drain contact layer; the isolation layer is provided with a recess extending away from the gate structure at a position corresponding to the gate structure; and the semiconductor layer is arranged in the recess and contacts the gate structure and the isolation layer.

[0010] Optionally, the NOR memory device includes a plurality of gate structures arranged in n rows and m columns on a horizontal plane and extending vertically through the source / drain contact layer and the isolation layer, wherein n and m are both natural numbers greater than 1; part or all of the gate structures in the same row are connected to the same word line; part or all of the source / drain contact layers located at the same vertical level in the storage transistors formed by the gate structures in the same column are connected to the same bit line / source line; and the source / drain contact layers located at the same vertical level in the storage transistors formed by the gate structures in adjacent columns are isolated from each other.

[0011] Optionally, the storage transistors formed by the gate structures in the same column share the source / drain contact layer, and one or both ends of the source / drain contact layer in each column are provided with contact holes for connecting metal lines of respective bit lines / source lines.

[0012] Optionally, at least one column of gate structures includes i sub-columns of gate structures, wherein i is a natural number greater than 1; and at least two adjacent sub-columns of gate structures are spaced apart in the column direction.

[0013] Optionally, each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in the column direction; or, each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in the row direction; or, each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in both the row direction and the column direction.

[0014] Optionally, the source / drain contact layer is a metal layer or a polysilicon layer, or the source / drain contact layer is made of a material containing metal or polysilicon; and / or the isolation layer is a silicon oxide layer or a silicon nitride layer, or the isolation layer is made of a material containing silicon oxide or silicon nitride; and / or the semiconductor layer is a polysilicon layer, or the semiconductor layer is made of a material containing polysilicon.

[0015] According to the second aspect of the present disclosure, a method for manufacturing a NOR memory device is provided, comprising: alternately stacking at least two source / drain contact layers and at least one isolation layer in a vertical direction on a substrate; forming a gate hole extending vertically through the source / drain contact layer and the isolation layer; forming a gate structure in the gate hole, and a semiconductor layer located at the periphery of the gate structure; and connecting two source / drain contact layers immediately above and below the isolation layer, respectively, to two bit lines / source lines; wherein the two source / drain contact layers immediately above and below the isolation layer, respectively, form a storage transistor with the gate structure and the semiconductor layer. It should be understood that the order of description of these steps does not mean the order of execution thereof, but the order of execution of these steps can be arbitrarily set as needed.

[0016] Optionally, the source / drain contact layers and isolation layers alternately stacked in the vertical direction include h+1 source / drain contact layers and h isolation layers, respectively, where h is a natural number greater than 1; a semiconductor layer is provided around the gate structure; each source / drain contact layer is connected to a respective different bit line / source line; and two source / drain contact layers immediately above and below each isolation layer, the gate structure, and a semiconductor layer located between the corresponding isolation layer and the gate structure form a corresponding storage transistor, thereby forming h storage transistors stacked vertically.

[0017] Optionally, the step of forming a gate structure in the gate hole and a semiconductor layer located outside the gate structure includes: depositing a semiconductor material in the gate hole to continuously cover the sidewalls of the gate hole to form a continuous semiconductor layer between the gate hole and the source / drain contact layer and the isolation layer; and forming the gate structure on the semiconductor layer in the gate hole.

[0018] Optionally, the step of forming a gate structure in the gate hole and a semiconductor layer located at the periphery of the gate structure includes: selectively etching the isolation layer exposed through the gate hole so that the isolation layer is provided with a recess extending in a direction away from the gate structure at a position corresponding to the gate structure; depositing a semiconductor material in the gate hole to continuously cover the sidewalls of the gate hole so as to form a continuous semiconductor layer between the gate hole and the source / drain contact layer and the isolation layer; etching back the semiconductor material to remove the semiconductor material on the sidewalls of the gate hole corresponding to the position of the source / drain contact layer, leaving the semiconductor material located in the recess of the isolation layer as the semiconductor layer; and forming the gate structure in the gate hole so that the gate structure contacts the sidewalls of the source / drain contact layer and the semiconductor layer.

[0019] Optionally, the step of forming a gate hole extending vertically through the source / drain contact layer and the isolation layer includes: forming a plurality of gate holes extending vertically through the source / drain contact layer and the isolation layer arranged in n rows and m columns on a horizontal plane, wherein n and m are both natural numbers greater than 1; the step of connecting two source / drain contact layers immediately above and below the isolation layer, respectively, to two bit lines / source lines includes: connecting part or all of the source / drain contact layers located at the same vertical level in the storage transistor formed through the gate holes in the same column to the same bit line / source line; and the method also includes: forming a groove penetrating the source / drain contact layers between the gate holes in adjacent columns or the correspondingly formed gate structures, and filling the groove with insulating material so that the source / drain contact layers in the storage transistor formed through the gate holes in adjacent columns are isolated from each other.

[0020] Optionally, in the method, the storage transistors formed by the respective gate holes in the same column share the source / drain contact layer, and contact holes for connecting metal lines of respective bit lines / source lines are formed in a stepped manner at one or both ends of the source / drain contact layer in each column.

[0021] Optionally, in the method, at least one column of gate structures includes i sub-columns of gate structures, wherein i is a natural number greater than 1; and at least two adjacent sub-columns of gate structures are spaced apart in the column direction.

[0022] Optionally, in the method, each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in the column direction; or, each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in the row direction; or, each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in both the row direction and the column direction.

[0023] Optionally, in the method, the source / drain contact layer is a metal layer or a polysilicon layer, or the source / drain contact layer is made of a material containing metal or polysilicon; and / or the isolation layer is a silicon oxide layer or a silicon nitride layer, or the isolation layer is made of a material containing silicon oxide or silicon nitride; and / or the semiconductor layer is a polysilicon layer, or the semiconductor layer is made of a material containing polysilicon.

[0024] Therefore, the present disclosure proposes a novel vertically stacked NOR memory device structure, which improves the integration density of the memory array and has a simple structure and an easy manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0026] Figure 1A An exemplary structure of a NOR memory device according to an embodiment of the present disclosure is shown in a cross-sectional view. Figure 1B for Figure 1A Top view of a NOR memory device with the interlayer dielectric layer removed.

[0027] Figure 2A An exemplary structure of a NOR memory device according to another embodiment of the present disclosure is shown in a cross-sectional view. Figure 2B for Figure 2A Top view of a NOR memory device with the interlayer dielectric layer removed.

[0028] Figure 3A FIG. 1 is a plan view of an array of NOR memory devices according to an embodiment of the present disclosure. Figure 3B Shown along Figure 3A The cross-sectional view is obtained by the dashed line AA in FIG. Figure 3C Shown along Figure 3A Schematic diagram of the cross section obtained by the dotted line BB.

[0029] Figure 4A FIG. 1 is a plan view schematically showing an array composed of NOR memory devices according to another embodiment of the present disclosure, Figure 4B Shown along Figure 4A The cross-sectional view is obtained by the dashed line A2-A2 in FIG. Figure 4C Shown along Figure 4A Schematic diagram of the cross section obtained by the dotted line B2-B2 in FIG.

[0030] Figure 5A FIG. 1 shows an exemplary plan view of an array composed of NOR memory devices according to another embodiment of the present disclosure. Figure 5B Another exemplary plan view of an array composed of NOR memory devices according to yet another embodiment of the present disclosure is shown. Figure 5C Shown along Figure 5B The cross-sectional view is obtained by the dashed line A3-A3 in FIG. Figure 5D Shown along Figure 5B Schematic diagram of the cross section obtained by the dotted line B3-B3 in FIG.

[0031] Figure 6 A circuit diagram of a NOR memory array according to an embodiment of the present disclosure is shown.

[0032] Figure 7 A circuit diagram of an exemplary write operation performed on a storage array by a NOR memory according to an embodiment of the present disclosure is shown.

[0033] Figure 8 A circuit diagram of another exemplary write operation performed on a storage array by a NOR memory according to an embodiment of the present disclosure is shown.

[0034] Fig. 9 A circuit diagram of an exemplary read operation performed on a storage array by a NOR memory according to an embodiment of the present disclosure is shown.

[0035] Fig. 10A FIG. 4 is a plan view of an array of NOR memory devices according to another embodiment of the present disclosure. Fig. 10B Shown along Fig. 10A The cross-sectional view is obtained by the dashed line A4-A4 in FIG. Fig. 10C Shown along Fig. 10A Schematic diagram of the cross section obtained by the dotted line B4-B4.

[0036] Fig.11 A circuit diagram of a NOR memory array according to another embodiment of the present disclosure is shown.

[0037] FIG. 12A to FIG. 12G is a cross-sectional view schematically showing steps in a method of manufacturing a NOR memory device according to an embodiment of the present disclosure.

[0038] FIG. 13A to FIG. 13I is a cross-sectional view schematically showing steps in a method of manufacturing a NOR memory device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] It should be understood that the terms "first" and "second" in this document are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0041] In the description of the present disclosure, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0042] In addition, it should be understood that for ease of description, the sizes of the various components shown in the drawings are not necessarily drawn in accordance with the actual proportional relationship, for example, the thickness or width of some layers may be exaggerated relative to other layers. Technologies, methods and devices known to ordinary technicians in the relevant fields may not be discussed in detail, but in the case of applying these technologies, methods and devices, these technologies, methods and devices should be regarded as part of this specification.

[0043] With the development of semiconductor technology, the size of devices is getting smaller and smaller, but it is currently difficult to further reduce the size in the plane direction. To this end, as mentioned above, in order to improve the integration density of the memory cell, the present disclosure turns to three-dimensional (3D) stacking technology and proposes a new type of NOR memory device structure that is easy to stack vertically, which can effectively reduce the area of ​​a single memory cell and meet the market's requirements for large capacity and small size of NOR memory.

[0044] The novel structure and manufacturing method of the present disclosure will be described in more detail below in conjunction with the accompanying drawings. In this article, in some embodiments, the memory device may include one or more memory transistors stacked in the vertical direction. In other embodiments, the memory device may include multiple groups of vertically stacked memory transistors arranged in an array on a horizontal plane, which may also be referred to as a memory array in this case, which is usually made in one chip. Usually, in addition to the memory array, the memory may also include a peripheral circuit for reading / writing the memory array, and the peripheral circuit can be made in the same or different chip as the memory array.

[0045] Figure 1A An exemplary structure of a NOR memory device according to an embodiment of the present disclosure is shown in a cross-sectional view. Figure 1B for Figure 1A FIG. 1 is a top view of a NOR memory device after removing an inter-layer dielectric layer (ILD) 110 .

[0046] In the present disclosure, a memory device is generally fabricated on a substrate, a horizontal plane refers to a surface parallel to a main surface of the substrate, and a vertical direction refers to a direction perpendicular to the main surface of the substrate. Figure 1A The cross-sectional view shows the stacking structure of the memory device in the vertical direction. It should be understood by those skilled in the art that the present disclosure has no limitation on the substrate used for manufacturing, and the substrate can be various substrates, such as a single crystal silicon wafer, a SOC substrate, etc., and in some cases, the substrate can be removed after the memory device is manufactured. Therefore, the substrate is omitted in some drawings of the present disclosure for the sake of clarity. In some embodiments, there may also be an insulating layer between the substrate and the memory device to isolate the influence of the substrate on the memory device.

[0047] In some embodiments, Figure 1A As shown in the cross-sectional view of FIG. 1 , the NOR memory device may include three vertically stacked memory transistors (i.e., first to third memory transistors MT1-MT3). In one implementation, each memory transistor may be used as a memory cell to store 1 bit of information. In another implementation, each memory transistor may also be used to store more than 1 bit of information.

[0048] Specifically, if Figure 1A As shown, the NOR memory device includes source / drain contact layers and isolation layers alternately stacked in a vertical direction, which are, from bottom to top, a first source / drain contact layer 101, a first isolation layer 102, a second source / drain contact layer 103, a second isolation layer 104, a third source / drain contact layer 105, a third isolation layer 106, and a fourth source / drain contact layer 107. Of course, the number of source / drain contact layers and isolation layers is only for illustration, and does not limit the protection scope of the present disclosure.

[0049] like Figure 1A and Figure 1B As shown, the NOR memory device also includes a gate structure 108 extending vertically through each source / drain contact layer and isolation layer, and a semiconductor layer 109 covering the periphery of the gate structure 108. These source / drain contact layers and isolation layers surround the gate structure 108 and the semiconductor layer 109 extending in the vertical direction, and are arranged along the direction in which the gate structure 108 extends. The semiconductor layer 109 serves as the active region of each storage transistor, including a channel region, a source region, and a drain region. Each source / drain contact layer is used to lead out the source / drain of each storage transistor and connect it to its corresponding bit line / source line, thereby forming three storage transistors arranged in the vertical direction (i.e., the source-drain current flows in the vertical direction). Figure 1A and Figure 1BIn the illustrated embodiment, the semiconductor layers 109 between each isolation layer and the gate structure 108 are continuous with each other, and cover the sidewalls of the gate structure 108 and each source / drain contact layer and the isolation layer. In other embodiments, the semiconductor layers 109 between each isolation layer and the gate structure 108 may be spaced apart from each other, and only cover the sidewalls of the gate structure 108 and each isolation layer; for example, this will be described in detail later in conjunction with FIG. 2 .

[0050] Although Figure 1A and Figure 1B Only one figure is used to represent the gate structure 108 used as the gate of the storage transistor, but it should be understood that the gate structure 108 can be composed of multiple layers, which at least include a functional layer for storing information and a conductive layer for applying voltage. For example, in some embodiments, the gate structure 108 can include a gate oxide layer, a charge trapping layer, an isolation layer, and a gate metal layer from the outside to the inside. Those skilled in the art will understand that the gate structure 108 is not limited to this, but can be set accordingly according to the type of storage transistor. Figure 1B The plan view of FIG. 1 shows that the cross section of the gate structure 108 can be circular, that is, the gate structure 108 is cylindrical; of course, this is just an example, and the embodiment of the present disclosure does not limit this, and the cross section of the gate structure 108 can be any shape. It should be understood that Figure 1B The shape of the semiconductor layer 109 between the gate structure 108 and the isolation layers shown in the plan view is also only exemplary, and the present disclosure is not limited thereto.

[0051] In some embodiments, Figure 1A and Figure 1B As shown, the gate metal layer in the gate structure 108 can be connected to the upper word line (Word Line, WL) through the contact hole in the interlayer dielectric layer (ILD) 110 located above, and each source / drain contact layer can be connected to the upper bit line / source line BL1-BL4 through the corresponding contact holes arranged in a step-like manner in the ILD 110. It should be understood that the word line and the bit line / source line can be located in one or more metal layers above the ILD 110, which can be located in the same or different metal layers, and the upper metal layers are omitted in the drawings for clarity, and the contact holes in the ILD 110 are used to refer to the word line or the bit line / source line to be connected in the end. Although not shown in the figure, in some embodiments, there may be other components on the steps formed by the stepped contact holes for the bit line / source line BL1-BL4 actually manufactured, such as spacers and metal silicides, which will be described later when discussing the manufacturing process.

[0052] In such Figure 1A and Figure 1BIn the illustrated embodiment, two source / drain contact layers immediately above and below each isolation layer are connected to two bit lines / source lines, respectively, and form a corresponding storage transistor with the gate structure 108 and the semiconductor layer 109 located between the corresponding isolation layer and the gate structure 108. For example, the first storage transistor MT1 includes: a first source / drain contact layer 101 connected to the bit line / source line BL1, a second source / drain contact layer 103 connected to the bit line / source line BL2, a gate structure 108, and at least a portion of the semiconductor layer 109 located between the gate structure 108 and the first isolation layer 102; the second storage transistor MT2 includes: a second source / drain contact layer 103 connected to the bit line / source line BL2, a third source / drain contact layer 105 connected to the bit line / source line BL3, a gate structure 108, and at least a portion of the semiconductor layer 109 located between the gate structure 108 and the second isolation layer 104; and the third storage transistor MT3 includes: a third source / drain contact layer 105 connected to the bit line / source line BL3, a fourth source / drain contact layer 107 connected to the bit line / source line BL4, a gate structure 108, and at least a portion of the semiconductor layer 109 located between the gate structure 108 and the third isolation layer 106. That is, two upper and lower adjacent storage transistors share a source / drain contact layer and also share a bit line / source line.

[0053] Since the source / drain regions at the upper and lower ends of the storage transistor are structurally the same, the source / drain regions at the upper and lower ends of the storage transistor can be used as both the source region and the drain region, and the upper and lower source / drain contact layers can be used as both the source region contact and the drain region contact, so the bit lines / source lines BL1-BL4 connected to each source / drain contact layer can also be used as both the bit lines (Bit Line, BL) of the storage transistor and the source lines (Source Line, SL), and since each two adjacent storage transistors share a bit line / source line, in some cases the bit line / source line of a storage transistor can also be used as the bit line / source line of the adjacent storage transistor. In other words, the bit lines and source lines of each storage transistor are not fixed, but are determined according to the voltages applied respectively during actual use. In this article, for the sake of simplicity and convenience, the bit lines and source lines are not distinguished in the accompanying drawings, but all metal lines connected to the source / drain regions are collectively referred to as bit lines / source lines BL. In actual use, the bit line / source line BL (BL1-BL4) in any of the accompanying drawings can be used as either a source line or a bit line; that is, when the source voltage required by the storage transistor is applied to the bit line / source line BL in any of the accompanying drawings, the metal line serves as the source line of the storage transistor, and the metal line can be called a source line at this time; when the drain voltage required by the storage transistor is applied to the bit line, the metal line serves as the bit line of the storage transistor, and the metal line can be called a bit line at this time.

[0054] Figure 1A and Figure 1B The case of three stacked storage transistors is shown only as an example, but more or fewer storage transistors can be stacked as needed, which share the same vertically extended gate structure, and only the number of source / drain contact layers and isolation layers alternately stacked in the vertical direction is changed and a semiconductor layer is ensured between each isolation layer and the gate structure. For example, in some embodiments, only one storage transistor can be stacked in the vertical direction, which includes two source / drain contact layers and an isolation layer alternately stacked in the vertical direction. For example, in other embodiments, h (h is a natural number greater than 1) storage transistors can be stacked in the vertical direction; in this case, the NOR-type memory device can include (h+1) source / drain contact layers and h isolation layers alternately stacked in the vertical direction, wherein a semiconductor layer exists between each isolation layer and the gate structure, and the (h+1) source / drain contact layers are respectively connected to (h+1) bit lines / source lines. Two source / drain contact layers respectively located immediately above and below each isolation layer, a gate structure, and a semiconductor layer located between the corresponding isolation layer and the gate structure form a corresponding storage transistor, thereby forming h storage transistors stacked vertically.

[0055] In some embodiments, the source / drain contact layer used in the present disclosure may be made of a material containing metal (e.g., tungsten) or polysilicon, or the source / drain contact layer may be made of metal or polysilicon. In some embodiments, the isolation layer used in the present disclosure may contain silicon oxide or silicon nitride, or the isolation layer may be made of silicon oxide or silicon nitride. In some embodiments, the semiconductor layer used in the present disclosure may be made of a material containing polysilicon, or the semiconductor layer may be made of polysilicon. In some embodiments, any of the metal lines such as word lines, bit lines / source lines, and corresponding contact holes used in the present disclosure may be made of a material containing tungsten, or any of the metal lines such as word lines, bit lines / source lines, and corresponding contact holes may be made of tungsten. A specific example of the manufacturing process of a NOR memory device according to the present disclosure will be described in detail later in conjunction with the accompanying drawings.

[0056] Those skilled in the art will appreciate that the NOR memory device disclosed herein is not limited to the above combination. Figure 1A and Figure 1BFor example, in some other embodiments, an insulating layer may be provided between adjacent storage transistors in the vertical direction, that is, an insulating layer may be provided between source / drain contact layers of adjacent storage transistors, so that each storage transistor has two independent source / drain contact layers without sharing the source / drain contact layer, and thus, as in a conventional NOR type memory device, each storage transistor is provided with independent bit lines and source lines. However, compared with the structure in which the insulating layer is provided in this way, the structure according to the present disclosure Figure 1A and Figure 1B The structure of the NOR memory device is simpler and easier to manufacture, and the number of required bit lines and source lines is reduced, thereby further improving the integration density.

[0057] Figure 2A An exemplary structure of a NOR memory device according to another embodiment of the present disclosure is shown in a cross-sectional view. Figure 2B for Figure 2A FIG. 1 is a top view of a NOR memory device with the ILD 210 removed.

[0058] Figure 2A , Figure 2B and Figure 1A , Figure 1B The difference between the exemplary structures of the NOR memory devices shown mainly lies in the arrangement of the semiconductor layers in each storage transistor. Figure 1A , Figure 1B In the embodiment shown, in each vertically stacked memory transistor, the semiconductor layers between the isolation layer and the gate structure are continuous with each other, and Figure 2A , Figure 2B In the illustrated embodiment, in each vertically stacked memory transistor, the semiconductor layers between the isolation layer and the gate structure may be spaced apart from each other.

[0059] For example, Figure 2A As shown, the semiconductor layer 209 in the first storage transistor MT201, the semiconductor layer 211 in the second storage transistor MT202, and the semiconductor layer 212 in the third storage transistor MT203 all surround the gate structure 208 to form their own active regions, but are separated from each other by a source / drain contact layer. Figure 2A The semiconductor layer shown is located below the source / drain contact layer and is therefore Figure 1B The top view is different. Figure 2B The semiconductor layer is not visible in the top view.

[0060] For example, in Figure 2AIn the illustrated embodiment, the gate structure 208 shared by each storage transistor contacts the side walls of each source / drain contact layer 201, 203, 205 and 207, the side walls of each isolation layer 202, 204 or 206 are recessed in the horizontal direction relative to the side walls of the source / drain contact layers immediately above and below them, and each semiconductor layer 209, 211 or 212 contacts the gate structure 208 and the side walls of the corresponding isolation layer 202, 204 or 206, and is located at the portion of the side walls of the corresponding isolation layer 202, 204 or 206 that is recessed in the horizontal direction relative to the side walls of the source / drain contact layers.

[0061] Compared to Figure 1A and Figure 1B In the example shown in which the semiconductor layers are continuous with each other, spacing the semiconductor layers in the vertically stacked storage transistors apart from each other can reduce mutual influence between the storage transistors, for example, avoiding interference caused by channel leakage in other storage transistors sharing the same gate structure.

[0062] It should be understood that in addition to the arrangement of the semiconductor layers discussed above, the present disclosure Figure 2A and Figure 2B The specific structure of the NOR memory device shown in FIG. 1 may refer to the drawings of other embodiments of the present disclosure and their related discussions, for example, may refer to FIG. Figure 1A and Figure 1B The contents of the illustrated embodiments will not be described in detail here. Those skilled in the art will understand that the present disclosure is not limited to the structure of the aforementioned NOR type memory device, and any other suitable structure may also be adopted.

[0063] The NOR memory device according to the present disclosure is discussed in detail above by taking a single group of vertically stacked memory transistors as an example, and in some embodiments, multiple groups of vertically stacked memory transistors are usually arranged in an array on a horizontal plane to form a three-dimensionally arranged memory array. The structures of some exemplary memory arrays arranged in three dimensions, their circuits, and manufacturing processes, etc. will be discussed below in conjunction with the accompanying drawings.

[0064] Figure 3A Schematically shows a plan view of a NOR type memory array according to an embodiment of the present disclosure, Figure 3B An example is shown along Figure 3A The cross-sectional view is obtained by the dashed line AA in FIG. Figure 3C An example is shown along Figure 3A Schematic diagram of the cross section obtained by the dotted line BB.

[0065] like Figure 3AAs shown, the NOR memory array 300 may include a plurality of gate structures 308 arranged in 3 rows×3 columns on a horizontal plane, wherein the gate structure 308 may have a structure in any of the aforementioned embodiments, vertically extending through alternately stacked source / drain contact layers and isolation layers, and serving as a gate of one or more vertically stacked memory transistors. The specific structure of each memory transistor may be Figure 1A-1B The structure described in the embodiment shown is of course not limited to this. It should be understood that Figure 3A In order to more clearly show the connection relationship between each row of gate structures and word lines WL1-WL3 in the plan view, the word lines WL1-WL3 are drawn as blank long rectangular frames so that the gate structures under the word lines and the contact holes connecting the word lines can be exposed.

[0066] Those skilled in the art will understand that the number of rows and columns illustrated in the present disclosure is only exemplary, and in practice, any n×m array can be made as needed, where n and m are natural numbers greater than 1. Those skilled in the art will understand that the use of an n×m layout is only one of the ways to implement the technical solution of the embodiment of the present disclosure, and the embodiment of the present disclosure is not limited thereto. At the same time, the "n rows" and "m columns" referred to in all embodiments of the present disclosure only refer to the arrangement of multiple gate structures in an array, and do not limit these gate structures to be arranged in a completely neat array as shown in the figure. The rows and columns in the array are not determined by the position of the gate structure, but by the connection relationship of the storage transistor formed by it (for example, the connection relationship with the word line, bit line / source line, etc.). In other words, the "column" referred to in the full text of each embodiment of the present disclosure may be a completely virtual concept, which may be a gate structure arranged in a horizontal direction or vertical direction approximately on a horizontal plane, or even a gate structure arranged in an arc or curve shape, which may be based on artificial settings / divisions. Similarly, the "row" referred to in the various embodiments of the present disclosure may be a completely virtual concept, which may be a gate structure arranged in a horizontal direction or a vertical direction approximately on a horizontal plane, or even a gate structure extended and arranged in an arc or curve shape, and may be based on artificial settings / divisions. The storage array referred to in the various embodiments of the present disclosure includes a gate structure of an n×m array, which does not limit the number of gate structures included in each row to be the same, nor does it limit the number of gate structures included in each column to be the same.

[0067] like Figure 3A The structure shown includes three rows of gate structures 308, and the number of gate structures 308 included in the three rows is equal, that is, each row includes three gate structures 308; but this is only an example and does not limit the protection scope of the technical solution disclosed in the present invention; those skilled in the art can understand that the number of gate structures 308 included in each row can be the same or different. Figure 3A The structure shown includes three columns of gate structures 308, and the number of gate structures 308 included in the three columns is equal, that is, each column includes three gate structures 308; but this is only an example and does not limit the protection scope of the technical solution disclosed in the present invention; those skilled in the art can understand that the number of gate structures 308 included in each column can be the same or different. Of course, if Figure 3A The method shown is 3×3, that is, n=3, m=3; and those skilled in the art will understand that n and m can be any numbers, and the embodiments of the present disclosure are not limited to this. In the present disclosure, the gate structure 308 can have, for example Figure 1A-1B The structure shown is used as a common gate for a group of storage transistors stacked in the vertical direction. The group of storage transistors may include h (h is a natural number greater than 1) storage transistors, and the storage transistor refers to a transistor with a data storage function. Thus, the storage transistors can form a three-dimensionally arranged storage array of n×m×h. Of course, it should be understood by those skilled in the art that the embodiment of the present disclosure does not limit the number of vertically stacked storage transistors in each group, which may be the same or different. Since multiple storage transistors can be stacked in the vertical direction, that is, multiple storage transistors only occupy the footprint of one storage transistor, the integration density of the storage array can be greatly improved.

[0068] In some embodiments, Figure 3B and Figure 3C As shown in the cross-sectional view, combined with the previous Figure 1A-1B Similar to the description, each gate structure 308 can form a group of vertically stacked memory transistors (hereinafter also referred to as a memory transistor group), that is, each gate structure 308 and its surrounding source / drain contact layers 301, 303, 305, 307 and semiconductor layer 309 can form three vertically stacked memory transistors (i.e., the first to third memory transistors MT301-MT303). In one implementation, each memory transistor can be used as a memory cell to store 1 bit of information. Figure 3B and Figure 3CAs shown, each storage transistor group includes 3 vertically stacked storage transistors; of course, this is only an example, and is not a limitation on the protection scope of the technical solution disclosed in the present invention; those skilled in the art can understand that the number of storage transistors included in each storage transistor group can be the same or different. For example, one or more storage transistor groups may include only 2 storage transistors (i.e., h=2 in a part of the storage transistor groups), while other storage transistor groups may include any number of storage transistors (e.g., h=3 in another part of the storage transistor groups); for another example, one or more storage transistor groups may include 4 storage transistors (i.e., h=4 in a part of the storage transistor groups), while other storage transistor groups may include any number of storage transistors (e.g., h=3 in another part of the storage transistor groups).

[0069] like Figure 3B and Figure 3C As shown, each storage transistor group can adopt the previous Figure 1A-1B The structure described in the embodiment shown is of course not limited to this. Figure 3B and Figure 3C In order to more clearly show the connection relationship between the gate structure and the word line, a metal line is drawn above the ILD 310 as the word line, but it should be understood that the present disclosure is not limited thereto. In some embodiments, the word lines WL of each row can be arbitrarily distributed in one or more metal layers above the ILD 310. Figure 3B and Figure 3C Although not shown in the figure, it should be understood that the respective bit lines / source lines BL for the source / drain contact layers of the respective columns and levels may also be arbitrarily distributed in one or more metal layers above the ILD 310 .

[0070] In addition, if Figure 3A and Figure 3C In the example shown, three storage transistor groups in the same column share four vertically stacked source / drain contact layers, namely, the first source / drain contact layer 301, the second source / drain contact layer 303, the third source / drain contact layer 305, and the fourth source / drain contact layer 307; that is, (h+1) source / drain contact layers are provided in the same column, and the (h+1) source / drain contact layers each extend along the direction of the column, and all storage transistors in the column use the (h+1) source / drain contact layer as their own source / drain contact layer. Figure 3A and Figure 3C As shown, the source / drain contact layers of the storage transistors at the same level in the vertical direction (also referred to as the same vertical level) are continuous. Therefore, the source / drain regions of all storage transistors on the same layer in the same column can be electrically connected using only one contact hole, further improving the integration density. The same layer refers to, for example, Figure 3B As shown, a storage transistor at the bottom of the 1st column, the 2nd column, and the 3rd column is called the same layer; correspondingly, a storage transistor at the top of the 1st column, the 2nd column, and the 3rd column is also called the same layer; a storage transistor in the middle of the 1st column, the 2nd column, and the 3rd column is also called the same layer.

[0071] For example, it can be Figure 3A and Figure 3C As shown in the figure, a stepped contact area 320 is made at the end of each column, wherein the stepped contact area 320 is provided with contact holes connecting the source / drain contact layers, and the contact holes are used to lead out the four source / drain contact layers and electrically connect them to the four metal lines (i.e., bit lines / source lines) BL31-BL34. It should be understood that the embodiments of the present disclosure are not limited to Figure 3A and Figure 3C Instead of the method shown in the figure for leading out each source / drain contact layer, various methods can be used; for example, in some possible embodiments, more than one contact hole for connecting to the corresponding metal line can be formed on one or more source / drain contact layers in the stepped contact area 320 to achieve a better electrical connection effect; in other possible embodiments, stepped contact areas can be made at both ends of each column, wherein the stepped contact areas at both ends are provided with contact holes for connecting each source / drain contact layer to the corresponding bit line / source line, and the contact holes at both ends of the same level are electrically connected to the same bit line / source line to reduce resistance and achieve a better electrical connection effect.

[0072] Of course, if Figure 3A and Figure 3C In the illustrated example, the h storage transistors in the same column all share the (h+1) source / drain contact layers. Those skilled in the art will appreciate that some storage transistors in the same column may share some source / drain contact layers, and some storage transistors may share other source / drain contact layers or be provided with independent source / drain contact layers. Correspondingly, the contact holes may also be arranged according to the structure of the source / drain contact layers, which will not be described in detail here.

[0073] In addition, if Figures 3A to 3CAs shown, each gate structure 308 of the same row is connected to the same word line WL1, WL2 or WL3, and as mentioned above, the storage transistors at the same stacking level in the storage transistor group formed by each gate structure 308 of the same column share the same bit line / source line. In addition, an isolation portion 330 is provided between the storage transistor groups formed by the gate structures 308 of adjacent columns to isolate the source / drain contact layers of the storage transistors in different columns, so as to isolate the bit lines / source lines for the storage transistors in different columns. In other words, the source / drain contact layers at the same vertical level in the storage transistors formed by the gate structures of adjacent columns are isolated from each other. Therefore, according to the storage array structure disclosed in the present invention, a storage cell can be uniquely determined only by word lines and bit lines; one of the storage cells is a storage transistor. Therefore, the architecture of the storage array disclosed in the present invention is simple, the design difficulty is greatly reduced, and the manufacturability is improved. Moreover, since there is an isolation portion between the bit lines of different columns, the leakage and crosstalk on the bit lines are reduced.

[0074] It should be understood that, although different filling patterns are used in the various drawings of the present disclosure to distinguish insulating components such as vertically stacked isolation layers, isolation portions between adjacent columns, and interlayer dielectric layers, in some possible embodiments, some or all of these insulating components may include the same insulating material (e.g., silicon oxide and / or silicon nitride), or be composed of the same insulating material, which may be the same material layer in essence, but may be formed in different manufacturing process steps or have different functions. Similarly, although different filling patterns are used in the various drawings of the present disclosure to distinguish conductive components such as contact holes, word lines, bit lines / source lines, source / drain contact layers, contact metals, and through holes, in some possible embodiments, some or all of these conductive components may include the same conductive material (e.g., tungsten), or be composed of the same conductive material, which may be the same material layer in essence, but may have different functions or may be formed in different manufacturing process steps.

[0075] It should be understood that in order to make the illustration clear and highlight the key points, there may be blank areas between some components in the cross-sectional view of the present disclosure, which does not limit these places to be empty. In some implementations, all or part of these blank areas can be filled with electrical insulating materials in actual devices to isolate and support these components.

[0076] Figure 4A FIG. 1 is a plan view schematically showing an array composed of NOR memory devices according to another embodiment of the present disclosure, Figure 4B Shown along Figure 4A The cross-sectional view is obtained by the dashed line A2-A2 in FIG. Figure 4C Shown along Figure 4A Schematic diagram of the cross section obtained by the dotted line B2-B2 in FIG.

[0077] FIG. 4A to FIG. 4C The exemplary memory array shown is Figures 3A to 3C The exemplary memory arrays shown differ primarily in the arrangement of semiconductor layers in each memory transistor. Figures 3A to 3C In the embodiment shown, each storage transistor group may adopt, for example, Figure 1A-1B In the structure described in the embodiment shown, that is, in each vertically stacked memory transistor, the semiconductor layers between the isolation layer and the gate structure are continuous with each other; FIG. 4A to FIG. 4C In the embodiment shown, each storage transistor group may adopt, for example, Figure 2A-2B In the structure described in the illustrated embodiment, that is, in each vertically stacked memory transistor, the semiconductor layers between the isolation layer and the gate structure may be spaced apart from each other, for example FIG. 4A to FIG. 4C The semiconductor layers 409, 411 and 412 are shown separated by source / drain contact layers.

[0078] It should be understood that the specific structure of each storage transistor group in the storage array of this embodiment is not limited to Figure 2A-2B The structure described in the illustrated embodiment may also adopt any other suitable structure as long as the semiconductor layers in each vertically stacked memory transistor are spaced apart from each other.

[0079] It should be understood that in addition to the arrangement of the semiconductor layers discussed above, the present disclosure FIG. 4A to FIG. 4C The specific structure of the storage array shown can refer to the drawings and related discussions of other embodiments of the present disclosure, for example, can refer to Figures 3A to 3C The contents of the illustrated embodiments will not be described in detail here. Those skilled in the art will understand that the present disclosure is not limited to the aforementioned NOR type memory array structure, and any other suitable structure may also be adopted.

[0080] In order to arrange the storage array more closely and further improve the array density, the Figure 3A or Figure 4A Part of the gate structure of one column in the memory array is moved a certain distance in the row direction, so that there is a gap between the adjacent gate structures in both the column direction and the row direction, that is, the spacing between adjacent gate structures is a distance in an oblique direction, thereby reducing the spacing in the column direction and / or the row direction, and further reducing the longitudinal size and / or the lateral size of the entire memory array. For example, at least one column of gate structures may include i sub-columns of gate structures, where i is a natural number greater than 1; wherein at least two adjacent sub-columns of gate structures are spaced in the column direction. That is to say, the adjacent gate structures in the row direction are not as shown in FIG. Figure 3A or Figure 4AIn that case, the positions in the column direction are not completely overlapped, but staggered by a certain distance. That is to say, an improved memory array arrangement can be proposed, which can reduce the area occupied by the entire memory array arranged on the horizontal plane, and further improve the array density. Such an arrangement is particularly useful in some cases. For example, in some embodiments, although a smaller-sized process can be used to manufacture the memory array, the size of the gate structure (such as the diameter of the gate circular hole) cannot be further reduced. For example, in some embodiments, the minimum size of the gate structure (including its width (diameter of the circular hole) and the spacing) may reach about 100nm and cannot be further reduced, and a smaller-sized process (such as a 40nm or 28nm process) can be used to manufacture the memory array, that is, the minimum size of the metal line (word line WL) connecting the gate structure (including its width and spacing) can be about 40nm or 28nm. At this time, the above-mentioned staggered arrangement method can minimize the area occupied by the gate structure array.

[0081] This improved method will be more clearly presented below with reference to the accompanying drawings.

[0082] Figure 5A An exemplary plan view of an array composed of NOR memory devices according to yet another embodiment of the present disclosure is shown.

[0083] It should be understood that Figure 5A The main intention is to show the arrangement of the gate structures in each column on the horizontal plane, so for the sake of clarity, Figure 5A The bit line / source line in the stepped contact area is not shown, only a blank circle is used to represent the gate structure 5008, and the contact hole between it and the word line is not shown. The overlap of the blank gate structure and the blank word line indicates that the two are connected. Figure 5A The storage transistor group formed by each gate structure 5008 shown can be formed by, for example, combining the above Figure 1A-1B , Figure 2A-2B , Figure 3A-3C or Figure 4A-4C The specific configurations described in the embodiments, or the combination of the configurations in these embodiments, or any other suitable configurations are not described in detail here, and therefore are not shown. Figure 5A For the corresponding cross-sectional view, reference may be made to the structure of the cross-sectional view described in the aforementioned embodiments.

[0084] like Figure 5A As shown, the NOR memory array 5001 includes a plurality of gate structures arranged in 6 rows×2 columns on a horizontal plane. Figure 3AAs mentioned above, the number of rows and columns and the number of gate structures included in each row / column illustrated in the present disclosure are merely exemplary. In practice, any n×m array can be made as needed, where n and m are natural numbers greater than 1, and the number of gate structures included in each row / column can also be arranged as needed.

[0085] like Figure 5A As shown, in some embodiments, two or more adjacent sub-columns may be set in one column, and each sub-column may include two or more gate structures; wherein the gate structures of adjacent sub-columns are staggered in the row direction. In some embodiments, the gate structures in each sub-column are arranged along the column direction, for example, aligned in the column direction, but the embodiments of the present disclosure are not limited thereto, and may also be arranged in other ways (for example, along a certain curve) in the column direction. Although Figure 5A An exemplary structure is shown in which one column includes two sub-columns. However, those skilled in the art will appreciate that this exemplary description is not a limitation on the embodiments of the present disclosure. Any number of sub-columns may be arranged in one column while ensuring the feasibility of technical feasibility. For example, three or more sub-columns may be arranged in one column.

[0086] In one implementation, in order to more densely arrange the storage array, Figure 5A Each gate structure 5008 in the two sub-columns has the same distance from the gate structure 5008 adjacent to it in the column direction, for example, the distance may be the minimum column spacing of the process or design. In one implementation, Figure 5A Each gate structure 5008 in the two sub-columns has the same distance with each gate structure 5008 adjacent to it in the row direction, for example, the distance can be the minimum row spacing of the process or design. In the above embodiment, the minimum row spacing can be the same as or different from the minimum column spacing. In a possible implementation, in order to arrange the storage array more tightly, each gate structure 5008 can have the same distance (for example, the minimum spacing) with each gate structure 5008 adjacent to it in the column direction or the row direction. In other words, the gate structures 5008 can be arranged in the most compact hexagonal pattern to further improve the array density.

[0087] like Figure 5A As shown, since the size of the metal line (word line WL) connecting the gate structure 5008 can be smaller than the size of the gate structure 5008, the gate structures 5008 in the two sub-columns can be connected to the corresponding word lines WL respectively, and the two word lines WL extend side by side with each other without contact.

[0088] In addition, in some embodiments, the number of sub-columns in each column can be appropriately designed according to the ratio of the minimum size of the gate structure to the word line WL, so as to better reduce the size of the entire memory array and improve the integration density. For example, in some embodiments, the minimum size of the gate structure can be exemplarily around 100nm, wherein the minimum size can refer to the width of the gate structure or the spacing of the gate structure; wherein the width of the gate structure can be the diameter of the circular hole. The minimum size of the metal line (word line WL) connecting the gate structure can be exemplarily around 28nm, and the minimum size includes the width of the metal line and the spacing between adjacent metal lines. It can be seen that the ratio of the minimum size of the gate structure to the word line WL in the above example can be around 4:1. In the above example, the minimum size of the gate structure and the word line WL can determine that a maximum of 4 sub-columns can be staggered in the same column, such as the following Figure 5B Of course, the above-mentioned minimum size of the gate structure and the minimum size of the word line WL are only examples and are not limitations of the embodiments of the present disclosure.

[0089] Figure 5B Another exemplary plan view of an array composed of NOR memory devices according to yet another embodiment of the present disclosure is shown. Figure 5C Shown along Figure 5B The cross-sectional view is obtained by the dashed line A3-A3 in FIG. Figure 5D Shown along Figure 5B Schematic diagram of the cross section obtained by the dotted line B3-B3 in FIG.

[0090] exist Figure 5B In the figure, the gate structure 508 of four sub-columns can be arranged alternately in the same column. For example, the structure of the gate structure 508 can refer to the drawings of other embodiments of the present disclosure, corresponding to a vertically stacked storage transistor group. Figure 5B The construction method of the gate structure 508 shown in FIG. 5 may refer to, for example, Figure 1A-1B , Figure 2A-2B , Figure 3A-3C or Figure 4A-4C The gate structure in the embodiment may also be a gate structure of any other shape or structure.

[0091] like Figure 5B As shown, since there are two gate structures 508 placed side by side in the row direction in column 1, as shown in the previous Figure 3A-3C or Figure 4A-4C It is difficult to stagger the connection by using a metal layer located above the gate structure 508 as the word line WL as in FIG. Figure 3A-3C or Figure 4A-4C A metal layer is added above the metal layer contacting the gate structure 508 as a word line WL. In a possible implementation, as shown in FIG. Figure 5B The floor plan and the subsequent corresponding Figure 5C and Figure 5D As shown in the cross-sectional view of FIG. 5 , a contact metal 540 is formed above each gate structure 508 to widen the connectable position of the gate structure 508, and then a through hole 550 electrically contacting the contact metal 540 is formed above the contact metal 540, and a metal line (word line WL) electrically contacting the through hole 550 is formed on the upper layer of the through hole 550. Of course, as required, a similar structure may also be formed above the gate structure shown in the previous embodiments. FIG. 5B to FIG. 5D The connection structure of the contact metal 540 and the through hole 550 in the embodiment of the present disclosure is not limited to this. Of course, part or all of the word lines WL in various embodiments of the present disclosure can also adopt other routing methods as needed, and are not limited to the straight line routing method shown in the drawings of the present disclosure, and each word line is not limited to being distributed in the same metal layer, but can be distributed in multiple metal layers as needed.

[0092] In a possible implementation, in order to arrange the storage array more closely, Figure 5B Each gate structure 508 in the four sub-columns has the same distance (eg, minimum spacing) with each gate structure 508 adjacent to it in the column direction or row direction. That is, the gate structures 508 in each column can be arranged in the most compact hexagonal pattern to further improve the array density.

[0093] In one possible implementation, Figure 5C and Figure 5D As shown in the cross-sectional view of FIG. 5 , each gate structure 508 in the memory array 5002 forms a memory transistor group corresponding to the gate structure 508, which may include three memory transistors (i.e., first to third memory transistors MT51-MT53) stacked vertically, which may adopt the aforementioned Figure 2A-2B or Figure 4B-Figure 4C The specific configuration of the memory transistor group in the illustrated embodiment. Figure 5C and Figure 5D The cross-sectional view of Figure 4B and Figure 4C The main difference in the structure of the storage transistor group shown in the cross-sectional view is that: Figure 5C As shown in the A3-A3 section, there may be multiple sub-columns of gate structures 508 in the same column at the same horizontal position, and the source / drain contact layers of each sub-column located at the same stacking level are continuous; in addition, as mentioned above, a connection structure of a contact metal 540 and a through hole 550 is added above the gate structure 508 to connect the word line WL. Figure 5C and Figure 5D Other specific structures of the storage transistor group shown in the cross-sectional view can be referred to in conjunction with the previous Figure 4B and Figure 4CThe contents of the above-mentioned embodiments will not be repeated here. Those skilled in the art will understand that the present disclosure is not limited to the above-mentioned structure of the storage transistor group, and a storage transistor group with any other structure may also be used, for example, Figure 1A-1B or Figure 3A-3C The specific configuration in the illustrated embodiment has a semiconductor layer extending continuously in the vertical direction.

[0094] In some embodiments, the columns separated by the isolation portion 530 can be referred to as planes in the storage array, and each plane can include a storage transistor group formed by the gate structure 508 of the corresponding column. Any number of planes (i.e., multiple columns) can be set according to actual capacity requirements. In any plane, M rows of gate structures 508 (equivalent to setting M sub-columns) can be placed according to layout wiring requirements, where M≥1, and N gate structures 508 can be placed in each row, where N≥1. Any two gate structures 508 in a plane will not be connected to the same word line WL, and the gate structures 508 between planes can be connected to the same word line WL through metal routing. In other words, any two gate structures 508 in the same column will not be connected to the same word line WL, and the gate structures 508 belonging to the same row between different columns can be connected to the same word line WL through metal routing. Although the figure only shows that a stepped contact area 520 is set at one end of the plane to lead out the source / drain contact layers of each level to their respective bit lines / source lines, stepped contact areas 520 can also be set at both ends of the plane to connect the two ends of the source / drain contact layer of the same level together and lead out, thereby reducing resistance.

[0095] It should be understood that in order to make the illustration clear and highlight the key points, Figure 5C and Figure 5D There are many blank areas between the components in the cross-sectional view, which does not limit these places to be empty. In some implementations, these whole or part of the blank areas can be filled with electrical insulating materials in actual devices to isolate and support these components.

[0096] Combine the following Figure 6-9 Describe in detail as above Figure 1A-1B , Figure 2A-2B , Figure 3A-3C , Figure 4A-4C , Figure 5A ,or Figure 5B-5D The circuit structure of the memory array and its corresponding read / write operations are shown. Figure 6-9 The description is made by taking an array of 3×3×3 as an example, but it should be understood that the present disclosure is not limited thereto.

[0097] Figure 6 FIG. 6 is a schematic diagram of a memory array circuit 600 according to an embodiment of the present disclosure.

[0098] like Figure 6 As shown, the gates of the storage transistors in the same row are connected to the same word line WL61, WL62 or WL63, and the storage transistors in the same column share the same bit line / source line BL611, BL621, BL631, BL641, or BL612, BL622, BL632, BL642, or BL613, BL623, BL633, BL643. As mentioned above, since the memory array of the present disclosure is arranged in three dimensions, each storage transistor group in each column includes three storage transistors stacked vertically, so in fact Figure 6 As shown, each column may include three sub-columns arranged in the vertical direction, and the storage transistors in the sub-columns adjacent in the vertical direction share a source / drain contact region. Figure 6 The circuit structure shown is only an example and is not limited in the embodiments of the present disclosure. Figure 7 or Figure 8 Write operations, Fig. 9 The read operation can only be applied to Figure 6 The circuit structure shown.

[0099] Figure 7 A NOR memory according to an embodiment of the present disclosure is shown. Figure 6 An example of a write operation to the memory array is shown. Figure 8 A NOR memory according to an embodiment of the present disclosure is shown. Figure 6 Another example of a memory array performing a write operation is shown. Fig. 9 A NOR memory according to an embodiment of the present disclosure is shown. Figure 6 An example of a read operation on the memory array shown. Figure 7 or Figure 8 The example of the write operation shown is Fig. 9 The embodiments of the read operation shown in the figure can be implemented separately or in combination, and can also be implemented together with one or more other embodiments of the present disclosure in an independent or combined manner, and the embodiments of the present disclosure are not limited to this. Figure 7 or Figure 8 The implementation method of write operation and Fig. 9 The implementation of the read operation shown in the figure is combined and implemented for exemplary description, but those skilled in the art will understand that the exemplary description is not a limitation of the embodiments of the present disclosure; the read / write operation unit 710, 810 or 910 may be a unit that only performs write operations to implement the following example. Figure 7 or Figure 8 The scheme shown, or only read operations to achieve such Fig. 9 The scheme shown.

[0100] It should be noted that in all embodiments of the present disclosure, the structures of the read / write operation unit 710, 810 or 910 may be the same or different. Although it is called a read / write operation unit, it means that it can be used only for performing a read operation, or only for performing a write operation, or for performing both a read operation and a write operation.

[0101] The following uses a read / write operation unit 710, 810 or 910 as an example to illustrate the Figure 6 The circuit diagram shown in the figure is used for writing and reading operations. Figure 7 , Figure 8 , Fig. 9 As shown, the NOR memory according to one embodiment of the present disclosure may further include a read / write operation unit 710, 810 or 910 in addition to the memory array of the aforementioned embodiments, for applying corresponding read / write voltages to each word line and bit line of the memory array to implement read / write operations. Figure 7 , Figure 8 and Fig. 9 The same operation unit 710, 810 or 910 is shown to implement the read / write operation, but the present disclosure is not limited thereto. In some embodiments, separate read operation units and write operation units may be used to implement the read operation and write operation, respectively, or different write operation units may be used to implement the read operation and write operation, respectively. Figure 7 and Figure 8 Two exemplary write operations. In addition, those skilled in the art will understand that there may be various circuit modes to implement the read / write operations that will be described in detail later. In addition, in some embodiments, an erase operation must be performed before a write operation is performed on the storage array. Although not shown in the figure, those skilled in the art will understand that the read / write operation unit 710, 810 or 910 may also use various modes to erase the storage transistors in the storage array. For example, in some embodiments, the gate voltage and drain voltage required for erasure may be applied to all word lines and all bit lines in the storage array at the same time, respectively, so as to achieve erasure of all storage transistors at the same time. It should be understood that in the present disclosure, the storage transistor after the erase process is implemented is regarded as storing data "1", and the storage transistor after the write process is implemented is regarded as storing data "0". That is to say, during the write operation, no write operation is actually performed on the storage transistor to which the data "1" is to be written.

[0102] Figure 7 An exemplary write operation 700 is shown for simultaneously writing to all storage transistors sharing the same word line WL61. Figure 7 Next to each storage transistor is marked "0" or "1" to indicate the data to be written into the storage transistor. Figure 7As shown, the word line to be written (and all gate structures connected to the word line) is applied with a gate write voltage V GW , while the remaining word lines are applied with 0V voltage. It should be understood that the 0V voltage is only an example, and in some embodiments, other gate voltages that do not affect the write operation can also be applied instead of 0V voltage; no matter which method is adopted, all embodiments of the present disclosure do not limit the aforementioned gate write voltage V GW and the gate voltages of the remaining word lines mentioned above, only the gate write voltage V GW The gate voltage of the remaining word lines is smaller than the gate voltage threshold for the write operation. In addition, the 12 bit lines / source lines BL611, BL621, BL631, BL641, BL612, BL622, BL632, BL642, BL613, BL623, BL633, and BL643 of the three storage transistor groups to be written connected to the same word line WL61 are simultaneously applied with source voltages V SW Or bit line write voltage V DW .from Figure 7 As can be seen from FIG. 1 , voltages are applied to the four bit lines / source lines of the same storage transistor group so that there is a write voltage difference (V DW -V SW ) in order to implement the write process, and there is no write voltage difference between the two source / drain regions of the storage transistor to which the data "1" is to be written; that is, the source voltage V SW and the aforementioned bit line write voltage V DW The size of the voltage between the two (V DW -V SW ) is greater than the drain-source voltage (V DS ) threshold value; in all embodiments of the present disclosure, the magnitude of the voltage applied to the two source / drain regions of the storage transistor to which the data "1" is to be written is not limited, and it is only necessary that the drain-source voltage is less than the drain-source voltage threshold value for the write operation (that is, there will not be enough current to achieve writing, and thus the write process will not occur); the voltage difference between the two source / drain regions of the storage transistor for writing the data "1" can be 0V or close to 0V. Of course, the write operation of the present disclosure is not limited to this, but a suitable voltage sequence can be applied to each word line and bit line / source line according to the type of storage transistor or other requirements. Of course, the opposite method can also be adopted, that is, there is a write voltage difference (V DW -V SW) in order to implement the write processing, and there is no write voltage difference greater than the threshold value between the two source / drain regions of the storage transistor to which the data "0" is to be written.

[0103] Figure 8 Shows the Figure 6 Another exemplary write operation 800 is performed by the circuit diagram shown in FIG. Figure 7 The main difference between the write operation 700 and the write operation 700 is that the write operation is performed on only one storage transistor in the storage transistor group at a time instead of all storage transistors. Figure 8 "Write '0'" is marked next to the storage transistor to be written in each storage transistor group. Figure 8 As shown, the word line to be written (and all gate structures connected to the word line) is applied with a gate write voltage V GW , while the remaining word lines are applied with 0V voltage. It should be understood that the 0V voltage is only an example, and in some embodiments, other gate voltages that do not affect the write operation can also be applied instead of 0V voltage. In addition, the 12 bit lines / source lines BL611, BL621, BL631, BL641, BL612, BL622, BL632, BL642, BL613, BL623, BL633, and BL643 of the three storage transistor groups to be written connected to the same word line WL61 are simultaneously applied with source voltages V SW Or bit line write voltage V DW .from Figure 8 As can be seen from FIG. 1 , for the same storage transistor group, a source voltage V is applied to the source of the storage transistor to be written and all bit lines / source lines on the same side as the source (i.e., the side opposite to the drain). SW , and a bit line write voltage V is applied to the drain of the storage transistor to be written and all bit lines / source lines on the same side as the drain (i.e., the side opposite to its source) DW In other words, voltage is applied to the four bit lines of the same storage transistor group so that there is a write voltage difference (V DW -V SW ) to implement the write process, while there is no write voltage difference between the two source / drain regions of the remaining storage transistors, so that no current sufficient to implement the write will flow, and the write process will not occur. Of course, the write operation of the present disclosure is not limited to this, but a suitable voltage sequence can be applied to each word line and bit line / source line according to the type of storage transistor or other requirements. Of course, the opposite method can also be adopted, and voltages are applied to the four bit lines / source lines of the same storage transistor group so that there is a write voltage difference (V 1) between the two source / drain regions of the storage transistor where only the data "1" is to be written. DW -V SW) in order to realize the writing process, while there is no writing voltage difference between the two source / drain regions of the remaining storage transistors to be written with data “0”.

[0104] Fig. 9 An exemplary read operation 900 is shown for reading one storage transistor in a group of all storage transistors that share the same word line WL61. Fig. 9 "Read" is marked next to the storage transistor to be read. Fig. 9 As shown, the word line to be read (and all gate structures connected to the word line) is applied with a gate read voltage V GR , while the remaining word lines are applied with a 0V voltage. It should be understood that the 0V voltage is only an example, and in some embodiments, other gate voltages that do not affect the read operation can also be applied instead of the 0V voltage. In addition, the 12 bit lines BL611, BL621, BL631, BL641, BL612, BL622, BL632, BL642, BL613, BL623, BL633, and BL643 of the three storage transistor groups to be read connected to the same word line WL61 are simultaneously applied with source voltages V SR Or the bit line read voltage V DR .from Fig. 9 As can be seen from FIG. 1 , for the same storage transistor group, a source voltage V is applied to the source of the storage transistor to be read and all bit lines / source lines on the same side as the source (i.e., the side opposite to the drain). SR , and a bit line read voltage V is applied to the drain of the storage transistor to be read and all bit lines / source lines on the same side as the drain (i.e., the side opposite to its source) DR In other words, voltages are applied to the four bit lines / source lines of the same storage transistor group so that there is a read voltage difference (V DR -V SR ) to implement the reading process, while there is no reading voltage difference between the two source / drain layers of the remaining storage transistors, so that no current sufficient to implement the reading will flow, and the reading process will not be affected. Of course, the reading operation of the present disclosure is not limited to this, but a suitable voltage sequence can be applied to each word line and bit line / source line according to the type of storage transistor or other requirements.

[0105] Using the above Figure 7 or Figure 8 , and / or Fig. 9 The writing operation 700 or 800 and / or the reading operation 900 shown can simply, conveniently and quickly implement the writing and / or reading of the storage array in each embodiment of the present disclosure. Figure 6-Figure 9One or more of the circuit structures and read / write operations shown may be combined with the NOR type memory device structure shown in any of the previous embodiments.

[0106] In addition, in some embodiments, in order to further reduce the lateral size of the storage array, the Figure 3A-3C , Figure 4A-4C or Figure 5A-5D The isolation parts between adjacent columns in the memory array shown. That is, an improved memory array arrangement can be proposed, which can reduce the area occupied by the entire memory array on the horizontal plane and further improve the array density.

[0107] Fig. 10A FIG. 4 is a plan view of an array of NOR memory devices according to another embodiment of the present disclosure. Fig. 10B Shown along Fig. 10A The schematic cross-sectional view obtained by the dotted line A4-A4 in FIG. Fig. 10C Shown along Fig. 10A The cross-sectional view is obtained by the dashed line B4-B4 in FIG. Fig.11 It is shown as an example Figures 10A-10C The circuit diagram of the memory array is shown.

[0108] Figure 10A-10C is Figure 5A The memory array in the embodiment shown has the isolation portions between the columns removed, but it should be understood that Figure 10A-10C The structure shown in the figure without the inter-column isolation part can be implemented in combination with the memory array structure in any of the aforementioned embodiments, and can also be applied to other memory array structures.

[0109] because Figure 10A-10C The memory array 1000 of the embodiment does not have an isolation portion between adjacent columns as in the above-mentioned embodiment. Therefore, the source / drain contact layers of the memory transistors of each stacking level in each memory transistor group in each column are not isolated, and the bit line or source line voltage cannot be applied to the memory transistors of each column separately. Figure 10A-10C As shown, all columns in the memory array 1000 share four bit lines BL101-BL104 drawn from the stepped contact region 1020. Therefore, the memory array 1000 cannot uniquely identify a memory transistor group only by bit lines and word lines as in the aforementioned embodiment. Figure 10B-Figure 10C A cross-sectional diagram of Fig.11As shown in the circuit diagram of FIG. 1 , the gate structure of each storage transistor group is not directly connected to each word line, but is connected to the word line through a selection transistor SLT. One of the source / drain of each selection transistor SLT is connected to the gate of each storage transistor group, the other source / drain is connected to the word line WL of the row to which the storage transistor group belongs, and the gate is connected to the selection line SSL of the column to which the storage transistor group belongs. Fig.11 As shown in the circuit schematic diagram, the gates of the selection transistors of the storage transistor group in the same column are all connected to the same selection line SSL101 or SSL102; in one implementation, the voltage on the selection line of a selected column can be made high voltage, so that the selection transistors of the column are all turned on, thereby transmitting the voltage on the word lines of each row to the gates of the storage transistor groups of each row, and the voltages on the selection lines of unselected columns are all low voltages that fail to turn on the selection transistors, so that the unselected columns cannot receive the voltage applied on the word lines.

[0110] exist Fig. 10A In the plan schematic diagram shown, dotted boxes are used to represent the word lines WL101-WL106 of each row and the selection lines SSL101-SSL102 of each column, respectively. The word lines and the selection lines can be used to uniquely select the storage transistor group that overlaps with them. In one possible implementation, each selection transistor SLT can have the same structure as an ordinary MOS transistor. Each selection transistor can be made in a chip that is the same as or different from the storage array 1000. For example, each selection transistor can be directly made above the upper surface of the gate structure body of each storage transistor group, or can be made in the peripheral area of ​​the storage array 1000 in the same chip, or can be made on another chip and connected to the gate structure of each storage transistor group in various ways. The word lines and selection transistors SLT can be made in various areas in various structural ways, and do not necessarily have to be made above the storage array 1000. Therefore, in Fig. 10B and Fig. 10C In the cross-sectional schematic diagram of FIG. 1 , the word line and the selection transistor portion are represented by circuit symbols rather than a cross-sectional schematic diagram.

[0111] In some embodiments, Fig. 10B and Fig. 10CAs shown in the cross-sectional view, each storage transistor group in the storage array 1000 may include three storage transistors (i.e., the first to third storage transistors MT101-MT103) stacked vertically. The main difference between the structure of the storage transistor group shown in the cross-sectional view in the aforementioned embodiment is that there is no isolation portion between adjacent columns, so that there is no isolation between the source / drain contact layers of the storage transistors in adjacent columns on the same stacking level; other specific structures can refer to the contents of the aforementioned embodiments and will not be repeated here. Those skilled in the art will understand that the present disclosure is not limited to the above-mentioned structure of the storage transistor group, and a storage transistor group with any other structure may also be used.

[0112] like Figure 10A-10C The write operation / read operation of the storage array 1000 shown in FIG. 1 may refer to the above-mentioned Figures 7 to 9 The content of the write operation / read operation is as follows, but other suitable write operation / read operation methods may also be adopted, which will not be repeated here.

[0113] The following are Figure 3A-3C The storage array shown and Figure 4A-4C The manufacturing process of the storage device according to the present disclosure is described in detail in combination with the accompanying drawings, taking the storage array shown as an example. It should be understood that these manufacturing processes are only for illustration and are not a limitation of the present disclosure, and the order of these process steps is not limited to the examples given in the accompanying drawings, but can be adjusted arbitrarily as needed. It should be understood that these manufacturing processes can be appropriately modified as needed to be applicable to various embodiments of the present disclosure. These manufacturing processes can be used to manufacture the storage array of the embodiment of the present disclosure, and can also be used to manufacture storage arrays of other structures, which are not limited here.

[0114] FIG. 12A to FIG. 12G is a cross-sectional view schematically showing various steps in a method for manufacturing a NOR memory device according to an embodiment of the present disclosure, wherein the specific structure of the NOR memory device corresponds to Figure 3A-3C The structure of the embodiment shown. Unless otherwise specified, FIG. 12A to FIG. 12G The cross-sectional views of each step in Figure 3C It should be understood that FIG. 12A to FIG. 12G The manufacturing process shown can also be applied to the specific structure of the memory device described in other embodiments of the present disclosure. The number of alternately stacked layers and the arrangement of the gate structure on the horizontal plane can be adjusted as needed, or the process step of forming an isolation portion between adjacent columns can be omitted.

[0115] like Fig. 12AAs shown, first, a plurality of source / drain contact layers and a plurality of isolation layers are alternately stacked on a substrate 313, namely, a first source / drain contact layer 301, a first isolation layer 302, a second source / drain contact layer 303, a second isolation layer 304, a third source / drain contact layer 305, a third isolation layer 306, and a fourth source / drain contact layer 307. In some embodiments, these layers may be sequentially deposited by various deposition processes, such as chemical vapor deposition (CVD).

[0116] In some embodiments, the substrate 313 may be a silicon substrate, such as a silicon wafer. In order to isolate the substrate from the influence of the device formed thereon, an insulating material layer 314 may be formed between the substrate 313 and the first source / drain contact layer 301 .

[0117] As described in the previous embodiments, the number of alternately stacked source / drain contact layers and isolation layers can be set as needed. For example, (h+1) source / drain contact layers and h isolation layers can be alternately stacked in the vertical direction to form h vertically stacked storage transistors, where h is a natural number greater than 1.

[0118] In some embodiments, each source / drain contact layer may include polysilicon or may be a polysilicon layer. In some embodiments, each isolation layer may include silicon oxide or may be a silicon oxide layer. In some embodiments, the thickness of each source / drain contact layer and each isolation layer may be in the range of 10-200nm (including the endpoint values). It should be understood that the present disclosure is not limited to the aforementioned exemplary materials and thickness values, but various suitable materials and thicknesses may be selected as needed. Moreover, the materials of each source / drain contact layer may be the same as or different from each other, and the materials of each isolation layer may also be the same as or different from each other. Each source / drain contact layer and isolation layer may be a layer composed of a single material, or a composite layer formed of multiple materials.

[0119] Then, if Fig. 12B As shown, a plurality of gate holes 315 are formed to vertically extend through each source / drain contact layer and each isolation layer. Figure 3A As shown, the plurality of gate holes 315 can be arranged in an array of n×m on a horizontal plane, where n and m are natural numbers greater than 1. It should be understood that the arrangement of the gate holes 315 on a horizontal plane is not limited thereto, but other suitable arrangements can be adopted, such as similar to Figure 5A and Figure 5B It should be understood that in the present disclosure, "gate hole" means a hole for forming a gate structure, but it is not limited to forming only a gate structure in the gate hole. As will be described later, a desired semiconductor layer can also be formed in the gate hole.

[0120] In some embodiments, the position of the gate hole 315 can be defined by photolithography, that is, the region except the position where the gate hole 315 is to be formed is covered by photoresist to expose the region where the gate hole 315 is to be formed, and then an etching process (such as reactive ion etching (RIE)) is performed until all source / drain contact layers and isolation layers are penetrated to form the gate hole 315. In some embodiments, the diameter of each gate hole 315 can be between 30-300 nm.

[0121] Then, if Fig. 12C As shown, a semiconductor layer 309 is formed in the gate hole 315 .

[0122] In some embodiments, semiconductor material may be deposited in the gate hole so as to continuously cover the sidewalls of each source / drain contact layer and each isolation layer, thereby forming a mutually continuous semiconductor layer 309. As described above, in the storage transistor group corresponding to each gate hole (wherein a gate structure will be formed later), three vertically stacked storage transistors share the continuous semiconductor layer 309.

[0123] In some embodiments, polysilicon material may be deposited by CVD process, and polysilicon material on undesired parts may be removed to form semiconductor layer 309. The thickness of deposited semiconductor layer 309 may be the desired channel thickness of the memory transistor, for example, between 10-100 nm. It should be understood that the material of semiconductor layer 309 is not limited to polysilicon, and may also be other suitable semiconductor materials. Fig. 12C It is shown that the semiconductor layer 309 is not formed on the portion of the insulating layer 314 exposed by the gate hole, but the present disclosure is not limited thereto, and the semiconductor layer 309 may be formed on all portions of the insulating layer 314 exposed by the gate hole, which generally has no effect on the operation of the storage transistor.

[0124] Then, if Fig.12D As shown, a gate structure 308 is formed on the semiconductor layer 309 in the gate hole 315 .

[0125] In some embodiments, in the gate hole 315, the various layers included in the gate structure 308 are sequentially formed on the semiconductor layer 309 to form the gate structure 308. For example, the gate structure 308 may include an ONO (oxide-nitride-oxide) stack for storing charges, and a gate electrode layer. A tunneling oxide layer may be first grown or deposited on the semiconductor layer 309, then a nitride layer for storing charges may be deposited, then an oxide layer may be deposited, and finally a metal (e.g., tungsten) or polysilicon may be deposited to fill the gate hole 315 to form a gate electrode.

[0126] Then, if Fig.12EAs shown, a step is formed at one end of each column of source / drain contact layers so that all source / drain contact layers are partially exposed in the horizontal plane, such as the front Figure 3A As shown in the plan view, it is convenient to subsequently form contact holes for connecting metal lines of respective bit lines / source lines on the exposed portions.

[0127] In some embodiments, the step can be formed by step etching and trimming. It should be understood that, although not shown in the figure, steps can also be formed at both ends of each column of source / drain contact layer so that the same source / drain contact layer can be simultaneously led out from both ends to the corresponding bit line / source line.

[0128] Then, if Fig.12F As shown, a spacer 317 is formed on the sidewall of each step, and a metal silicide 316 is formed on the surface of the exposed portion of each source / drain contact layer.

[0129] In some embodiments, the sidewall spacers 317 and the self-aligned metal silicide 316 may be formed by a SAB (Self-Aligned Block) process. In some embodiments, the spacers 317 may include silicon oxide, silicon nitride, or a combination of the two.

[0130] Then, if Figure 12G As shown, an interlayer dielectric layer 310 is formed, and holes are drilled therein and then filled with metal material to form various contact holes 318 .

[0131] In some embodiments, a flat interlayer dielectric layer 310 can be formed by depositing an electrically insulating material and performing chemical mechanical polishing (CMP); then, holes are formed in the interlayer dielectric layer 310 by etching, and at this time, the surfaces of the steps and the gate metal layer become etching barriers, so that the etching stops on the surfaces of these layers to form the desired holes; then, a metal material (such as tungsten) is deposited in each hole to form each contact hole 318.

[0132] Those skilled in the art will understand that a metal layer (including, for example, a word line, a bit line / source line, etc.) connected to each contact hole 318 needs to be formed subsequently, and its process is omitted here.

[0133] In addition, if Figure 3A and Figure 3B As shown, an isolation portion is provided between the storage transistor groups formed by the gate structures of adjacent columns to isolate the source / drain contact layers of the storage transistors in different columns, thereby isolating the bit lines / source lines for the storage transistors in different columns. Figure 12A-12GAfter each step, trench isolation processing can be performed to form an isolation portion between adjacent columns. For example, in some embodiments, a trench penetrating each source / drain contact layer can be formed between the gate holes of adjacent columns or the corresponding gate structures, and an insulating material can be filled in the trench to form an isolation portion, so that each source / drain contact layer in the storage transistor formed through the gate holes of adjacent columns is isolated from each other. The structure of the isolation portion can refer to Figure 3A and Figure 3B The structure shown will not be described in detail here.

[0134] It should be understood that the processes in the above-mentioned steps are merely exemplary and not restrictive, and the present disclosure may adopt various other suitable process treatments to achieve the construction of each step.

[0135] It should be understood that the order of the process steps shown above is merely exemplary and not restrictive, and the present disclosure can adjust the order of the process steps as needed; for example, the steps of forming the stepped contact area (such as Figure 12E-12G ) can be combined with the steps of forming the gate structure and the semiconductor layer (such as Figure 12B-Figure 12D shown) in any order, or all before each other, for example, Fig.12E Steps in forming steps, Fig.12F The step of forming the spacer and the metal silicide in Figure 12G The steps of forming the ILD layer and the contact holes in the Fig. 12A , Fig. 12B , Fig. 12C or Fig.12D Since the storage device disclosed in the present invention has a simple structure and a simple manufacturing process, the manufacturing process can be flexibly set.

[0136] FIG. 13A to FIG. 13I is a cross-sectional view schematically showing various steps in a method for manufacturing a NOR memory device according to another embodiment of the present disclosure, wherein the specific structure of the NOR memory device corresponds to Figure 4A-4C The structure of the embodiment shown. Unless otherwise specified, FIG. 13A to FIG. 13I The cross-sectional views of each step in Figure 4C It should be understood that FIG. 13A to FIG. 13I The manufacturing process shown can also be applied to the specific structure of the memory device described in other embodiments of the present disclosure. The number of alternately stacked layers and the arrangement of the gate structure on the horizontal plane can be adjusted as needed, or the process step of forming an isolation portion between adjacent columns can be omitted.

[0137] because Figure 4A-4C The memory device structure in the embodiment shown is similar to Figure 3A-3CThe main difference in the memory device configuration in the illustrated embodiment is the arrangement of semiconductor layers in each vertically stacked memory transistor, so FIG. 13A to FIG. 13I The manufacturing process shown is combined with the previous FIG. 12A to FIG. 12G The main difference in the manufacturing process shown is the step of forming the semiconductor layer, while the other steps can refer to the previous FIG. 12A to FIG. 12G The corresponding steps in the description are as follows, and some contents are not repeated here.

[0138] like Fig.13A As shown, first, a plurality of source / drain contact layers and a plurality of isolation layers are alternately stacked on a substrate 413, namely, a first source / drain contact layer 401, a first isolation layer 402, a second source / drain contact layer 403, a second isolation layer 404, a third source / drain contact layer 405, a third isolation layer 406, and a fourth source / drain contact layer 407. In some embodiments, these layers may be sequentially deposited by various deposition processes, such as chemical vapor deposition (CVD).

[0139] The detailed description of the substrate 413, the insulating material layer 414 thereon, each source / drain contact layer, and each isolation layer can be referred to. Fig. 12A The description of the steps shown will not be repeated here.

[0140] Then, if Fig. 13B As shown, a plurality of gate holes 415 are formed to vertically extend through each source / drain contact layer and each isolation layer. Figure 4A As shown, the plurality of gate holes 415 may be arranged in an array of n×m on a horizontal plane, where n and m are natural numbers greater than 1. It should be understood that the arrangement of the gate holes 415 on a horizontal plane is not limited thereto, but other suitable arrangements may be adopted, such as similar to Figure 5A and Figure 5B As illustrated.

[0141] The detailed description of the steps of forming the gate hole 415 can be referred to Fig. 12B The description of the steps shown will not be repeated here.

[0142] Then, if Fig. 13C As shown, each isolation layer exposed by each gate hole 415 is selectively etched so that the sidewall of the isolation layer is recessed relative to the sidewall of the source / drain contact layer in a horizontal direction, thereby forming a recessed portion 419 as shown in the figure.

[0143] In some embodiments, the selective etching process can be performed by wet etching, for example, only etching the material of the isolation layer exposed in each gate hole, without etching the material of each source / drain contact layer, or etching the two with a high selectivity. The wet etching time can be controlled to control the depth of the recessed portion 419, thereby limiting the thickness of the channel to be formed subsequently, which is, for example, 10-100 nm.

[0144] Then, if Fig.13D As shown, a semiconductor material 421 is deposited in the gate hole to continuously cover the sidewalls of each source / drain contact layer and each isolation layer. At this time, the semiconductor material 421 fills up each recessed portion 419 formed in the previous step.

[0145] In some embodiments, polysilicon material may be deposited by CVD process as semiconductor material 421. It should be understood that semiconductor material 421 is not limited to polysilicon, but may be other suitable semiconductor materials. Fig.13D It is shown that the semiconductor material 421 is not formed on the top source / drain contact layer 407 and on the portion of the insulating layer 414 exposed through the gate hole, but the present disclosure is not limited to this. The semiconductor material 421 may also be deposited on the source / drain contact layer 407 and on all portions of the insulating layer 414 exposed through the gate hole, and these portions of the semiconductor material 421 may also be removed in subsequent steps.

[0146] Then, if Fig.13E As shown, the semiconductor material 421 is etched back to remove the semiconductor material on the sidewalls of each source / drain contact layer, leaving the semiconductor material on the sidewalls of each isolation layer to serve as semiconductor layers 409, 411 and 412 separated from each other.

[0147] In some embodiments, the semiconductor material 421 may be etched back by wet etching, and the gate hole 415 may be subjected to RIE treatment after the wet etching as needed to form a flat hole wall.

[0148] Then, if Fig.13F As shown, a gate structure 408 is formed in the gate hole 415, so that the gate structure 408 contacts the sidewalls of each source / drain contact layer and each semiconductor layer 409, 411 and 412. The specific description of this step process can be referred to Fig.12D The description of the steps shown will not be repeated here.

[0149] Then, if Figure 13G As shown, a step is formed at one end of each column of source / drain contact layers so that all source / drain contact layers are partially exposed in the horizontal plane, such as the front Figure 4AAs shown in the plan view, it is convenient to form contact holes for connecting metal lines of respective bit lines / source lines on the exposed parts. The specific description of the process of this step can be referred to Fig.12E The description of the steps shown will not be repeated here.

[0150] Then, if Fig.13H As shown, a spacer 417 is formed on the sidewall of each step, and a metal silicide 416 is formed on the exposed surface of each source / drain contact layer. The specific description of this step process can be referred to Fig.12F The description of the steps shown will not be repeated here.

[0151] Then, if Fig.13I As shown, an interlayer dielectric layer 410 is formed, and holes are punched therein and then filled with metal material to form various contact holes 418. The specific description of this step process can be referred to Figure 12G The description of the steps shown will not be repeated here.

[0152] Those skilled in the art will understand that a metal layer (including, for example, a word line, a bit line / source line, etc.) connected to each contact hole 418 needs to be formed subsequently, and its process is omitted here.

[0153] In addition, if Figure 4A and Figure 4B As shown, an isolation portion is provided between the storage transistor groups formed by the gate structures of adjacent columns to isolate the source / drain contact layers of the storage transistors in different columns, thereby isolating the bit lines / source lines for the storage transistors in different columns. Figure 13A-13I After each step, trench isolation processing can be performed to form an isolation portion between adjacent columns. For example, in some embodiments, a trench penetrating each source / drain contact layer can be formed between the gate holes of adjacent columns or the corresponding gate structures, and an insulating material can be filled in the trench to form an isolation portion, so that each source / drain contact layer in the storage transistor formed through the gate holes of adjacent columns is isolated from each other. The structure of the isolation portion can refer to Figure 4A and Figure 4B The structure shown will not be described in detail here.

[0154] It should be understood that the processes in the above-mentioned steps are merely exemplary and not restrictive, and the present disclosure may adopt various other suitable process treatments to achieve the construction of each step.

[0155] It should be understood that the order of the process steps shown above is merely exemplary and not restrictive, and the present disclosure can adjust the order of the process steps as needed; for example, the steps of forming the stepped contact area (such as Figure 13G-13I ) can be combined with the steps of forming the gate structure and the semiconductor layer (such as Figure 13B-13F shown) in any order, or all before each other, for example, Figure 13G Steps in forming steps, Fig.13H The step of forming the spacer and the metal silicide in Fig.13I The steps of forming the ILD layer and the contact holes in the Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E or Fig.13F Since the storage device disclosed in the present invention has a simple structure and a simple manufacturing process, the manufacturing process can be flexibly set.

[0156] In addition, the NOR-type memory device or memory array and the corresponding NOR-type memory according to the present disclosure as described above can be applied to various electronic devices with storage requirements, for example, smart phones and their peripheral electronic devices (such as Bluetooth headsets and wearable devices), electronic devices using the Internet of Things, vehicle-mounted electronic devices, etc.

[0157] Those skilled in the art will appreciate that appropriate changes may be made to the various circuit structures of the present disclosure as needed, and these changes are within the protection scope of the present disclosure.

[0158] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A NOR memory device, comprising: At least two source / drain contact layers and at least one isolation layer alternately stacked in a vertical direction; a gate structure extending vertically through the source / drain contact layer and the isolation layer; as well as A semiconductor layer located at the periphery of the gate structure; Wherein, two source / drain contact layers respectively adjacent to the isolation layer above and below are connected to two bit lines / source lines respectively, and form a storage transistor with the gate structure and the semiconductor layer.

2. The NOR memory device according to claim 1, wherein: The source / drain contact layers and the isolation layers alternately stacked in the vertical direction include h+1 source / drain contact layers and h isolation layers, respectively, where h is a natural number greater than 1; A semiconductor layer is provided on the periphery of the gate structure; Each source / drain contact layer is connected to a respective different bit line / source line; as well as Two source / drain contact layers respectively immediately above and below each isolation layer, the gate structure, and a semiconductor layer located between the corresponding isolation layer and the gate structure form a corresponding storage transistor, thereby forming h storage transistors stacked vertically.

3. The NOR memory device according to claim 1 or 2, wherein: The semiconductor layer is disposed between the gate structure, the source / drain contact layer and the isolation layer, and extends continuously in a vertical direction around the gate structure.

4. The NOR memory device according to claim 1 or 2, wherein: The semiconductor layer includes semiconductor sub-layers which are spaced apart in a vertical direction and arranged between each isolation layer and the gate structure.

5. The NOR memory device according to claim 4, wherein: The gate structure contacts the sidewall of the source / drain contact layer; The isolation layer is provided with a recess extending in a direction away from the gate structure at a position corresponding to the gate structure; as well as The semiconductor layer is disposed in the recess and contacts the gate structure and the isolation layer.

6. The NOR memory device according to claim 1 or 2, wherein: The NOR memory device comprises a plurality of gate structures arranged in n rows and m columns on a horizontal plane and extending vertically through the source / drain contact layer and the isolation layer, wherein n and m are both natural numbers greater than 1; Some or all of the gate structures in the same row are connected to the same word line; Part or all of the source / drain contact layers located at the same vertical level in the storage transistors formed by the gate structures in the same column are connected to the same bit line / source line; and Source / drain contact layers located at the same vertical level in the memory transistors formed by the gate structures of adjacent columns are isolated from each other.

7. The NOR memory device according to claim 6, wherein: The storage transistors formed by the gate structures in the same column share the source / drain contact layer, and one or two ends of the source / drain contact layer in each column are provided with contact holes for connecting metal lines of respective bit lines / source lines.

8. The NOR memory device according to claim 6, wherein: At least one column of gate structures includes i sub-columns of gate structures, where i is a natural number greater than 1; The gate structures of at least two adjacent sub-columns are spaced apart in the column direction.

9. The NOR memory device according to claim 8, wherein: Each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in the column direction; or, Each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in the row direction; or, Each gate structure in the i sub-columns has the same distance from each gate structure adjacent to it in the row direction and the column direction.

10. The NOR memory device according to any one of claims 1 to 9, wherein: The source / drain contact layer is a metal layer or a polysilicon layer, or the source / drain contact layer is made of a material containing metal or polysilicon; and / or The isolation layer is a silicon oxide layer or a silicon nitride layer, or the isolation layer is made of a material containing silicon oxide or silicon nitride; and / or The semiconductor layer is a polysilicon layer, or the semiconductor layer is made of a material containing polysilicon.

11. A method for manufacturing a NOR type memory device, comprising: At least two source / drain contact layers and at least one isolation layer are alternately stacked in a vertical direction on the substrate; forming a gate hole extending vertically through the source / drain contact layer and the isolation layer; forming a gate structure in the gate hole and a semiconductor layer located at the periphery of the gate structure; as well as connecting two source / drain contact layers respectively adjacent to the isolation layer above and below the isolation layer to two bit lines / source lines; Wherein, two source / drain contact layers respectively adjacent to the isolation layer above and below form a storage transistor with the gate structure and the semiconductor layer.

12. The method according to claim 11, wherein: The source / drain contact layers and the isolation layers alternately stacked in the vertical direction include h+1 source / drain contact layers and h isolation layers, respectively, where h is a natural number greater than 1; A semiconductor layer is provided on the periphery of the gate structure; Each source / drain contact layer is connected to a respective different bit line / source line; as well as Two source / drain contact layers respectively immediately above and below each isolation layer, the gate structure, and a semiconductor layer located between the corresponding isolation layer and the gate structure form a corresponding storage transistor, thereby forming h storage transistors stacked vertically.

13. The method according to claim 12, wherein: The step of forming a gate structure in the gate hole and a semiconductor layer located outside the gate structure comprises: Depositing a semiconductor material in the gate hole to continuously cover the sidewall of the gate hole to form a continuous semiconductor layer between the gate hole and the source / drain contact layer and the isolation layer; and The gate structure is formed on the semiconductor layer in the gate hole.

14. The method according to claim 11 or 12, wherein: The step of forming a gate structure in the gate hole and a semiconductor layer located outside the gate structure comprises: Selectively etching the isolation layer exposed by the gate hole so that the isolation layer is provided with a recess extending in a direction away from the gate structure at a position corresponding to the gate structure; Depositing a semiconductor material in the gate hole to continuously cover the sidewall of the gate hole to form a continuous semiconductor layer between the gate hole and the source / drain contact layer and the isolation layer; Etching back the semiconductor material to remove the semiconductor material on the sidewall of the gate hole corresponding to the source / drain contact layer position, leaving the semiconductor material located in the recess of the isolation layer as the semiconductor layer; and The gate structure is formed in the gate hole so that the gate structure contacts the sidewall of the source / drain contact layer and the semiconductor layer.

15. The method according to any one of claims 11 to 14, wherein: The source / drain contact layer is a metal layer or a polysilicon layer, or the source / drain contact layer is made of a material containing metal or polysilicon; and / or The isolation layer is a silicon oxide layer or a silicon nitride layer, or the isolation layer is made of a material containing silicon oxide or silicon nitride; and / or The semiconductor layer is a polysilicon layer, or the semiconductor layer is made of a material containing polysilicon.

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