In-memory calculation method, in-memory calculation architecture and in-memory calculation chip for floating point numbers

Abstract

The present application relates to an in-memory calculation method for floating-point numbers, an in-memory calculation architecture, and an in-memory calculation chip, the in-memory calculation method comprising: calculating the inference accuracy loss of a target convolutional neural network for a test set under different convolution magnitude combinations, the target convolutional neural network being used to extract feature information from an image through multiple convolution operations; determining a convolution magnitude combination as a target convolution magnitude combination from at least one convolution magnitude combination corresponding to a loss of inference accuracy less than a target value, the target convolution magnitude combination comprising a reference magnitude for each convolution operation; for any convolution operation of the target convolutional neural network, the corresponding reference magnitude is used to implement floating-point number calculations for the convolution operation. The present invention obtains a reference magnitude adapted to the target convolutional neural network through testing in advance at the software network level. This not only improves the in-memory calculation efficiency of floating-point numbers, but also reduces the chip area and power consumption of the memory.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an in-memory calculation method, an in-memory calculation architecture, and an in-memory calculation chip for floating-point numbers. Background Art

[0002] In-memory computing has emerged as a promising solution to overcome the inherent problems of the von Neumann architecture. In-memory computing solutions based on static random access memory improve the energy efficiency of convolution operations for multiplication and accumulation by suppressing data transfer between system storage and computing functions. In recent years, advanced artificial intelligence chips require high-precision input precision, weight precision, and output precision to achieve high inference accuracy and high energy efficiency. However, existing integer-based in-memory computing static random access memory lacks support for floating-point calculations and is prone to loss of precision when applied to complex data sets or neural network models. These integer in-memory computing memories can perform floating-point convolution operations, process floating-point input exponents through digital circuits with additional floating-point to integer converters or off-chip away from the integer in-memory computing static random access memory, and process weight exponents in combination with off-chip software pre-calibration, which will bring additional area, power consumption and latency.

[0003] In recent years, the in-memory calculation of floating-point numbers has attracted the attention of scholars. The focus is on the processing of the exponent and mapping it to the mantissa level. In order to make the mantissa perform convolution operations at a uniform order of magnitude, most of them use digital logic to find the maximum value after the exponential addition operation, the subtraction circuit and the final mantissa insertion circuit. However, these cumbersome logic operations will still bring additional chip area and power consumption.

[0004] The current in-memory calculation method of floating-point numbers will bring additional chip area and power consumption problems, and no effective solution has been proposed yet. Summary of the invention

[0005] The present invention provides an in-memory calculation method, an in-memory calculation architecture and an in-memory calculation chip for a floating-point number, so as to solve the problem that the current in-memory calculation method for a floating-point number will bring about additional chip area and power consumption.

[0006] In a first aspect, the present invention provides an in-memory calculation method for floating-point numbers, comprising:

[0007] Calculating the inference accuracy loss of a target convolutional neural network on a test set under different combinations of convolution magnitudes, wherein the target convolutional neural network is used to extract feature information from an image through multiple convolution operations;

[0008] Determine a convolution magnitude combination as a target convolution magnitude combination from the convolution magnitude combinations corresponding to at least one inference accuracy loss that is less than a target value, wherein the target convolution magnitude combination includes a reference magnitude of each convolution operation;

[0009] For any convolution operation of the target convolutional neural network, a corresponding benchmark level is used to implement floating-point number calculation of the convolution operation.

[0010] In a second aspect, the present invention provides an in-memory computing architecture configured to implement multiple convolution operations in a target convolutional neural network by multiplexing, including:

[0011] An index processing module, used to realize the index calculation of the input index and the weight index, and generate a pre-insertion 0 signal according to the index calculation result and the reference magnitude signal;

[0012] a zero-insertion module, configured to set the input mantissa to zero when the pre-0-insertion signal indicates that the number of inserted zeros is greater than the number of bits of the input mantissa, and to perform a zero-insertion operation on the input mantissa according to the number of inserted zeros indicated by the pre-0-insertion signal when the pre-0-insertion signal indicates that the number of inserted zeros is less than the number of bits of the input mantissa, so that the magnitudes of the input mantissas are all the reference magnitudes of the convolution operation;

[0013] The mantissa calculation module is used to perform mantissa calculation on each of the input mantissas after the 0 insertion operation to obtain a mantissa calculation result.

[0014] Compared with the related art, the present invention does not determine the reference magnitude and generate the reference magnitude signal at the hardware circuit level, but obtains the reference magnitude adapted to the target convolutional neural network through testing in advance at the software network level. Then, when the target convolutional neural network is running, the reference magnitude signal is generated by an external FPGA and provided to the full adder. This not only improves the in-memory calculation efficiency of floating-point numbers, but also reduces the chip area and power consumption of the memory.

[0015] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flow chart of an in-memory calculation method of floating-point numbers provided in an embodiment of the present invention;

[0017] Figure 2 It is a schematic diagram of the floating point number format used in the present invention;

[0018] Figure 3 is a schematic diagram of a combination of a unit index processing circuit and an SRAM cell array in some embodiments of the present invention;

[0019] Figure 4 is a schematic diagram of an index processing module in some embodiments of the present invention;

[0020] Figure 5 is a schematic diagram of an insert-0 shift submodule in some embodiments of the present invention;

[0021] Figure 6 is an index processing operation flow of an index processing module in some embodiments of the present invention;

[0022] Figure 7 This is the plug-in 0 judgment process of the plug-in 0 judgment submodule in some embodiments of the present invention. DETAILED DESCRIPTION

[0023] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0024] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0025] In an embodiment of the present invention, a floating point number in-memory calculation method is provided. Figure 1 is a flow chart of an in-memory calculation method for floating-point numbers provided in an embodiment of the present invention, such as Figure 1 As shown, the process includes the following steps:

[0026] Step S110, calculating the inference accuracy loss of the target convolutional neural network on the test set under different combinations of convolution magnitudes, where the target convolutional neural network is used to extract feature information from the image through multiple convolution operations.

[0027] Among them, the convolution operation in the convolutional neural network needs to run the in-memory calculation of floating-point numbers, and the calculation function is provided by the hardware circuit. The in-memory calculation method of floating-point numbers provided by the present invention may have certain parameter differences when facing different convolutional neural networks, and the target convolutional neural network is the convolutional neural network targeted by the current in-memory calculation method of floating-point numbers.

[0028] There are multiple convolutional layers in a convolutional neural network, and convolutional layers are used to perform convolution operations. Each convolutional layer has its own computational magnitude, and generally, the deeper the convolutional layer, the smaller its computational magnitude. The convolutional magnitude combination is the computational magnitude combination of each convolutional layer in the convolutional neural network. Under different convolutional magnitude combinations, the convolutional neural network may have different reasoning accuracy. This step is to calculate the reasoning accuracy of the target convolutional neural network under different convolutional magnitude combinations. Specifically, the target convolutional neural network is mainly used for image feature extraction.

[0029] Step S120, determining a convolution level combination as a target convolution level combination from the convolution level combinations corresponding to at least one inference accuracy loss that is less than the target value, wherein the target convolution level combination includes a reference level for each convolution operation.

[0030] In this step, it is necessary to determine a set of target convolution magnitude combinations suitable for the target convolutional neural network. When the target convolution magnitude combination is adopted, the accuracy loss of the target convolutional neural network is less than the target value. The target value is a preset value, which can be set by the user according to the actual task. The target value is the upper limit of the inference accuracy loss acceptable to the user.

[0031] The target convolution magnitude combination includes the base magnitude of each convolution operation. For any convolution operation, the base magnitude is the uniform magnitude of floating-point operations in the convolution operation, that is, each floating-point number will be converted to this magnitude before performing floating-point operations.

[0032] Specifically, refer to Figure 2 The floating point format targeted by the present invention may be BF16. The data type of the floating point number in this format may be divided into a sign bit, an exponent bit, and a mantissa bit, which implement different functions. The number of bits at each position is different according to different floating point data types. The specific functions are as follows:

[0033] Sign bit: Determines the sign of a floating-point number, usually 1 bit, with 0 or 1 representing a positive or negative floating-point number.

[0034] Exponent bit: used to store the exponent part in scientific notation and determines the range of the data.

[0035] Mantissa: used to store the mantissa (decimal) part, which determines the precision of the data.

[0036] Step S130: For any convolution operation of the target convolutional neural network, a corresponding reference level is used to implement floating-point calculation of the convolution operation.

[0037] The floating point number includes an exponent and a mantissa, and the exponent calculation includes exponent addition calculation and exponent subtraction calculation. The floating point number calculation of the convolution operation is implemented using the corresponding reference level, including:

[0038] Performing exponential addition calculation on the input exponent and the weight exponent to obtain an exponential calculation result, performing exponential subtraction calculation on the reference magnitude signal and the exponential calculation result to generate a pre-insertion 0 signal; obtaining the input mantissa of the convolution operation; performing a 0 insertion operation on the input mantissa according to the pre-insertion 0 signal so that the magnitude of the input mantissa is the reference magnitude of the convolution operation; performing mantissa calculation on each input mantissa after the 0 insertion operation to obtain a mantissa calculation result.

[0039] The convolution operation is characterized by multiplying the convolution kernel and the image element by element and then adding them. At the hardware circuit level, the convolution kernel is a set of fixed weights, which are usually stored in the SRAM array unit of the in-memory computing circuit. The elements in the image enter the computing operation as input of the in-memory computing circuit, ultimately realizing the multiplication and accumulation process.

[0040] The usual calculation process is: first, add the weight exponent to the input exponent through a full adder to obtain the exponential calculation result. The input of the full adder also includes a reference magnitude signal, which is a signal indicating the size of the reference magnitude; then perform exponential subtraction calculation on the reference magnitude signal and the exponential calculation result to obtain a zero insertion signal. Before performing the mantissa calculation, the input mantissa is inserted with zeros so that the magnitudes of each input mantissa are aligned to the reference magnitude. Finally, the mantissa calculation is performed to obtain the mantissa technical result.

[0041] In the prior art, its reference magnitude signal needs to be determined in real time during in-memory calculations. Specifically, for a group of floating-point number calculations, the prior art is to determine the maximum value in the group of floating-point numbers through an additional circuit, and use the magnitude of the maximum value as the reference magnitude and generate a reference magnitude signal to provide to the full adder. However, this solution will reduce the efficiency of in-memory calculations, because for each group of floating-point number calculations, it is necessary to determine the reference signal by finding the maximum value, and setting up an additional circuit will increase the chip area and power consumption of the memory.

[0042] The core improvement of the present invention is that the reference magnitude is not determined and the reference magnitude signal is not generated at the hardware circuit level, but the reference magnitude adapted to the target convolutional neural network is obtained by testing in advance at the software network level. Then, when the target convolutional neural network is run, the reference magnitude signal is generated by an external FPGA and provided to the full adder. This not only improves the in-memory calculation efficiency of floating-point numbers, but also reduces the chip area and power consumption of the memory.

[0043] In summary, the present invention provides an in-memory floating-point calculation method that can reduce chip area and power consumption and improve calculation efficiency, thereby solving the problem that the current in-memory floating-point calculation method will bring additional chip area and power consumption.

[0044] In some preferred embodiments, exponential addition calculation and exponential subtraction calculation are implemented by reusing the same exponential processing module; the result of exponential addition calculation is the output of the exponential processing module, and the result of exponential subtraction calculation is the two's complement of the output of the exponential processing module.

[0045] Generally, in the prior art, an addition circuit and a subtraction circuit are provided to implement exponential addition calculation and exponential subtraction calculation respectively. In the above embodiment of the present invention, exponential addition calculation and exponential subtraction calculation are implemented by multiplexing the same exponential processing module.

[0046] The exponential processing module includes a plurality of cascaded unit exponential processing circuits, the unit exponential processing circuit includes a 1-bit full adder, and the reference magnitude signal and the weight index are connected to one of the input terminals of the 1-bit full adder through a 2-to-1 selector. Accordingly, the unit exponential processing circuit also has some other structures, which will be described in detail later.

[0047] Specifically, the exponential processing module is composed of a plurality of SRAM cell arrays and a unit exponential processing circuit. The SRAM cell array is used to store weight exponents, and the unit exponential processing circuit is used for exponential calculation.

[0048] For example, the combination of a single unit index processing circuit and an SRAM cell array is as follows: Figure 3 The working process of this combination is as follows:

[0049] When the Control signal is 0, the 2-to-1 selector MUX0 selects the output signal WE (weight index signal), MUX1 selects the output signal INE (input index signal), Ci-1 is the high-order carry signal of the lower full adder, and EMAX is the reference magnitude signal. Therefore, the signals WE, INE, and Ci-1 are respectively used as the input signals of the input terminals A, B, and Ci-1 of the full adder FA. The full adder FA implements the addition operation WE+INE+Ci-1 and outputs the sum SUM and the carry Ci; under the action of the clock signal CP, the output terminals Q and Output SUM and the opposite signal of SUM respectively , the SUM signal and the carry Ci signal are the results of the addition operation between the single-bit input index and the weight index.

[0050] Reference Figure 4 , multiple unit exponent processing circuits are cascaded to form a complete exponent processing module. Through the combination of multiple unit exponent processing circuits, the carry signal of the lower bit is transmitted to the addition of the higher bit. In this way, the addition of the input exponent and the weight exponent between multiple bits can be realized by adding the carry. Among them, the unit exponent processing circuit of the highest bit and the unit exponent processing circuit of the lowest bit are different from other unit exponent processing circuits. For the unit exponent processing circuit of the lowest bit, it is Figure 4 On the basis of the unit exponential processing circuit shown, a two-to-one selector MUX2 is added, wherein the output terminal DOUT of MUX2 is connected to the low-order carry terminal Ci-1 of the 1-bit full adder circuit FA in the lowest-order exponential processing circuit, and the input terminals D0 and D1 of MUX2 are respectively connected to the logic signals 0 and 1. The highest-order exponential processing circuit does not need to be combined with the SRAM cell array, and does not need a two-to-one selector, only the 1-bit full adder circuit FA and the rising edge triggered D flip-flop DFF, the input terminal D of DFF is connected to the high-order carry terminal Ci of the lower bit, and the output terminal is connected to the input port A of the full adder FA, and the input port B of the full adder FA is connected to the reference magnitude signal.

[0051] In general, the input of the cascaded combination of multiple unit exponent processing circuits includes the weight exponent signal WE[0:7] stored in the SRAM cell array, the reference magnitude signal EMAX[0:8] and the input exponent signal INE[0:7] provided by the external FPGA, and the control signals of the MUX selector and the FA full adder. Figure 6 ,The calculation process of the index processing module is illustrated by some examples as follows.

[0052] First, the exponential addition operation is performed. When the Control signal is 0, the 2-to-1 selector MUX0 in the lowest exponential processing circuit selects the output signal WE[0], MUX1 selects the output signal INE[0], and MUX2 selects the output signal 0. Therefore, the signals WE[0], INE[n], and 0 are respectively used as the input signals of the full adder FA input terminals A, B, and Ci-1 of the lowest exponential processing circuit. The full adder FA implements the addition operation WE[0]+INE[0]+0, and outputs the sum SUM[0] and the carry Ci[0]. Under the action of the rising edge clock signal CP, the output terminals Q and Output SUM[0] and the opposite signal of SUM respectively , the low-order carry signal Ci is transmitted to the high-order Ci-1, and through the addition of the carry, the final SUM[0:8] is the sum of the addition operation of the input index and the weight index between multiple bits;

[0053] Secondly, the exponential subtraction operation, when Control = 1, the 2-to-1 selector MUX0 in the lowest exponential processing circuit selects the output signal EMAX[0], and MUX1 selects the output signal , MUX2 selects output signal 1. So the signal EMAX[0], , 1 are used as the input signals of the input terminals A, B, Ci-1 of the least significant bit exponential processing circuit full adder FA, and the full adder FA implements EMUX[0]+ +1, through the combination of multiple unit exponent processing circuits, SUM[0:8] will be inverted to [0:8], and add 1 to the lowest bit to make it in two's complement form, and enter the addition with EMAX[0:8], that is, the addition operation of the unit exponent processing circuit sub-array combination is multiplexed in two's complement form instead of the subtraction operation, thereby providing a pre-insertion 0 signal.

[0054] Taking decimal form WE=6, INE=10 as an example, their 8-bit binary representations are 0000110(6) and 0001010(10) respectively.

[0055] Addition and summation: The control terminal of the binary selector Control=0, the input signal Cin of the least significant full adder=0; the final sum is calculated by 8 full adders to be a 9-bit number WE[0:6]+INE[0:6]=000010000(16), and the value of SUM is stored in the Q port of the D flip-flop.

[0056] Subtraction operation: The control terminal of the two-choice selector Control = 1, the input signal Cin of the least significant full adder = 1; when EMAX = 14 in decimal form, the two's complement form is 000001110 (14), the full adder receives EMAX and the D flip-flop End data, that is , realizing subtraction EMAX[0:8]-SUM[0:8]=111111110 (-2), expressed in 2's complement form. When expressed in decimal form, EMAX=18, the two's complement form is 000010010 (18), which is the full adder receiving EMAX and the D flip-flop. End data, that is , implementing the subtraction EMAX[0:8]-SUM[0:8]=000000010(2).

[0057] In some embodiments, performing a zero insertion operation on an input mantissa according to a pre-zero insertion signal includes:

[0058] If the pre-0 insertion signal indicates that the number of inserted 0s is greater than the number of bits of the input mantissa, the input mantissa is set to zero; if the pre-0 insertion signal indicates that the number of inserted 0s is less than the number of bits of the input mantissa, the input mantissa is inserted with 0s according to the number of inserted 0s indicated by the pre-0 insertion signal.

[0059] The above steps are mainly implemented by the insertion 0 module, which can be subdivided into an insertion 0 judgment submodule and an insertion 0 shift submodule. The insertion 0 judgment submodule is used to judge the relationship between the number of insertion 0s indicated by the pre-insertion 0 signal and the number of bits of the input mantissa.

[0060] Exemplarily, according to the number of input mantissa bits of the BF16 data type, it can be determined that the maximum number of inserted zeros is 8 (7 mantissa bits+1 sign bit), and the pre-inserted zero signal is processed based on this.

[0061] Reference Figure 7 , specifically:

[0062] If the pre-inserted 0 signal indicates that the number of inserted 0s is greater than the number of bits of the input mantissa, the next stage can be directly passed on as a 0 signal. The reason is that the magnitude of the addition sum is much smaller than the optimal magnitude, and the gap is too large, so this data can be directly discarded.

[0063] If the pre-0 insertion signal indicates that the number of inserted zeros is less than the number of bits of the input mantissa, the pre-0 insertion signal is directly transmitted to the next stage as the inserting zero signal.

[0064] If the pre-insertion 0 signal indicates that there is no need to insert 0, the signal that there is no need to insert 0 is directly transmitted to the next stage.

[0065] Reference Figure 5 , which is the implementation circuit of the insert 0 shift submodule, including 8 rising edge triggered flip-flops (DFF0~DFF7), the circuit connection mode: all CP ports of DFF0~DFF7 are connected together, share CP signal, and RESET ports are also connected together and share RESET signal, the D port of DFF0 is always connected to 0 signal, and the Q port is connected to the D port of DFF1, the Q port of DFF1 is connected to the D port of DFF2, the Q port of DFF2 is connected to the D port of DFF3, the Q port of DFF3 is connected to the D port of DFF4, the Q port of DFF4 is connected to the D port of DFF5, the Q port of DFF5 is connected to the D port of DFF6, the Q port of DFF6 is connected to the D port of DFF7, and the Q port of DFF7 is provided as output to the next level circuit, and its main working contents include:

[0066] The insertion 0 signal generated by the insertion 0 judgment module is used to control the number of rising edges of the control signal input to the insertion 0 trigger and thus control the number of 0 insertions in the mantissa. Then, the cascade of the rising edge triggered D flip-flops is used to implement the mantissa insertion 0 operation. An example of interpolation with a shift of 2 is given. According to the BF16 data type, 8 rising edge triggered D flip-flops are cascaded to implement 8 bits of the input mantissa. When the insertion 0 signal indicates that the shift amount is 2, that is, the rising edge of CP is 2, the adjusted input mantissa 8 bits are finally implemented for mantissa in-memory calculation.

[0067] The in-memory calculation method of floating-point numbers provided by the present invention is described below through an overall embodiment.

[0068] In some embodiments, the in-memory calculation method of floating-point numbers includes: performing network-level verification on the inference process values ​​of the test set according to the convolutional neural network, selecting the optimal magnitude for the convolution process of each layer, that is, setting the baseline magnitude of each convolution layer under an acceptable loss of accuracy, aligning the calculation magnitude to it in a single convolution operation, and using this as a standard for subsequent operations.

[0069] Among them, the data type of floating-point numbers can be divided into sign bit, exponent bit, and mantissa bit, which have different functions. And according to different floating-point data types, the number of bits in each position is different. The specific functions are as follows:

[0070] Sign bit: Determines the sign of a floating-point number, usually 1 bit, with 0 or 1 representing a positive or negative floating-point number.

[0071] Exponent bit: used to store the exponent part in scientific notation and determines the range of the data.

[0072] Mantissa: used to store the mantissa (decimal) part, which determines the precision of the data.

[0073] Convolutional neural networks mainly use multiple convolution operations to extract information about different features in an image. The characteristic of a convolution operation is that the convolution kernel is element-by-element multiplied by the image and then added. At the hardware circuit level, the convolution kernel is a set of fixed weights, usually stored in the SRAM array unit of the in-memory computing circuit. The elements in the image enter the computing operation as inputs (input exponent and input mantissa) of the in-memory computing circuit, ultimately realizing the multiplication and accumulation process.

[0074] Since the floating point number performs convolution operation, that is, the exponent bits of two floating point numbers are added, and the mantissa bits are multiplied and accumulated, the processing of the exponent bits and the mantissa bits is separated in the circuit, which requires that the mantissa bits of the image element input must have the same order of magnitude when entering the mantissa bit processing circuit, so that accumulation at the same order of magnitude can be performed. The present invention maintains all values ​​before entering the mantissa processing circuit at a reference order of magnitude in a convolution layer, simplifies the operation, and realizes the preprocessing of the image element before entering the mantissa bit with acceptable precision loss, simpler circuit and lower energy consumption.

[0075] The in-memory calculation of floating-point numbers includes an exponent processing module, an input mantissa insertion 0 module, and a mantissa processing module.

[0076] The exponential processing module includes a plurality of unit exponential processing circuits, each of which is combined with a 1*8 SRAM cell array to form a calculation subarray. The calculation subarray can obtain the convolution operation between the input exponent and the weight exponent between single bits by adding the single-bit weight exponent obtained from the SRAM cell array and the external input exponent, and the combination of the subarrays formed by the unit exponential processing circuits constitutes the convolution operation between floating-point numbers with multi-bit exponents, that is, the addition operation between the floating-point input exponent and the weight exponent; then, through a control signal, the sum between the input exponent and the weight exponent realized by the addition operation is inverted and 1 is added to the lowest bit, so that the subtraction is converted into an addition operation in the form of two's complement, and the combination of multiple unit exponential processing circuits is multiplexed to realize the subtraction operation between the optimal magnitude and the sum of the addition operation, so as to provide a pre-insertion 0 signal for the next module.

[0077] The input mantissa inserting 0 module includes an inserting 0 judgment module and an inserting 0 shift module. The specific operations are as follows:

[0078] The 0-insertion judgment module is used to judge the control signal of the input mantissa 0-insertion module, and to process the pre-insertion 0 number obtained by the subtraction operation. The main contents include: according to the number of bits of the input mantissa, the maximum number of 0s that can be inserted can be judged, and the pre-insertion 0 signal is processed based on this; if the pre-insertion 0 signal indicates that the number of inserted 0s is greater than the number of bits of the input mantissa, it can be directly passed to the next stage as a set 0 signal; if the pre-insertion 0 signal indicates that the number of inserted 0s is less than the number of bits of the input mantissa, the pre-insertion 0 signal is directly passed to the next stage as a 0-insertion signal; if the pre-insertion 0 signal indicates that there is no need to insert 0, the no-insertion-0 signal is directly passed to the next stage.

[0079] The input mantissa insertion and shifting module is a module that specifically implements the insertion and shifting operation. By using the insertion and shifting signal obtained by the insertion and shifting judgment module, the input mantissa is subjected to the insertion and shifting operation, and the main contents include:

[0080] The insert 0 signal generated by the insert 0 judgment module is used to control the number of rising edges of the control signal input to the insert 0 trigger and thus control the number of 0s inserted in the mantissa, and then the cascade of D flip-flops triggered by the rising edge is used to implement the mantissa insert 0 operation.

[0081] The in-memory calculation method of floating-point numbers in the above embodiment has the following technical effects:

[0082] 1. By reducing the operations in the traditional in-memory computing solution based on floating-point calculations, the traditional maximum value search operation is replaced by selecting the optimal magnitude through testing the convolutional neural network. After adding the input and the weight index, the subtraction operation is directly performed. In this way, there is no need to find the maximum value circuit, which greatly reduces the circuit area, power consumption and delay.

[0083] 2. The present invention proposes an exponential processing module based on a novel in-memory calculation method. According to the novel in-memory calculation method, an SRAM cell array and a unit exponent processing circuit are combined into a sub-array. This sub-array serves as a basis. In the mode of "storage module + calculation module", through the combination of sub-arrays, that is, the cascade of multi-bit unit exponent processing circuits, the addition operation between the input mantissa and the weighted mantissa and the subtraction operation between the optimal magnitude and its addition operation can be realized by a circuit through a control signal, thereby providing a pre-insertion 0 signal for the next module.

[0084] 3. The present invention proposes an input mantissa insertion 0 module based on an exponential processing circuit. According to a new in-memory calculation scheme, the module is composed of two modules: an insertion 0 judgment module and an insertion 0 shift module. The pre-insertion 0 signal of the exponential processing module is classified by the insertion 0 judgment module, and a specific insertion 0 signal is provided to the insertion 0 shift module, so that the number of insertions of 0 is controlled by the number of rising edges, and then the D flip-flop triggered by the rising edge is controlled to perform the insertion 0 operation on the input mantissa, so as to complete the order of magnitude adjustment of the input mantissa before entering the mantissa in-memory calculation circuit, so as to achieve the consistency of order of magnitude after the multiplication operation in the mantissa in-memory calculation stage, and the addition operation can be directly performed, and then the whole convolution operation applied to floating-point numbers is completed.

[0085] In an embodiment of the present invention, an in-memory computing architecture is also provided, which is configured to implement multiple convolution operations in a target convolutional neural network by multiplexing, including:

[0086] The index processing module is used to realize the index calculation of the input index and the weight index, and generate a pre-insertion 0 signal according to the index calculation result and the reference magnitude signal.

[0087] The exponential processing module includes a plurality of cascaded unit exponential processing circuits, and the unit exponential processing circuit includes a 1-bit full adder.

[0088] The 0-insertion module is used to set the input mantissa to zero when the pre-insertion 0 signal indicates that the number of inserted 0s is greater than the number of bits of the input mantissa, and to perform a 0-insertion operation on the input mantissa according to the number of inserted 0s indicated by the pre-insertion 0 signal when the pre-insertion 0 signal indicates that the number of inserted 0s is less than the number of bits of the input mantissa, so that the magnitude of the input mantissa is the benchmark magnitude of the convolution operation.

[0089] The insert 0 module includes an insert 0 determination submodule and an insert 0 shift submodule.

[0090] The insert 0 judgment submodule is used to judge whether the number of inserted 0s indicated by the pre-insertion 0 signal is less than the number of bits of the input mantissa. If so, the pre-insertion 0 signal is transmitted to the insert 0 shift submodule; otherwise, the set 0 signal is transmitted to the insert 0 shift submodule.

[0091] The zero-insertion and shifting submodule is used to insert zero into the input mantissa according to the pre-insertion zero signal, and to set the input mantissa to zero according to the set zero signal.

[0092] The mantissa calculation module is used to perform mantissa calculation on each input mantissa after the 0 insertion operation to obtain a mantissa calculation result.

[0093] It should be noted that the above-mentioned in-memory computing architecture is built based on the in-memory computing method provided by the present invention, and is used to implement the in-memory computing method provided by the present invention. Therefore, the operating principle and detailed features of the in-memory computing architecture can refer to the introduction of the in-memory computing method above.

[0094] In an embodiment of the present invention, an in-memory computing chip is also provided, which integrates the in-memory computing architecture provided by the present invention.

[0095] In an embodiment of the present invention, a static random access memory is also provided, which adopts the in-memory computing chip provided by the present invention.

[0096] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0097] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. A method for calculating a floating point number in memory, wherein the floating point number comprises an exponent and a mantissa, characterized in that: include: Calculating the inference accuracy loss of a target convolutional neural network on a test set under different combinations of convolution magnitudes, wherein the target convolutional neural network is used to extract feature information from an image through multiple convolution operations; Determine a convolution magnitude combination as a target convolution magnitude combination from the convolution magnitude combinations corresponding to at least one inference accuracy loss that is less than a target value, wherein the target convolution magnitude combination includes a reference magnitude of each convolution operation; For any convolution operation of the target convolutional neural network: obtain the input exponent of the convolution operation; perform exponential addition calculation on the input exponent and the weight exponent to obtain an exponential calculation result, perform exponential subtraction calculation on the reference magnitude signal and the exponential calculation result to generate a pre-insertion 0 signal; obtain the input mantissa of the convolution operation; perform a 0 insertion operation on the input mantissa according to the pre-insertion 0 signal so that the magnitude of the input mantissa is the reference magnitude of the convolution operation; perform a mantissa calculation on each of the input mantissas after the 0 insertion operation to obtain a mantissa calculation result.

2. The in-memory calculation method of floating-point numbers according to claim 1, wherein: The exponential addition calculation and the exponential subtraction calculation are implemented by reusing the same exponential processing module; The result of the exponential addition calculation is the output of the exponential processing module, and the result of the exponential subtraction calculation is the two's complement of the output of the exponential processing module.

3. The method for calculating floating point numbers according to claim 2, wherein: The exponential processing module includes a plurality of cascaded unit exponential processing circuits, each of which includes a 1-bit full adder, and the reference magnitude signal and the weight index are connected to one of the input terminals of the 1-bit full adder via a 2-to-1 selector.

4. The in-memory calculation method of floating-point numbers according to claim 1, wherein: Performing a 0-insertion operation on the input mantissa according to the pre-insertion 0 signal includes: If the pre-insertion 0 signal indicates that the number of inserted 0s is greater than the number of bits of the input mantissa, the input mantissa is set to zero; If the number of inserted zeros indicated by the pre-insertion-0 signal is less than the number of bits of the input mantissa, a zero insertion operation is performed on the input mantissa according to the number of inserted zeros indicated by the pre-insertion-0 signal.

5. The in-memory calculation method of floating-point numbers according to claim 1, wherein: Multiple convolution operations in the target convolutional neural network are implemented by reusing the in-memory computing architecture.

6. The in-memory calculation method of floating-point numbers according to claim 5, wherein: The in-memory computing architecture includes: An index processing module, used to realize the index calculation of the input index and the weight index, and generate a pre-insertion 0 signal according to the index calculation result and the reference magnitude signal; a zero-insertion module, configured to set the input mantissa to zero when the pre-0-insertion signal indicates that the number of inserted zeros is greater than the number of bits of the input mantissa, and to perform a zero-insertion operation on the input mantissa according to the number of inserted zeros indicated by the pre-0-insertion signal when the pre-0-insertion signal indicates that the number of inserted zeros is less than the number of bits of the input mantissa, so that the magnitudes of the input mantissas are all the reference magnitudes of the convolution operation; The mantissa calculation module is used to perform mantissa calculation on each of the input mantissas after the 0 insertion operation to obtain a mantissa calculation result.

7. The in-memory calculation method of floating-point numbers according to claim 6, wherein: The plug 0 module includes a plug 0 determination submodule and a plug 0 shift submodule; The insert 0 judgment submodule is used to judge whether the number of inserted 0s indicated by the pre-insert 0 signal is less than the number of bits of the input mantissa, and if so, transmit the pre-insert 0 signal to the insert 0 shift submodule, and if not, transmit the set 0 signal to the insert 0 shift submodule; The zero-insertion and shifting submodule is used to insert zero into the input mantissa according to the pre-zero-insertion signal, and to set the input mantissa to zero according to the zero-setting signal.

8. The in-memory calculation method of floating point numbers according to claim 6, wherein: The exponential processing module includes a plurality of cascaded unit exponential processing circuits, each of which includes a 1-bit full adder, and the reference magnitude signal and the weight index are connected to one of the input terminals of the 1-bit full adder via a 2-to-1 selector.

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