Memory training method, memory controller, processor and electronic equipment

Abstract

The invention relates to a memory training method, a memory controller, a processor and electronic equipment, and belongs to the field of electronic circuits. The memory training method is applied to a memory controller and comprises the following steps: acquiring an initial transmission delay range; wherein the initial transmission delay range is a transmission delay range of theoretically correct transmission of DQ data; the transmission delay of a DQS time sequence signal or a DQ data signal is adjusted based on the initial transmission delay range, a target transmission delay range for actually and correctly transmitting DQ data is determined from the initial transmission delay range, and the DQS time sequence signal and the DQ data signal are interaction signals between the memory controller and the memory chip; the target transmission delay range is smaller than or equal to the initial transmission delay range, and the target transmission delay range is the relative timing margin of the DQ data signal and the DQS timing signal. Through memory training, the accuracy of data transmission between the memory controller and the memory chip can be improved, and meanwhile, the efficiency of memory training can be improved.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to a memory training method, a memory controller, a processor and an electronic device. Background Art

[0002] Most electronic devices integrate processors and memory chips. The processor and memory chip need to be driven by a memory controller, and the memory controller and memory chip are connected through a memory bus. The data signal line DQ transmits the data signal. DQ is the abbreviation of the data signal defined in the Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) protocol. The timing signal line DQS can transmit the data strobe pulse signal. DQS is the abbreviation of the data strobe pulse signal defined in the DDR protocol.

[0003] The memory controller transmits data through DQ and DQS in the process of accessing memory chip data. In the process of the memory controller writing data to the memory chip, the memory controller can send DQ and DQS to the memory chip. The DQ can carry the data that the memory controller wants to write to the memory chip, and the DQS can trigger the memory chip to identify the level state of the above DQ, and then write the data carried in the DQ to the memory chip. Conversely, in the process of the memory controller reading the memory chip data, the memory chip sends data from the DQ to the memory controller, and the memory controller collects the DQ data according to the DQS.

[0004] According to the working principle of DQ and DQS, the accuracy of data transmission between the memory controller and the memory chip depends on the relative timing position alignment between DQ and DQS, that is, only when DQ has sufficient timing margin relative to DQS can the receiving end of DQ have a lower bit error rate, thereby ensuring the accuracy of data transmission. Voltage, temperature, and frequency may cause changes in the phase of DQ and DQS. How to make DQ have sufficient timing margin relative to DQS to improve the accuracy of data transmission has become the focus of the industry. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a memory training method, a memory controller, a processor and an electronic device to improve the accuracy of data transmission between the memory controller and the memory chip.

[0006] The embodiment of the present application is implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a memory training method, which is applied to a memory controller, and the method includes: obtaining an initial transmission delay range; wherein the initial transmission delay range is a theoretical transmission delay range for correctly transmitting DQ data; adjusting the transmission delay of a DQS timing signal or a DQ data signal based on the initial transmission delay range, and determining a target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip; the target transmission delay range is less than or equal to the initial transmission delay range, and the target transmission delay range is a relative timing margin between the DQ data signal and the DQS timing signal.

[0008] In the above embodiment, memory training is used to ensure that the DQ data signal and the DQS timing signal have sufficient relative timing margin to improve the accuracy of data transmission between the memory controller and the memory chip. At the same time, since the maximum transmission delay range that can be adjusted (i.e., the initial transmission delay range) is given in advance, during adjustment, the transmission delay of the DQS timing signal or the DQ data signal is adjusted only within the initial transmission delay range and will not exceed the initial transmission delay range. This can reduce unnecessary adjustment processes, thereby quickly determining the target transmission delay range for actually correctly transmitting the DQ data from the initial transmission delay range, which is beneficial to improving the efficiency of memory training.

[0009] In combination with a possible implementation manner of the first aspect, a target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range, including: using a binary method to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range.

[0010] In the above embodiment, the binary search method is used to determine the target transmission delay range for actually correctly transmitting the DQ data from the initial transmission delay range. This allows the target transmission delay range for actually correctly transmitting the DQ data to be quickly determined without traversing every value within the initial transmission delay range, which is beneficial to improving the efficiency of memory training.

[0011] In combination with a possible implementation method of the first aspect, a target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range using a binary search method, including: dividing the initial transmission delay range into two parts from the middle position, namely, a first interval and a second interval, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; determining whether the first interval includes a first transmission delay range for correctly transmitting DQ data; if the first interval does not include the first transmission delay range for correctly transmitting DQ data, determining a target transmission delay range for correctly transmitting DQ data from the second interval.

[0012] In the above embodiment, the initial transmission delay range is first divided into a first interval and a second interval, and then it is determined whether the first interval includes the first transmission delay range for correctly transmitting the DQ data. If not, the target transmission delay range for correctly transmitting the DQ data is determined from the second interval. In this way, the target transmission delay range for actually correctly transmitting the DQ data can be quickly determined.

[0013] In combination with a possible implementation manner of the first aspect, if the first interval includes a first transmission delay range for correctly transmitting DQ data, the method also includes: determining whether the middle value of the initial transmission delay range can correctly transmit the DQ data; if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, determining that the first transmission delay range is the target transmission delay range.

[0014] In the above embodiment, when the first interval includes the first transmission delay range for correctly transmitting DQ data, if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, it indicates that the valid interval is on the left or right side of the middle value, and at the same time, the first transmission delay range for correctly transmitting the DQ data can be determined from the first interval. Therefore, it can be determined that the second interval cannot correctly transmit the DQ data, so that it can be determined that the first transmission delay range is the required target transmission delay range. Since the traversal of the second interval is reduced, the efficiency of memory training can be improved.

[0015] In combination with a possible implementation manner of the embodiment of the first aspect, if the middle value of the initial transmission delay range can correctly transmit DQ data, the method also includes: determining a second transmission delay range for correctly transmitting DQ data from the second interval; determining the target transmission delay range based on the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0016] In the above embodiment, when the middle value of the initial transmission delay range can correctly transmit the DQ data, it indicates that the valid interval is on the left and right sides of the middle value. Therefore, it is necessary to determine the second transmission delay range for correctly transmitting the DQ data from the second interval, and then determine the target transmission delay range based on the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range. In this way, the accuracy and completeness of the target transmission delay range can be guaranteed, thereby ensuring that the DQ data signal and the DQS timing signal have sufficient relative timing margin.

[0017] In combination with a possible implementation manner of the embodiment of the first aspect, a target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range by using a binary search method, including: dividing the initial transmission delay range into two from the middle position, into a first interval and a second interval, wherein the first interval and the second interval do not contain the middle value of the initial transmission delay range; judging whether the middle value of the initial transmission delay range can correctly transmit the DQ data; if the middle value of the initial transmission delay range can correctly transmit the DQ data, determining a first transmission delay range and a second transmission delay range for correctly transmitting the DQ data from the first interval and the second interval respectively; determining the target transmission delay range according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0018] In the above embodiment, it is first determined whether the middle value of the initial transmission delay range can correctly transmit the DQ data, so that it can be determined whether the effective interval is on the left or right side of the middle value, or on the left or right side of the middle value. When the middle value of the initial transmission delay range can correctly transmit the DQ data, it indicates that the effective interval is on the left and right sides of the middle value. Therefore, it is necessary to determine the first transmission delay range and the second transmission delay range for correctly transmitting the DQ data from the first interval and the second interval respectively, and then determine the target transmission delay range according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range. In this way, the accuracy and integrity of the target transmission delay range can be guaranteed, thereby ensuring that the DQ data signal and the DQS timing signal have sufficient relative timing margin.

[0019] In combination with a possible implementation manner of the embodiment of the first aspect, if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, the method also includes: if the first interval includes the first transmission delay range for correctly transmitting the DQ data, determining the first transmission delay range as the target transmission delay range; if the first interval does not include the first transmission delay range for correctly transmitting the DQ data, determining the target transmission delay range for correctly transmitting the DQ data from the second interval.

[0020] In the above embodiment, if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, it indicates that the valid interval is on the left or right side of the middle value, and then it is determined whether the first interval includes the first transmission delay range for correctly transmitting the DQ data. When the first interval includes the first transmission delay range for correctly transmitting the DQ data, the first transmission delay range is directly determined as the target transmission delay range; when the first interval does not include the first transmission delay range for correctly transmitting the DQ data, the target transmission delay range for correctly transmitting the DQ data is determined from the second interval, so that the required target transmission delay range can be quickly determined.

[0021] In combination with a possible implementation manner of the embodiment of the first aspect, a first transmission delay range and a second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval respectively, including: using binary search to determine the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval respectively.

[0022] In the above embodiment, the first transmission delay range and the second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval respectively by using the binary search method, which is beneficial to further improve the memory training efficiency.

[0023] In the second aspect, an embodiment of the present application also provides a memory controller, including: a delay adjustment module and a control module; the delay adjustment module is used to adjust the transmission delay of a DQS timing signal or a DQ data signal, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip; the control module is used to obtain an initial transmission delay range; wherein the initial transmission delay range is a theoretical transmission delay range for correctly transmitting DQ data; and the delay adjustment module is controlled to adjust the transmission delay of the DQS timing signal or the DQ data signal based on the initial transmission delay range, and determine a target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range, wherein the target transmission delay range is less than or equal to the initial transmission delay range, and the target transmission delay range is a relative timing margin between the DQ data signal and the DQS timing signal.

[0024] In combination with a possible implementation manner of the embodiment of the second aspect, the control module is specifically used to: determine a target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range by using a binary search method.

[0025] In combination with a possible implementation manner of the second aspect embodiment, the control module is specifically used to: divide the initial transmission delay range from the middle position into two, into a first interval and a second interval, wherein the first interval and the second interval do not include the middle value of the initial transmission delay range; determine whether the first interval includes the first transmission delay range for correctly transmitting DQ data; if the first interval does not include the first transmission delay range for correctly transmitting DQ data, determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0026] In combination with a possible implementation manner of the second aspect embodiment, if the first interval includes a first transmission delay range for correctly transmitting DQ data, the control module is specifically used to: determine whether the middle value of the initial transmission delay range can correctly transmit the DQ data; if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, determine the first transmission delay range as the target transmission delay range; if the middle value of the initial transmission delay range can correctly transmit the DQ data, determine a second transmission delay range for correctly transmitting the DQ data from the second interval; determine the target transmission delay range based on the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0027] In combination with a possible implementation manner of the second aspect embodiment, the control module is specifically used to: divide the initial transmission delay range from the middle position into two parts, a first interval and a second interval, wherein the first interval and the second interval do not contain the middle value of the initial transmission delay range; determine whether the middle value of the initial transmission delay range can correctly transmit the DQ data; if the middle value of the initial transmission delay range can correctly transmit the DQ data, determine the first transmission delay range and the second transmission delay range for correctly transmitting the DQ data from the first interval and the second interval respectively; determine the target transmission delay range according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0028] In combination with a possible implementation manner of the second aspect, if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, the control module is specifically used to: if the first interval includes the first transmission delay range for correctly transmitting the DQ data, determine the first transmission delay range as the target transmission delay range; if the first interval does not include the first transmission delay range for correctly transmitting the DQ data, determine the target transmission delay range for correctly transmitting the DQ data from the second interval.

[0029] In the third aspect, an embodiment of the present application also provides a processor, comprising: a processor core and a memory controller provided as the above-mentioned second aspect embodiment and / or any possible implementation method combined with the above-mentioned second aspect embodiment; the processor core is used to send training instructions to the memory controller; the memory controller is used to perform memory training in response to the training instructions.

[0030] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a memory chip and a processor as provided in the embodiment of the third aspect above, wherein the memory chip is connected to a memory controller in the processor.

[0031] In the fifth aspect, an embodiment of the present application also provides an electronic device, comprising: a processor, a memory chip, and a memory controller provided as the above-mentioned second aspect embodiment and / or any possible implementation method combined with the above-mentioned second aspect embodiment, the memory controller is connected to the processor and the memory chip respectively; the processor is used to send training instructions to the memory controller; the memory controller is used to perform memory training in response to the training instructions.

[0032] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0034] Figure 1 A schematic diagram of the connection between a memory controller and a memory chip provided in an embodiment of the present application is shown.

[0035] Figure 2 A flow chart of a memory training method provided in an embodiment of the present application is shown.

[0036] Figure 3 A schematic flow chart of a first implementation of S2 provided in an embodiment of the present application is shown.

[0037] Figure 4 A flow chart of a second implementation of S2 provided in an embodiment of the present application is shown.

[0038] Figure 5A schematic flow chart of a third implementation of S2 provided in an embodiment of the present application is shown.

[0039] Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0041] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0042] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0043] In electronic devices, the memory controller and memory chips are connected via a memory bus. Figure 1 As shown, the memory bus mainly includes at least one data signal line (represented by DQ), a timing signal line (represented by DQS) and a signal line for sending read and write commands (represented by CA). Among them, CA is the bus for the memory controller to send read and write commands, DQ is the bus for sending and receiving data between the memory controller and the memory chip, and DQS is the reference signal sampled by the receiving end.

[0044] The scenario of the memory training method shown in the embodiment of the present application can occur in a scenario where a memory controller writes data to a memory chip, or it can also occur in a scenario where a memory controller reads data from a memory chip.

[0045] In a possible implementation, it can be as follows Figure 1 As shown, multiple data signal lines (such as DQ0-DQn) share one DQS and CA bus. Compared with each data signal line corresponding to one DQS and CA bus, the number of buses can be saved, thereby saving power consumption.

[0046] In order to improve the accuracy of data transmission between a memory controller and a memory chip, the embodiment of the present application provides a memory training method, a memory controller, a processor and an electronic device. Figure 2 The method shown is used to illustrate the memory training method provided by the embodiment of the present application. The memory training method provided by the embodiment of the present application can be applied to a memory controller, that is, the execution subject of the memory training method can be a memory controller.

[0047] S1: Get the initial transmission delay range.

[0048] When the memory needs to be trained, the initial transmission delay range (i.e., the initial delay line range) can be obtained, wherein the initial transmission delay range is the transmission delay range for theoretically correct transmission of DQ data, that is, the transmission delay range for theoretically correct transmission of DQ data between the memory controller and the memory chip. The initial transmission delay range is the theoretical relative timing margin between the DQ data signal and the DQS timing signal, and the initial transmission delay range can be obtained by testing before the memory chip leaves the factory.

[0049] In one implementation, the initial transmission delay range can be stored in the register group in advance, and the memory controller can directly obtain the initial transmission delay range from the register group after receiving the training instruction from the processor (or processor core), thereby starting the memory training. In another implementation, the initial transmission delay range can also be sent from the processor (or processor core), and the memory controller starts the memory training after receiving the initial transmission delay range sent from the processor (or processor core).

[0050] S2: adjusting the transmission delay of the DQS timing signal or the DQ data signal based on the initial transmission delay range, and determining a target transmission delay range for actually correctly transmitting the DQ data from within the initial transmission delay range.

[0051] After obtaining the initial transmission delay range, the transmission delay of the DQS timing signal or the DQ data signal can be adjusted based on the initial transmission delay range, and the target transmission delay range for actually correctly transmitting the DQ data can be determined from the initial transmission delay range. Among them, the target transmission delay range is less than or equal to the initial transmission delay range, and the target transmission delay range is the relative timing margin between the DQ data signal and the DQS timing signal. Within this relative timing margin, the DQ data can be correctly transmitted between the memory controller and the memory chip. The purpose of memory training is to maintain sufficient timing margin for the DQ data transmitted between the memory controller and the memory chip.

[0052] It is understandable that in actual scenarios, the DQS timing signal and the DQ data signal will be affected by factors such as chip voltage, temperature, and frequency, which may cause the actual transmission delay range for correctly transmitting DQ data between the memory controller and the memory chip to be reduced. Therefore, it is necessary to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range.

[0053] In actual scenarios, there is usually a delayline range in the middle of the initial transmission delay range that can be sampled successfully, that is, the delay line valid window (that is, the target transmission delay range), and the values ​​on both sides of the initial transmission delay range will fail to be sampled. If the DQ data transmitted by the DQ data signal is sampled successfully using the DQS timing signal, it is considered that the DQ data can be correctly transmitted. If the DQ data transmitted by the DQ data signal is sampled unsuccessfully using the DQS timing signal, it is considered that the DQ data cannot be correctly transmitted. Taking reading and writing data as an example, if the data at the sending end is consistent with the data sampled at the receiving end, the sampling is considered successful, otherwise the sampling is considered failed. In order to ensure that the data can be transmitted correctly, multiple samplings can be performed during sampling. If multiple samplings are successful, it is considered that the DQ data can be correctly transmitted. If at least one sampling fails in multiple samplings, it is considered that the DQ data cannot be correctly transmitted. Usually, the receiving end samples the DQ data signal when the DQS jumps, and uses the instantaneous level state of the sampled DQ as the DQ data.

[0054] When adjusting the transmission delay of the DQS timing signal or the DQ data signal based on the initial transmission delay range, the transmission delay of the DQS timing signal can be kept unchanged and the transmission delay of the DQ data signal can be adjusted within the initial transmission delay range; or the transmission delay of the DQ data signal can be kept unchanged and the transmission delay of the DQS timing signal can be adjusted within the initial transmission delay range. Figure 1In the example shown, multiple DQ lines correspond to one DQS line, and the preferred solution is: keep the transmission delay of the DQS timing signal unchanged, and adjust the transmission delay of the DQ data signal within the initial transmission delay range. When there are many DQ lines to be trained, each DQ line can be trained in the same way to determine the relative timing margin between each DQ line and the DQS line. Among them, when adjusting the transmission delay, the relative transmission delay increased or decreased between the DQS timing signal and the DQ data signal cannot exceed the initial transmission delay range.

[0055] Since the maximum adjustable transmission delay range (i.e., the initial transmission delay range) is given in advance in the present application, during adjustment, the transmission delay of the DQS timing signal or the DQ data signal is adjusted only within the initial transmission delay range without exceeding the initial transmission delay range. This can reduce unnecessary adjustment processes, thereby quickly determining the target transmission delay range for actually correctly transmitting the DQ data from the initial transmission delay range, which is beneficial to improving the efficiency of memory training.

[0056] When adjusting the transmission delay of the DQS timing signal or the DQ data signal, the transmission delay of the DQS timing signal or the DQ data signal can be adjusted by traversing each value in the initial transmission delay range, so as to determine the target transmission delay range. In this implementation, it is necessary to traverse each value in the initial transmission delay range. For example, assuming that the initial transmission delay range is (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5), it is necessary to traverse each value in it to determine whether the DQ data can be correctly transmitted under each transmission delay, so as to determine the target transmission delay range. The positive and negative signs in the above ranges represent the offset direction, such as -0.3 in the range can be regarded as shifting the transmission delay of the DQ or DQS signal to the left by 0.3t, and 0.2 can be regarded as shifting the transmission delay of the DQ or DQS signal to the right by 0.2t, where t is the period of the signal, and the other values ​​are similar. The numerical values ​​exemplified here are only for the purpose of helping understanding and should not be understood as limiting the present application.

[0057] In order to further improve the efficiency of memory training, in one implementation, when determining the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range, the binary search method can be used to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range. Among them, the binary search method is a search algorithm for finding a specific element in an ordered array. It quickly locates the target value by reducing the search range by half each time. In this way, the target transmission delay range for actually correctly transmitting DQ data can be quickly determined without traversing every value in the initial transmission delay range, which is conducive to improving the efficiency of memory training.

[0058] In some implementations, other methods may be used to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range. For example, the binary division method may be replaced by the trisection method or other division methods, which may theoretically improve the efficiency of memory training.

[0059] In a possible implementation manner, when the target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range by using the dichotomy method, the principle can be as follows: Figure 3 The process shown includes the following steps.

[0060] S21: Divide the initial transmission delay range into two from the middle position, namely, a first interval and a second interval.

[0061] The initial transmission delay range is divided into two from the middle position, into a first interval and a second interval, and neither the first interval nor the second interval contains the middle value of the initial transmission delay range. Among them, the first interval can be a left interval, and correspondingly, the second interval is a right interval, and vice versa, the first interval can be a right interval, and correspondingly, the second interval is a left interval. For example, taking the initial transmission delay range of (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5) in the above example, the first interval can be (-0.5, -0.4, -0.3, -0.2, -0.1), and the second interval can be (0.1, 0.2, 0.3, 0.4, 0.5).

[0062] It can be understood that the intermediate value at the middle position can be one or two. For example, for the initial transmission delay range of (-0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5), the first interval can be (-0.4, -0.3, -0.2, -0.1), the second interval can be (0.2, 0.3, 0.4, 0.5), and the intermediate value is (0, 0.1). For another example, for the initial transmission delay range of (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4), the first interval can be (-0.5, -0.3, -0.2), the second interval can be (0.1, 0.2, 0.3, 0.4), and the intermediate value is (-0.1, 0).

[0063] S22: Determine whether the first interval includes a first transmission delay range for correctly transmitting DQ data.

[0064] After dividing the initial transmission delay range into a first interval and a second interval, determine whether the first interval includes the first transmission delay range for correctly transmitting the DQ data, that is, determine whether the first transmission delay range for correctly transmitting the DQ data can be determined from the first interval; if the first transmission delay range for correctly transmitting the DQ data cannot be determined from the first interval, that is, the first interval does not include the first transmission delay range for correctly transmitting the DQ data, then execute S23; if the first transmission delay range for correctly transmitting the DQ data can be determined from the first interval, that is, the first interval includes the first transmission delay range for correctly transmitting the DQ data, then execute S24.

[0065] Among them, when determining the first transmission delay range for correctly transmitting DQ data from the first interval, it can be determined by traversing each value in the first interval to determine whether the first transmission delay range for correctly transmitting DQ data can be determined from the first interval. In order to improve the efficiency of memory training, in one implementation, the first transmission delay range for correctly transmitting DQ data can be determined from the first interval using a binary search method. At this time, the implementation process of determining whether the first transmission delay range for correctly transmitting DQ data can be determined from the first interval can be: determining whether the first transmission delay range for correctly transmitting DQ data can be determined from the first interval using a binary search method.

[0066] When the first transmission delay range for correctly transmitting DQ data is determined from the first interval by using the binary search method, it is first determined whether the middle value of the first interval can correctly transmit DQ data. If it can, it means that the middle value is within the valid window, and the valid boundaries are distributed on the left and right sides of the middle value; if it cannot, it means that the valid boundaries are distributed on the left or right side of the middle value; then, it is determined whether the middle values ​​of the left and right areas of the middle value can correctly transmit DQ data, and so on, until the middle value of a certain range (such as the range has only 2 values) cannot be found. When the middle value of a certain range (such as the range has only 2 values) cannot be found by using the binary search method, it is first determined whether the value in the range that is closer to the initial middle value (the middle value of the initial transmission delay range) can correctly transmit DQ data. If the DQ data can be correctly transmitted, it is then determined whether another value in the range can correctly transmit DQ data. If the value closer to the initial middle value cannot correctly transmit DQ data, it is not necessary to determine whether the value in the range that is farther from the initial middle value (the other value in the range) can correctly transmit DQ data.

[0067] S23: Determine a target transmission delay range for correctly transmitting DQ data from the second interval.

[0068] When the first transmission delay range for correctly transmitting the DQ data cannot be determined from the first interval, that is, when the first interval does not include the first transmission delay range, a target transmission delay range for correctly transmitting the DQ data is determined from the second interval.

[0069] When determining the target transmission delay range for correctly transmitting DQ data from the second interval, the target transmission delay range for correctly transmitting DQ data can also be determined by traversing each value in the second interval. In order to improve the efficiency of memory training, in one implementation, the target transmission delay range for correctly transmitting DQ data can be determined from the second interval using a binary search method.

[0070] S24: Determine whether the middle value of the initial transmission delay range can correctly transmit DQ data.

[0071] When the first transmission delay range for correctly transmitting DQ data can be determined from the first interval, it is determined whether the middle value of the initial transmission delay range can correctly transmit DQ data. When the middle value of the initial transmission delay range cannot correctly transmit DQ data, S25 is executed, and when the middle value of the initial transmission delay range can correctly transmit DQ data, S26 is executed.

[0072] S25: Determine the first transmission delay range as the target transmission delay range.

[0073] When the middle value of the initial transmission delay range cannot correctly transmit the DQ data, the first transmission delay range is determined as the target transmission delay range.

[0074] S26: Determine a second transmission delay range for correctly transmitting DQ data from the second interval.

[0075] When the middle value of the initial transmission delay range can correctly transmit the DQ data, a second transmission delay range for correctly transmitting the DQ data is determined from the second interval.

[0076] When determining the second transmission delay range for correctly transmitting DQ data from the second interval, each value in the second interval may be traversed to determine the second transmission delay range for correctly transmitting DQ data. In order to improve the efficiency of memory training, in one implementation, the second transmission delay range for correctly transmitting DQ data may be determined from the second interval using a binary search method.

[0077] S27: Determine the target transmission delay range according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0078] After determining the second transmission delay range for correctly transmitting DQ data from the second interval, the target transmission delay range is determined according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range. The target transmission delay range is the union of the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range. For example, taking the initial transmission delay range of (-0.5, -0.4, -0.3, -0.2, -0.1, 0, 0.1, 0.2, 0.3, 0.4, 0.5) in the above example, assuming that the first transmission delay range is (-0.3, -0.2, -0.1) and the second transmission delay range is (0.1, 0.2), the target transmission delay range is (-0.3, -0.2, -0.1, 0, 0.1, 0.2).

[0079] In another possible implementation, when the target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range by using the dichotomy method, the principle can be as follows: Figure 4 As shown, the following steps are included.

[0080] S201: Divide the initial transmission delay range into two from the middle position, namely, a first interval and a second interval, and determine whether the middle value of the initial transmission delay range can correctly transmit DQ data.

[0081] The initial transmission delay range is divided into a first interval and a second interval, and it is determined whether the middle value of the initial transmission delay range can correctly transmit the DQ data. If the middle value of the initial transmission delay range can correctly transmit the DQ data, S202 is executed, otherwise S204 is executed.

[0082] S202: Determine a first transmission delay range and a second transmission delay range for correctly transmitting DQ data from the first interval and the second interval respectively.

[0083] When the middle value of the initial transmission delay range can correctly transmit the DQ data, a first transmission delay range and a second transmission delay range for correctly transmitting the DQ data are determined from the first interval and the second interval respectively.

[0084] S203: Determine the target transmission delay range according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0085] After the first transmission delay range and the second transmission delay range are determined, the target transmission delay range is determined according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0086] S204: Determine whether the first interval includes a first transmission delay range for correctly transmitting DQ data.

[0087] When the middle value of the initial transmission delay range cannot correctly transmit the DQ data, it is determined whether the first interval includes the first transmission delay range for correctly transmitting the DQ data, that is, it is determined whether the first transmission delay range for correctly transmitting the DQ data can be determined from the first interval. If the first transmission delay range for correctly transmitting the DQ data can be determined from the first interval, S205 is executed; if the first transmission delay range for correctly transmitting the DQ data cannot be determined from the first interval, S206 is executed.

[0088] S205: Determine the first transmission delay range as the target transmission delay range.

[0089] When the first transmission delay range for correctly transmitting the DQ data can be determined from the first interval, that is, when the first interval includes the first transmission delay range for correctly transmitting the DQ data, the first transmission delay range is determined as the target transmission delay range.

[0090] S206: Determine a target transmission delay range for correctly transmitting DQ data from the second interval.

[0091] When the first transmission delay range for correctly transmitting the DQ data cannot be determined from the first interval, that is, the first interval does not include the first transmission delay range for correctly transmitting the DQ data, a target transmission delay range for correctly transmitting the DQ data is determined from the second interval.

[0092] Figure 4 The embodiment shown is Figure 3Compared with the illustrated embodiment, the main difference lies in that the order of determining whether the middle value of the initial transmission delay range can correctly transmit DQ data and determining whether the first interval includes the first transmission delay range for correctly transmitting DQ data is different.

[0093] In another possible implementation, when the target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range by using the dichotomy method, the principle can be as follows: Figure 5 As shown, the following steps are included.

[0094] S200: Divide the initial transmission delay range into two from the middle position, namely, a first interval and a second interval.

[0095] S202: Determine a first transmission delay range and a second transmission delay range for correctly transmitting DQ data from the first interval and the second interval respectively.

[0096] After the initial transmission delay range is divided into a first interval and a second interval, a first transmission delay range and a second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval respectively.

[0097] S203: Determine the target transmission delay range according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0098] After the first transmission delay range and the second transmission delay range are determined, the target transmission delay range is determined according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0099] When determining the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively, in one implementation, each value in the first interval and the second interval may be traversed to determine the first transmission delay range and the second transmission delay range for correctly transmitting DQ data from the first interval and the second interval, respectively. In another implementation, the first transmission delay range and the second transmission delay range for correctly transmitting DQ data may be determined from the first interval and the second interval by using a binary search method, respectively. Figure 5 The embodiment shown is Figure 4 Compared with the embodiment shown, the main difference is that the logic of the judgment part is missing, and the middle value of the initial transmission delay range is assumed to be able to correctly transmit the DQ data.

[0100] For a better understanding, the above memory training method is explained with an example below. Assume that the initial delayline range is [-0.5:0.5] and the final effective window is [-0.3:0.1].

[0101] The following is the above Figure 4 The logic shown is explained, with the middle value 0 as the dividing point, the initial delayline range is divided into two, the left interval [-0.5:-0.1], the right interval [0.1:0.5], and it is determined whether the middle value 0 can correctly transmit DQ data, that is, the transmission delay of the DQS timing signal or the DQ data signal is adjusted based on the middle value 0, and then the DQ data transmitted by the DQ data signal is sampled and trained using the DQS timing signal. If the DQ data can be correctly transmitted (training success or sampling success), it means that 0 is within the valid window, and the valid boundaries are distributed on the left and right sides of the middle value 0. If the middle value 0 cannot correctly transmit the DQ data (training failure or sampling failure), it means that the valid boundaries are distributed on the left or right sides of the middle value 0. The principle of the first scan training is shown in Table 1, and the gray part in Table 1 is the part where the valid window is located.

[0102] Table 1

[0103]

[0104] Taking the left interval scanned first as an example, the middle value of the left interval [-0.5:-0.1] is -0.3, and the middle value -0.3 of the left interval is scanned for the second time to determine whether the DQ data can be correctly transmitted, that is, the transmission delay of the DQS timing signal or the DQ data signal is adjusted based on the middle value -0.3, and then the DQ data transmitted by the DQ data signal is sampled and trained using the DQS timing signal. If the DQ data can be correctly transmitted (sampling is successful), it means that -0.3 is within the valid window, and the valid boundaries are distributed on the left and right sides of the middle value -0.3. If the middle value -0.3 cannot correctly transmit the DQ data (sampling fails), it means that the valid boundaries are distributed on the left or right sides of the middle value -0.3. The principle of the second scan training is shown in Table 2, and the gray part in Table 2 is the part where the valid window is located.

[0105] Table 2

[0106]

[0107] In this example, the middle value -0.3 can correctly transmit DQ data, so the scan continues to scan [-0.5:-0.4] on the left side of the middle value -0.3. Since this interval only contains two values, the middle value cannot be scanned. At this time, -0.4, which is closer to the window center 0, is scanned first. If -0.4 cannot correctly transmit DQ data, it means that the left boundary is -0.3. The principle of the third training scan is shown in Table 3, and the gray part in Table 3 is the part where the valid window is located.

[0108] Table 3

[0109]

[0110] In this example, -0.4 cannot transmit DQ data correctly, that is, the training fails, so the scanning of the left interval is ended and switched to the right interval. The middle value of the right interval [0.1:0.5] is 0.3. It is judged whether 0.3 can transmit DQ data correctly, that is, the transmission delay of the DQS timing signal or the DQ data signal is adjusted based on the middle value 0.3, and then the DQ data transmitted by the DQ data signal is sampled and trained using the DQS timing signal. If the DQ data can be transmitted correctly (sampling is successful), it means that 0.3 is within the valid window, and the valid boundaries are distributed on the left and right sides of the middle -0.3. If the middle value 0.3 cannot transmit DQ data correctly (sampling fails), it means that the valid boundaries are distributed on the left or right sides of the middle value 0.3. The principle of the first scanning training of the right interval is shown in Table 4. The gray part in Table 4 is the part where the valid window is located.

[0111] Table 4

[0112]

[0113] In this example, 0.3 cannot transmit DQ data correctly, that is, the training fails, which indicates that the right boundary of the window is between [0.1:0.2]. Since there is no center value in this scanning interval, 0.1, which is closer to the center of the window, is scanned first. If 0.1 can transmit DQ data correctly, then 0.2 is scanned. In this example, 0.2 cannot transmit DQ data correctly, so the right boundary is 0.1. The principle of the second scanning training right interval is shown in Table 5, and the gray part in Table 5 is the part where the valid window is located.

[0114] Table 5

[0115]

[0116] In the above example, the first transmission delay range is (-0.3, -0.2, -0.1), the second transmission delay range is 0.1, the middle value of the initial transmission delay range is 0, and the target transmission delay range is (-0.3:0.1), which is the gray part in Tables 1 to 5.

[0117] It can be seen intuitively from the above examples that using the binary search method to determine the target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range can significantly improve efficiency compared to traversing each value in the initial transmission delay range to determine the target transmission delay range for actually correctly transmitting DQ data.

[0118] The embodiment of the present application also provides a memory controller, which can receive a training instruction sent by a processor (or processor core) and respond to the training instruction to perform memory training. The memory controller includes a delay adjustment module and a control module, and memory training is completed through the delay adjustment module and the control module.

[0119] The delay adjustment module is used to adjust the transmission delay of the DQS timing signal or the DQ data signal, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip. The delay adjustment module can adjust the transmission delay of the DQS timing signal or the DQ data signal under the control of the control module, and by adjusting the transmission delay of the DQS timing signal or the DQ data signal, the phase of the DQS timing signal or the DQ data signal can be adjusted.

[0120] In one possible implementation, the delay adjustment module may include a register group and a phase adjuster. The phase adjuster may adjust the transmission delay of the DQS timing signal or the DQ data signal according to the value in the register group. The register group may serve as a control interface for the control module to control the delay circuit, so that the control module may control the delay adjustment module based on the value in the register group configured based on the initial transmission delay range.

[0121] The control module can be a logic circuit with certain logical operation capabilities or a software module, which can control the delay adjustment module to adjust the transmission delay of the DQS timing signal or the DQ data signal, so that the memory controller can execute the memory training method shown in the embodiment of the present application.

[0122] A control module is used to obtain an initial transmission delay range; wherein the initial transmission delay range is a theoretical transmission delay range for correctly transmitting DQ data; and control the delay adjustment module to adjust the transmission delay of the DQS timing signal or the DQ data signal based on the initial transmission delay range, and determine a target transmission delay range for actually correctly transmitting the DQ data from the initial transmission delay range, wherein the target transmission delay range is less than or equal to the initial transmission delay range, and the target transmission delay range is a relative timing margin between the DQ data signal and the DQS timing signal.

[0123] In a possible implementation manner, the control module is specifically configured to: determine a target transmission delay range for actually correctly transmitting the DQ data from the initial transmission delay range by using a binary search method.

[0124] In one possible implementation, the control module is specifically used to: divide the initial transmission delay range from the middle position into two, into a first interval and a second interval; determine whether the first interval includes the first transmission delay range for correctly transmitting DQ data; if the first interval does not include the first transmission delay range for correctly transmitting DQ data, determine the target transmission delay range for correctly transmitting DQ data from the second interval.

[0125] In one possible implementation, if the first interval includes a first transmission delay range for correctly transmitting DQ data, the control module is further specifically used to: determine whether the middle value of the initial transmission delay range can correctly transmit the DQ data; if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, determine the first transmission delay range as the target transmission delay range; if the middle value of the initial transmission delay range can correctly transmit the DQ data, determine a second transmission delay range for correctly transmitting the DQ data from the second interval; determine the target transmission delay range based on the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0126] In one possible implementation manner, the control module is specifically used to: divide the initial transmission delay range from the middle position into two, namely, a first interval and a second interval, and determine whether the middle value of the initial transmission delay range can correctly transmit the DQ data; if the middle value of the initial transmission delay range can correctly transmit the DQ data, determine the first transmission delay range and the second transmission delay range for correctly transmitting the DQ data from the first interval and the second interval respectively; determine the target transmission delay range according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

[0127] In one possible implementation, if the middle value of the initial transmission delay range cannot correctly transmit the DQ data, the control module is specifically used to: if the first interval includes the first transmission delay range for correctly transmitting the DQ data, determine the first transmission delay range as the target transmission delay range; if the first interval does not include the first transmission delay range for correctly transmitting the DQ data, determine the target transmission delay range for correctly transmitting the DQ data from the second interval.

[0128] The implementation principle and technical effects provided by the memory controller embodiment are the same as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the memory controller embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0129] The embodiment of the present application also provides a processor, which includes: a processor core and the above-mentioned memory controller. In this embodiment, the memory controller is integrated into the processor. In some implementations, the processor and the memory controller can be parallel devices rather than inclusion relationships.

[0130] The processor core is used to send training instructions to the memory controller; the memory controller is used to respond to the training instructions to perform memory training, thereby executing the above-mentioned memory training method.

[0131] Based on the same inventive concept, an embodiment of the present application also provides an electronic device, which includes a memory chip and a processor. The memory chip is connected to a memory controller in the processor. At this time, the processor core in the processor is used to send training instructions to the memory controller; the memory controller is used to respond to the training instructions to perform memory training, thereby executing the above-mentioned memory training method.

[0132] In one implementation, when the memory controller is no longer integrated in the processor, the electronic device includes: a processor, a memory chip and the above-mentioned memory controller, and the memory controller is connected to the processor and the memory chip respectively; the processor is used to send training instructions to the memory controller; the memory controller is used to respond to the training instructions to perform memory training, thereby executing the above-mentioned memory training method.

[0133] In one implementation, Figure 6 As shown, the electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230 and a processor 240. The processor includes the above-mentioned memory controller.

[0134] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, wherein the computer program includes at least one software function module that can be stored in the memory 220 in the form of software or firmware (Firmware) or solidified in the operating system (Operating System, OS) of the electronic device 200. The processor 240 is used to execute the software function module or computer program stored in the memory 220. For example, the processor 240 is used to execute the above-mentioned memory training method.

[0135] Among them, the memory 220 can be, but is not limited to, a random access memory (Random Access Memory, RAM), a programmable read-only memory (Programmable Read-Only Memory, PROM), an erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable read-only memory (ElectricErasable Programmable Read-Only Memory, EEPROM), etc.

[0136] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processor (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0137] Among them, the above-mentioned electronic device 200 includes but is not limited to smart phones, tablet computers, servers, base stations, smart cameras, autonomous driving vehicles, etc.

[0138] An embodiment of the present application also provides a non-volatile computer-readable storage medium (hereinafter referred to as storage medium), on which a computer program is stored. When the computer program is run by a computer such as the above-mentioned electronic device 200, the memory training method shown above is executed.

[0139] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0140] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0141] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0142] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a computer-readable storage medium, including several instructions for a computer device (which can be a personal computer, a laptop, a server, or an electronic device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0143] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory training method, characterized in that: Applied to a memory controller, the method comprises: Acquire an initial transmission delay range; wherein the initial transmission delay range is a transmission delay range for theoretically correctly transmitting DQ data; The transmission delay of the DQS timing signal or the DQ data signal is adjusted based on the initial transmission delay range, and a target transmission delay range for actually correctly transmitting the DQ data is determined from the initial transmission delay range, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip; and the target transmission delay range is less than or equal to the initial transmission delay range.

2. The method according to claim 1, characterized in that Determining a target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range includes: A target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range using a binary search method.

3. The method according to claim 2, characterized in that Determining a target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range using a binary search method includes: Divide the initial transmission delay range into two from the middle position, namely, a first interval and a second interval, wherein the first interval and the second interval do not include the middle value of the initial transmission delay range; Determining whether the first interval includes a first transmission delay range for correctly transmitting DQ data; If the first interval does not include a first transmission delay range for correctly transmitting the DQ data, a target transmission delay range for correctly transmitting the DQ data is determined from the second interval.

4. The method according to claim 3, characterized in that If the first interval includes a first transmission delay range for correctly transmitting DQ data, the method further includes: Determining whether the middle value of the initial transmission delay range can correctly transmit DQ data; If the middle value of the initial transmission delay range cannot correctly transmit the DQ data, the first transmission delay range is determined to be the target transmission delay range.

5. The method according to claim 4, characterized in that If the middle value of the initial transmission delay range can correctly transmit the DQ data, the method further includes: Determine a second transmission delay range for correctly transmitting DQ data from the second interval; The target transmission delay range is determined according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

6. The method according to claim 2, characterized in that Determining a target transmission delay range for actually correctly transmitting DQ data from the initial transmission delay range using a binary search method includes: Divide the initial transmission delay range into two from the middle position, namely, a first interval and a second interval, wherein the first interval and the second interval do not include the middle value of the initial transmission delay range; Determining whether the middle value of the initial transmission delay range can correctly transmit DQ data; If the middle value of the initial transmission delay range can correctly transmit the DQ data, determining a first transmission delay range and a second transmission delay range for correctly transmitting the DQ data from the first interval and the second interval respectively; The target transmission delay range is determined according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

7. The method according to claim 6, characterized in that If the middle value of the initial transmission delay range cannot correctly transmit the DQ data, the method further includes: If the first interval includes a first transmission delay range for correctly transmitting DQ data, determining the first transmission delay range as the target transmission delay range; If the first interval does not include a first transmission delay range for correctly transmitting the DQ data, a target transmission delay range for correctly transmitting the DQ data is determined from the second interval.

8. The method according to claim 6, characterized in that Determining a first transmission delay range and a second transmission delay range for correctly transmitting DQ data from the first interval and the second interval respectively includes: A first transmission delay range and a second transmission delay range for correctly transmitting DQ data are determined from the first interval and the second interval respectively by using a binary search method.

9. A memory controller, characterized in that: include: A delay adjustment module, used to adjust the transmission delay of a DQS timing signal or a DQ data signal, wherein the DQS timing signal and the DQ data signal are interaction signals between the memory controller and the memory chip; A control module is used to obtain an initial transmission delay range; wherein the initial transmission delay range is a theoretical transmission delay range for correctly transmitting DQ data; and control the delay adjustment module to adjust the transmission delay of the DQS timing signal or the DQ data signal based on the initial transmission delay range, and determine a target transmission delay range for actually correctly transmitting the DQ data from the initial transmission delay range, wherein the target transmission delay range is less than or equal to the initial transmission delay range.

10. The memory controller according to claim 9, characterized in that: The control module is specifically used for: A target transmission delay range for actually correctly transmitting DQ data is determined from the initial transmission delay range using a binary search method.

11. The memory controller according to claim 10, characterized in that: The control module is specifically used for: The initial transmission delay range is divided into two from the middle position, namely, a first interval and a second interval, wherein neither the first interval nor the second interval contains the middle value of the initial transmission delay range; whether the first interval includes the first transmission delay range for correctly transmitting DQ data; if the first interval does not include the first transmission delay range for correctly transmitting DQ data, determine the target transmission delay range for correctly transmitting DQ data from the second interval.

12. The memory controller according to claim 11, characterized in that: If the first interval includes a first transmission delay range for correctly transmitting DQ data, the control module is specifically configured to: Determining whether the middle value of the initial transmission delay range can correctly transmit DQ data; If the middle value of the initial transmission delay range cannot correctly transmit the DQ data, determining the first transmission delay range as the target transmission delay range; If the middle value of the initial transmission delay range can correctly transmit DQ data, determine the second transmission delay range for correctly transmitting DQ data from the second interval; determine the target transmission delay range based on the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

13. The memory controller according to claim 10, characterized in that: The control module is specifically used for: Divide the initial transmission delay range into two from the middle position, namely, a first interval and a second interval, wherein the first interval and the second interval do not include the middle value of the initial transmission delay range; Determining whether the middle value of the initial transmission delay range can correctly transmit DQ data; If the middle value of the initial transmission delay range can correctly transmit the DQ data, determining a first transmission delay range and a second transmission delay range for correctly transmitting the DQ data from the first interval and the second interval respectively; The target transmission delay range is determined according to the first transmission delay range, the middle value of the initial transmission delay range, and the second transmission delay range.

14. The memory controller according to claim 13, characterized in that: If the middle value of the initial transmission delay range cannot correctly transmit the DQ data, the control module is specifically used to: If the first interval includes a first transmission delay range for correctly transmitting DQ data, determining the first transmission delay range as the target transmission delay range; If the first interval does not include a first transmission delay range for correctly transmitting the DQ data, a target transmission delay range for correctly transmitting the DQ data is determined from the second interval.

15. A processor, characterized in that: include: A processor core and a memory controller as claimed in any one of claims 9 to 14; The processor core is used to send a training instruction to the memory controller; The memory controller is used to execute memory training in response to the training instruction.

16. An electronic device, characterized in that: include: A memory chip and a processor as claimed in claim 15, wherein the memory chip is connected to a memory controller in the processor.

17. An electronic device, characterized in that: include: A processor, a memory chip, and a memory controller as described in any one of claims 9 to 14, wherein the memory controller is connected to the processor and the memory chip respectively; The processor is used to send a training instruction to the memory controller; The memory controller is used to execute memory training in response to the training instruction.

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