Refresh control circuit and memory
By introducing a refresh control circuit in the memory, the shielding mechanism of the self-refresh control signal generation module and the self-refresh signal generation module is solved, and the performance problems caused by the failure to complete the refresh under short-term commands are ensured that the refresh operation is performed under normal operating voltage. , improves memory performance.
Patent Information
- Application Number
- CN202310776149.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-27
- Publication Date
- 2025-01-03
AI Technical Summary
In storage systems, when the memory receives a short-term command to enter and exit the self-refresh mode, it may cause the self-refresh process to end but not complete a refresh process, resulting in a delayed phase-locked loop (DLL) locking in the refresh process in a relatively small refresh process. Low operating voltage affects memory performance.
Provide a refresh control circuit, including a self-refresh control signal generation module and a self-refresh signal generation module, through the masking signal, the self-refresh control signal is blocked and outputted after the preset time is completed, ensuring that the memory does not immediately perform the refresh operation after entering the self-refresh mode. , until the self-refresh control signal masking time is over, then output to avoid the DLL being locked in the refresh process.
It effectively avoids memory performance problems caused by short-term commands, ensures that the memory performs refresh operations under normal operating voltage, and improves the performance and stability of the memory.
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Figure CN119252299A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a refresh control circuit and a memory. Background Art
[0002] At present, the refresh mode of the memory can be divided into automatic refresh mode and self-refresh mode. In the automatic refresh mode, the refresh command is periodically issued by the controller, and the memory is responsible for executing the refresh command; in the self-refresh mode, the controller is responsible for sending commands to enter and exit the self-refresh mode. During the self-refresh mode process, the refresh command is periodically generated by the memory itself.
[0003] Among them, after receiving the command to enter the self-refresh mode, the memory usually first operates to execute the command as a refresh command in the automatic refresh mode, and then periodically generates refresh commands after the execution is completed. However, it takes a certain amount of time for the memory to execute a refresh command, and each execution of the refresh command is accompanied by the re-locking of the delay locked loop (DLL). In the actual operation of the storage system, the memory may receive short-term commands to enter and exit the self-refresh mode, which will result in the memory not completing an initial refresh when the process of the self-refresh mode has ended. In this case, the DLL will be locked at a lower operating voltage during the refresh process, but the next read and write of the memory will be at a normal operating voltage, which will inevitably cause a series of problems and affect the performance of the memory. Summary of the invention
[0004] The present disclosure provides a refresh control circuit and a memory, which can effectively improve the performance of the memory.
[0005] In a first aspect, an embodiment of the present disclosure provides a refresh control circuit, which is applied to a memory, and the refresh control circuit includes: a self-refresh control signal generation module and a self-refresh signal generation module, wherein:
[0006] The self-refresh control signal generation module includes at least one input terminal and a first output terminal, wherein the at least one input terminal is used to receive a self-refresh mode signal; the self-refresh control signal generation module is configured to: when the self-refresh mode signal received by the at least one input terminal indicates that the memory enters the self-refresh mode, output a self-refresh control signal of a first level at the first output terminal; when the self-refresh mode signal received by the at least one input terminal indicates that the memory exits the self-refresh mode, output a self-refresh control signal of a second level at the first output terminal;
[0007] The self-refresh signal generating module includes a first input terminal and a second output terminal, the first input terminal is connected to the first output terminal and is used to receive the self-refresh control signal, and the second output terminal is used to output a self-refresh signal, and the self-refresh signal is used to indicate that the memory enters a self-refresh operation; the self-refresh signal generating module is configured to: generate a shielding signal based on the self-refresh control signal, and output the self-refresh control signal after shielding it for a preset period of time based on the shielding signal.
[0008] In some embodiments, the preset time length is the time interval between two refresh commands successively received by the memory.
[0009] In some embodiments, the shielding signal is a clock signal whose starting level is the second level.
[0010] In some embodiments, the self-refresh signal generation module includes a shielding signal generation unit and a shielding unit;
[0011] The shielding signal generating unit is connected to the first output terminal and is used to receive the self-refresh control signal output by the first output terminal; the shielding signal generating unit is configured to: generate the shielding signal based on the received self-refresh control signal;
[0012] The shielding unit is connected to the first output terminal and the shielding signal generating unit respectively, and is used to receive the self-refresh control signal and the shielding signal; the shielding unit is configured to: shield the self-refresh control signal for a preset time period based on the shielding signal and then output it.
[0013] In some embodiments, the shielding signal generating unit includes an oscillator, a frequency divider, and a first inverter; the shielding unit includes a first AND gate;
[0014] The output end of the oscillator is connected to the input end of the frequency divider, the output end of the frequency divider is connected to one input end of the first AND gate, the input end of the first inverter is connected to the first output end, and the output end of the first inverter is connected to the reset end of the frequency divider; the other input end of the first AND gate is connected to the first output end; and the output end of the first AND gate is the second output end.
[0015] In some embodiments, the self-refresh mode signal includes a self-refresh entry signal and a self-refresh exit signal;
[0016] The self-refresh control signal generating module is configured to: receive the self-refresh entry signal and the self-refresh exit signal, and generate the self-refresh control signal based on the transition edge of the self-refresh entry signal and the transition edge of the self-refresh exit signal, wherein the effective level of the self-refresh control signal starts at the transition edge of the self-refresh entry signal and ends at the transition edge of the self-refresh exit signal.
[0017] In some embodiments, the self-refresh control signal generation module includes a second inverter, a first NOR gate, and a first latch, wherein the first latch includes a first NAND gate and a second NAND gate; wherein:
[0018] The receiving end of the second inverter is used to receive the self-refresh entry signal, and the output end of the second inverter is connected to an input end of the first NAND gate; the other input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to an input end of the second NAND gate; the other input end of the second NAND gate is connected to the output end of the first NOR gate, one input end of the first NOR gate is used to receive the self-refresh exit signal, and the other input end of the first NOR gate is used to receive a start reset signal; the output end of the first NAND gate is the first output end.
[0019] In some embodiments, the self-refresh entry signal is a self-refresh mode entry command signal; and the self-refresh exit signal is a self-refresh mode exit command signal.
[0020] In some embodiments, the self-refresh mode signal includes a first mode signal and a second mode signal;
[0021] The self-refresh control signal generating module is configured to receive the first mode signal and the second mode signal, and when the first mode signal is at an effective level, generate a signal which is inverted from the second mode signal as the self-refresh control signal.
[0022] In some embodiments, the self-refresh control signal generation module includes a third inverter, a second NOR gate, a third NAND gate, and a second latch, and the second latch includes a fourth NAND gate and a fifth NAND gate; wherein:
[0023] The receiving end of the third inverter is used to receive the second mode signal, the output end of the third inverter is connected to an input end of the third NAND gate, the other input end of the third NAND gate is used to receive the first mode signal, and the output end of the third NAND gate is connected to an input end of the fourth NAND gate; the other input end of the fourth NAND gate is connected to the output end of the fifth NAND gate, and the output end of the fourth NAND gate is connected to an input end of the fifth NAND gate; the other input end of the fifth NAND gate is connected to the output end of the second NOR gate, one input end of the second NOR gate is used to receive the second mode signal, and the other input end of the second NOR gate is used to receive a start reset signal; the output end of the fourth NAND gate is the first output end.
[0024] In some embodiments, the refresh control circuit also includes a refresh operation module, and the refresh operation module includes a first OR gate; one input end of the first OR gate is used to receive an automatic refresh signal, and the other input end of the first OR gate is connected to the second output end for receiving the self-refresh signal, and the output end of the first OR gate is used to output a refresh signal; the refresh signal is used to instruct the memory to perform a refresh operation.
[0025] In some embodiments, the automatic refresh signal is an automatic refresh command signal sent by a controller corresponding to the memory.
[0026] In some embodiments, the self-refresh mode signal includes a first mode signal and a second mode signal;
[0027] The refresh control circuit also includes a second AND gate; one input end of the second AND gate is used to receive the first mode signal, another input end of the second AND gate is used to receive the second mode signal, and the output end of the second AND gate is used to output the automatic refresh signal.
[0028] In some embodiments, the first mode signal is a refresh command signal sent by a controller corresponding to the memory, and the second mode signal is a clock enable signal input externally.
[0029] In a second aspect, an embodiment of the present disclosure provides a memory, comprising a refresh control circuit as provided in the first aspect.
[0030] In the refresh control circuit provided by the embodiment of the present disclosure, the self-refresh control signal generating module receives the self-refresh mode signal and converts the self-refresh mode signal into the self-refresh control signal, and uses the level state of the self-refresh control signal to instruct the memory to enter the self-refresh mode or to exit the self-refresh mode; the self-refresh signal generating module shields the self-refresh control signal for a preset time period through a shielding signal and then outputs it, so that the memory will not perform a refresh operation after initially receiving the command to enter the self-refresh mode, but will output it after shielding the self-refresh control signal for a preset time period. Under the premise of ensuring that the memory can perform normal refresh operations, it can avoid the situation where the self-refresh process has ended but the memory has not yet completed a refresh process when the memory receives a short-term command to enter / exit the self-refresh mode, thereby causing the DLL to be locked at a lower operating voltage during the refresh process, but the next read and write of the memory is at a normal operating voltage, thereby causing a series of problems such as timing matching, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 A schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure Figure 1 ;
[0032] Figure 2 A schematic diagram of the structure of a self-refresh signal generating module 200 provided in an embodiment of the present disclosure Figure 1 ;
[0033] Figure 3 A schematic diagram of the structure of a self-refresh signal generating module 200 provided in an embodiment of the present disclosure Figure 2 ;
[0034] Figure 4 A schematic diagram of the structure of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure Figure 1 ;
[0035] Figure 5 A schematic diagram of the structure of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure Figure 2 ;
[0036] Figure 6 A schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure Figure 2 ;
[0037] Figure 7 A schematic diagram of the structure of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure Figure 3 ;
[0038] Figure 8A schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION
[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. In addition, although the disclosure in the present disclosure is introduced according to one or several exemplary examples, it should be understood that each aspect of the disclosure can also constitute a complete implementation method separately.
[0040] It should be noted that the brief description of terms in the present disclosure is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.
[0041] The terms "first", "second", "third", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar or similar objects or entities, and are not necessarily meant to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, for example, they can be implemented in an order other than those given in the diagrams or descriptions of the embodiments of the present disclosure.
[0042] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.
[0043] It should be understood that when an element is referred to as being “connected” or “electrically connected” to other elements in an embodiment of the present disclosure, the element may be directly connected or electrically connected to the other elements; or there may be several intermediate elements, and the element may be connected or electrically connected to the other elements through the several intermediate elements.
[0044] The term "module" used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or a combination of hardware and / or software code that can perform the functions associated with the element.
[0045] The embodiments of the present disclosure relate to the field of semiconductor memory technology, and can optionally be applied to the chip design of dynamic random access memory (DRAM), including controlling the refresh mode of DRAM. It should be noted that the refresh control circuit provided in the embodiments of the present disclosure can be applied to DRAM as well as other memories with refresh operations, such as NAND Flash or NOR Flash, which is not limited in the embodiments of the present disclosure.
[0046] It can be understood that a memory generally includes a plurality of bit lines (BL), a plurality of word lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding WL and a corresponding BL.
[0047] In some embodiments, each storage unit includes a transistor and a capacitor, the gate of the transistor is connected to WL, one of the source / drain of the transistor is connected to BL, and the other is connected to the capacitor. When the signal on WL turns on the above transistor, BL can write a high-level signal "1" to the above capacitor. When the signal on WL turns off the above transistor, the charge on the above capacitor slowly leaks over time. The time between the leakage of the above capacitor from the high-level signal "1" to the low-level signal "0" is the data retention time of the above capacitor.
[0048] In order to prevent the data stored in the capacitor from being lost, the memory needs to refresh all the data stored in it within a limited time. During the refresh process, the memory first reads the original data, compares the level of the capacitor with the reference level, determines the 1 / 0 value of the data, and then writes the original data back. During the writing process, the capacitor is fully charged (if the data is 1), which is like a charging operation.
[0049] In some embodiments, the refresh mode of the memory can be divided into automatic refresh mode and self-refresh mode. In the automatic refresh mode, the refresh command is periodically issued by the controller, and the memory is responsible for executing the refresh command; in the self-refresh mode, the controller is only responsible for sending commands to enter and exit the self-refresh mode. During the self-refresh mode process, the refresh command is periodically generated by the memory itself.
[0050] Among them, after receiving the command to enter the self-refresh mode, the memory usually first operates to execute the command as a refresh command in the automatic refresh mode, and then generates refresh commands periodically after the execution is completed. However, in the actual operation of the storage system, there will be a large number of short-term commands to enter and exit the self-refresh mode. In this case, it is easy to affect the performance of the memory. For example, after receiving the command to enter the self-refresh mode, the memory will first use the command as a refresh command in the automatic refresh mode to refresh the memory. It takes a certain amount of time for the memory to execute a refresh command, during which time the DLL is re-locked; however, in actual operation, the memory may repeatedly receive commands to enter and exit the self-refresh mode in a short period of time, which will result in the situation that when the self-refresh process has ended, the memory has not yet completed an automatic refresh process. In this case, the DLL will be locked at a lower operating voltage during the refresh process, but the next read and write of the memory will be at a normal operating voltage, which will inevitably cause a series of problems and affect the performance of the memory.
[0051] In view of the above technical problems, the embodiment of the present disclosure provides a refresh control circuit, including a self-refresh control signal generation module and a self-refresh signal generation module, wherein the self-refresh control signal generation module receives a self-refresh mode signal and converts the self-refresh mode signal into a self-refresh control signal, and uses the level state of the self-refresh control signal to indicate that the memory enters the self-refresh mode or indicates that the memory exits the self-refresh mode; the self-refresh signal generation module outputs the self-refresh control signal after shielding the self-refresh control signal for a preset time through a shielding signal, so that the memory does not perform a refresh operation after receiving the command to enter the self-refresh mode at the beginning, but outputs the self-refresh control signal after shielding the self-refresh control signal for a preset time, and can avoid the situation that the memory has not completed a refresh process when receiving a short-term command to enter / exit the self-refresh mode, thereby causing the DLL to be locked at a lower operating voltage during the refresh process, but the next read and write of the memory is at a normal operating voltage, thereby causing a series of problems such as timing matching, thereby improving the performance of the memory. The detailed technical solution can refer to the following embodiments.
[0052] Reference Figure 1 , Figure 1 A schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure Figure 1 .
[0053] In some embodiments of the present disclosure, the refresh control circuit includes a self-refresh control signal generating module 100 and a self-refresh signal generating module 200 .
[0054] In some embodiments, the self-refresh control signal generating module 100 includes at least one input terminal and a first output terminal, and the at least one input terminal is used to receive the self-refresh mode signal S1.
[0055] In some implementations, the self-refresh mode signal S1 may be a signal sent by a controller corresponding to the memory, received by the memory, and generated after being decoded by a decoder in the memory.
[0056] The self-refresh mode signal S1 may be used to instruct the memory to enter the self-refresh mode or to instruct the memory to exit the self-refresh mode.
[0057] In some embodiments, the self-refresh control signal generating module 100 is configured as follows: when the self-refresh mode signal S1 received by the at least one input terminal indicates that the memory enters the self-refresh mode, a first-level self-refresh control signal S2 is output at the first output terminal; when the self-refresh mode signal S1 received by the at least one input terminal indicates that the memory exits the self-refresh mode, a second-level self-refresh control signal S2 is output at the first output terminal.
[0058] Optionally, the first level may be a high level, and the second level may be a low level. However, the present invention is not limited thereto, and the first level may be a low level, and the second level may be a high level.
[0059] In some embodiments, the self-refresh mode signal S1 may include multiple signals.
[0060] Exemplarily, for the storage medium of large-capacity memory, synchronous dynamic random access memory (SDRAM) is usually used, such as double data rate synchronous dynamic random access memory (DDR SDRAM, DDR for short). Among them, the fifth generation DDR (hereinafter referred to as DDR5) will have a separate self-refresh mode entry command signal (hereinafter referred to as SRE CMD signal) and self-refresh mode exit command signal (hereinafter referred to as SRX CMD signal), the SRE CMD signal is used to control the memory to enter the self-refresh mode, and the SRX CMD signal is used to control the memory to exit the self-refresh mode. The fourth generation DDR (hereinafter referred to as DDR4) uses the refresh command signal (hereinafter referred to as REF CMD signal) and the clock enable signal (hereinafter referred to as CKE signal) to work together to control the memory to enter the self-refresh mode or control the memory to exit the self-refresh mode.
[0061] In some embodiments, when the memory is DDR5, the self-refresh mode signal S1 includes a SRE CMD signal and a SRX CMD signal; when the memory is DDR4, the self-refresh mode signal S1 includes a REF CMD signal and a CKE signal.
[0062] It can be understood that in the embodiment of the present disclosure, the self-refresh control signal generation module 100 can be used to convert the multiple signals contained in the self-refresh mode signal S1 into a self-refresh control signal S2, and the level state of the self-refresh control signal S2 is used to indicate that the memory enters the self-refresh mode or indicates that the memory exits the self-refresh mode.
[0063] Exemplarily, when the self-refresh control signal S2 is at a high level, the self-refresh control signal S2 instructs the memory to enter the self-refresh mode; when the self-refresh control signal S2 is at a low level, the self-refresh control signal S2 instructs the memory to exit the self-refresh mode.
[0064] In some embodiments, the self-refresh signal generating module 200 includes a first input terminal and a second output terminal. The first input terminal is connected to the first output terminal of the self-refresh control signal generating module 100 for receiving the self-refresh control signal S2, and the second output terminal is used to output a self-refresh signal S3, which is used to indicate that the memory enters a self-refresh operation.
[0065] In some embodiments, the self-refresh signal generating module 200 is configured to generate a shielding signal based on the self-refresh control signal S2, and output the self-refresh control signal S2 after shielding it for a preset time period based on the shielding signal.
[0066] In some embodiments, when the self-refresh control signal S2 received by the self-refresh signal generating module 200 flips from a low level to a high level, the self-refresh signal generating module 200 generates a shielding signal, and based on the shielding signal, shields the self-refresh control signal S2 for a preset time and then outputs it.
[0067] It is understandable that after the memory receives the command signal to enter the self-refresh mode, the conventional operation will first use the command signal as an automatic refresh command to perform the automatic refresh operation, and then start the internal self-refresh command generation circuit after the execution is completed, and regularly generate the self-refresh command. However, in the case of a large number of short-term commands to enter / exit the self-refresh mode, the memory will be caused to repeatedly perform the automatic refresh operation, resulting in a series of problems affecting the performance of the memory. In the disclosed embodiment, by generating a self-refresh control signal S2, the self-refresh control signal S2 can be used to accurately characterize the state of the self-refresh mode process (specifically, it can be shown that when the self-refresh control signal S2 is high, the memory is in the self-refresh mode process, and when the self-refresh control signal S2 is low, the memory is not in the self-refresh mode process). The self-refresh signal generation module 200 generates a shielding signal based on the self-refresh control signal S2, and outputs the self-refresh control signal S2 after shielding the preset duration based on the shielding signal. Through the shielding signal, the initial refresh operation after the memory enters the self-refresh mode can be shielded, thereby improving the impact of the short-term command to enter / exit the self-refresh mode.
[0068] Furthermore, the preset time length can be set according to actual application requirements. For example, the preset time length can be set to the running time of the first automatic refresh operation after entering the self-refresh operation. This can solve a series of problems such as the DLL repeatedly locking under low voltage due to short-term commands to enter / exit the self-refresh mode.
[0069] In some embodiments, the preset time length is the time interval between two refresh commands received consecutively by the memory, that is, tREFI. The refresh command includes an automatic refresh command and a self-refresh command.
[0070] In some implementations, the preset time duration may also be greater than tREFI.
[0071] In some embodiments, when the self-refresh control signal S2 output after shielding for a preset period of time is at a high level, the self-refresh signal generation module 200 can periodically output a self-refresh signal S3 at the second output terminal, and the memory performs a self-refresh operation based on the self-refresh signal S3.
[0072] Optionally, the self-refresh signal S3 may be effective at a high level, that is, when the self-refresh signal S3 is at a high level, the memory performs a self-refresh operation.
[0073] It can be understood that after the above-mentioned self-refresh control signal S2 is flipped from a low level to a high level, the self-refresh control signal S2 is shielded by a shielding signal, thereby preventing the memory from performing a refresh operation after it first receives a command to enter the self-refresh mode, and outputting the self-refresh control signal S2 after shielding it for a preset period of time. This can ensure that the memory can perform normal refresh operations while avoiding the situation where the self-refresh process has ended but the memory has not completed a refresh process when the memory receives a large number of short-term commands to enter / exit the self-refresh mode. This can prevent the DLL from being repeatedly locked at a lower operating voltage, but the memory is read and written at a normal operating voltage, thereby improving the performance of the memory.
[0074] Reference Figure 2 , Figure 2 A schematic diagram of the structure of a self-refresh signal generating module 200 provided in an embodiment of the present disclosure Figure 1 In some embodiments of the present disclosure, the self-refresh signal generation module 200 includes a shielding signal generation unit 201 and a shielding unit 202. The shielding signal generation unit 201 is connected to the first output terminal of the self-refresh control signal generation module, and is used to receive the self-refresh control signal S2 outputted by the first output terminal.
[0075] In some embodiments, the shielding signal generating unit 201 is configured to generate a shielding signal S4 based on the received self-refresh control signal S2 .
[0076] The shielding signal S4 is a clock signal whose starting level is the second level.
[0077] In some embodiments, the starting level of the shielding signal S4 may also be a clock signal that is inverted with respect to the level of the self-refresh control signal when the memory enters the self-refresh mode. For example, when the self-refresh control signal indicates that the memory enters the self-refresh mode at a high level, the starting level of the shielding signal S4 is a low level; when the self-refresh control signal indicates that the memory enters the self-refresh mode at a low level, the starting level of the shielding signal S4 is a high level.
[0078] In some implementations, the shielding unit 202 is connected to the first output terminal and the shielding signal generating unit 201 , respectively, and is configured to receive the self-refresh control signal S2 and the shielding signal S4 .
[0079] In some embodiments, the shielding unit 202 is configured to: shield the self-refresh control signal S2 for a preset time period based on the shielding signal S4 and then output it.
[0080] In the disclosed embodiment, since the starting level of the shielding signal S4 is a clock signal that is inverted with respect to the level of the self-refresh control signal when instructing the memory to enter the self-refresh mode, when the self-refresh control signal first instructs the memory to enter the self-refresh mode, the shielding signal S4 can be used to shield the self-refresh control signal, so that the memory will not perform a refresh operation after it first receives the command to enter the self-refresh mode, thereby avoiding the situation where the self-refresh process has ended but the memory has not yet completed a refresh process when the memory receives a short-term command to enter / exit the self-refresh mode.
[0081] Reference Figure 3 , Figure 3 A schematic diagram of the structure of a self-refresh signal generating module 200 provided in an embodiment of the present disclosure Figure 2 .
[0082] In some implementations, the shielding signal generating unit 201 includes an oscillator 2011 , a frequency divider 2012 , and a first inverter NOT1 ; and the shielding unit 202 includes a first AND gate AND1 .
[0083] Among them, the oscillator 2011 is used to output a clock signal CLK with a specific frequency, and the output end of the oscillator 2011 is connected to the input end of the divider 2012; the divider 2012 is used to divide the input clock signal CLK and output a divided clock signal CLK-DIV with a preset frequency, and the output end of the divider 2012 is connected to an input end of the first AND gate AND1; the input end of the first inverter NOT1 is connected to the first output end of the above-mentioned self-refresh control signal generating module, and is used to receive the self-refresh control signal S2 output by the above-mentioned first output end; the output end of the first inverter NOT1 is connected to the reset end R of the divider 2012; the other input end of the first AND gate AND1 is also connected to the above-mentioned first output end, and is used to receive the self-refresh control signal S2 output by the above-mentioned first output end. The output end of the first AND gate AND1 is the second output end of the self-refresh signal generating module 200, and is used to output the self-refresh signal S3.
[0084] The oscillator 2011 can generate a sine wave or other repetitive waveform with a desired amplitude and frequency at the output without an external excitation signal. In the disclosed embodiment, the oscillator 2011 can be used to generate a clock signal CLK with a specific frequency oscillating between a high level and a low level.
[0085] The frequency divider 2012 is an electronic circuit that makes the frequency of the output signal an integer fraction of the frequency of the input signal. In the embodiment of the present disclosure, the input signal of the frequency divider 2012 is the clock signal CLK, and the output signal is the divided clock signal CLK-DIV. In some embodiments, when the reset terminal R of the frequency divider 2012 receives a reset signal, the frequency of the clock signal CLK is divided and the divided clock signal CLK-DIV is output.
[0086] Optionally, the frequency divider 2012 may divide the frequency of the clock signal CLK by two, four, or eight, which is not limited in the embodiments of the present disclosure.
[0087] Among them, the AND gate is also called "AND circuit", logical "product" or logical "AND" circuit, and is a basic logic gate circuit that performs "AND" operation. In the embodiment of the present disclosure, the first AND gate AND1 has two input terminals and one output terminal. When the inputs of the two input terminals of the first AND gate AND1 are both high level (logical 1), its output terminal outputs a high level, otherwise its output terminal outputs a low level (logical 0).
[0088] In some embodiments, the self-refresh signal S3 is effective at a high level, that is, the memory performs a refresh operation only when the self-refresh signal S3 is at a high level, and does not perform a refresh operation when the self-refresh signal S3 is at a low level.
[0089] In some implementations, the divided clock signal CLK-DIV may be used as the shielding signal S4, wherein the divided clock signal CLK-DIV is a clock signal with a low initial level.
[0090] In some embodiments, by setting the frequency of the divided clock signal CLK-DIV, the duration for which the starting level of the divided clock signal CLK-DIV remains at a low level can reach the above-mentioned preset duration. For example, by setting the frequency of the divided clock signal CLK-DIV, half a cycle of the divided clock signal CLK-DIV can be greater than or equal to the above-mentioned preset duration.
[0091] In some implementations, the frequency of the divided clock signal CLK-DIV matches the refresh frequency of the memory.
[0092] Exemplarily, assuming that the time interval tREFI between two refresh commands received continuously by the memory is a (ns), the frequency of the divided clock signal CLK-DIV can match the refresh frequency, and the divided clock signal CLK-DIV has a low level of a (ns) at the beginning. For the short-term command to enter the self-refresh mode (high level), due to the existence of the first AND gate AND1, the output self-refresh signal S3 can be made low. That is, in the time period when the divided clock signal CLK-DIV is still at a low level, no matter whether the self-refresh control signal S2 is at a low level or a high level, the self-refresh signal S3 is at a low level, that is, the short high level of the self-refresh control signal S2 can be intercepted by the low level of the divided clock signal CLK-DIV.
[0093] In some implementations, the first inverter NOT1 may also be a NOT gate circuit, which can change the output level to a level opposite to the input level.
[0094] It can be understood that when the self-refresh mode signal S1 instructs the memory to enter the self-refresh mode, the self-refresh control signal S2 will flip from a low level to a high level. After the self-refresh control signal S2 flips from a low level to a high level, the self-refresh control signal S2 is inverted by the first inverter NOT1, and a low level signal is applied to the reset terminal R of the divider 2012 as the reset signal of the divider 2012, and the divider 2012 starts to work (previously, when the self-refresh control signal S2 is at a low level, the reset terminal R of the divider 2012 is at a high level, and the divider 2012 is disabled), and outputs the divided clock signal CLK-DIV.
[0095] Since the starting level of the divided clock signal CLK-DIV is a low level and the duration of the continuous low level is equal to the above-mentioned preset duration, one input terminal of the first AND gate AND1 will continue to receive a low level within the above-mentioned preset duration. Therefore, within the above-mentioned preset duration, even if the self-refresh control signal S2 received by the other receiving terminal of the first AND gate AND1 is a high level, the self-refresh signal S3 outputted by the output terminal of the first AND gate AND1 is still a low level, and the memory does not perform a refresh operation.
[0096] It can be understood that for a short-term command to enter the self-refresh mode, that is, when the time for which the self-refresh control signal S2 maintains a high level is less than the above-mentioned preset time length, due to the existence of the above-mentioned divided clock signal CLK-DIV, the self-refresh signal S3 outputted from the output end of the first AND gate AND1 will remain at a low level unchanged, that is, the first AND gate AND1 can use the above-mentioned divided clock signal CLK-DIV to shield the self-refresh control signal S2 within the above-mentioned preset time length.
[0097] In some embodiments, when the self-refresh control signal S2 maintains a high level for a time greater than the above-mentioned preset time length, the output end of the first AND gate AND1 will output a high-level self-refresh signal S3 at the end of the above-mentioned preset time length. At this time, the memory itself will periodically generate a refresh command and perform a refresh operation according to the generated refresh command.
[0098] In the refresh control circuit provided by the embodiment of the present disclosure, the self-refresh signal generation module outputs the self-refresh control signal after shielding it for a preset time through a shielding signal, so that the memory does not perform a refresh operation after receiving the command to enter the self-refresh mode at the beginning, but outputs the self-refresh control signal after shielding it for a preset time. Under the premise of ensuring that the memory can perform normal refresh operations, it can avoid the situation that the self-refresh process has ended but the memory has not completed a refresh process when the memory receives a short-term command to enter / exit the self-refresh mode, and avoids the DLL being locked at a low operating voltage during the refresh process, but the next read and write of the memory is at a normal operating voltage, which causes a series of problems such as timing matching. Thus, the performance of the memory is improved.
[0099] Based on the description in the above embodiments, in some embodiments of the present disclosure, the self-refresh mode signal S1 received by the above memory includes a self-refresh entry signal and a self-refresh exit signal. The self-refresh control signal generation module 100 is configured to: receive the above self-refresh entry signal and the self-refresh exit signal, and generate a self-refresh control signal S2 based on the transition edge of the above self-refresh entry signal and the transition edge of the self-refresh exit signal, wherein the effective level of the self-refresh control signal S2 starts from the transition edge of the above self-refresh entry signal and ends at the transition edge of the above self-refresh exit signal.
[0100] Exemplarily, taking the memory as DDR5 as an example, the self-refresh entry signal may be a SRE CMD (Self Refresh Entry Command) signal, and the self-refresh exit signal may be a SRX CMD (Self Refresh Exit Command) signal.
[0101] Reference Figure 4 , Figure 4 A schematic diagram of the structure of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure Figure 1 In some embodiments of the present disclosure, the self-refresh control signal generation module 100 includes a second inverter NOT2, a first NOR gate NOR1, and a first latch 101; wherein the first latch 101 includes a first NAND gate NAND1 and a second NAND gate NAND2.
[0102] In some embodiments, a receiving end of the second inverter NOT2 is used to receive a SRE CMD signal, and an output end of the second inverter NOT2 is connected to an input end of the first NAND gate NAND1; another input end of the first NAND gate NAND1 is connected to an output end of the second NAND gate NAND2, and the output end of the first NAND gate NAND1 is connected to an input end of the second NAND gate NAND2; another input end of the second NAND gate NAND2 is connected to an output end of the first NOR gate NOR1, one input end of the first NOR gate NOR1 is used to receive a SRX CMD signal, and another input end of the first NOR gate NOR1 is used to receive a start reset signal PWR Reset; the output end of the first NAND gate NAND1 is a first output end of the self-refresh control signal generation module 100, which is used to output a self-refresh control signal S2.
[0103] In some embodiments, the first NOR gate NOR1 may also be replaced by a NOT gate, whose input terminal is used to receive the SRX CMD signal and whose output terminal is connected to an input terminal of the second NAND gate NAND2. That is, in some embodiments, the reset signal PWR Reset may not be required.
[0104] Among them, the NOR gate can realize the logic NOR function. The NOR gate has two input terminals and one output terminal. Only when both input terminals receive a low level (logic 0), the output terminal outputs a high level (logic 1). It can also be understood that any input is a high level (logic 1) and the output is a low level (logic 0).
[0105] The NAND gate has two inputs and one output. If both inputs receive a high level (logic 1), the output outputs a low level (logic 0); if at least one of the two inputs receives a low level (logic 0), the output outputs a high level (logic 1).
[0106] In some implementations, PWR Reset remains low after the memory system is powered on.
[0107] Among them, PWR Reset is reset when the memory system is powered on to ensure the initial state of the latch in the circuit. PWR Reset will flip to a high level when necessary to restart the circuit and make the memory system exit the self-refresh mode.
[0108] In some embodiments, both the SRE CMD signal and the SRX CMD signal are valid at a high level, that is, when the SRE CMD signal is at a high level and the SRX CMD signal is at a low level, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is at a high level; when the SRE CMD signal is at a low level and the SRX CMD signal is at a high level, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is at a low level.
[0109] Reference Figure 5 , Figure 5 A schematic diagram of the structure of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure Figure 2 In some embodiments of the present disclosure, the self-refresh control signal generation module 100 includes a fourth inverter NOT4 and a third latch 103 ; wherein the third latch 103 includes a third NOR gate NOR3 and a fourth NOR gate NOR4 .
[0110] In some embodiments, one input end of the third NOR gate NOR3 is used to receive the SRE CMD signal, another input end of the third NOR gate NOR3 is connected to the output end of the fourth NOR gate NOR4, the output end of the third NOR gate NOR3 is connected to one input end of the fourth NOR gate NOR4, and another input end of the fourth NOR gate NOR4 is used to receive the SRX CMD signal; the input end of the fourth inverter NOT4 is connected to the output end of the third NOR gate NOR3, and the output end of the fourth NOR gate NOR4 is the first output end of the self-refresh control signal generation module 100, which is used to output the self-refresh control signal S2.
[0111] In some embodiments, both the SRE CMD signal and the SRX CMD signal are valid at a high level, that is, when the SRE CMD signal is at a high level and the SRX CMD signal is at a low level, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is at a high level; when the SRE CMD signal is at a low level and the SRX CMD signal is at a high level, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is at a low level.
[0112] The self-refresh control signal generation module provided in the embodiment of the present disclosure can convert the received self-refresh entry signal and self-refresh exit signal into a self-refresh control signal, and use the level state of the self-refresh control signal to instruct the memory to enter the self-refresh mode or instruct the memory to exit the self-refresh mode; thereby, it is beneficial to subsequently shield short-term commands to enter / exit the self-refresh mode, thereby improving the performance of the memory.
[0113] Reference Figure 6 , Figure 6A schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure Figure 2 In some embodiments of the present disclosure, the refresh control circuit includes a self-refresh control signal generating module 100 , a self-refresh signal generating module 200 , a refresh operation module 300 and a decoder 400 .
[0114] In some embodiments, the self-refresh control signal generation module 100 may be Figure 4 or Figure 5 The self-refresh control signal generating module 100 and the self-refresh signal generating module 200 may be Figure 2 or Figure 3 The detailed structure of the self-refresh signal generating module 200 shown can refer to the description in the above embodiment, and will not be described in detail in this embodiment.
[0115] In some embodiments, the refresh operation module 300 includes a first OR gate OR; one input end of the first OR gate OR is used to receive an automatic refresh signal, and the other input end of the first OR gate OR is connected to the second output end of the self-refresh signal generation module 200 for receiving a self-refresh signal S3, and the output end of the first OR gate OR is used to output a refresh signal S5, which is used to instruct the memory to perform a refresh operation.
[0116] In some embodiments of the present disclosure, the automatic refresh signal is an automatic refresh command AREF CMD signal sent by a controller corresponding to the memory.
[0117] The AREF CMD signal is a refresh signal periodically sent by the controller when the memory is in an automatic refresh mode.
[0118] Among them, the OR gate is also called the OR circuit, the logic and circuit. The above OR gate has two input terminals and one output terminal. As long as one of the two input terminals is at a high level (logic 1), the output terminal output is a high level (logic 1); only when the inputs of the two input terminals are all at a low level (logic 0), the output terminal output is a low level (logic 0).
[0119] In some implementations, the decoder 400 is configured to receive a signal S output by a controller corresponding to the memory, decode the signal S and output the above-mentioned SRE CMD signal, SRX CMD signal and AREF CMD signal.
[0120] In some embodiments of the present disclosure, the self-refresh mode signal S1 received by the memory includes a first mode signal and a second mode signal. The self-refresh control signal generation module 100 is configured to: receive the first mode signal and the second mode signal, and when the first mode signal is at an effective level, generate a signal inverted from the second mode signal as the self-refresh control signal S2.
[0121] Exemplarily, taking the above-mentioned memory as DDR4 as an example, the above-mentioned first mode signal can be a refresh command signal (hereinafter referred to as REF CMD signal) sent by a controller corresponding to the memory, and the second mode signal can be an externally input clock enable signal (hereinafter referred to as CKE signal).
[0122] The refresh control circuit provided in the embodiment of the present disclosure utilizes a refresh operation module to enable the memory to execute an automatic refresh signal periodically issued by a controller in an automatic refresh mode, and to execute a self-refresh signal periodically generated by the memory itself in a self-refresh mode, thereby ensuring that data stored in the memory is not lost.
[0123] Reference Figure 7 , Figure 7 A schematic diagram of the structure of a self-refresh control signal generating module 100 provided in an embodiment of the present disclosure Figure 3 In some embodiments of the present disclosure, the self-refresh control signal generation module 100 includes a third inverter NOT3, a second NOR gate NOR2, a third NAND gate NAND3, and a second latch 102. The second latch 102 includes a fourth NAND gate NAND4 and a fifth NAND gate NAND5; wherein:
[0124] In some embodiments, a receiving end of the third inverter NOT3 is used to receive a CKE signal, an output end of the third inverter NOT3 is connected to an input end of the third NAND gate NAND3, another input end of the third NAND gate NAND3 is used to receive a REF CMD signal, and an output end of the third NAND gate NAND3 is connected to an input end of a fourth NAND gate NAND4; another input end of the fourth NAND gate NAND4 is connected to an output end of a fifth NAND gate NAND5, and an output end of the fourth NAND gate NAND4 is connected to an input end of a fifth NAND gate NAND5; another input end of the fifth NAND gate NAND5 is connected to an output end of the second NOR gate NOR2, one input end of the second NOR gate NOR2 is used to receive a CKE signal, and another input end of the second NOR gate NOR2 is used to receive a start reset signal PWR Reset; an output end of the fourth NAND gate NAND4 is a first output end of the self-refresh control signal generation module 100, which is used to output a self-refresh control signal S2.
[0125] In some implementations, PWR Reset remains low after the memory system is powered on.
[0126] In some embodiments, the REF CMD signal is effective at a high level. When the REF CMD signal is at a high level, the memory enters a refresh mode. During the period when the REF CMD signal is at a high level, if the CKE signal is at a low level, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is at a high level, and the memory enters a self-refresh mode; if the CKE signal is at a high level, the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is at a low level, and the memory enters an automatic refresh mode. When the REF CMD signal is at a low level, the memory exits the refresh mode, and the self-refresh control signal S2 output by the self-refresh control signal generation module 100 is at a low level.
[0127] The self-refresh control signal generation module provided in the embodiment of the present disclosure can convert the received refresh command signal and clock enable signal into a self-refresh control signal, and use the level state of the self-refresh control signal to instruct the memory to enter the self-refresh mode or to instruct the memory to exit the self-refresh mode; this can help to subsequently shield short-term commands to enter / exit the self-refresh mode, thereby improving the performance of the memory.
[0128] Reference Figure 8 , Figure 8 A schematic diagram of a refresh control circuit provided in an embodiment of the present disclosure Figure 3 In some embodiments of the present disclosure, the refresh control circuit includes a self-refresh control signal generating module 100, a self-refresh signal generating module 200, a refresh operation module 300, a decoder 400 and a second AND gate AND2.
[0129] In some embodiments, the self-refresh control signal generation module 100 may be Figure 7 The self-refresh control signal generating module 100 and the self-refresh signal generating module 200 may be Figure 2 or Figure 3 The detailed structure of the self-refresh signal generating module 200 shown can refer to the description in the above embodiment, and will not be described in detail in this embodiment.
[0130] In some embodiments, the refresh operation module 300 includes a first OR gate OR; an input end of a second AND gate AND2 is used to receive a REF CMD signal, another input end of the second AND gate AND2 is used to receive a CKE signal, and an output end of the second AND gate AND2 is connected to an input end of the first OR gate OR to output an AREF CMD signal. Another input end of the first OR gate OR is connected to a second output end of the self-refresh signal generation module 200 to receive a self-refresh signal S3, and an output end of the first OR gate OR is used to output a refresh signal S5, which is used to instruct the memory to perform a refresh operation.
[0131] In some embodiments, the REF CMD signal is effective at a high level. When the REF CMD signal is at a high level, the memory enters a refresh mode. During the period when the REF CMD signal is at a high level, if the CKE signal is at a high level, the AREF CMD signal is at a high level. If the CKE signal is at a low level, the AREF CMD signal is at a low level. Among them, the AREF CMD signal is effective at a high level. When the AREF CMD signal is at a high level, the memory performs a refresh operation in the automatic refresh mode.
[0132] In some implementations, the decoder 400 is configured to receive a signal S output by a controller corresponding to the memory, decode the signal S, and then output the REF CMD signal and the CKE signal.
[0133] The refresh control circuit provided in the embodiment of the present disclosure utilizes a refresh operation module to enable the memory to execute an automatic refresh signal periodically issued by a controller in an automatic refresh mode, and to execute a self-refresh signal periodically generated by the memory itself in a self-refresh mode, thereby ensuring that data stored in the memory is not lost.
[0134] Based on the contents described in the above embodiments, a memory is also disclosed in the embodiments of the present disclosure. The memory includes a refresh control circuit as described in the above embodiments, which will not be described in detail in the embodiments of the present disclosure.
[0135] In the several embodiments provided in the present disclosure, it should be understood that the division of the modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.
[0136] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0137] In addition, each functional module in each embodiment of the present disclosure may be integrated into one processing unit, each module may exist physically separately, or two or more modules may be integrated into one unit. The above module integration unit may be implemented in the form of hardware or in the form of hardware plus software functional units.
[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A refresh control circuit, applied to a memory, characterized in that: The refresh control circuit comprises: a self-refresh control signal generating module and a self-refresh signal generating module, wherein: The self-refresh control signal generation module includes at least one input terminal and a first output terminal, wherein the at least one input terminal is used to receive a self-refresh mode signal; the self-refresh control signal generation module is configured to: when the self-refresh mode signal received by the at least one input terminal indicates that the memory enters the self-refresh mode, output a self-refresh control signal of a first level at the first output terminal; when the self-refresh mode signal received by the at least one input terminal indicates that the memory exits the self-refresh mode, output a self-refresh control signal of a second level at the first output terminal; The self-refresh signal generating module includes a first input terminal and a second output terminal, the first input terminal is connected to the first output terminal and is used to receive the self-refresh control signal, and the second output terminal is used to output a self-refresh signal, and the self-refresh signal is used to indicate that the memory enters a self-refresh operation; the self-refresh signal generating module is configured to: generate a shielding signal based on the self-refresh control signal, and output the self-refresh control signal after shielding it for a preset period of time based on the shielding signal.
2. The refresh control circuit according to claim 1, characterized in that: The preset time length is the time interval between two refresh commands received consecutively by the memory.
3. The refresh control circuit according to claim 1 or 2, characterized in that: The shielding signal is a clock signal whose starting level is the second level.
4. The refresh control circuit according to claim 3, characterized in that: The self-refresh signal generation module includes a shielding signal generation unit and a shielding unit; The shielding signal generating unit is connected to the first output terminal and is used to receive the self-refresh control signal output by the first output terminal; The shielding signal generating unit is configured to: generate the shielding signal based on the received self-refresh control signal; The shielding unit is connected to the first output terminal and the shielding signal generating unit respectively, and is used for receiving the self-refresh control signal and the shielding signal; The shielding unit is configured to: shield the self-refresh control signal for a preset time period based on the shielding signal and then output it.
5. The refresh control circuit according to claim 4, characterized in that: The shielding signal generating unit includes an oscillator, a frequency divider and a first inverter; the shielding unit includes a first AND gate; The output end of the oscillator is connected to the input end of the frequency divider, the output end of the frequency divider is connected to one input end of the first AND gate, the input end of the first inverter is connected to the first output end, and the output end of the first inverter is connected to the reset end of the frequency divider; the other input end of the first AND gate is connected to the first output end; and the output end of the first AND gate is the second output end.
6. The refresh control circuit according to claim 1, characterized in that: The self-refresh mode signal includes a self-refresh entry signal and a self-refresh exit signal; The self-refresh control signal generating module is configured to: receive the self-refresh entry signal and the self-refresh exit signal, and generate the self-refresh control signal based on the transition edge of the self-refresh entry signal and the transition edge of the self-refresh exit signal, wherein the effective level of the self-refresh control signal starts at the transition edge of the self-refresh entry signal and ends at the transition edge of the self-refresh exit signal.
7. The refresh control circuit according to claim 6, characterized in that: The self-refresh control signal generating module includes a second inverter, a first NOR gate and a first latch, wherein the first latch includes a first NAND gate and a second NAND gate; wherein: The receiving end of the second inverter is used to receive the self-refresh entry signal, and the output end of the second inverter is connected to an input end of the first NAND gate; the other input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to an input end of the second NAND gate; the other input end of the second NAND gate is connected to the output end of the first NOR gate, one input end of the first NOR gate is used to receive the self-refresh exit signal, and the other input end of the first NOR gate is used to receive a start reset signal; the output end of the first NAND gate is the first output end.
8. The refresh control circuit according to claim 6 or 7, characterized in that: The self-refresh entry signal is a self-refresh mode entry command signal; the self-refresh exit signal is a self-refresh mode exit command signal.
9. The refresh control circuit according to claim 1, characterized in that: The self-refresh mode signal includes a first mode signal and a second mode signal; The self-refresh control signal generating module is configured to receive the first mode signal and the second mode signal, and when the first mode signal is at an effective level, generate a signal which is inverted from the second mode signal as the self-refresh control signal.
10. The refresh control circuit according to claim 9, characterized in that: The self-refresh control signal generating module includes a third inverter, a second NOR gate, a third NAND gate and a second latch, and the second latch includes a fourth NAND gate and a fifth NAND gate; wherein: The receiving end of the third inverter is used to receive the second mode signal, the output end of the third inverter is connected to an input end of the third NAND gate, the other input end of the third NAND gate is used to receive the first mode signal, and the output end of the third NAND gate is connected to an input end of the fourth NAND gate; the other input end of the fourth NAND gate is connected to the output end of the fifth NAND gate, and the output end of the fourth NAND gate is connected to an input end of the fifth NAND gate; the other input end of the fifth NAND gate is connected to the output end of the second NOR gate, one input end of the second NOR gate is used to receive the second mode signal, and the other input end of the second NOR gate is used to receive a start reset signal; the output end of the fourth NAND gate is the first output end.
11. The refresh control circuit according to claim 1, characterized in that: The refresh control circuit also includes a refresh operation module, which includes a first OR gate; one input end of the first OR gate is used to receive an automatic refresh signal, the other input end of the first OR gate is connected to the second output end, used to receive the self-refresh signal, and the output end of the first OR gate is used to output a refresh signal; the refresh signal is used to instruct the memory to perform a refresh operation.
12. The refresh control circuit according to claim 11, characterized in that: The automatic refresh signal is an automatic refresh command signal sent by a controller corresponding to the memory.
13. The refresh control circuit according to claim 11, characterized in that: The self-refresh mode signal includes a first mode signal and a second mode signal; The refresh control circuit also includes a second AND gate; one input end of the second AND gate is used to receive the first mode signal, another input end of the second AND gate is used to receive the second mode signal, and the output end of the second AND gate is used to output the automatic refresh signal.
14. The refresh control circuit according to any one of claims 9, 10 and 13, characterized in that: The first mode signal is a refresh command signal sent by a controller corresponding to the memory, and the second mode signal is a clock enable signal input from the outside.
15. A memory, characterized in that: Comprising the refresh control circuit as claimed in any one of claims 1 to 14.