A silicon substrate gallium nitride wafer including a large mismatch stress control structure and its preparation method and application

Abstract

The present invention discloses a silicon substrate gallium nitride wafer including a large mismatch stress regulation structure, and a preparation method and application thereof, and relates to the field of semiconductor material technology. The silicon substrate gallium nitride wafer including a large mismatch stress regulation structure is composed of a silicon substrate, an aluminum nitride amorphous film barrier layer, an ultra-thin porous aluminum oxide weakly bonded decoupling layer, an aluminum nitride single crystal film nucleation layer template layer, and a gallium nitride single crystal film quality improvement layer stacked in sequence. The present invention controls the pore size and pore density in the ultra-thin porous aluminum oxide weakly bonded decoupling layer, thereby achieving the weakly bonded decoupling effect regulation of the aluminum nitride single crystal film nucleation layer template layer thereon, thereby achieving large mismatch stress regulation of silicon substrate gallium nitride materials, crack-free thickness and material crystal quality, and improving material preparation efficiency. The silicon substrate gallium nitride wafer including a large mismatch stress regulation structure of the present invention can be used to develop and produce gallium nitride-based power electronic devices, microwave radio frequency devices, and optoelectronic devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor materials, and in particular to a silicon substrate gallium nitride wafer comprising a large mismatch stress regulating structure, and a preparation method and application thereof. Background Art

[0002] Silicon (Si) single crystal substrates have large single crystals, low prices, mature device processes, and easy system integration. In recent years, they have developed into one of the mainstream single crystal substrate materials for compound semiconductor materials and device preparation and production. In particular, with the advancement of epitaxial growth technology of silicon (Si) substrate gallium nitride (GaN) single crystal thin film materials, the material size has expanded from 2 inches to 8 inches, the crack-free thickness has increased from less than 2 microns to 3 microns (μm) or even more than 5 microns (μm), and the dislocation density has increased from 10 10 cm -2 Above this level is reduced to the same level as sapphire graphic substrate (no higher than 5×10 8 cm -2 ), and began to be applied and promoted in the field of light-emitting diode devices and low-voltage power electronic devices (withstand voltage not higher than 650V), thereby promoting the development of LED semiconductor lighting, Mini LED display, Micro-LED display and consumer electronic products such as mobile phone fast charging. However, since silicon (Si) has a cubic diamond crystal structure with a lattice constant of 0.5341nm, the in-plane lattice constant of the Si (111) crystal plane is 0.383nm, and the in-plane thermal expansion coefficient is 3.59×10 -6 K -1 Gallium nitride (GaN) has a hexagonal wurtzite crystal structure, with lattice constants a = 0.31885nm, c = 0.5185nm, and a-axis thermal expansion coefficient of 5.59×10 -6 K -1 , c-axis thermal expansion coefficient is 3.17×10 -6 K -1 The preparation and growth of gallium nitride (GaN) epitaxial layer on silicon (Si) single crystal substrate not only has very large lattice mismatch (mismatch -16.9%) and thermal mismatch (mismatch 56%), but also has relatively serious interface reaction and interface component interdiffusion problems. For example, the surface of the silicon (Si) substrate is first contacted with a nitrogen (N) source, and the silicon (Si) surface is nitrided to form amorphous silicon nitride (Si x N y ), gallium nitride (GaN) in amorphous silicon nitride (Si x N y ) is difficult to nucleate on the surface, and the low nucleation density often results in large gallium nitride (GaN) granular polycrystalline growth; if the surface of the silicon (Si) substrate first contacts the gallium (Ga) source, the metal gallium (Ga) droplets will melt back and corrode the surface of the silicon (Si) substrate to form a silicon-gallium alloy (Si xGa y ) irregular undulating surface, the surface of the silicon (Si) substrate is damaged and it is difficult to achieve single crystal growth of a flat surface of the gallium nitride (GaN) film. In addition, if the growth is prepared at high temperature (such as above 1000°C) and low pressure, the silicon (Si) surface is easy to decompose to produce a large number of silicon (Si) atoms, which diffuse into the gallium nitride (GaNg) epitaxial layer at a high concentration, which will form an n-type heavy doping with uncontrollable doping concentration in the gallium nitride (GaN) epitaxial layer. If the dislocation diffuses upward along the line, it will also form silicon (Si) spots and leakage channels, making it more difficult to improve the voltage resistance performance of silicon (Si) substrate gallium nitride (GaN) power electronic devices.

[0003] In order to overcome the above-mentioned large mismatch heteroepitaxial technology problems that often occur in the preparation on silicon (Si) substrates, a high-temperature MOCVD process with a growth temperature of more than 1000°C is currently often used to sequentially prepare a large mismatch stress control structure including an aluminum nitride (AlN) single crystal thin film barrier layer buffer layer, a multi-layer aluminum gallium nitride (AlGaN) single crystal thin film component gradient buffer layer or a multi-layer insertion layer (such as a low-temperature aluminum nitride (AlN) insertion layer or an aluminum nitride / gallium nitride (AlN / GaN) superlattice) on a silicon single crystal substrate, and then prepare a crack-free gallium nitride single crystal thin film quality improvement layer (crack-free thickness of at least 2μm, dislocation density not higher than 1×10 10 cm -2 ). Among them, aluminum nitride (AlN) has a hexagonal wurtzite structure, lattice constant a = 0.3112nm, c = 0.4882nm; a-axis thermal expansion coefficient is 4.15×10 -6 K -1 , c-axis thermal expansion coefficient is 5.27×10 -6 K -1. Although the lattice constant of the C-plane of aluminum nitride (AlN) is smaller than that of the C-plane gallium nitride (GaN) and Si (111) crystal plane, there is still a large lattice mismatch. In order to better block the high-concentration diffusion of silicon (Si) atoms generated by the decomposition of the silicon (Si) substrate surface into the gallium nitride (GaN) epitaxial layer, the thickness of the aluminum nitride single crystal thin film barrier buffer layer must be at least 100nm to have a good effect in blocking silicon (Si) diffusion. The increase in the thickness of aluminum nitride (AlN) actually reduces its effect of coordinating lattice mismatch stress, which is one of the reasons why it is still difficult to further reduce the dislocation density of gallium nitride (GaN) on silicon (Si) substrates. The in-plane thermal expansion coefficient of the C-plane of aluminum nitride (AlN) is between that of the Si (111) crystal plane and that of the C-plane gallium nitride. Therefore, it can only partially share the thermal stress caused by the large difference in thermal expansion coefficients between the silicon (Si) substrate and the gallium nitride (GaN) epitaxial layer due to the large temperature drop. This results in the smaller crack-free thickness of the GaN epitaxial layer as the size of the silicon (Si) substrate increases. This is one of the reasons why the crack-free thickness of the GaN epitaxial layer on a 6-inch silicon (Si) substrate is difficult to increase to more than 5μm and the crack-free thickness of the GaN epitaxial layer on an 8-inch silicon (Si) substrate is difficult to increase to more than 3μm. If the crack-free thickness of the GaN epitaxial layer on a silicon (Si) substrate is to be further increased, the thickness or number of the multi-layer aluminum gallium nitride (AlGaN) single crystal thin film composition gradient buffer layer has to be increased, which will greatly reduce the material preparation efficiency and increase the material preparation production cost. In addition, since the crystallization quality of the high-temperature aluminum nitride (AlN) single crystal thin film barrier layer buffer layer and the multi-layer aluminum gallium nitride (AlGaN) single crystal thin film component gradient buffer layer and stress regulation layer prepared by the high-temperature metal organic chemical vapor deposition (MOCVD) process is still relatively poor and there are high-density grain boundaries and line dislocations, the silicon (Si) atoms decomposed at high temperature on the surface of the silicon (Si) single crystal substrate may also diffuse through these channels into the device structure layer prepared and grown subsequently. This is also one of the reasons why it is currently difficult to achieve the voltage resistance performance improvement and high-yield mass production of silicon (Si) substrate gallium nitride (GaN) power electronic devices with a voltage resistance of more than 650V.

[0004] Therefore, if we want to more effectively block silicon (Si) diffusion and achieve further improvement in the quality, crack-free thickness, and material preparation efficiency of gallium nitride (GaN) epitaxial materials on silicon (Si) substrates, as well as low-stress and high-crystalline quality preparation, we also need to design and prepare new stress regulation structures to more effectively overcome the technical problems of large-mismatch heteroepitaxial growth of gallium nitride (GaN) on silicon (Si) substrates. Summary of the invention

[0005] The technical problem to be solved by the present invention is that the large mismatch stress regulation structure designed for the existing silicon substrate gallium nitride preparation is difficult to more effectively block silicon diffusion, and it is difficult to achieve the crystal quality, crack-free thickness, further improvement of material preparation efficiency and low-stress and high-crystallization quality preparation of silicon substrate gallium nitride materials. The present invention aims to provide a silicon substrate gallium nitride wafer including a large mismatch stress regulation structure.

[0006] In order to solve the above problems, the present invention proposes the following technical solutions:

[0007] In a first aspect, the present invention provides a silicon substrate gallium nitride wafer including a large mismatch stress control structure, comprising:

[0008] A silicon single crystal substrate with a thickness of 300-2000 μm;

[0009] An aluminum nitride amorphous thin film barrier layer with a thickness of 50-100 nm, disposed on the silicon single crystal substrate;

[0010] An ultra-thin porous aluminum oxide weakly bonded decoupling layer with a thickness of 20-50 nm, disposed on the aluminum nitride amorphous film barrier layer;

[0011] A 200-500nm thick aluminum nitride single crystal thin film nucleation layer template layer, disposed on the ultra-thin porous aluminum oxide weakly bonded decoupling layer;

[0012] A gallium nitride single crystal film quality improvement layer with a thickness not less than 3 μm is arranged on the aluminum nitride single crystal film nucleation layer template layer.

[0013] It can be understood that in the silicon substrate gallium nitride wafer of the present invention including a large mismatch stress regulation structure, the large mismatch stress regulation structure is composed of a silicon single crystal substrate, an aluminum nitride amorphous film barrier layer, an ultra-thin porous aluminum oxide weakly bonded decoupling layer, and an aluminum nitride single crystal film nucleation layer template layer stacked in sequence; the gallium nitride single crystal film quality improvement layer is located on the aluminum nitride single crystal film nucleation layer template layer.

[0014] Furthermore, the size of the silicon single crystal substrate includes but is not limited to 1 inch, 2 inches, 4 inches, 6 inches, 8 inches, and 12 inches in diameter.

[0015] Furthermore, the gallium nitride single crystal film quality improvement layer has no cracks and a dislocation density not higher than 5×10 8 cm -2 .

[0016] Furthermore, the porosity of the ultra-thin porous alumina weakly bonded decoupling layer is 15-85%.

[0017] Furthermore, the dislocation density of the aluminum nitride single crystal thin film nucleation layer template layer is not higher than 1×10 8 cm -2And the surface roughness is not higher than 1.0nm.

[0018] In a second aspect, the present invention provides a method for preparing a silicon substrate gallium nitride wafer comprising a large mismatch stress regulating structure as described in the first aspect, comprising the following steps:

[0019] S1. preparing a silicon single crystal substrate, and performing a high-vacuum high-temperature baking treatment on the surface of the silicon single crystal substrate to remove the residual oxide layer and adsorbed impurities on the surface;

[0020] S2, forming an aluminum nitride amorphous thin film barrier layer on the silicon single crystal substrate;

[0021] S3, forming an ultra-thin zinc aluminum oxide polycrystalline thin film layer having a single preferred orientation in the C direction on the aluminum nitride amorphous thin film barrier layer;

[0022] S4, forming an aluminum nitride polycrystalline thin film layer having a single preferred orientation in the C direction on the ultra-thin zinc aluminum oxide polycrystalline thin film layer having a single preferred orientation in the C direction;

[0023] S5. Under a hydrogen atmosphere, the ultra-thin zinc aluminum oxide polycrystalline thin film layer having a single preferred orientation in the C direction is subjected to a high-temperature high-vacuum annealing treatment to decompose the zinc component in the ultra-thin zinc aluminum oxide polycrystalline thin film layer and precipitate from the grain boundary gaps of the aluminum nitride polycrystalline thin film layer having a single preferred orientation in the C direction, thereby obtaining the ultra-thin porous aluminum oxide weakly bonded decoupled layer;

[0024] S6. Under an ammonia atmosphere, performing a high-temperature high-vacuum annealing treatment on the aluminum nitride polycrystalline thin film layer having a single preferred orientation in the C direction to recrystallize the aluminum nitride polycrystalline thin film layer to obtain the aluminum nitride single crystal thin film nucleation layer template layer;

[0025] S7. A gallium nitride single crystal film quality improvement layer is formed on a large mismatch stress regulation structure comprising a silicon single crystal substrate, an aluminum nitride amorphous film barrier layer, an ultra-thin porous aluminum oxide weakly bonded decoupling layer, and an aluminum nitride single crystal film nucleation layer template layer to obtain a silicon substrate gallium nitride wafer comprising a large mismatch stress regulation structure.

[0026] Furthermore, in step S5, the conditions for high temperature and high vacuum annealing in a hydrogen atmosphere are: annealing temperature 700-900° C., hydrogen atmosphere pressure 50-100 Pa, and high temperature and high vacuum annealing time 0.5-5.0 hours.

[0027] Furthermore, in step S6, the conditions for high temperature and high vacuum annealing in an ammonia atmosphere are: annealing temperature 900-1100° C., ammonia atmosphere pressure 5-50 Pa, and high temperature and high vacuum annealing time 1.0-10.0 hours.

[0028] Furthermore, the atomic percentage concentration of the zinc component in the ultra-thin zinc-aluminum-oxygen polycrystalline film layer is 15-85%.

[0029] Furthermore, the silicon substrate gallium nitride wafer containing a large mismatch stress regulation structure obtained by the method is used to prepare gallium nitride power electronic devices, gallium nitride microwave radio frequency devices, gallium nitride light emitting diode devices, gallium nitride laser diode devices, and gallium nitride ultraviolet detector devices.

[0030] Compared with the prior art, the technical effects achieved by the present invention include:

[0031] The silicon substrate gallium nitride wafer with a large mismatch stress control structure provided by the present invention is composed of a silicon substrate, an aluminum nitride amorphous film barrier layer, an ultra-thin porous aluminum oxide weakly bonded decoupling layer, an aluminum nitride (AlN) single crystal film nucleation layer template layer and a gallium nitride (GaN) single crystal film quality improvement layer stacked in sequence. Among them, the aluminum nitride amorphous film barrier layer has a small grain size and a very dense film layer. Compared with the conventional polycrystalline or poorly crystalline aluminum nitride single crystal film material used as a barrier layer and a buffer layer, it has a better effect of blocking the thermal diffusion of silicon atoms decomposed at high temperature on the surface of the silicon substrate into the gallium nitride epitaxial layer; the ultra-thin porous aluminum oxide weakly bonded decoupling layer has a larger thermal expansion coefficient than the silicon single crystal substrate and the gallium nitride epitaxial layer, and can better transfer the thermal stress generated during the large-scale cooling process to the ultra-thin porous aluminum oxide weakly bonded decoupling layer for release, and is not affected by the expansion of the size of the silicon single crystal substrate; the aluminum nitride (AlN) single crystal film nucleation layer template layer of the present invention has a larger thermal expansion coefficient than the conventional aluminum nitride (AlN) single crystal film barrier layer. The higher crystallization quality of the barrier buffer layer and the multilayer aluminum gallium nitride (AlGaN) single crystal film component gradient buffer layer can not only provide a single crystal film template with better crystallization quality, but also is more conducive to the high-density nucleation growth of gallium nitride, and can more effectively reduce the lattice mismatch stress and dislocation density of the gallium nitride single crystal film quality improvement layer epitaxially grown thereon, thereby having a higher crystallization quality; by regulating the thickness and porosity of the ultra-thin aluminum oxide weakly bonded decoupling layer, not only can the large mismatch stress and dislocation density of the gallium nitride (GaN) single crystal film quality improvement layer be further reduced, but also the crack-free thickness and yield of the gallium nitride (GaN) single crystal film quality improvement layer can be greatly improved.

[0032] Further, according to the method for preparing a silicon substrate gallium nitride wafer containing a large mismatch stress control structure described in the present invention, the ultra-thin porous aluminum oxide weakly bonded decoupling layer is formed by an ultra-thin zinc aluminum oxide film layer containing a zinc component being subjected to a high-temperature and high-vacuum annealing process in a hydrogen atmosphere to completely thermally decompose and precipitate the zinc component. Among them, the zinc aluminum oxide thin film material with a high zinc component content has a strong polarity, and it is easy to achieve a hexagonal crystal structure C-axis single preferential orientation polycrystalline growth with a columnar crystal arrangement even on the surface of an amorphous substrate. Using the ultra-thin zinc aluminum oxide polycrystalline film with a hexagonal crystal structure C-axis single preferential orientation growth as a template, the aluminum nitride columnar crystal arrangement C-axis single preferential orientation polycrystalline growth with the same hexagonal crystal structure can also be achieved. After high-temperature and high-vacuum annealing in a hydrogen atmosphere, the zinc component in the ultra-thin zinc aluminum oxide film layer will be decomposed and completely precipitated, thereby forming an ultra-thin porous aluminum oxide weakly bonded decoupling layer. The ultra-thin porous alumina weakly bonded decoupling layer can achieve weak bonding and decoupling between the aluminum nitride polycrystalline thin film nucleation layer template layer thereon and the bottom silicon substrate and the aluminum nitride amorphous thin film barrier layer; the aluminum nitride polycrystalline thin film nucleation layer with weak bonding decoupling and single preferred orientation of the C-axis is then subjected to high-temperature and high-vacuum annealing treatment in an ammonia atmosphere. Only high-temperature and high-vacuum annealing treatment at 900-1100°C is required to achieve grain fusion and merging in the aluminum nitride polycrystalline thin film nucleation layer template layer, and then recrystallize to form an aluminum nitride single crystal thin film nucleation layer template layer with higher crystallization quality, which is lower than the recrystallization temperature (1400-1600°C) of conventional sapphire aluminum nitride polycrystalline thin films.

[0033] Furthermore, the structure of the wafer of the silicon substrate gallium nitride large mismatch stress control structure provided by the present invention can realize the silicon substrate gallium nitride large mismatch stress control, and the "unsupported substrate" model design based on the flexible substrate is compared with the existing flexible substrate preparation technology, such as sacrificial layer bonding technology, ion implantation buried layer technology and few-layer two-dimensional material technology, which are difficult to control the weak bond decoupling effect. By adjusting the zinc component concentration and layer thickness in the ultra-thin zinc aluminum oxide polycrystalline film layer, the pore size and pore density in the ultra-thin porous aluminum oxide weak bond decoupling layer after high temperature and high vacuum annealing can be controlled, thereby realizing the weak bond decoupling effect control of the aluminum nitride single crystal film nucleation layer template layer thereon. Ultra-thin porous aluminum oxide weak bond decoupling layers with different thicknesses and different pore sizes and densities are designed and prepared on silicon single crystal substrates of different sizes, which can not only improve the crystallization quality of the thin aluminum nitride nucleation layer template layer thereon, but also greatly reduce the stress and dislocation density of the subsequent epitaxially grown thicker gallium nitride single crystal film quality improvement layer and greatly improve the crack-free thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0035] Figure 1 The structure diagram of the silicon substrate gallium nitride wafer including the large mismatch stress control structure of the embodiment 1 of the present invention is shown in FIG. 100 is the large mismatch stress control structure, which is composed of a silicon single crystal substrate 101, an aluminum nitride amorphous film barrier layer 102, an ultra-thin porous aluminum oxide weak bonding decoupling layer 103, and an aluminum nitride single crystal film nucleation layer template layer 104 stacked in sequence; 200 is a gallium nitride epitaxial layer, which is a gallium nitride single crystal film quality improvement layer 201.

[0036] Figure 2 This is a schematic diagram of the structure of forming an ultra-thin zinc aluminum oxide polycrystalline film layer and an aluminum nitride polycrystalline film layer having a single preferred orientation in the C direction on the aluminum nitride amorphous film barrier layer in the method for preparing a silicon substrate gallium nitride wafer with a large mismatch stress control structure according to Example 1 of the present invention. Among them, 1031 is an ultra-thin zinc aluminum oxide polycrystalline film layer, and 1041 is an aluminum nitride polycrystalline film layer.

[0037] Figure 3 This is a schematic diagram of the structure of the ultra-thin porous aluminum oxide weakly bonded decoupling layer and the aluminum nitride single crystal film nucleation layer template layer formed on the aluminum nitride amorphous film barrier layer in the method for preparing a silicon substrate gallium nitride wafer with a large mismatch stress control structure according to Example 1 of the present invention. Among them, 103 is the ultra-thin porous aluminum oxide weakly bonded decoupling layer, and 104 is the aluminum nitride single crystal film nucleation layer template layer. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0040] It should also be understood that the terms used in this description of the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present invention. As used in the description of the embodiments of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms.

[0041] Example 1

[0042] This embodiment discloses a 6-inch silicon substrate gallium nitride wafer including a large mismatch stress control structure, the structure of which is as follows: Figure 1 As shown. 100 is a large mismatch stress control structure, which is composed of a silicon single crystal substrate 101, an aluminum nitride amorphous film barrier layer 102, an ultra-thin porous aluminum oxide weak bonding decoupling layer 103, and an aluminum nitride single crystal film nucleation layer template layer 104 stacked in sequence; 200 is a gallium nitride epitaxial layer, which is a gallium nitride single crystal film quality improvement layer 201.

[0043] The structure and preparation method of the silicon substrate gallium nitride wafer including the large mismatch stress control structure of this embodiment are described as follows:

[0044] A 6-inch 500 μm thick silicon single crystal substrate (101).

[0045] A 60nm thick aluminum nitride amorphous thin film barrier layer (102) is formed on a 6-inch 500μm thick silicon single crystal substrate (101). In some embodiments, the 60nm thick aluminum nitride amorphous thin film barrier layer (102) can be prepared by a medium-low temperature physical vapor deposition process with a growth temperature of 250-550°C; in this embodiment, it is prepared by a medium-low temperature physical vapor deposition process with a growth temperature of 450°C.

[0046] A 30nm thick ultra-thin porous aluminum oxide weakly bonded decoupling layer (103); a 300nm thick aluminum nitride single crystal film nucleation layer template layer (104). Figure 2 and Figure 3In this embodiment, an ultra-thin zinc aluminum oxide polycrystalline film layer (1031) with a zinc component atomic percentage concentration of 55% and a single preferred orientation along the C axis and an aluminum nitride polycrystalline film layer (1041) with a thickness of 300 nm and a single preferred orientation along the C axis are sequentially formed on the aluminum nitride amorphous film barrier layer (102) with a thickness of 60 nm, and the ultra-thin zinc aluminum oxide polycrystalline film layer (1031) is first subjected to high temperature high vacuum annealing at 850° C. and a hydrogen atmosphere pressure of 60 Pa for 1.0 hour to make the zinc component in the ultra-thin zinc aluminum oxide polycrystalline film layer (1031) have a single preferred orientation along the C axis. The aluminum nitride polycrystalline film layer (1041) is completely thermally decomposed and precipitated from the grain boundary gap of the aluminum nitride polycrystalline film layer (1041) with a single preferred orientation in the C direction to form an ultra-thin porous aluminum oxide weakly bonded decoupled layer (103) with a porosity of 55%, and then subjected to high temperature and high vacuum annealing at a high temperature of 1050° C. and an ammonia atmosphere pressure of 20 Pa for 1 hour to recrystallize the aluminum nitride polycrystalline film layer (1041) to form an aluminum nitride single crystal film nucleation layer template layer (104), wherein the dislocation density of the aluminum nitride single crystal film nucleation layer template layer (104) is not higher than 5×10 7 cm -2 And the surface roughness is not higher than 0.5nm.

[0047] In some embodiments, the ultra-thin zinc aluminum oxide polycrystalline film layer (1031) can be prepared by a medium-high temperature physical vapor deposition process with a growth temperature of 450-750°C; the aluminum nitride polycrystalline film layer (1041) can be prepared by a medium-high temperature physical vapor deposition process with a growth temperature of 450-750°C. In this embodiment, the ultra-thin zinc aluminum oxide polycrystalline film layer (1031) is prepared by a medium-high temperature physical vapor deposition process with a growth temperature of 550°C; the aluminum nitride polycrystalline film layer (1041) is prepared by a medium-high temperature physical vapor deposition process with a growth temperature of 550°C.

[0048] A gallium nitride single crystal thin film quality improvement layer (201) with a crack-free thickness of not less than 7 μm. In this embodiment, the gallium nitride single crystal thin film quality improvement layer (201) can be prepared by conventional metal organic chemical vapor deposition (MOCVD) process and grown on the above-mentioned 300 nm thick aluminum nitride single crystal thin film nucleation layer template layer (104); in this embodiment, the gallium nitride single crystal thin film quality improvement layer (201) has a dislocation density of not more than 1×10 8 cm -2 .

[0049] The 6-inch silicon substrate gallium nitride wafer containing a large mismatch stress control structure prepared by the above embodiment can be used to manufacture gallium nitride-based power electronic devices with a withstand voltage of not less than 1200V.

[0050] Example 2

[0051] See also Figure 1-3This embodiment provides an 8-inch silicon substrate gallium nitride wafer including a large mismatch stress regulation structure. The structure of the 8-inch silicon substrate gallium nitride wafer including a large mismatch stress regulation structure (100) includes, from bottom to top:

[0052] An 8-inch 1000 μm thick silicon single crystal substrate (101);

[0053] A 100 nm thick aluminum nitride amorphous film barrier layer (102);

[0054] A 40 nm thick ultra-thin porous aluminum oxide weakly bonded decoupling layer (103);

[0055] A 500nm thick aluminum nitride single crystal thin film nucleation layer template layer (104);

[0056] A gallium nitride single crystal thin film quality improvement layer (201) having a crack-free thickness of not less than 5 μm.

[0057] The method for preparing the 8-inch silicon substrate gallium nitride wafer including the large mismatch stress control structure comprises the following steps:

[0058] S1. Prepare an 8-inch thick 1000 μm silicon single crystal substrate (101), and bake it at a high temperature and high vacuum for 30 minutes at a substrate heating temperature of 1100° C. to remove the residual oxide layer and adsorbed impurities on the surface of the silicon single crystal substrate (101).

[0059] S2, forming an aluminum nitride amorphous thin film barrier layer (102) with a thickness of 100 nm on the silicon single crystal substrate (101), which is prepared by a medium-low temperature chemical vapor deposition process with a growth temperature of 550° C. in this embodiment;

[0060] S3, forming an ultra-thin zinc aluminum oxide polycrystalline thin film layer (1031) with a thickness of 40 nm and a zinc component atomic percentage concentration of 65% and a single preferred orientation in the C direction on the aluminum nitride amorphous thin film barrier layer (102), and this embodiment is prepared by a medium-high temperature chemical vapor deposition process with a growth temperature of 750° C.;

[0061] S4, forming a 500 nm thick aluminum nitride polycrystalline film layer (1041) having a single preferred orientation in the C direction on the ultra-thin zinc aluminum oxide polycrystalline film layer (1031), which is prepared by a medium-high temperature chemical vapor deposition process with a growth temperature of 850° C. in this embodiment;

[0062] S5. The ultra-thin zinc aluminum oxide polycrystalline thin film layer (1031) with a single preferred orientation in the C direction is subjected to high-temperature high-vacuum annealing at 850° C. for 2 hours in a 60 Pa hydrogen atmosphere, so that the zinc component in the ultra-thin zinc aluminum oxide polycrystalline thin film layer (1031) is decomposed and precipitated from the grain boundary gap of the aluminum nitride polycrystalline thin film layer (1041) with a single preferred orientation in the C direction, thereby obtaining an ultra-thin porous aluminum oxide weakly bonded decoupled layer (103) with a porosity of 65%;

[0063] S6. The aluminum nitride polycrystalline thin film layer (1041) having a single preferred orientation in the C direction and formed on the ultra-thin porous aluminum oxide weakly bonded decoupled layer (103) is subjected to high-temperature high-vacuum annealing at 1100° C. for 2 hours in a 50 Pa ammonia atmosphere to recrystallize the aluminum nitride polycrystalline thin film layer (1041) to obtain an aluminum nitride single crystal thin film nucleation layer template layer (104). In this embodiment, the dislocation density of the aluminum nitride single crystal thin film nucleation layer template layer (104) is not higher than 1×10 8 cm -2 And the surface roughness is not higher than 0.6nm;

[0064] S7. A gallium nitride single crystal film quality improvement layer (201) having a crack-free thickness of not less than 5 μm is formed on a large mismatch stress control structure (100) comprising a silicon single crystal substrate (101), an aluminum nitride amorphous film barrier layer (102), an ultra-thin porous aluminum oxide weakly bonded decoupling layer (103), and an aluminum nitride single crystal film nucleation layer template layer (104), to obtain an 8-inch silicon substrate gallium nitride wafer comprising a large mismatch stress control structure. In this embodiment, the dislocation density of the gallium nitride single crystal film quality improvement layer (201) is not higher than 5×10 8 cm -2 .

[0065] The 8-inch silicon substrate gallium nitride wafer containing a large mismatch stress control structure prepared by the above embodiment can be used to manufacture high-frequency and high-power gallium nitride-based microwave radio frequency devices.

[0066] The silicon substrate gallium nitride wafer including the large mismatch stress regulation structure provided by the embodiment of the present invention regulates the large mismatch stress of the silicon substrate gallium nitride by utilizing the large mismatch stress regulation structure composed of the silicon single crystal substrate, the aluminum nitride amorphous film barrier layer, the ultra-thin porous aluminum oxide weakly bonded decoupling layer, and the aluminum nitride (AlN) single crystal film nucleation layer template layer, which can not only further improve the crystallization quality, crack-free thickness and material preparation efficiency of the silicon substrate gallium nitride material, but also more effectively block silicon diffusion and reduce the influence of the large mismatch stress on the material growth quality.

[0067] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0068] The above is a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A silicon substrate gallium nitride wafer comprising a large mismatch stress control structure, characterized in that: include: A silicon single crystal substrate with a thickness of 300-2000µm; An aluminum nitride amorphous thin film barrier layer with a thickness of 50-100 nm, disposed on the silicon single crystal substrate; An ultra-thin porous aluminum oxide weakly bonded decoupling layer with a thickness of 20-50 nm, disposed on the aluminum nitride amorphous film barrier layer; A 200-500nm thick aluminum nitride single crystal thin film nucleation layer template layer, disposed on the ultra-thin porous aluminum oxide weakly bonded decoupling layer; A gallium nitride single crystal film quality improvement layer with a thickness of not less than 3µm, disposed on the aluminum nitride single crystal film nucleation layer template layer; The method for preparing the silicon substrate gallium nitride wafer including the large mismatch stress regulating structure comprises the following steps: S1. preparing a silicon single crystal substrate, and performing a high-vacuum high-temperature baking treatment on the surface of the silicon single crystal substrate to remove the residual oxide layer and adsorbed impurities on the surface; S2, forming an aluminum nitride amorphous thin film barrier layer on the silicon single crystal substrate; S3, forming an ultra-thin zinc aluminum oxide polycrystalline thin film layer having a single preferred orientation in the C direction on the aluminum nitride amorphous thin film barrier layer; S4, forming an aluminum nitride polycrystalline thin film layer having a single preferred orientation in the C direction on the ultra-thin zinc aluminum oxide polycrystalline thin film layer having a single preferred orientation in the C direction; S5. Under a hydrogen atmosphere, the ultra-thin zinc aluminum oxide polycrystalline thin film layer having a single preferred orientation in the C direction is subjected to a high-temperature high-vacuum annealing treatment to decompose the zinc component in the ultra-thin zinc aluminum oxide polycrystalline thin film layer and precipitate from the grain boundary gaps of the aluminum nitride polycrystalline thin film layer having a single preferred orientation in the C direction, thereby obtaining the ultra-thin porous aluminum oxide weakly bonded decoupled layer; S6. Under an ammonia atmosphere, performing a high-temperature high-vacuum annealing treatment on the aluminum nitride polycrystalline thin film layer having a single preferred orientation in the C direction to recrystallize the aluminum nitride polycrystalline thin film layer to obtain the aluminum nitride single crystal thin film nucleation layer template layer; S7, forming a gallium nitride single crystal film quality improvement layer on a large mismatch stress regulation structure comprising a silicon single crystal substrate, an aluminum nitride amorphous film barrier layer, an ultra-thin porous aluminum oxide weakly bonded decoupling layer, and an aluminum nitride single crystal film nucleation layer template layer, to obtain a silicon substrate gallium nitride wafer comprising a large mismatch stress regulation structure; Wherein, in the step S5, the conditions of high temperature and high vacuum annealing in hydrogen atmosphere include: annealing temperature 700-900° C., hydrogen atmosphere pressure 50-100 Pa; In the step S6, the conditions for high temperature and high vacuum annealing in an ammonia atmosphere include: an annealing temperature of 900-1100° C. and an ammonia atmosphere pressure of 5-50 Pa.

2. The silicon substrate gallium nitride wafer comprising a large mismatch stress regulating structure according to claim 1, characterized in that: The size of the silicon single crystal substrate includes but is not limited to 1 inch, 2 inches, 4 inches, 6 inches, 8 inches, and 12 inches in diameter.

3. The silicon substrate gallium nitride wafer comprising a large mismatch stress regulating structure according to claim 2, characterized in that: The gallium nitride single crystal film quality improvement layer has no cracks and a dislocation density of no more than 5×10 8 cm -2 .

4. The silicon substrate gallium nitride wafer comprising a large mismatch stress regulating structure according to claim 1, characterized in that: The porosity of the ultra-thin porous alumina weakly bonded decoupling layer is 15-85%.

5. The silicon substrate gallium nitride wafer comprising a large mismatch stress regulating structure according to claim 1, characterized in that: The dislocation density of the aluminum nitride single crystal film nucleation layer template layer is not higher than 1×10 8 cm -2 And the surface roughness is not higher than 1.0nm.

6. A method for preparing a silicon substrate gallium nitride wafer comprising a large mismatch stress regulating structure as described in any one of claims 1 to 5.

7. The method for preparing the silicon substrate gallium nitride wafer comprising the large mismatch stress regulating structure according to claim 6, characterized in that: In the step S5, the high temperature and high vacuum annealing time in the hydrogen atmosphere is 0.5-5.0 hours.

8. The method for preparing the silicon substrate gallium nitride wafer with the large mismatch stress control structure according to claim 6, characterized in that: In the step S6, the high temperature and high vacuum annealing time in the ammonia atmosphere is 1.0-10.0 hours.

9. The method for preparing the silicon substrate gallium nitride wafer comprising the large mismatch stress regulating structure according to claim 6, characterized in that: The atomic percentage concentration of the zinc component in the ultra-thin zinc-aluminum-oxygen polycrystalline film layer is 15-85%.

10. Use of the silicon substrate gallium nitride wafer comprising a large mismatch stress regulation structure as described in any one of claims 1 to 5, or the silicon substrate gallium nitride wafer comprising a large mismatch stress regulation structure obtained by the method as described in any one of claims 6 to 9 in the preparation of gallium nitride power electronic devices, gallium nitride microwave radio frequency devices, gallium nitride light emitting diode devices, gallium nitride laser diode devices, and gallium nitride ultraviolet detector devices.

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