Semiconductor packaging structure and forming method thereof

Abstract

The invention discloses a semiconductor packaging structure and a forming method thereof, and the forming method comprises the steps: providing a first carrier plate, bonding an upper insulating layer of a bridging chip on the upper surface of the first carrier plate, and forming a first plastic packaging layer which covers the upper surface of the first carrier plate and the bridging chip; the first plastic packaging layer and the lower insulating layer are thinned, a first rewiring layer is formed on the surface of the thinned first plastic packaging layer and the surface of the thinned lower insulating layer, and the process for forming the first rewiring layer comprises an electroplating process; the upper insulating layer and the first plastic packaging layer are thinned, a second rewiring layer is formed on the surface of the thinned upper insulating layer and the surface of the thinned first plastic packaging layer, and the process for forming the second rewiring layer comprises an electroplating process; and providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the second rewiring layer, and electrically connecting the semiconductor chip with the second rewiring layer. According to the method, the connection strength at the connection points can be ensured, and the reliability of the packaging structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a semiconductor packaging structure and a method for forming the same. Background Art

[0002] In order to achieve better performance, maintain smaller size and lower power consumption, the existing packaging technology has developed from the early 2D packaging towards 2.5D packaging and 3D packaging.

[0003] Embedded BridgeDie technology is also increasingly used in 2.5D packaging and 3D packaging.

[0004] In the existing packaging structure with an embedded bridge chip, the micro-bumps on the bridge chip and the micro-pads on the interposer located below the bridge chip are generally fixed by welding with solder (such as solder). In this fixing method, due to the presence of multiple thermal curing steps during the packaging process, defects such as voids and / or cracks are easily generated at the welding points between the micro-bumps on the bridge chip and the micro-pads on the interposer, which reduces the connection strength at the welding points and affects the reliability of the packaging structure. Summary of the invention

[0005] The technical problem to be solved by the present application is to provide a semiconductor packaging structure and a method for forming the same, so as to improve the connection strength between the bridge chip and the wiring layer connection point and improve the reliability of the packaging structure.

[0006] To this end, the present application provides, on one hand, a method for forming a semiconductor packaging structure, comprising:

[0007] A bridge chip is provided, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; an upper insulating layer covering the first metal column and the front side of the substrate; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; a lower insulating layer covering the second metal column and the back side of the substrate;

[0008] Providing a first carrier board, and bonding the upper insulating layer of the bridge chip to the upper surface of the first carrier board;

[0009] forming a first plastic packaging layer covering the upper surface of the first carrier board and the bridge chip;

[0010] Thinning a side of the first plastic encapsulation layer away from the first carrier to expose a side surface of the second metal column away from the back side of the substrate;

[0011] forming a first redistribution layer on the surface of the thinned first plastic encapsulation layer, the first redistribution layer being electrically connected to the second metal pillar, and a process for forming the first redistribution layer comprising an electroplating process;

[0012] Providing a second carrier board, and bonding the first redistribution layer to a surface of the second carrier board;

[0013] The first carrier is removed to expose the upper insulating layer; a side of the first plastic encapsulation layer away from the second carrier is thinned to expose a surface of the first metal column away from the front surface of the substrate; a second redistribution layer is formed on the surface of the thinned first plastic encapsulation layer, the second redistribution layer is electrically connected to the first metal column, and the process of forming the second redistribution layer includes an electroplating process;

[0014] Providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the second redistribution layer, wherein the semiconductor chip is electrically connected to the second redistribution layer;

[0015] A second plastic encapsulation layer is formed to cover the upper surface of the second redistribution layer and the semiconductor chip.

[0016] In an optional embodiment, the method further includes: removing the second carrier board to expose the first redistribution layer; and forming a welding protrusion electrically connected to the first redistribution layer on the lower surface of the first redistribution layer.

[0017] In an optional embodiment, the first redistribution layer includes a first organic dielectric layer and a first metal circuit layer located in the first organic dielectric layer; the first organic dielectric layer is a single-layer or multi-layer stacking structure, and the corresponding first metal circuit layer is a single-layer or multi-layer stacking structure; the first redistribution layer is electrically connected to the second metal column, including: the first metal circuit layer is electrically connected to the second metal column.

[0018] In an optional embodiment, when the first organic dielectric layer and the first metal circuit layer are both one layer, the formation process of the first redistribution layer includes: forming a first organic dielectric layer on the surface of the thinned first plastic sealing layer and the lower insulating layer by a coating process; performing an exposure process, a development process and a thermal curing process on the first organic dielectric layer formed by coating, and forming a first opening in the first organic dielectric layer to expose the surface of one end of the second metal column; forming a seed layer on the upper surface of the first organic dielectric layer and the side wall and bottom surface of the first opening; forming a photoresist layer on the upper surface of the seed layer; patterning the photoresist layer to form a second opening in the photoresist layer to expose the seed layer in the first opening and a portion of the upper surface of the seed layer outside the first opening; forming a first metal circuit layer in the second opening by an electroplating process; and removing the photoresist layer.

[0019] In an optional embodiment, the second redistribution layer includes a second organic dielectric layer and a second metal circuit layer located in the second organic dielectric layer; the second organic dielectric layer is a single-layer or multi-layer stacking structure, and the corresponding second metal circuit layer is a single-layer or multi-layer stacking structure; the second redistribution layer also includes a micro-pad located on the upper surface of the second organic dielectric layer on the top layer and electrically connected to the second metal circuit layer.

[0020] In an optional embodiment, the semiconductor chip is mounted on the upper surface of the second redistribution layer, and the electrical connection between the semiconductor chip and the second redistribution layer includes: the micro-bumps on the semiconductor chip are welded together with the micro-pads; the electrical connection between the second redistribution layer and the first metal column includes: the second metal circuit layer is electrically connected to the first metal column.

[0021] In an optional embodiment, it also includes: before forming the first plastic encapsulation layer, a columnar connection structure is formed on the upper surface of the first carrier on one side or multiple sides of the bridge chip; the first plastic encapsulation layer also covers the columnar connection structure; the first redistribution layer and the second redistribution layer are also electrically connected to the columnar connection structure.

[0022] In an optional embodiment, the front surface of the substrate of the bridge chip also has a redistribution layer, and the redistribution layer serves as a part of the substrate; the pad is located on the upper surface of the redistribution layer and is electrically connected to the redistribution layer; and the through-hole connection structure is electrically connected to the redistribution layer.

[0023] In an optional embodiment, the redistribution layer includes a passivation layer and a metal circuit layer located in the passivation layer; the passivation layer is a single-layer or multi-layer stacking structure, and the corresponding metal circuit layer is a single-layer or multi-layer stacking structure; the pad is electrically connected to the metal circuit layer.

[0024] In an optional embodiment, a deep trench capacitor is further formed in the substrate of the bridge chip, and the deep trench capacitor is electrically connected to the redistribution layer.

[0025] In an optional embodiment, the formation process of the bridge chip includes: providing a substrate; forming a through-hole connection structure and a deep trench capacitor in the substrate; forming a redistribution layer on the front side of the substrate; forming a solder pad on the upper surface of the redistribution layer; forming a raised first metal column on the upper surface of the solder pad; forming an upper insulating layer covering the first metal column and the front side of the substrate; thinning the back side of the substrate to expose one end surface of the through-hole connection structure; forming a raised second metal column on the exposed surface of the through-hole connection structure; forming a lower insulating layer covering the second metal column and the back side of the substrate; and cutting the substrate to form a plurality of discrete bridge chips.

[0026] On the other hand, the present application also provides a method for forming a semiconductor package structure, comprising:

[0027] A bridge chip is provided, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; and a lower insulating layer covering the second metal column and the back side of the substrate;

[0028] Providing a carrier board, and bonding the lower insulating layer of the bridge chip to the upper surface of the carrier board;

[0029] Forming a first plastic packaging layer covering the upper surface of the carrier board and the bridge chip and filling between the first metal pillars;

[0030] Thinning a side of the first plastic encapsulation layer away from the carrier to expose a surface of an end of the first metal column away from the front side of the substrate;

[0031] forming an upper redistribution layer on the surface of the thinned first plastic encapsulation layer, wherein the upper redistribution layer is electrically connected to the first metal column, and a process for forming the upper redistribution layer includes an electroplating process;

[0032] Providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the upper redistribution layer, wherein the semiconductor chip is electrically connected to the upper redistribution layer;

[0033] forming a second plastic encapsulation layer covering the upper surface of the upper redistribution layer and the semiconductor chip;

[0034] removing the carrier to expose the lower insulating layer;

[0035] A welding protrusion electrically connected to the second metal pillar is formed on the lower insulating layer.

[0036] On the other hand, the present application also provides a method for forming a semiconductor package structure, comprising:

[0037] A bridge chip is provided, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; an upper insulating layer covering the first metal column and the front side of the substrate; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; a lower insulating layer covering the second metal column and the back side of the substrate;

[0038] Providing a first carrier board, and bonding the lower insulating layer of the bridge chip to the upper surface of the first carrier board;

[0039] forming a first plastic packaging layer covering the upper surface of the first carrier board and the bridge chip;

[0040] Thinning the surface of the first plastic encapsulation layer away from the first carrier to expose an end surface of the first metal column away from the front surface of the substrate;

[0041] Forming a first redistribution layer on the surfaces of the first plastic encapsulation layer and the lower insulating layer after thinning, wherein the first redistribution layer is electrically connected to the first metal pillar, and the process of forming the first redistribution layer includes an electroplating process;

[0042] Providing a second carrier board, and bonding the first redistribution layer to a surface of the second carrier board;

[0043] The first carrier is removed to expose the lower insulating layer; the surface of the first plastic encapsulation layer away from the second carrier is thinned to expose the end surface of the second metal column away from the back side of the substrate;

[0044] Forming a second redistribution layer on the surfaces of the thinned upper insulating layer and the first plastic encapsulation layer, wherein the second redistribution layer is electrically connected to the second metal pillar, and a process for forming the second redistribution layer includes an electroplating process;

[0045] Providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the second redistribution layer, wherein the semiconductor chip is electrically connected to the second redistribution layer;

[0046] forming a second plastic encapsulation layer covering the upper surface of the second redistribution layer and the semiconductor chip;

[0047] The second carrier board is removed, and a welding protrusion electrically connected to the first redistribution layer is formed on the lower surface of the first redistribution layer.

[0048] On the other hand, the present application also provides a semiconductor packaging structure, including:

[0049] A bridge chip, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; an upper insulating layer covering the first metal column and the front side of the substrate, the upper surface of the upper insulating layer exposing an end surface of the first metal column away from the front side of the substrate; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; a lower insulating layer covering the second metal column and the back side of the substrate, the lower surface of the lower insulating layer exposing an end surface of the second metal column away from the back side of the substrate;

[0050] A first plastic encapsulation layer covering the bridge chip, wherein the upper surface of the first plastic encapsulation layer exposes the upper surface of the upper insulating layer and an end surface of the first metal column away from the front surface of the substrate, and the lower surface of the first plastic encapsulation layer exposes the lower surface of the lower insulating layer and an end surface of the second metal column away from the back surface of the substrate;

[0051] A first redistribution layer located on the lower surfaces of the first plastic encapsulation layer and the lower insulating layer, the first redistribution layer being electrically connected to the second metal pillar;

[0052] A second redistribution layer located on the upper surfaces of the first plastic encapsulation layer and the upper insulating layer, the second redistribution layer being electrically connected to the first metal column;

[0053] A semiconductor chip, wherein the semiconductor chip is mounted on the upper surface of the second redistribution layer, and the semiconductor chip is electrically connected to the second redistribution layer;

[0054] A second plastic packaging layer covers the upper surface of the second redistribution layer and the semiconductor chip.

[0055] In an optional embodiment, the first metal pillar and the second metal pillar have the same height.

[0056] In an optional embodiment, the first redistribution layer includes a first organic dielectric layer and a first metal circuit layer located in the first organic dielectric layer; the first organic dielectric layer is a single-layer or multi-layer stacking structure, and the corresponding first metal circuit layer is a single-layer or multi-layer stacking structure; the first redistribution layer is electrically connected to the second metal column, including: the first metal circuit layer is electrically connected to the second metal column.

[0057] In an optional embodiment, the second redistribution layer includes a second organic dielectric layer and a second metal circuit layer located in the second organic dielectric layer; the second organic dielectric layer is a single-layer or multi-layer stacking structure, and the corresponding second metal circuit layer is a single-layer or multi-layer stacking structure; the second redistribution layer also includes a micro-pad located on the upper surface of the second organic dielectric layer on the top layer and electrically connected to the second metal circuit layer.

[0058] In an optional embodiment, the semiconductor chip is mounted on the upper surface of the second redistribution layer, and the electrical connection between the semiconductor chip and the second redistribution layer includes: the micro-bumps on the semiconductor chip are welded together with the micro-pads; the electrical connection between the second redistribution layer and the first metal column includes: the second metal circuit layer is electrically connected to the first metal column.

[0059] In an optional embodiment, it also includes: a columnar connection structure located on one side or multiple sides of the bridge chip; the first plastic encapsulation layer also covers the columnar connection structure; the first redistribution layer and the second redistribution layer are also electrically connected to the columnar connection structure.

[0060] In an optional embodiment, the front surface of the substrate of the bridge chip also has a redistribution layer, and the redistribution layer serves as a part of the substrate; the pad is located on the upper surface of the redistribution layer and is electrically connected to the redistribution layer; and the through-hole connection structure is electrically connected to the redistribution layer.

[0061] In an optional embodiment, the redistribution layer includes a passivation layer and a metal circuit layer located in the passivation layer; the passivation layer is a single-layer or multi-layer stacking structure, and the corresponding metal circuit layer is a single-layer or multi-layer stacking structure; the pad is electrically connected to the metal circuit layer.

[0062] In an optional embodiment, a deep trench capacitor is further formed in the substrate of the bridge chip, and the deep trench capacitor is electrically connected to the redistribution layer.

[0063] In an optional embodiment, an underfill layer is further filled between the semiconductor chip and the upper surface of the second redistribution layer.

[0064] In an optional embodiment, the upper insulating layer and the lower insulating layer are made of the same material.

[0065] In an optional embodiment, the material of the upper insulating layer and the lower insulating layer is a plastic packaging material or an organic insulating dielectric material.

[0066] On the other hand, the present application also provides a semiconductor packaging structure, including:

[0067] A bridge chip, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; and a lower insulating layer covering the second metal column and the back side of the substrate;

[0068] A first plastic encapsulation layer covering the bridge chip and filling between the first metal pillars, wherein the upper surface of the first plastic encapsulation layer exposes one end surface of the first metal pillar away from the front surface of the substrate, and the lower surface of the first plastic encapsulation layer exposes one end surface of the second metal pillar away from the back surface of the substrate;

[0069] An upper redistribution layer located on the upper surface of the first plastic encapsulation layer, the upper redistribution layer being electrically connected to the first metal column;

[0070] A semiconductor chip, wherein the semiconductor chip is mounted on the upper surface of the upper redistribution layer, and the semiconductor chip is electrically connected to the upper redistribution layer;

[0071] A second plastic packaging layer covering the upper surface of the upper redistribution layer and the semiconductor chip;

[0072] A welding protrusion is located on the lower insulating layer and is electrically connected to the second metal column.

[0073] On the other hand, the present application also provides a semiconductor packaging structure, including:

[0074] A bridge chip, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; an upper insulating layer covering the first metal column and the front side of the substrate; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; a lower insulating layer covering the second metal column and the back side of the substrate;

[0075] A first plastic packaging layer covering the bridge chip, wherein the upper surface of the first plastic packaging layer exposes one end surface of the second metal column away from the back surface of the substrate, and the lower surface of the first plastic packaging layer exposes one end surface of the first metal column away from the front surface of the substrate;

[0076] A first redistribution layer located on the lower surfaces of the first plastic encapsulation layer and the upper insulating layer, the first redistribution layer being electrically connected to the first metal column;

[0077] A second redistribution layer located on the upper surfaces of the upper insulating layer and the first plastic encapsulation layer, wherein the second redistribution layer is electrically connected to the second metal pillar;

[0078] A semiconductor chip, wherein the semiconductor chip is mounted on the upper surface of the second redistribution layer, and the semiconductor chip is electrically connected to the second redistribution layer;

[0079] A second plastic packaging layer covering the upper surface of the second redistribution layer and the semiconductor chip;

[0080] A welding protrusion is located on the lower surface of the first redistribution layer and is electrically connected to the first redistribution layer.

[0081] Compared with the prior art, the advantages of the technical solution of this application are:

[0082] The semiconductor packaging structure and its forming method in the aforementioned embodiments of the present application, in one embodiment, provide a first carrier board, after bonding the upper insulating layer of the bridge chip to the upper surface of the first carrier board, form a first plastic sealing layer covering the upper surface of the first carrier board and the bridge chip; thin the first plastic sealing layer and the lower insulating layer to expose the end surface of the second metal column away from the back of the substrate; form a first redistribution layer on the surface of the thinned first plastic sealing layer and the lower insulating layer, the first redistribution layer is electrically connected to the second metal column, and the process of forming the first redistribution layer includes an electroplating process; provide a second carrier board, bond the first redistribution layer On the upper surface of the second carrier; remove the first carrier to expose the upper insulating layer; thin the upper insulating layer and the first plastic layer to expose the end surface of the first metal column away from the front side of the substrate; form a second redistribution layer on the surface of the thinned upper insulating layer and the first plastic layer, the second redistribution layer is electrically connected to the first metal column, and the process of forming the second redistribution layer includes an electroplating process; provide a semiconductor chip, and mount the semiconductor chip on the upper surface of the second redistribution layer, the semiconductor chip is electrically connected to the second redistribution layer; form a second plastic layer covering the upper surface of the second redistribution layer and the semiconductor chip. The front and back connection terminals of the bridge chip described in the present application are respectively the first metal column and the second metal column, the connection between the first metal column and the second metal wiring layer formed by the electroplating process in the second redistribution layer, and the connection between the second metal column and the first metal wiring layer formed by the electroplating process in the first redistribution layer. Compared with the connection method of solder (such as solder), the connection strength at the connection point can be guaranteed (will not be affected by the curing process), and there will be no defects such as voids and / or cracks, thereby improving the reliability of the packaging structure. The upper insulating layer and the lower insulating layer protect the bridge chip from crack defects in the subsequent packaging process, and the front and back of the bridge chip are symmetrical structures (the front is the first metal column and the upper insulating layer, and the back is the second metal column and the lower insulating layer), so that the stress on the front and back of the bridge chip can be balanced, preventing the bridge chip from warping or deformation, and further ensuring the connection strength at the connection points of the first metal column and the second metal column on the front and back of the bridge chip and the corresponding metal wiring layer, thereby further improving the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 , Figure 8-Figure 15 This is a structural schematic diagram of a formation process of a semiconductor packaging structure in one embodiment of the present application;

[0084] Figure 2-Figure 7 It is a structural schematic diagram of the formation process of the bridge chip in one embodiment of the present application;

[0085] Fig.16 A structural schematic diagram of a formation process of a semiconductor packaging structure in another embodiment of the present application;

[0086] Fig.17 It is a structural schematic diagram of the formation process of a semiconductor packaging structure in another embodiment of the present application. DETAILED DESCRIPTION

[0087] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0088] On one hand, the present application provides a method for forming a semiconductor packaging structure. The formation process of the semiconductor packaging structure is described in detail below with reference to the accompanying drawings.

[0089] refer to Figure 1 , providing a bridge chip 100, the bridge chip 100 includes a substrate 101, the substrate 101 includes a front side and a back side opposite to each other, the front side of the substrate 101 has a pad 113, the substrate 101 has a through-hole connection structure 110, and the back side of the substrate 101 exposes one end surface of the through-hole connection structure 110; the bridge chip 100 also includes: a first metal column 105 protruding from the front side of the substrate 101 and electrically connected to the corresponding pad 113; an upper insulating layer 106 covering the first metal column 105 and the front side of the substrate 101; a second metal column 108 protruding from the back side of the substrate 101 and electrically connected to the corresponding through-hole connection structure 110; and a lower insulating layer 109 covering the second metal column 108 and the back side of the substrate 101.

[0090] The substrate 101 is the main body of the bridge chip 100. In one embodiment, the material of the substrate 101 is silicon (Si). In other embodiments, the material of the substrate 101 may also be germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide.

[0091] In one embodiment, the front surface of the substrate 101 of the bridge chip 100 also has a redistribution layer 102, and the redistribution layer 102 serves as a part of the substrate 101; the pad 113 is located on the upper surface of the redistribution layer 102 and is electrically connected to the redistribution layer 102; the through-hole connection structure 110 is electrically connected to the redistribution layer 102.

[0092] In one embodiment, the redistribution layer 102 includes a passivation layer 104 and a metal circuit layer 103 located in the passivation layer 104; the passivation layer 104 may be a single-layer or multi-layer stacked structure, and the corresponding metal circuit layer 103 may also be a single-layer or multi-layer stacked structure; the pad 113 is electrically connected to the metal circuit layer 103. When the passivation layer 104 and the metal circuit layer 103 are both multi-layer stacked structures, one layer of the metal circuit layer is correspondingly formed in one layer of the passivation layer 104. In a specific embodiment, the material of the passivation layer 104 is one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the material of the metal circuit layer 103 is one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0093] In one embodiment, a deep trench capacitor 111 is formed in the substrate 101 of the bridge chip 100, and the deep trench capacitor 111 is electrically connected to the redistribution layer 102, and the deep trench capacitor 111 can be used for decoupling and voltage stabilization. In other embodiments, other functional chips are formed in the substrate 101 of the bridge chip 100, which can play a role in power management and protecting the battery from damage such as overcharging, overdischarging, and overcurrent.

[0094] The bridge chip 100 also includes: a first metal column 105 protruding from the front side of the substrate 101 and electrically connected to the corresponding pad 113; an upper insulating layer 106 covering the first metal column 105 and the front side of the substrate 101; a second metal column 108 protruding from the back side of the substrate 101 and electrically connected to the corresponding through-hole connection structure 110; and a lower insulating layer 109 covering the second metal column 108 and the back side of the substrate 101. The front and back sides of the bridge chip 100 are connected to the outside by the first metal pillar 105 and the second metal pillar 108 respectively. The first metal pillar 105 and the second metal pillar 108 have the same height. The first metal pillar 105 is subsequently connected to the second metal circuit layer formed by the electroplating process in the second redistribution layer, and the second metal pillar 108 is subsequently connected to the first metal circuit layer formed by the electroplating process in the first redistribution layer. Compared with the connection method of solder (such as solder), the direct connection between the metal pillar and the metal wiring can ensure the connection strength at the connection point (will not be affected by the curing process), and will not have defects such as voids and / or cracks, thereby improving the reliability of the packaging structure. The upper insulating layer 106 and the lower insulating layer 109 protect the bridge chip 100 from crack defects during the subsequent packaging process, and the front and back sides of the bridge chip 100 are symmetrical structures (the front side is the first metal column 105 and the upper insulating layer 106, and the back side is the second metal column 108 and the lower insulating layer 109), so that the stress on the front and back sides of the bridge chip 100 can be balanced, preventing the bridge chip 100 from warping or deformation, and further ensuring the connection strength at the connection points of the first metal column 105 and the second metal column 108 on the front and back sides of the bridge chip 100 and the corresponding metal circuit layers, thereby further improving the reliability of the packaging structure.

[0095] In one embodiment, continue to refer to Figure 1, the upper insulating layer 106 exposes the end surface of the first metal pillar 105 away from the front surface of the substrate 101, and the upper surface of the upper insulating layer 106 is flush with the exposed surface of the first metal pillar 105, and the lower insulating layer 109 exposes the end surface of the second metal pillar 108 away from the back surface of the substrate 101, and the lower surface of the lower insulating layer 109 is flush with the end surface of the first metal pillar 105. In other embodiments, the upper insulating layer 106 can also cover the end surface of the first metal pillar 105 away from the front surface of the substrate 101, and the lower insulating layer 109 can also cover the end surface of the second metal pillar 108 away from the back surface of the substrate 101. When the first plastic encapsulation layer is subsequently thinned, the upper insulating layer 106 or the lower insulating layer 109 can be thinned at the same time to expose the end surface of the first metal pillar 105 away from the front surface of the substrate 101, or to expose the end surface of the second metal pillar 108 away from the back surface of the substrate 101.

[0096] In one embodiment, the material of the first metal pillar 105 and the second metal pillar 108 is one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, Tin, TaN, Ta, TaC, W, and WN. The upper insulating layer 106 and the lower insulating layer 109 are made of the same material, which can be a molding compound or an organic insulating dielectric material. The molding compound is an epoxy resin or a resin of other materials, which has a smaller thermal expansion coefficient and is more conducive to the warpage management of the bridge chip. The organic insulating dielectric material can be a polymer layer made of polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO), or other suitable polymer dielectric materials; the organic insulating dielectric material can also be an epoxy adhesive material (such as a die attach film (DAF) or a non-conductive film (NCF)).

[0097] In one embodiment, a die attach film (DAF) 112 may be attached to the surface of the lower insulating layer 109 away from the back of the substrate 101 to facilitate subsequent bonding of the bridge chip 100 to the first carrier.

[0098] In one embodiment, the formation process of the bridge chip 100 includes: referring to Figure 2, providing a substrate 101, the substrate comprising a plurality of chip regions and a cutting region between the chip regions, and subsequently forming the same structure on each chip region; forming a through-hole connection structure 110 and a deep trench capacitor 111 in the substrate 101; forming a redistribution layer 102 on the front surface of the substrate 101, the redistribution layer 102 comprising a passivation layer 104 and a metal wiring layer 103 located in the passivation layer 104; forming a pad 113 on the upper surface of the redistribution layer 102, the pad 113 being electrically connected to the metal wiring layer 103; referring to Figure 3 , forming a raised first metal column 105 on the upper surface of the pad 113, wherein the process for forming the first metal column 105 includes an electroplating process; forming an upper insulating layer 106 covering the first metal column 105 and the front surface of the substrate 101, wherein the upper insulating layer 106 may be formed by spin coating, injection molding, compression molding or transfer molding; referring to Figure 4 , bonding the upper surface of the upper insulating layer 106 to the surface of a carrier 120, the bonding can be performed through a temporary bonding layer, and the carrier 120 can be a glass carrier; Figure 5 , thinning and etching the back side of the substrate 101 to expose one end surface of the through-hole connection structure 110, wherein the thinning and etching process includes first thinning the substrate 101 to a certain height, then performing a chemical mechanical polishing process to remove part of the substrate, and then performing an etching process to continue removing part of the substrate until one end surface of the through-hole connection structure 110 is exposed, and one end surface of the through-hole connection structure 110 is higher than the surface of the substrate 101; forming a second passivation layer 107 of a certain thickness on the back side of the etched substrate 101, performing a chemical mechanical polishing process to remove a part of the protruding through-hole connection structure 110, the surface of the second passivation layer 107 is flush with the exposed end surface of the through-hole connection structure 110, and the material of the second passivation layer 107 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride; refer to Figure 6 , forming a raised second metal column 108 on the exposed surface of the through-hole connection structure 110, the formation process of the second metal column 108 includes an electroplating process, and the diameter of the second metal column 108 is larger than the diameter of the through-hole connection structure 110, which can not only improve the connection quality between the second metal column and the through-hole connection structure, but also facilitate the heat dissipation during the subsequent operation of the bridge chip; forming a lower insulating layer 109 covering the second metal column 108 and the back side of the substrate 101, and the formation of the lower insulating layer 109 can be achieved by spin coating, injection molding, compression molding or transfer molding; reference Figure 7The substrate 101 is cut along the cutting area to form a plurality of discrete bridge chips 100. The manufacturing efficiency of the bridge chip 100 is improved by adopting the semiconductor integrated manufacturing process.

[0099] refer to Figure 8 , providing a first carrier board 210 , and bonding the upper insulating layer 106 of the bridge chip 100 to the upper surface of the first carrier board 210 .

[0100] The first carrier board 210 supports and protects the bridge chip 100 in the subsequent packaging process. In one embodiment, the first carrier board 210 is a glass carrier board.

[0101] In one embodiment, the upper insulating layer 106 of the bridge chip 100 is bonded to the upper surface of the first carrier 210 through a temporary bonding layer 211. The temporary bonding layer 211 can be a temporary bonding glue and a multi-layer metal layer structure such as Al / Ti / Cu.

[0102] In one embodiment, the first carrier 210 may have a plurality of packaging areas, and the same structure is subsequently formed on each packaging area. For example, when the bridge chip 100 is bonded to the upper surface of the first carrier 210, the same bridge chip 100 is bonded to the upper surface of each packaging area of ​​the first carrier 210. The number of bridge chips 100 bonded to the upper surface of each packaging area of ​​the first carrier 210 is at least one.

[0103] In one embodiment, it further includes: before the first plastic encapsulation layer is subsequently formed, a columnar connection structure 200 is formed on the upper surface of the first carrier 210 on one or more sides of the bridge chip 100. The columnar connection structure 200 is used for electrical connection between the first redistribution layer and the second redistribution layer in the subsequently formed packaging structure. The material of the columnar connection structure 200 is metal, and the material of the columnar connection structure 200 can specifically be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, Tin, TaN, Ta, TaC, W, and WN, and the formation process of the columnar connection structure 200 includes electroplating.

[0104] refer to Fig. 9 , forming a first plastic packaging layer 201 covering the upper surface of the first carrier board 210 and the bridge chip 100 .

[0105] In one embodiment, the material of the first plastic encapsulation layer 201 can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin containing filler; or can also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol containing filler. In some embodiments, the filler can be an inorganic filler or an organic filler. In some embodiments, the process of forming the plastic encapsulation layer includes compression molding or transfer molding.

[0106] In one embodiment, the first plastic encapsulation layer 201 also covers the columnar connection structure 200 .

[0107] refer to Fig.10 , thinning the surface of the first plastic encapsulation layer 201 away from the first carrier board to expose the end surface of the second metal column 108 away from the back side of the substrate 101; forming a first redistribution layer 202 on the surface of the thinned first plastic encapsulation layer 201, the first redistribution layer 202 is electrically connected to the second metal column 108, and the process of forming the first redistribution layer 202 includes an electroplating process.

[0108] In one embodiment, when the lower insulating layer 109 in the bridge chip 100 exposes the end surface of the second metal pillar 108 away from the back side of the substrate 101, and the lower surface of the lower insulating layer 109 is flush with the end surface of the first metal pillar 105, after the surface of the first plastic encapsulation layer 201 away from the first carrier is thinned, the second metal pillar 108 and the surface of the lower insulating layer 109 away from the substrate 101 are exposed. In other embodiments, the lower insulating layer 109 may also cover the end surface of the second metal pillar 108 away from the back side of the substrate 101, and when the surface of the first plastic encapsulation layer 201 away from the first carrier is thinned, the surface of the lower insulating layer 109 away from the back side of the substrate 101 may be thinned at the same time to expose the end surface of the second metal pillar 108 away from the back side of the substrate 101.

[0109] In one embodiment, thinning the first plastic encapsulation layer 201 (and the lower insulating layer 109 ) includes a chemical mechanical polishing process.

[0110] In one embodiment, the first redistribution layer 202 is also electrically connected to the columnar connection structure 200 .

[0111] In one embodiment, the first redistribution layer 202 includes a first organic dielectric layer 203 and a first metal circuit layer 204 located in the first organic dielectric layer 203; the first organic dielectric layer 203 is a single-layer or multi-layer stacked structure, and the corresponding first metal circuit layer 204 is a single-layer or multi-layer stacked structure. When the first organic dielectric layer 203 and the first metal circuit layer 204 are both multi-layer stacked structures, each layer of the first organic dielectric layer 203 has a corresponding layer of the first metal circuit layer 204, and the upper first metal circuit layer 204 is electrically connected to the adjacent lower first metal circuit layer 204.

[0112] In a specific example, the material of the first organic dielectric layer 203 can be polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO), or a polymer layer made of other suitable polymer dielectric materials. The material of the first metal circuit layer 204 is one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0113] In one embodiment, when the first organic dielectric layer 203 and the first metal circuit layer 204 are both one layer, the formation process of the first redistribution layer 202 includes: forming the first organic dielectric layer 203 on the surfaces of the thinned first plastic encapsulation layer 201 and the lower insulating layer 109 by a coating process; performing an exposure process, a development process and a thermal curing process on the first organic dielectric layer 203 formed by coating, and forming a first opening in the first organic dielectric layer 203 to expose the surface of one end of the second metal column 108; forming a seed layer on the upper surface of the first organic dielectric layer 203 and the sidewall and bottom surface of the first opening; forming a photoresist layer on the upper surface of the seed layer; patterning the photoresist layer to form a second opening in the photoresist layer to expose the seed layer in the first opening and a portion of the upper surface of the seed layer outside the first opening; forming the first metal circuit layer 204 in the second opening by an electroplating process; and removing the photoresist layer. When both the first organic dielectric layer 203 and the first metal wiring layer 204 are multi-layer stacked structures, the aforementioned steps of forming the first organic dielectric layer 203 and the first metal wiring layer 204 are repeated. The first metal wiring layer 204 formed by the electroplating process in the first redistribution layer is connected to the second metal column 108. Compared with the connection method of solder (such as solder), the connection strength at the connection point can be guaranteed (will not be affected by the curing process), and defects such as voids and / or cracks will not occur, thereby improving the reliability of the packaging structure.

[0114] In one embodiment, the first redistribution layer 202 is electrically connected to the second metal pillar 108 , including: the first metal wiring layer 204 is electrically connected to the second metal pillar 108 .

[0115] In one embodiment, the first redistribution layer 202 has an opening exposing a portion of the surface of the first metal wiring layer 204 , so as to subsequently form a soldering protrusion electrically connected to the first redistribution layer 202 .

[0116] refer to Fig.11 , provide a second carrier 212 , and bond the first redistribution layer 202 to the upper surface of the second carrier 212 .

[0117] In one embodiment, the first redistribution layer 202 is bonded to the upper surface of the second carrier 212 via a temporary bonding layer 213. The temporary bonding layer 213 may be a combination of a temporary bonding adhesive, a metal barrier layer, and a peeling layer, or may be a pyrolytic bonding adhesive.

[0118] refer to Fig.12 , remove the first carrier 210 to expose the upper insulating layer 106 ; thin the first plastic layer 201 away from the second carrier 210 to expose the end surface of the first metal column 105 away from the front surface of the substrate 101 .

[0119] In one embodiment, when the upper insulating layer 106 in the bridge chip 100 exposes one end surface of the first metal pillar 105 away from the front surface of the substrate 101, and the upper surface of the upper insulating layer 106 is flush with the exposed surface of the first metal pillar 105, after thinning the surface of the first plastic encapsulation layer 201 away from the second carrier 210, the surfaces of the first metal pillar 105 and the upper insulating layer 106 away from the substrate 101 are exposed. In other embodiments, the upper insulating layer 106 may also cover one end surface of the first metal pillar 105 away from the front surface of the substrate 101, and when thinning the surface of the first plastic encapsulation layer 201 away from the second carrier 210, the surface of the upper insulating layer 106 away from the front surface of the substrate 101 may be thinned at the same time to expose one end surface of the first metal pillar 105 away from the front surface of the substrate 101.

[0120] Thinning the first plastic encapsulation layer 201 (and the upper insulating layer 106 ) includes a chemical mechanical polishing process.

[0121] In one embodiment, after eliminating or reducing the viscosity of the release layer in the temporary bonding layer 213 by laser or heating, the first carrier is removed, and then the metal barrier layer and the temporary bonding adhesive are removed.

[0122] In one embodiment, while the upper insulating layer 106 and the first plastic encapsulation layer 201 are thinned, the columnar connection structure 200 is also thinned.

[0123] refer to Fig.13 A second redistribution layer 205 is formed on the surface of the thinned first plastic encapsulation layer 201. The second redistribution layer 205 is electrically connected to the first metal column 105. The process of forming the second redistribution layer 205 includes an electroplating process.

[0124] In one embodiment, the second redistribution layer 205 includes a second organic dielectric layer 206 and a second metal circuit layer 207 located in the second organic dielectric layer 206; the second organic dielectric layer 206 is a single-layer or multi-layer stacking structure, and the corresponding second metal circuit layer 207 is a single-layer or multi-layer stacking structure; the second redistribution layer 205 also includes a micro pad 208 located on the upper surface of the second organic dielectric layer 206 and electrically connected to the second metal circuit layer 207. When the second organic dielectric layer 206 and the second metal circuit layer 207 are both multi-layer stacking structures, each layer of the second organic dielectric layer 206 has a corresponding layer of the second metal circuit layer 207, and the upper second metal circuit layer 207 is electrically connected to the adjacent lower second metal circuit layer 207.

[0125] In one embodiment, the second redistribution layer 205 is electrically connected to the first metal pillar 105 , including: the second metal line layer 207 is electrically connected to the first metal pillar 105 .

[0126] In a specific example, the material of the second organic dielectric layer 206 can be polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO), or a polymer layer made of other suitable polymer dielectric materials. The material of the second metal circuit layer 207 and the micro pad 208 is one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, and WN.

[0127] In one embodiment, when the second organic dielectric layer 206 and the second metal wiring layer 207 are both one layer, the formation process of the second redistribution layer 205 includes: forming the second organic dielectric layer 206 on the surface of the thinned upper insulating layer 106 and the first plastic encapsulation layer 201 by a coating process; performing an exposure process, a development process and a thermal curing process on the first organic dielectric layer 202 formed by coating, and forming a third opening in the first organic dielectric layer 202 to expose the surface of one end of the second metal column 108; forming a seed layer on the upper surface of the first organic dielectric layer 202 and the sidewall and bottom surface of the third opening; forming a photoresist layer on the upper surface of the seed layer; patterning the photoresist layer to form a fourth opening in the photoresist layer to expose the seed layer in the third opening and a portion of the upper surface of the seed layer outside the third opening; forming a second metal wiring layer 207 in the fourth opening by an electroplating process; and removing the photoresist layer. When the second organic dielectric layer 206 and the second metal wiring layer 207 are both multi-layer stacked structures, the aforementioned steps of forming the second organic dielectric layer 206 and the second metal wiring layer 207 are repeated. The second metal wiring layer 207 formed by the electroplating process in the second redistribution layer 205 is connected to the second metal column 108. Compared with the connection method of solder (such as solder), the connection strength at the connection point can be guaranteed (will not be affected by the curing process), and defects such as voids and / or cracks will not occur, thereby improving the reliability of the packaging structure.

[0128] In one embodiment, the second redistribution layer 205 is also electrically connected to the columnar connection structure 200. The second redistribution layer 205 is also electrically connected to the columnar connection structure 200 includes: the second metal line layer 207 is electrically connected to the columnar connection structure 200.

[0129] refer to Fig.14 , provide a semiconductor chip 300, mount the semiconductor chip 300 on the upper surface of the second redistribution layer 205, and electrically connect the semiconductor chip 300 to the second redistribution layer 205; form a second plastic encapsulation layer 304 covering the upper surface of the second redistribution layer 205 and the semiconductor chip 300.

[0130] The semiconductor chip 300 includes a back surface and an active surface relative to each other. An integrated circuit (not shown in the figure) (having a specific function) is formed in the semiconductor chip 300. The active surface has a plurality of micro-bumps 301, and the plurality of micro-bumps 301 are electrically connected to the integrated circuit. In one embodiment, the semiconductor chip 300 is mounted on the upper surface of the second redistribution layer 205. The electrical connection between the semiconductor chip 300 and the second redistribution layer 205 includes: the micro-bumps 301 on the semiconductor chip 300 are welded together with the micro-pads 208 through a solder layer 302. In a specific embodiment, the material of the micro-bumps 301 is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver, and the material of the solder layer 302 is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0131] The semiconductor chip 300 includes but is not limited to a signal processing semiconductor chip, a logic control semiconductor chip, a storage semiconductor chip, a sensor semiconductor chip, a power semiconductor chip or a radio frequency semiconductor chip according to different functions.

[0132] In one embodiment, the number of the mounted semiconductor chips 300 is one or more, and an underfill layer 303 is further filled between the semiconductor chip 300 and the upper surface of the second redistribution layer 205 .

[0133] In one embodiment, the material of the second plastic encapsulation layer 304 can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin containing filler; or can also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol containing filler. In some embodiments, the filler can be an inorganic filler or an organic filler. In some embodiments, the process of forming the plastic encapsulation layer includes compression molding or transfer molding.

[0134] In one embodiment, reference Fig.15 , further comprising: removing the second carrier board 212 to expose the first redistribution layer 202 ; and forming a welding protrusion 209 electrically connected to the first redistribution layer 202 on the lower surface of the first redistribution layer 202 .

[0135] In one embodiment, the bottom of the welding protrusion 209 also has a protruding metal layer. The material of the protruding metal layer is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver. The material of the welding protrusion 209 is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0136] In one embodiment, after forming the welding protrusion 209 , the method further includes: thinning the second plastic encapsulation layer 304 to expose the back side of the semiconductor chip 300 .

[0137] In another embodiment of the present application, a method for forming a semiconductor packaging structure is further provided (the difference between this embodiment and the aforementioned embodiment is that: an upper insulating layer covering the first metal pillar is not formed on the front side of the bridge chip, the space between the first metal pillars is filled with the first plastic sealing layer during the process, and a redistribution layer is not formed on the back side of the packaging structure. The second metal pillar is directly electrically connected to the welding protrusion. In addition to the advantages of the aforementioned embodiment, this embodiment can also save the process time of the bridge chip). For details, refer to Fig.16 ,include:

[0138] A bridge chip 100 is provided, wherein the bridge chip 100 includes a substrate 101, wherein the substrate 101 includes a front side and a back side opposite to each other, wherein the front side of the substrate 101 has a pad 113, wherein the substrate 101 has a through-hole connection structure 110, and the back side of the substrate 101 exposes one end surface of the through-hole connection structure 110; the bridge chip 100 further includes: a first metal column 105 protruding from the front side of the substrate 101 and electrically connected to the corresponding pad 113; a second metal column 108 protruding from the back side of the substrate 101 and electrically connected to the corresponding through-hole connection structure 110; and a lower insulating layer 109 covering the second metal column 108 and the back side of the substrate 101;

[0139] Providing a carrier board (not shown in the figure), and bonding the lower insulating layer 109 of the bridge chip to the upper surface of the carrier board;

[0140] Forming a first plastic encapsulation layer 201 covering the upper surface of the carrier and the bridge chip 100 and filling between the first metal pillars 105;

[0141] The first plastic encapsulation layer 201 is thinned at a side away from the carrier to expose a surface of the first metal column 105 at an end away from the front surface of the substrate 101;

[0142] An upper redistribution layer 215 is formed on the surface of the thinned first plastic encapsulation layer 201, wherein the upper redistribution layer 215 is electrically connected to the first metal pillar 105, and the process of forming the upper redistribution layer 215 includes an electroplating process;

[0143] Providing a semiconductor chip 300, mounting the semiconductor chip 300 on the upper surface of the upper redistribution layer 215, wherein the semiconductor chip 300 is electrically connected to the upper redistribution layer 215;

[0144] Forming a second plastic encapsulation layer 304 covering the upper surface of the upper redistribution layer 215 and the semiconductor chip 300;

[0145] removing the carrier to expose the lower insulating layer 109;

[0146] A welding protrusion 209 electrically connected to the second metal pillar 108 is formed on the lower insulating layer 109 .

[0147] In one embodiment, the front surface of the substrate 101 of the bridge chip 100 further comprises a redistribution layer 102, and the redistribution layer 102 is a part of the substrate 101; the pad 113 is located on the upper surface of the redistribution layer 102 and is electrically connected to the redistribution layer 102; the through-hole connection structure 110 is electrically connected to the redistribution layer 102. In one embodiment, the redistribution layer 102 comprises a passivation layer 104 and a metal circuit layer 103 located in the passivation layer 104; the passivation layer 104 may be a single-layer or multi-layer stacked structure, and the corresponding metal circuit layer 103 may also be a single-layer or multi-layer stacked structure; the pad 113 is electrically connected to the metal circuit layer 103.

[0148] The structure of the upper redistribution layer 215 is substantially the same as that of the second redistribution layer in the aforementioned embodiment. In a specific embodiment, the upper redistribution layer 215 includes a third organic dielectric layer 216 and a third metal wiring layer 217 located in the third organic dielectric layer 216; the third organic dielectric layer 216 is a single-layer or multi-layer stacking structure, and the corresponding third metal wiring layer 217 is a single-layer or multi-layer stacking structure. When the third organic dielectric layer 216 and the third metal wiring layer 217 are both multi-layer stacking structures, each layer of the third organic dielectric layer 216 has a corresponding layer of the third metal wiring layer 217, and the upper third metal wiring layer 217 is electrically connected to the adjacent lower third metal wiring layer 217.

[0149] In one embodiment, before forming a welding protrusion 209 electrically connected to the second metal pillar 108 on the lower insulating layer 109, a lower organic dielectric layer 213 may be formed on the surface of the lower insulating layer 109, wherein the lower organic dielectric layer 213 has an opening exposing the surface of the second metal pillar 108; a protruding metal layer is formed in the opening; and the welding protrusion 209 is formed on the protruding metal layer.

[0150] On the other hand, the present application also provides a semiconductor packaging structure, referring to Fig.15 ,include:

[0151] The bridge chip 100 includes a substrate 101, the substrate 101 includes a front side and a back side opposite to each other, the front side of the substrate 101 has a pad 113, the substrate 101 has a through-hole connection structure 110, and the back side of the substrate 101 exposes one end surface of the through-hole connection structure 110; the bridge chip 100 also includes: a first metal column 105 protruding from the front side of the substrate 101 and electrically connected to the corresponding pad 113; a first metal column 105 covering the first metal column 105 and the substrate an upper insulating layer 106 on the front side of the substrate 101, wherein the upper surface of the upper insulating layer 106 exposes one end surface of the first metal pillar 105 away from the front side of the substrate 101; a second metal pillar 108 protruding from the back side of the substrate 101 and electrically connected to the corresponding through-hole connection structure 110; and a lower insulating layer 109 covering the second metal pillar 108 and the back side of the substrate 101, wherein the lower surface of the lower insulating layer 109 exposes one end surface of the second metal pillar 108 away from the back side of the substrate 101;

[0152] A first plastic encapsulation layer 201 covering the bridge chip 100, wherein the upper surface of the first plastic encapsulation layer 201 exposes the upper surface of the upper insulating layer 106 and one end surface of the first metal column 105 away from the front surface of the substrate 101, and the lower surface of the first plastic encapsulation layer 201 exposes the lower surface of the lower insulating layer 109 and one end surface of the second metal column 108 away from the back surface of the substrate 101;

[0153] A first redistribution layer 202 located on the lower surfaces of the first plastic encapsulation layer 201 and the lower insulating layer 109, wherein the first redistribution layer 202 is electrically connected to the second metal pillar 108;

[0154] A second redistribution layer 205 located on the upper surfaces of the first plastic encapsulation layer 201 and the upper insulating layer 106, wherein the second redistribution layer 205 is electrically connected to the first metal pillar 105;

[0155] A semiconductor chip 300, wherein the semiconductor chip 300 is mounted on the upper surface of the second redistribution layer 205, and the semiconductor chip 300 is electrically connected to the second redistribution layer 205;

[0156] A second plastic packaging layer 304 covers the upper surface of the second redistribution layer 205 and the semiconductor chip 300 .

[0157] In one embodiment, the first redistribution layer 202 includes a first organic dielectric layer 203 and a first metal circuit layer 204 located in the first organic dielectric layer 203; the first organic dielectric layer 203 is a single-layer or multi-layer stacking structure, and the corresponding first metal circuit layer 204 is a single-layer or multi-layer stacking structure; the first redistribution layer 202 is electrically connected to the second metal column 108, including: the first metal circuit layer 204 is electrically connected to the second metal column 108.

[0158] In one embodiment, the second redistribution layer 205 includes a second organic dielectric layer 206 and a second metal circuit layer 207 located in the second organic dielectric layer 206; the second organic dielectric layer 206 is a single-layer or multi-layer stacking structure, and the corresponding second metal circuit layer 207 is a single-layer or multi-layer stacking structure; the second redistribution layer 205 also includes a micro pad 208 located on the upper surface of the second organic dielectric layer 206 and electrically connected to the second metal circuit layer 207.

[0159] In one embodiment, the semiconductor chip 300 is mounted on the upper surface of the second redistribution layer 205, and the electrical connection between the semiconductor chip 300 and the second redistribution layer 205 includes: the micro-bumps 301 on the semiconductor chip 300 are welded together with the micro-pads 208 through the solder layer 302; the electrical connection between the second redistribution layer 205 and the first metal column 105 includes: the second metal circuit layer 207 is electrically connected to the first metal column 105.

[0160] In one embodiment, it also includes: a columnar connection structure 200 located on one side or multiple sides of the bridge chip 100; the first plastic encapsulation layer 201 also covers the columnar connection structure 200; the first redistribution layer 202 and the second redistribution layer 205 are also electrically connected to the columnar connection structure 200.

[0161] In one embodiment, the front surface of the substrate 101 of the bridge chip 100 also has a redistribution layer 102, and the redistribution layer 102 serves as a part of the substrate 101; the pad 113 is located on the upper surface of the redistribution layer 102 and is electrically connected to the redistribution layer 102; the through-hole connection structure 10 is electrically connected to the redistribution layer 102.

[0162] In one embodiment, the redistribution layer 102 includes a passivation layer 104 and a metal circuit layer 103 located in the passivation layer 104; the passivation layer 104 is a single-layer or multi-layer stacking structure, and the corresponding metal circuit layer 103 is a single-layer or multi-layer stacking structure; the pad 113 is electrically connected to the metal circuit layer 103.

[0163] In one embodiment, a deep trench capacitor 111 is further formed in the substrate 101 of the bridge chip 100 , and the deep trench capacitor 111 is electrically connected to the redistribution layer 102 .

[0164] In one embodiment, the material of the upper insulating layer 106 and the lower insulating layer 109 is a molding compound or an organic insulating dielectric material.

[0165] Another embodiment of the present application further provides a semiconductor packaging structure, which is different from the above-mentioned embodiment in that: an upper insulating layer covering the first metal column is not formed on the front side of the bridge chip, the first metal columns are filled with a first plastic sealing layer, and a redistribution layer is not formed on the back side of the packaging structure. The second metal column is directly electrically connected to the welding protrusion. Specifically, refer to Fig.16 ,include:

[0166] A bridge chip 100, the bridge chip 100 comprising a substrate 101, the substrate 101 comprising a front side and a back side opposite to each other, the front side of the substrate 101 comprising a pad 113, the substrate 101 comprising a through-hole connection structure 110, and the back side of the substrate 101 exposing one end surface of the through-hole connection structure 110; the bridge chip 100 further comprising: a first metal column 105 protruding from the front side of the substrate 101 and electrically connected to the corresponding pad 113; a second metal column 108 protruding from the back side of the substrate 101 and electrically connected to the corresponding through-hole connection structure 110; and a lower insulating layer 109 covering the second metal column 108 and the back side of the substrate 101;

[0167] A first plastic encapsulation layer 201 covering the bridge chip 100 and filling the first metal pillars 105, wherein the upper surface of the first plastic encapsulation layer 201 exposes one end surface of the first metal pillar 105 away from the front surface of the substrate 101, and the lower surface of the first plastic encapsulation layer 201 exposes one end surface of the second metal pillar 108 away from the back surface of the substrate 101;

[0168] An upper redistribution layer 215 located on the upper surface of the first plastic encapsulation layer 201, wherein the upper redistribution layer 215 is electrically connected to the first metal pillar 105;

[0169] A semiconductor chip 300, wherein the semiconductor chip 300 is mounted on the upper surface of the upper redistribution layer 215, and the semiconductor chip 300 is electrically connected to the upper redistribution layer 215;

[0170] A second plastic packaging layer 304 covering the upper surface of the upper redistribution layer 215 and the semiconductor chip 300;

[0171] A welding protrusion 209 is located on the lower insulating layer 109 and is electrically connected to the second metal pillar 108 .

[0172] Another embodiment of the present application further provides a semiconductor packaging structure. The difference between this embodiment and the above-mentioned embodiment is that: during the formation of the semiconductor packaging structure, the first metal column of the bridge chip is packaged downward to meet different packaging requirements. Specifically, refer to Fig.17 ,include:

[0173] A bridge chip 100, the bridge chip 100 comprising a substrate 101, the substrate 101 comprising a front side and a back side opposite to each other, the front side of the substrate 101 comprising a pad 113, the substrate 101 comprising a through-hole connection structure 110, and the back side of the substrate 101 exposing one end surface of the through-hole connection structure 110; the bridge chip 100 further comprising: a first metal column 105 protruding from the front side of the substrate 101 and electrically connected to the corresponding pad 113; an upper insulating layer 106 covering the first metal column 105 and the front side of the substrate 101; a second metal column 108 protruding from the back side of the substrate 101 and electrically connected to the corresponding through-hole connection structure 110; and a lower insulating layer 109 covering the second metal column 108 and the back side of the substrate 101;

[0174] A first plastic encapsulation layer 201 covering the bridge chip 100, wherein the upper surface of the first plastic encapsulation layer 201 exposes one end surface of the second metal column 108 away from the back surface of the substrate 101, and the lower surface of the first plastic encapsulation layer 201 exposes one end surface of the first metal column 105 away from the front surface of the substrate 101;

[0175] A first redistribution layer 202 located on the lower surfaces of the first plastic encapsulation layer 201 and the upper insulating layer 106, wherein the first redistribution layer 202 is electrically connected to the first metal pillar 105;

[0176] A second redistribution layer 205 is located on the upper surface of the first plastic encapsulation layer 201 and the lower insulating layer 109, and the second redistribution layer 205 is electrically connected to the second metal pillar 108;

[0177] A semiconductor chip 300, wherein the semiconductor chip 300 is mounted on the upper surface of the second redistribution layer 205, and the semiconductor chip 300 is electrically connected to the second redistribution layer 205;

[0178] A second plastic packaging layer 304 covering the upper surface of the second redistribution layer 205 and the semiconductor chip 300;

[0179] A welding protrusion 209 is located on the lower surface of the first redistribution layer 202 and is electrically connected to the first redistribution layer 202 .

[0180] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for forming a semiconductor packaging structure, characterized in that: include: A bridge chip is provided, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; an upper insulating layer covering the first metal column and the front side of the substrate; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; a lower insulating layer covering the second metal column and the back side of the substrate; Providing a first carrier board, and bonding the upper insulating layer of the bridge chip to the upper surface of the first carrier board; forming a first plastic packaging layer covering the upper surface of the first carrier board and the bridge chip; Thinning a side of the first plastic encapsulation layer away from the first carrier to expose a side surface of the second metal column away from the back side of the substrate; forming a first redistribution layer on the surface of the thinned first plastic encapsulation layer, the first redistribution layer being electrically connected to the second metal pillar, and a process for forming the first redistribution layer comprising an electroplating process; Providing a second carrier board, and bonding the first redistribution layer to a surface of the second carrier board; The first carrier is removed to expose the upper insulating layer; the side of the first plastic encapsulation layer away from the second carrier is thinned to expose the end surface of the first metal column away from the front surface of the substrate; a second redistribution layer is formed on the surface of the thinned first plastic encapsulation layer, the second redistribution layer is electrically connected to the first metal column, and the process of forming the second redistribution layer includes an electroplating process; a semiconductor chip is provided, and the semiconductor chip is mounted on the upper surface of the second redistribution layer, and the semiconductor chip is electrically connected to the second redistribution layer; A second plastic encapsulation layer is formed to cover the upper surface of the second redistribution layer and the semiconductor chip.

2. The method for forming a semiconductor package structure according to claim 1, wherein: Also includes: removing the second carrier board to expose the first redistribution layer; A soldering bump electrically connected to the first redistribution layer is formed on the lower surface of the first redistribution layer.

3. The method for forming a semiconductor package structure according to claim 1 or 2, wherein: The first redistribution layer includes a first organic dielectric layer and a first metal circuit layer located in the first organic dielectric layer; the first organic dielectric layer is a single-layer or multi-layer stacked structure, and the corresponding first metal circuit layer is a single-layer or multi-layer stacked structure; The first redistribution layer is electrically connected to the second metal column, including: the first metal line layer is electrically connected to the second metal column.

4. The method for forming a semiconductor package structure according to claim 3, wherein: When the first organic dielectric layer and the first metal circuit layer are both one layer, the formation process of the first redistribution layer includes: forming the first organic dielectric layer on the surface of the thinned first plastic sealing layer and the lower insulating layer by using a coating process; performing an exposure process, a development process and a thermal curing process on the first organic dielectric layer formed by coating, and forming a first opening in the first organic dielectric layer to expose the surface of one end of the second metal column; forming a seed layer on the upper surface of the first organic dielectric layer and the side wall and bottom surface of the first opening; forming a photoresist layer on the upper surface of the seed layer; patterning the photoresist layer, and forming a second opening in the photoresist layer to expose the seed layer in the first opening and a portion of the upper surface of the seed layer outside the first opening; forming the first metal circuit layer in the second opening by using an electroplating process; and removing the photoresist layer.

5. The method for forming a semiconductor package structure according to claim 1 or 2, wherein: The second redistribution layer includes a second organic dielectric layer and a second metal circuit layer located in the second organic dielectric layer; the second organic dielectric layer is a single-layer or multi-layer stacking structure, and the corresponding second metal circuit layer is a single-layer or multi-layer stacking structure; the second redistribution layer also includes a micro-pad located on the upper surface of the second organic dielectric layer on the top layer and electrically connected to the second metal circuit layer.

6. The method for forming a semiconductor package structure according to claim 5, wherein: The semiconductor chip is mounted on the upper surface of the second redistribution layer, and the electrical connection between the semiconductor chip and the second redistribution layer includes: the micro-bumps on the semiconductor chip are welded together with the micro-pads; the electrical connection between the second redistribution layer and the first metal column includes: the second metal circuit layer is electrically connected to the first metal column.

7. The method for forming a semiconductor package structure according to claim 1, wherein: Also includes: Before forming the first plastic encapsulation layer, a columnar connection structure is formed on the upper surface of the first carrier on one side or multiple sides of the bridge chip; the first plastic encapsulation layer also covers the columnar connection structure; the first redistribution layer and the second redistribution layer are also electrically connected to the columnar connection structure.

8. The method for forming a semiconductor package structure according to claim 1, wherein: The front surface of the substrate of the bridge chip also has a redistribution layer, and the redistribution layer is a part of the substrate; the pad is located on the upper surface of the redistribution layer and is electrically connected to the redistribution layer; The through hole connection structure is electrically connected to the redistribution layer.

9. The method for forming a semiconductor package structure according to claim 8, wherein: The redistribution layer includes a passivation layer and a metal circuit layer located in the passivation layer; the passivation layer is a single-layer or multi-layer stacking structure, and the corresponding metal circuit layer is a single-layer or multi-layer stacking structure; the pad is electrically connected to the metal circuit layer.

10. The method for forming a semiconductor package structure according to claim 8, wherein: A deep trench capacitor is also formed in the substrate of the bridge chip, and the deep trench capacitor is electrically connected to the redistribution layer.

11. The method for forming a semiconductor package structure according to claim 10, wherein: The formation process of the bridge chip includes: providing a substrate; forming a through-hole connection structure and a deep trench capacitor in the substrate; forming a redistribution layer on the front side of the substrate; forming a solder pad on the upper surface of the redistribution layer; forming a raised first metal column on the upper surface of the solder pad; forming an upper insulating layer covering the first metal column and the front side of the substrate; thinning the back side of the substrate to expose one end surface of the through-hole connection structure; forming a raised second metal column on the exposed surface of the through-hole connection structure; forming a lower insulating layer covering the second metal column and the back side of the substrate; and cutting the substrate to form a plurality of discrete bridge chips.

12. A method for forming a semiconductor packaging structure, characterized in that: include: A bridge chip is provided, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; and a lower insulating layer covering the second metal column and the back side of the substrate; Providing a carrier board, and bonding the lower insulating layer of the bridge chip to the upper surface of the carrier board; Forming a first plastic packaging layer covering the upper surface of the carrier board and the bridge chip and filling between the first metal pillars; Thinning a side of the first plastic encapsulation layer away from the carrier to expose a surface of an end of the first metal column away from the front side of the substrate; forming an upper redistribution layer on the surface of the thinned first plastic encapsulation layer, wherein the upper redistribution layer is electrically connected to the first metal column, and a process for forming the upper redistribution layer includes an electroplating process; Providing a semiconductor chip, mounting the semiconductor chip on the upper surface of the upper redistribution layer, wherein the semiconductor chip is electrically connected to the upper redistribution layer; forming a second plastic encapsulation layer covering the upper surface of the upper redistribution layer and the semiconductor chip; removing the carrier to expose the lower insulating layer; A welding protrusion electrically connected to the second metal pillar is formed on the lower insulating layer.

13. A semiconductor packaging structure, characterized in that: include: A bridge chip, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; an upper insulating layer covering the first metal column and the front side of the substrate, the upper surface of the upper insulating layer exposing an end surface of the first metal column away from the front side of the substrate; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; a lower insulating layer covering the second metal column and the back side of the substrate, the lower surface of the lower insulating layer exposing an end surface of the second metal column away from the back side of the substrate; A first plastic encapsulation layer covering the bridge chip, wherein the upper surface of the first plastic encapsulation layer exposes the upper surface of the upper insulating layer and an end surface of the first metal column away from the front surface of the substrate, and the lower surface of the first plastic encapsulation layer exposes the lower surface of the lower insulating layer and an end surface of the second metal column away from the back surface of the substrate; A first redistribution layer located on the lower surfaces of the first plastic encapsulation layer and the lower insulating layer, the first redistribution layer being electrically connected to the second metal pillar; A second redistribution layer located on the upper surfaces of the first plastic encapsulation layer and the upper insulating layer, the second redistribution layer being electrically connected to the first metal column; A semiconductor chip, wherein the semiconductor chip is mounted on the upper surface of the second redistribution layer, and the semiconductor chip is electrically connected to the second redistribution layer; A second plastic packaging layer covers the upper surface of the second redistribution layer and the semiconductor chip.

14. The semiconductor package structure according to claim 13, wherein: The first metal pillar and the second metal pillar have the same height.

15. The semiconductor package structure according to claim 13, wherein: The upper insulating layer and the lower insulating layer are made of the same material.

16. The semiconductor package structure according to claim 13, wherein: The first redistribution layer includes a first organic dielectric layer and a first metal circuit layer located in the first organic dielectric layer; the first organic dielectric layer is a single-layer or multi-layer stacked structure, and the corresponding first metal circuit layer is a single-layer or multi-layer stacked structure; The first redistribution layer is electrically connected to the second metal column, including: the first metal line layer is electrically connected to the second metal column.

17. The semiconductor package structure according to claim 13, wherein: The second redistribution layer includes a second organic dielectric layer and a second metal circuit layer located in the second organic dielectric layer; the second organic dielectric layer is a single-layer or multi-layer stacking structure, and the corresponding second metal circuit layer is a single-layer or multi-layer stacking structure; the second redistribution layer also includes a micro-pad located on the upper surface of the second organic dielectric layer on the top layer and electrically connected to the second metal circuit layer.

18. The semiconductor package structure according to claim 13, wherein: The front surface of the substrate of the bridge chip also has a redistribution layer, and the redistribution layer serves as a part of the substrate; the solder pad is located on the upper surface of the redistribution layer and is electrically connected to the redistribution layer; the through-hole connection structure is electrically connected to the redistribution layer; the redistribution layer includes a passivation layer and a metal circuit layer located in the passivation layer; the passivation layer is a single-layer or multi-layer stacked structure, and the corresponding metal circuit layer is a single-layer or multi-layer stacked structure; the solder pad is electrically connected to the metal circuit layer.

19. The semiconductor package structure according to claim 13, wherein: An underfill layer is also filled between the semiconductor chip and the upper surface of the second redistribution layer.

20. A semiconductor packaging structure, characterized in that: include: A bridge chip, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; and a lower insulating layer covering the second metal column and the back side of the substrate; A first plastic encapsulation layer covering the bridge chip and filling between the first metal pillars, wherein the upper surface of the first plastic encapsulation layer exposes an end surface of the first metal pillar away from the front surface of the substrate, and the lower surface of the first plastic encapsulation layer exposes an end surface of the second metal pillar away from the back surface of the substrate; an upper redistribution layer located on the upper surface of the first plastic encapsulation layer, wherein the upper redistribution layer is electrically connected to the first metal pillar; A semiconductor chip, wherein the semiconductor chip is mounted on the upper surface of the upper redistribution layer, and the semiconductor chip is electrically connected to the upper redistribution layer; A second plastic packaging layer covering the upper surface of the upper redistribution layer and the semiconductor chip; A welding protrusion is located on the lower insulating layer and is electrically connected to the second metal column.

21. A semiconductor packaging structure, characterized in that: include: A bridge chip, the bridge chip comprising a substrate, the substrate comprising a front side and a back side opposite to each other, the front side of the substrate having a pad, the substrate having a through-hole connection structure, and the back side of the substrate exposing an end surface of the through-hole connection structure; the bridge chip further comprising: a first metal column protruding from the front side of the substrate and electrically connected to the corresponding pad; an upper insulating layer covering the first metal column and the front side of the substrate; a second metal column protruding from the back side of the substrate and electrically connected to the corresponding through-hole connection structure; a lower insulating layer covering the second metal column and the back side of the substrate; A first plastic packaging layer covering the bridge chip, wherein the upper surface of the first plastic packaging layer exposes one end surface of the second metal column away from the back surface of the substrate, and the lower surface of the first plastic packaging layer exposes one end surface of the first metal column away from the front surface of the substrate; A first redistribution layer located on the lower surfaces of the first plastic encapsulation layer and the upper insulating layer, the first redistribution layer being electrically connected to the first metal column; A second redistribution layer located on the upper surfaces of the upper insulating layer and the first plastic encapsulation layer, wherein the second redistribution layer is electrically connected to the second metal pillar; A semiconductor chip, wherein the semiconductor chip is mounted on the upper surface of the second redistribution layer, and the semiconductor chip is electrically connected to the second redistribution layer; A second plastic packaging layer covering the upper surface of the second redistribution layer and the semiconductor chip; A welding protrusion is located on the lower surface of the first redistribution layer and is electrically connected to the first redistribution layer.

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