Packaging structure and forming method thereof
By designing equal length row-direction interconnection lines and row-arrange chip interconnection methods on the substrate, the problem of low X-direction communication rate between chip modules in the prior art is solved, and the performance of the package structure and wiring difficulty are improved. simplify.
Patent Information
- Application Number
- CN202411351843.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-01-03
AI Technical Summary
In the existing system-level package, the X-direction communication rate between adjacent chip modules is lower than that of the Y-direction, and the wiring is difficult, which affects the performance of the packaging structure.
The chip interconnection method of equal length row-direction interconnection lines and column-direction interconnection lines on the substrate is adopted to ensure that the communication rate in row-direction direction is consistent or small, and is mounted on the first chip through the second chip. Back to simplify wiring.
Improve the performance of the package structure, ensure consistency of the communication rate of the chip in different directions, increase connection channels, simplify wiring difficulty and improve communication rate.
Smart Images
Figure CN119252828A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor packaging, and in particular to a packaging structure and a method for forming the same. Background Art
[0002] System in Package (SiP) integrates chips with various functions such as optoelectronics, digital / logic, radio frequency, storage, etc. into a package in the form of chip stacking or package stacking, thereby realizing a system that can realize multiple functions.
[0003] The demand for data computing in today's emerging fields (servers, mobile devices, artificial intelligence, automotive electronics, data storage, etc.) is growing exponentially. In order to meet the needs of high-performance computing such as high density, high speed, high heat dissipation, low power consumption, and low latency, the existing system-level packaging is expanding towards wafer scale, that is, integrating multiple chip modules (die modules) with the same or different functions on a silicon wafer to form a wafer-scale system-level packaging structure. Each existing chip module includes a logic chip (logic die) mounted on an interposer, and multiple memory chips (memory die) located on the interposer on both sides of the logic chip. Since the logic chips between adjacent chip modules need to communicate or transmit data, wiring is required in the interposer between the chip modules to achieve interconnection between the logic chips of adjacent chip modules. The interconnection between the logic chips of the existing adjacent chip modules can only be connected through the wiring in the Y direction. In the X direction, since there are memory chips mounted between the adjacent logic chips, if the wiring is performed in the X direction, the length of the wiring in the X direction will increase relative to the length of the wiring in the Y direction, which will make the communication rate between the adjacent logic chips in the X direction lower than the communication rate in the Y direction, affecting the performance of the packaging structure, and the wiring difficulty will also increase when wiring in the X direction. Summary of the invention
[0004] The problem to be solved by the present application is to provide a packaging structure and a method for forming the same, so as to improve the communication rates of chips in the packaging structure in different directions to be consistent or with a small difference, and to increase the bandwidth, thereby improving the performance of the packaging structure.
[0005] In order to solve the above problems, the present application provides a packaging structure, which is characterized by comprising: A substrate having a plurality of discrete first wirings for interconnection in a row direction and a plurality of discrete second wirings for interconnection in a column direction, wherein the length of the second wirings is equal to the length of the first wirings; A plurality of first chips, wherein the plurality of first chips are mounted on the upper surface of the substrate in rows and columns, and two adjacent first chips arranged in a row direction are interconnected through the first wiring, and two adjacent first chips arranged in a column direction are interconnected through the second wiring; A second chip is mounted on the back side of the first chip, and the second chip is electrically connected to the first chip.
[0006] In an optional embodiment, the substrate includes a relative upper surface and a lower surface, the upper surface of the substrate has a plurality of discrete first pads and a plurality of discrete second pads, the two ends of each of the first wirings are respectively electrically connected to the corresponding two first pads, and the two ends of each of the second wirings are respectively electrically connected to the corresponding other two second pads.
[0007] In an optional embodiment, the first chip includes a relative back side and an active side, the back side of the first chip has a plurality of discrete first connecting terminals, the active side of the first chip has a plurality of discrete first welding protrusions, the first connecting terminals are electrically connected to the corresponding first welding protrusions, and a portion of the first welding protrusions are welded together with the corresponding first welding pads, and then electrically connected to the corresponding first wiring, and another portion of the first welding protrusions are welded together with the corresponding second welding pads, and then electrically connected to the corresponding second wiring.
[0008] In an optional embodiment, the second chip includes a relative back side and an active side, the active side of the second chip has a plurality of discrete second welding protrusions; the electrical connection between the second chip and the first chip includes: the second welding protrusions are welded together with the first connection terminals.
[0009] In an optional embodiment, the first chip is a logic chip, and the second chip is a memory chip.
[0010] In an optional embodiment, two adjacent first chips arranged along the row direction are interconnected through the first wiring, and two adjacent first chips arranged along the column direction are interconnected through the second wiring, including: two adjacent first chips arranged along the row direction are interconnected through the portion of the first welding protrusions and the first wiring, and communicate or transmit data, and two adjacent first chips arranged along the column direction are interconnected through the portion of the first welding protrusions and the second wiring, and communicate or transmit data.
[0011] In an optional embodiment, the number of the second chips is one or more.
[0012] In an optional embodiment, when there are multiple second chips, the multiple second chips are mounted on the back side of the first chip respectively along the horizontal direction, or the multiple second chips are stacked and mounted on the back side of the first chip in sequence along the vertical direction.
[0013] In an optional embodiment, the first chip is a memory chip, and the second chip is a logic chip.
[0014] In an optional embodiment, when two adjacent first chips arranged along the row direction are interconnected through the first wiring, and two adjacent first chips arranged along the column direction are interconnected through the second wiring, no communication or data transmission is performed between the two adjacent first chips.
[0015] In an optional embodiment, two adjacent second chips arranged along the row direction are interconnected and communicate or transmit data through a part of the second welding bumps on the second chip, a corresponding part of the first connecting terminals and the first welding bumps on the first chip, and a corresponding first welding pad and first wiring in the substrate; and two adjacent second chips arranged along the column direction are interconnected and communicate or transmit data through another part of the second welding bumps on the second chip, another corresponding part of the first connecting terminals and the first welding bumps on the first chip, and a corresponding second welding pad and second wiring in the substrate.
[0016] In an optional embodiment, the upper surface of the substrate also has a plurality of discrete third pads; the substrate also has a plurality of discrete third wirings, and the third wirings are electrically connected to the third pads; and a portion of the first welding protrusions on the first chip are welded together with the third pads.
[0017] In an optional embodiment, it also includes: a heat dissipation device mounted on the back side of the second chip.
[0018] On the other hand, the present application also provides a method for forming a packaging structure, comprising: Providing a substrate having a plurality of discrete first wirings for interconnection in a row direction and a plurality of discrete second wirings for interconnection in a column direction, wherein the length of the second wirings is equal to the length of the first wirings; Providing a plurality of first chips, arranging the plurality of first chips in rows and columns and mounting them on the upper surface of the substrate, wherein two adjacent first chips arranged in a row direction are interconnected through the first wiring, and two adjacent first chips arranged in a column direction are interconnected through the second wiring; A second chip is mounted on the back side of the first chip, and the second chip is electrically connected to the first chip.
[0019] In an optional embodiment, the substrate includes a relative upper surface and a lower surface, the upper surface of the substrate has a plurality of discrete first pads and a plurality of discrete second pads, the two ends of each of the first wirings are respectively electrically connected to the corresponding two first pads, and the two ends of each of the second wirings are respectively electrically connected to the corresponding other two second pads.
[0020] In an optional embodiment, the first chip includes a relative back side and an active side, the back side of the first chip has a plurality of discrete first connecting terminals, the active side of the first chip has a plurality of discrete first welding protrusions, the first connecting terminals are electrically connected to the corresponding first welding protrusions, and when the plurality of first chips are arranged in rows and columns and mounted on the upper surface of the substrate, a portion of the first welding protrusions are welded together with the corresponding first welding pads, and then electrically connected to the corresponding first wiring, and another portion of the first welding protrusions are welded together with the corresponding second welding pads, and then electrically connected to the corresponding second wiring.
[0021] In an optional embodiment, the second chip includes a relative back side and an active side, the active side of the second chip has a plurality of discrete second welding protrusions, and when the second chip is mounted on the back side of the first chip, the second welding protrusions are welded together with the first connecting terminals.
[0022] In an optional embodiment, the first chip is a logic chip and the second chip is a memory chip, or the first chip is a memory chip and the second chip is a logic chip.
[0023] In an optional embodiment, the number of the second chips is one or more; when the number of the second chips is multiple, the multiple second chips are mounted on the back side of the first chip respectively in the horizontal direction, or the multiple second chips are stacked in sequence in the vertical direction and mounted on the back side of the first chip.
[0024] In an optional embodiment, the method further includes: mounting a heat dissipation device on the back side of the second chip.
[0025] The advantages of the technical solution of this application are: The packaging structure and the method for forming the same in the present application, wherein the packaging structure comprises: a substrate, wherein the substrate has a plurality of discrete first wirings for interconnection in the row direction and a plurality of discrete second wirings for interconnection in the column direction, wherein the length of the second wirings is equal to the length of the first wirings; a plurality of first chips, wherein the plurality of first chips are arranged in rows and columns and mounted on the upper surface of the substrate, and two adjacent first chips arranged in the row direction are interconnected through the first wirings, and two adjacent first chips arranged in the column direction are interconnected through the second wirings; and a second chip mounted on the back side of the first chip, wherein the second chip is electrically connected to the first chip. That is, in the packaging structure of the present application, two adjacent first chips arranged in the row direction are interconnected through the first wiring, and two adjacent first chips arranged in the column direction are interconnected through the second wiring. The lengths of the first wiring and the second wiring are the same, so that two adjacent first chips in a plurality of first chips arranged in rows and columns can be interconnected not only in the row direction but also in the column direction, which increases the connection channels and improves the bandwidth. In addition, since the first wiring used for interconnection in the row direction and the second wiring used for interconnection in the column direction are the same in length, the rates in the row direction and the column direction can be kept consistent or have a small difference when various same or different communications or data transmissions are performed between two adjacent first chips in a plurality of first chips arranged in rows and columns, thereby improving the performance of the packaging structure. In addition, since the second chip is mounted on the back of the first chip, on the one hand, the connection distance between the second chip and the first chip is shortened, so that the communication rate between the second chip and the first chip is increased. On the other hand, it will not occupy the mounting space on the upper surface of the substrate between the adjacent first chips and the wiring space in the substrate, simplifying the wiring difficulty of the first wiring and the second wiring in the substrate, and making it easier to make the length of the first wiring equal to the length of the second wiring. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1-Figure 3 This is a schematic diagram of the packaging structure in one embodiment of the present application, wherein: Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line BB1; Figure 4-Figure 6 This is a schematic diagram of a packaging structure in another embodiment of the present application, wherein: Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 6 for Figure 4 Schematic diagram of the cross-sectional structure along the cutting line BB1; Figure 4 , Figure 7-Figure 8 This is a schematic diagram of a packaging structure in another embodiment of the present application, wherein: Figure 7 for Figure 4 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 8 for Figure 4 Schematic diagram of the cross-sectional structure along the cutting line BB1. DETAILED DESCRIPTION
[0026] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.
[0027] On the one hand, the present application first provides a packaging structure, and the packaging structure of the present application is described in detail below with reference to the accompanying drawings.
[0028] An embodiment of the present application provides a packaging structure, referring to Figure 1-Figure 3 ,in, Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 3 for Figure 1 A schematic cross-sectional structure diagram along the cutting line BB1, wherein the packaging structure comprises: A substrate 101, wherein the substrate 101 has a plurality of discrete first wirings 102 for interconnection in a row direction and a plurality of discrete second wirings 103 for interconnection in a column direction, wherein the length of the second wirings 103 is equal to the length of the first wirings 102; A plurality of first chips 201, wherein the plurality of first chips 201 are mounted on the upper surface of the substrate 101 in rows and columns, and two adjacent first chips 201 arranged in a row direction are interconnected through the first wiring 102, and two adjacent first chips 201 arranged in a column direction are interconnected through the second wiring 103; The second chip 301 is mounted on the back side of the first chip 201 , and the second chip 301 is electrically connected to the first chip 201 .
[0029] The substrate 101 serves as a support carrier and a connection carrier of the packaging structure. In one embodiment, the upper surface of the substrate 101 has a plurality of discrete first pads (not shown in the figure) and a plurality of discrete second pads (not shown in the figure). The substrate 101 has a plurality of discrete first wirings 102 for interconnection in the row direction and a plurality of discrete second wirings 103 for interconnection in the column direction. The two ends of each first wiring 102 are electrically connected to the corresponding two first pads, and the two ends of each second wiring 103 are electrically connected to the corresponding other two second pads. When the plurality of first chips 201 are arranged in rows and columns and mounted on the upper surface of the substrate 101, two adjacent first chips 201 arranged in the row direction are electrically connected to the corresponding first pads so as to be interconnected through the first wiring 102, and two adjacent first chips 201 arranged in the column direction are electrically connected to the corresponding second pads so as to be interconnected through the second wiring 103. It should be noted that, in one embodiment, the row direction is the X-axis direction, and the column direction is the Y-axis direction.
[0030] In one embodiment, the plurality of discrete first wirings 102 are divided into a plurality of groups, each group of the second wirings includes a plurality of discrete first wirings 102, each group of the second wirings is used to connect two adjacent second chips 201 of the plurality of first chips 201 arranged along the row direction, the plurality of groups of the first wirings are arranged in rows and columns in the substrate 101, and each group of the first wirings is located in the substrate 101 between two adjacent first chips 201 arranged along the row direction. In one embodiment, the arrangement of the plurality of first wirings 102 in different groups of the first wirings is the same. In one embodiment, the plurality of first wirings 102 in each group of the first wirings are the same in length. In another embodiment, the lengths of some of the first wirings 102 in each group of the first wirings are the same, and the lengths of some of the first wirings 102 are different.
[0031] In one embodiment, the plurality of discrete second wirings 103 are divided into a plurality of groups, each group of the second wirings includes a plurality of discrete second wirings 103, each group of the second wirings is used to connect two adjacent second chips 301 of a plurality of first chips 201 arranged along the column direction, the plurality of groups of the second wirings are arranged in rows and columns in the substrate 101, and each group of the second wirings is located in the substrate 101 between two adjacent first chips 201 arranged along the column direction. In one embodiment, the arrangement of the plurality of second wirings 103 in different groups of the second wirings is the same. In one embodiment, the lengths of the plurality of second wirings 103 in each group of the second wirings are the same. In another embodiment, the lengths of some of the second wirings 103 in each group of the second wirings are the same, and the lengths of some of the second wirings 103 are different.
[0032] The length of the second wiring 103 is equal to the length of the first wiring 102, including two situations. The first situation: when the lengths of the plurality of first wirings 102 in each group of the first wirings are the same, and the lengths of the plurality of second wirings 103 in each group of the second wirings are the same, the lengths of the plurality of first wirings 102 in each group of the first wirings are the same as the lengths of the plurality of second wirings 103 in each group of the second wirings. The first situation: when the lengths of some of the first wirings 102 in each group of the first wirings are the same, and the lengths of some of the first wirings 102 are different, and the lengths of some of the second wirings 103 in each group of the second wirings are the same, and the lengths of some of the second wirings 103 are different, the lengths of the second wirings 103 and the first wirings 102 having the same function in each group of the second wirings as in each group of the first wirings are the same, or the lengths of the second wirings 103 and the first wirings 102 transmitting the same signal in each group of the second wirings as in each group of the first wirings are the same, or the lengths of the second wirings 103 and the first wirings 102 transmitting the same data in each group of the second wirings as in each group of the first wirings are the same. That is, in the present application, two adjacent first chips 201 arranged along the row direction are interconnected through the first wiring 102, and two adjacent first chips 201 arranged along the column direction are interconnected through the second wiring 103. The first wiring 102 and the second wiring 103 have the same length, so that two adjacent first chips 201 in a plurality of first chips 201 arranged in rows and columns can be interconnected not only in the row direction but also in the column direction, thereby increasing the connection channels and improving the bandwidth. Moreover, since the first wiring 102 used for interconnection in the row direction and the second wiring 103 used for interconnection in the column direction have the same length, the rates in the row direction and the column direction can be kept consistent or very close when various same or different communications or data transmissions are performed between two adjacent first chips 201 in the plurality of first chips 201 arranged in rows and columns, thereby improving the performance of the packaging structure.
[0033] In one embodiment, the upper surface of the substrate 101 further has a plurality of discrete third pads (not shown in the figure), and the lower surface of the substrate 101 may also have a plurality of discrete fourth pads (not shown in the figure), and an external protrusion (not shown in the figure) may be formed on the lower surface of the second pad, and the external protrusion is used to be electrically connected to other devices, substrates or packaging structures; the substrate 101 also has a plurality of discrete third wirings 104, one end of the third wiring 104 is electrically connected to the corresponding third pad, in a specific embodiment, the other end of the third wiring 104 can be electrically connected to the corresponding fourth pad on the lower surface of the substrate 101, in another specific embodiment, the other end of the third wiring 104 can be electrically connected to another third pad on the upper surface of the substrate 101, and in another specific embodiment, the other end of the third wiring 104 can be electrically connected to the corresponding first pad or second pad on the upper surface of the substrate 101. In one embodiment, in addition to being electrically connected to the first wiring 102 and the second wiring 103 , the first chip 201 may also be electrically connected to the third pad and the third wiring 104 .
[0034] In one embodiment, the first wiring 102, the second wiring 103 and the third wiring 104 may include one or more of a metal layer, a connection plug, a through silicon via connection structure (TSV), a via connection structure, and a metal conductive column. In one embodiment, the material of the first pad, the second pad, the third pad, the fourth pad, the first wiring 102, the second wiring 103 and the third wiring 104 is metal, which may be one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the external protrusion is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.
[0035] In one embodiment, the substrate 101 may be one of a silicon substrate, an RDL substrate (Re-distribution Layer), a resin substrate, a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a flexible circuit board (FPC). In one embodiment, the substrate may be a single-layer board or a multi-layer board. In one embodiment, the substrate 101 may be used as an interposer.
[0036] In one embodiment, the substrate 101 may be a silicon wafer.
[0037] In one embodiment, the substrate 101 may have a larger size. When the substrate 101 is circular, the diameter of the substrate 101 may be 300 mm ± 10 mm, 450 ± 15 mm. When the substrate 101 is square, the diagonal size of the substrate 101 may be 300 mm ± 15 mm, 450 ± 20 mm.
[0038] The first chip 201 is mounted on the upper surface of the substrate 101 by a flip-chip process. In one embodiment, the first chip 201 includes a relative back side and an active side, the back side of the first chip 201 has a plurality of discrete first connection terminals 203, the first connection terminals 203 include a through silicon via interconnection structure (TSV, Through Silicon Via), or a through silicon via interconnection structure and a pad connected to the top of the through silicon via interconnection structure, the active side of the first chip 201 has a plurality of discrete first welding protrusions 202, the first connection terminals 203 are also electrically connected to the corresponding first welding protrusions 202, and the plurality of discrete first welding protrusions 202 can be divided into multiple parts, a part of the first welding protrusions 202 is welded together with the corresponding first pad, so as to be electrically connected to the first wiring 102, and two adjacent first chips 201 arranged in the row direction are interconnected through the first wiring 102 (refer to Figure 1 and Figure 2 ), another part of the first welding protrusions 202 are welded together with the corresponding second welding pads, thereby being electrically connected to the second wiring 103, and the two adjacent first chips 201 arranged along the column direction are interconnected through the second wiring 103 (refer to Figure 1 and Figure 3 In one embodiment, a portion of the first welding protrusions 202 on the first chip 201 is welded to the third welding pad, thereby being electrically connected to the third wiring 104 .
[0039] In one embodiment, an integrated circuit (having a specific function) (such as a logic control circuit, not shown in the figure) is formed in the first chip 201, and the first welding protrusion 202 and the first connecting terminal 203 are electrically connected to the integrated circuit. In a specific embodiment, the first welding protrusion 202 can be a solder protrusion or include a metal protrusion and a solder layer located on the top surface of the metal protrusion. In a specific embodiment, the material of the first connecting terminal 203 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver, the material of the metal protrusion is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver, the material of the solder protrusion or solder layer is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.
[0040] The second chip 301 is mounted on the back of the first chip 201 by a flip-chip process. In one embodiment, the second chip 301 includes a relative back and an active surface, and the active surface of the second chip 301 has a plurality of discrete second welding protrusions 302; the second chip 301 is electrically connected to the first chip 201, including: the second welding protrusions 302 are welded together with the first connection terminals 203. In the present application, when the second chip 301 is mounted on the back of the first chip 201, on the one hand, the connection distance between the second chip 301 and the first chip 201 is shortened, so that the communication rate between the second chip 301 and the first chip 201 is improved; on the other hand, it does not occupy the mounting space on the upper surface of the substrate 101 between adjacent first chips 201 and the wiring space in the substrate 101, which simplifies the wiring difficulty of the first wiring 102 and the second wiring 103 in the substrate 101, and can more easily make the length of the first wiring 102 equal to the length of the second wiring 103.
[0041] The number of the second chips 301 is one or more. Figure 1-Figure 3 When there are multiple second chips 301, specifically, there may be 2, 3, 4 or more chips, and the multiple second chips 301 are respectively mounted on the back side of the first chip 201 along the horizontal direction (the direction parallel to the upper surface of the substrate 101).
[0042] In another embodiment, reference Figure 4-Figure 6 ,in, Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 6 for Figure 4 The schematic diagram of the cross-sectional structure along the cutting line BB1 direction, when the number of the second chips 301 is multiple, specifically, it can be 2, 3, 4 or more, and the multiple second chips 301 are stacked and mounted on the back of the first chip 201 in sequence along the vertical direction. Specifically, the back of the second chip 301 also has a second connection terminal 303, and the second connection terminal 303 includes a through silicon via interconnection structure (TSV, Through Silicon Via), or a through silicon via interconnection structure and a pad connected to the top of the through silicon via interconnection structure. When the multiple second chips 301 are stacked in the vertical direction, the second welding protrusion 302 on the active surface of the upper second chip 301 is welded to the second connection terminal 303 on the back of the adjacent lower second chip 301, and the second welding protrusion 302 on the active surface of the bottom second chip 301 is welded to the first connection terminal 203 on the back of the first chip 201. It should be noted that the back of the top second chip 301 may not have a second connection terminal 303.
[0043] In one embodiment, the material of the second connection terminal 303 is one or more of aluminum, copper, titanium, nickel, tin, tungsten, platinum, chromium, tantalum, gold, and silver.
[0044] In one embodiment, an integrated circuit with a specific function is formed in the second chip 301 , and the second connection terminal 303 and the second welding protrusion 302 are electrically connected to the integrated circuit.
[0045] In one embodiment, the second solder bump 302 is a micro solder ball (μbump). The material of the micro bump 302 is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-indium, tin-gold, tin-copper, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.
[0046] In other embodiments, the active surface of the second chip 301 may not be provided with micro solder balls, but may be provided with a plurality of discrete bonding metal layers. The multiple second chips 301 are stacked and mounted on the back side of the first chip 201 in sequence along the vertical direction, and the upper and lower second chips 301 are not bonded together by micro solder balls, but are bonded together by hybrid bonding (including metal diffusion bonding and silicon oxygen bonding).
[0047] In one embodiment, continue to refer to Figure 1-Figure 3 or Figure 4-Figure 6 The packaging structure further includes: a plastic encapsulation layer 105 covering the second chip 301 and the first chip 201, and filling between the second chip 301 and the first chip 201 and between the first chip 201 and the upper surface of the substrate 101. The plastic encapsulation layer 105 may or may not expose the back surface of the second chip 201.
[0048] In one embodiment, the material of the molding layer 105 is a liquid epoxy molding compound (LMC). In other embodiments, the material of the molding layer 105 may also be other liquid resin molding compounds, such as liquid polyimide resin molding compounds, liquid benzocyclobutene resin molding compounds or liquid polybenzoxazole resin molding compounds. In other embodiments, the material of the molding layer 105 may also be other resin materials containing fillers or not containing fillers.
[0049] The function of the first chip 201 is different from the function of the second chip 301. In one embodiment, continue to refer to Figure 1-Figure 3 or Figure 4-Figure 6, the first chip 201 is a logic chip, the second chip 301 is a memory chip, the memory chip is used to store data, and the logic chip is used to control and manage the memory chip. The memory chip includes but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), and resistive random access memory (RRAM). The logic chip includes but is not limited to a graphics processing unit (GPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), or other known electronic circuits used as processors.
[0050] In one embodiment, continue to refer to Figure 1-Figure 3 or Figure 4-Figure 6 When the first chip 201 is a logic chip and the second chip 301 is a memory chip, two adjacent first chips 201 arranged in the row direction are interconnected through the first wiring 102, and two adjacent first chips 201 arranged in the column direction are interconnected through the second wiring 103, including: two adjacent first chips 201 arranged in the row direction are interconnected through the first welding protrusion 202 and the first wiring 102, and communicate or transmit data, and two adjacent first chips 102 arranged in the column direction are interconnected through the first welding protrusion 202 and the second wiring 102, and communicate or transmit data. There is no direct connection between the adjacent second chips 201 in the row direction or column direction.
[0051] In another embodiment, Figure 4 , Figure 7-Figure 8 ,in, Figure 7 for Figure 4 Schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 8 for Figure 4The schematic diagram of the cross-sectional structure along the cutting line BB1 direction shows that the first chip 201 is a memory chip, and the second chip 301 is a logic chip. When two adjacent first chips 201 arranged along the row direction are interconnected through the first wiring 102, and two adjacent first chips 201 arranged along the column direction are interconnected through the second wiring 102, there is no communication or data transmission between the two adjacent first chips 201. Specifically, two adjacent second chips 301 arranged along the row direction are interconnected and communicate or transmit data through a portion of the second welding protrusion 302 on the second chip 301, a corresponding portion of the first connection terminal 203 on the first chip 201, the first welding protrusion 202, and the corresponding first pad in the substrate 101 and the first wiring 102 (refer to Figure 4 and Figure 7 ); and two adjacent second chips 301 arranged along the column direction are interconnected and communicate or transmit data through another part of the second welding protrusions 302 on the second chip 301, another part of the first connection terminals 203 and the first welding protrusions 202 on the first chip 201, and the corresponding second pads and second wirings 103 in the substrate 101 (refer to Figure 4 and Figure 8 ). That is, when the logic chip (second chip 301) is mounted on top of the memory chip (first chip 201), the memory chip is used to store data, and the logic chip is used to control and manage the memory chip. Communication or data transmission can be performed between adjacent logic chips (second chips 301) in the row direction or column direction, while there is no communication or output transmission between adjacent memory chips (first chips 201) in the row direction or column direction. Since the lengths of the first connection terminals 203 are the same, the second wiring 103 and the first wiring 102 are also the same length, so that when various same or different communications or data transmissions are performed between two adjacent first chips 201 in a plurality of first chips 201 arranged in rows and columns, the rates in the row direction and column direction can be kept consistent or very close, thereby improving the performance of the packaging structure, increasing the connection channels, and improving the bandwidth. Furthermore, since the logic chip generates a large amount of heat during operation, in the packaging structure of this embodiment, when the logic chip (the second chip 301) is mounted on the back of the memory chip (the first chip 201), a heat dissipation device can be conveniently mounted on the back of the logic chip (the second chip 301). The heat dissipation device releases or dissipates the heat of the logic chip (the second chip 301), which is beneficial to the heat dissipation of the packaging structure and further improves the performance of the packaging structure.
[0052] In one embodiment, the logic chip and the memory chip are three-dimensionally stacked by means of w2w (wafer to wafer) hybrid bonding, and the wafer-to-wafer alignment has higher accuracy and efficiency.
[0053] In one embodiment, the plastic encapsulation layer 105 exposes the back side of the second chip 301 and further includes: a heat dissipation device mounted on the back side of the second chip 301, wherein the heat dissipation device is a heat sink or a heat sink, and the heat sink includes an air-cooled or liquid-cooled heat sink.
[0054] The present application also provides a method for forming a packaging structure. In one embodiment, the method for forming the packaging structure, referring to Figure 1-Figure 3 ,include: Providing a substrate 101, wherein a plurality of discrete first wirings 102 for interconnection in a row direction and a plurality of discrete second wirings 103 for interconnection in a column direction are formed in the substrate 101, wherein the length of the second wirings 103 is equal to the length of the first wirings 101; Providing a plurality of first chips 201, and mounting the plurality of first chips 201 on the upper surface of the substrate 101 in rows and columns, and interconnecting two adjacent first chips 201 arranged in a row direction through the first wiring 102, and interconnecting two adjacent first chips 201 arranged in a column direction through the second wiring 103; A second chip 301 is mounted on the back side of the first chip 201 , and the second chip 301 is electrically connected to the first chip 201 .
[0055] In one embodiment, the substrate 101 includes a relative upper surface and a lower surface, and the upper surface of the substrate 101 has a plurality of discrete first pads (not shown in the figure) and a plurality of discrete second pads (not shown in the figure), and the two ends of each of the first wirings 102 are respectively electrically connected to the corresponding two first pads, and the two ends of each of the second wirings 103 are respectively electrically connected to the corresponding other two second pads.
[0056] In one embodiment, the first chip 201 includes a relative back side and an active side, the back side of the first chip 201 has a plurality of discrete first connection terminals 203, and the active side of the first chip 201 has a plurality of discrete first welding protrusions 202, the first connection terminals 203 are electrically connected to the corresponding first welding protrusions 202, and when the plurality of first chips 201 are arranged in rows and columns and mounted on the upper surface of the substrate 101, a portion of the first welding protrusions 202 are welded together with the corresponding first welding pads, and then electrically connected to the corresponding first wiring 102, and another portion of the first welding protrusions 202 are welded together with the corresponding second welding pads, and then electrically connected to the corresponding second wiring 102.
[0057] In one embodiment, the second chip 301 includes a relative back surface and an active surface, the active surface of the second chip 301 has a plurality of discrete second welding protrusions, and when the second chip is mounted on the back surface of the first chip, the second welding protrusions are welded together with the first connection terminals.
[0058] In one embodiment, reference Figure 1-Figure 3 Or refer to Figure 4-Figure 6 , the first chip 201 is a logic chip, and the second chip 301 is a memory chip; or refer to Figure 4 , Figure 7-Figure 8 , the first chip 201 is a memory chip, and the second chip 301 is a logic chip.
[0059] In one embodiment, the number of the second chips 301 is one or more; when the number of the second chips 301 is multiple, the multiple second chips 301 are respectively mounted on the back side of the first chip along the horizontal direction (refer to Figure 1-Figure 3 ), or a plurality of the second chips 301 are stacked and mounted on the back side of the first chip 201 in sequence along the vertical direction (refer to Figure 4-Figure 6 ).
[0060] In one embodiment, the method further includes: mounting a heat dissipation device (not shown in the figure) on the back side of the second chip 301 .
[0061] It should be noted that the parts in this embodiment (the method for forming the packaging structure) that are the same or similar to those in the aforementioned embodiment (the packaging structure) are not repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the aforementioned embodiment for details.
[0062] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.
Claims
1. A packaging structure, characterized in that: include: A substrate having a plurality of discrete first wirings for interconnection in a row direction and a plurality of discrete second wirings for interconnection in a column direction, wherein the length of the second wirings is equal to the length of the first wirings; A plurality of first chips, wherein the plurality of first chips are mounted on the upper surface of the substrate in rows and columns, and two adjacent first chips arranged in a row direction are interconnected through the first wiring, and two adjacent first chips arranged in a column direction are interconnected through the second wiring; A second chip is mounted on the back side of the first chip, and the second chip is electrically connected to the first chip.
2. The packaging structure according to claim 1, characterized in that: The substrate includes a relative upper surface and a lower surface, the upper surface of the substrate has a plurality of discrete first pads and a plurality of discrete second pads, the two ends of each of the first wirings are electrically connected to the corresponding two first pads, and the two ends of each of the second wirings are electrically connected to the corresponding other two second pads.
3. The packaging structure according to claim 2, characterized in that: The first chip includes a relative back side and an active side, the back side of the first chip has a plurality of discrete first connecting terminals, the active side of the first chip has a plurality of discrete first welding protrusions, the first connecting terminals are electrically connected to the corresponding first welding protrusions, and a portion of the first welding protrusions are welded together with the corresponding first welding pads, and then electrically connected to the corresponding first wiring, and another portion of the first welding protrusions are welded together with the corresponding second welding pads, and then electrically connected to the corresponding second wiring.
4. The packaging structure according to claim 3, characterized in that: The second chip comprises an opposite back surface and an active surface, and the active surface of the second chip has a plurality of discrete second welding protrusions; the electrical connection between the second chip and the first chip comprises: the second welding protrusions are welded together with the first connection terminals.
5. The packaging structure according to claim 4, characterized in that: The first chip is a logic chip, and the second chip is a memory chip.
6. The packaging structure according to claim 5, characterized in that: Two adjacent first chips arranged along the row direction are interconnected through the first wiring, and two adjacent first chips arranged along the column direction are interconnected through the second wiring, including: two adjacent first chips arranged along the row direction are interconnected through the portion of the first welding protrusions and the first wiring, and communication or data transmission is performed, and two adjacent first chips arranged along the column direction are interconnected through the portion of the first welding protrusions and the second wiring, and communication or data transmission is performed.
7. The packaging structure according to claim 5, characterized in that: The number of the second chips is one or more.
8. The packaging structure according to claim 7, characterized in that: When there are multiple second chips, the multiple second chips are mounted on the back side of the first chip respectively along the horizontal direction, or the multiple second chips are stacked and mounted on the back side of the first chip in sequence along the vertical direction.
9. The packaging structure according to claim 4, characterized in that: The first chip is a memory chip, and the second chip is a logic chip.
10. The packaging structure according to claim 9, characterized in that: When two adjacent first chips arranged along the row direction are interconnected via the first wiring, and two adjacent first chips arranged along the column direction are interconnected via the second wiring, no communication or data transmission is performed between the two adjacent first chips.
11. The packaging structure according to claim 10, characterized in that: Two adjacent second chips arranged along the row direction are interconnected and communicate or transmit data through a part of the second welding bumps on the second chip, a corresponding part of the first connecting terminals and the first welding bumps on the first chip, and a corresponding first welding pad and first wiring in the substrate; and two adjacent second chips arranged along the column direction are interconnected and communicate or transmit data through another part of the second welding bumps on the second chip, another corresponding part of the first connecting terminals and the first welding bumps on the first chip, and a corresponding second welding pad and second wiring in the substrate.
12. The packaging structure according to claim 3, characterized in that: The upper surface of the substrate also has a plurality of discrete third pads; the substrate also has a plurality of discrete third wirings, and the third wirings are electrically connected to the third pads; and a portion of the first welding protrusions on the first chip are welded together with the third pads.
13. The packaging structure according to claim 1, characterized in that: Also includes: A heat dissipation device is mounted on the back side of the second chip.
14. A method for forming a packaging structure, characterized in that: include: Providing a substrate having a plurality of discrete first wirings for interconnection in a row direction and a plurality of discrete second wirings for interconnection in a column direction, wherein the length of the second wirings is equal to the length of the first wirings; Providing a plurality of first chips, arranging the plurality of first chips in rows and columns and mounting them on the upper surface of the substrate, wherein two adjacent first chips arranged in a row direction are interconnected through the first wiring, and two adjacent first chips arranged in a column direction are interconnected through the second wiring; A second chip is mounted on the back side of the first chip, and the second chip is electrically connected to the first chip.
15. The method for forming a package structure according to claim 14, wherein: The substrate includes a relative upper surface and a lower surface, the upper surface of the substrate has a plurality of discrete first pads and a plurality of discrete second pads, the two ends of each of the first wirings are electrically connected to the corresponding two first pads, and the two ends of each of the second wirings are electrically connected to the corresponding other two second pads.
16. The method for forming a package structure according to claim 15, wherein: The first chip includes a relative back side and an active side, the back side of the first chip has a plurality of discrete first connection terminals, the active side of the first chip has a plurality of discrete first welding protrusions, the first connection terminals are electrically connected to the corresponding first welding protrusions, when the plurality of first chips are arranged in rows and columns and mounted on the upper surface of the substrate, a part of the first welding protrusions are welded together with the corresponding first welding pads, and then electrically connected to the corresponding first wiring, and another part of the first welding protrusions are welded together with the corresponding second welding pads, and then electrically connected to the corresponding second wiring.
17. The method for forming a package structure according to claim 16, wherein: The second chip includes a relative back surface and an active surface. The active surface of the second chip has a plurality of discrete second welding protrusions. When the second chip is mounted on the back surface of the first chip, the second welding protrusions are welded together with the first connection terminals.
18. The method for forming a package structure according to claim 17, wherein: The first chip is a logic chip and the second chip is a memory chip, or the first chip is a memory chip and the second chip is a logic chip.
19. The method for forming a package structure according to claim 18, wherein: The number of the second chips is one or more; when the number of the second chips is multiple, the multiple second chips are mounted on the back side of the first chip respectively along the horizontal direction, or the multiple second chips are stacked and mounted on the back side of the first chip in sequence along the vertical direction.
20. The method for forming a package structure according to claim 14, wherein: Also includes: A heat dissipation device is mounted on the back side of the second chip.