Hardware phase locking method and device

Abstract

The invention discloses a hardware phase locking method and device. The hardware phase locking method specifically comprises the following steps: setting a state machine with multiple states; respectively operating the state machines in different states to obtain m frequency count values, and obtaining system frequency and sampling interruption timing according to the m frequency count values, m being greater than or equal to 4; and calculating the maximum value and the minimum value of the frequency count based on the system frequency so as to be used for judging the effective range of the next frequency count value. According to the invention, the problem that phase and frequency detection is abnormal when a zero crossing point deviates due to deep drop or harmonic waves of system voltage in traditional hard phase locking can be solved.

Description

Technical Field

[0001] The present invention relates to the field of phase locking technology, and in particular to a hardware phase locking method and device. Background Art

[0002] In the prior art, the phase-locked loop (PLL) is a widely used frequency and phase detection technology. Phase-locked loops can be divided into two types: software phase-locked (soft phase-locked) and hardware phase-locked (hard phase-locked). Hard phase-locked calculates the system voltage frequency by detecting the counting time of two adjacent zero-crossing points of the system voltage, and then obtains the step size of a single phase, and performs phase detection based on this. However, when the voltage drops deeply or there is harmonic interference, the existing hardware phase-locked technology will cause the zero-crossing point to shift due to the filtering on the hardware synchronization, thereby affecting the correct detection of frequency and phase. This shift will cause the reference current to be abnormal, which will affect the quality of the output current and the stability of the system. Summary of the invention

[0003] The purpose of the present invention is to provide a hardware phase locking method and device, which can solve the problem of abnormal phase and frequency detection in traditional hard phase locking when the system voltage is offset due to a deep drop or harmonics causing the zero crossing point to shift.

[0004] In order to solve the above technical problems, the present invention provides a hardware phase locking method, which specifically includes the following:

[0005] Set up a state machine with multiple states;

[0006] respectively operate the state machines in different states to obtain m frequency count values, and obtain the system frequency and sampling interrupt timing according to the m frequency count values, m≥4; and

[0007] Based on the system frequency, the maximum value and the minimum value of the frequency count are calculated for use in determining the effective range of the frequency count value next time.

[0008] Furthermore, the setting of a state machine with multiple states specifically includes: setting a state machine in the FPGA, the state machine has at least five states, and the at least five states include an idle state, a first state, a second state, a third state and a fourth state.

[0009] Furthermore, the state machines in different states are operated respectively to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained according to the m frequency count values, where m≥4, specifically including: when the state machine is in an idle state, the positive zero crossing point of the system voltage is detected; if a zero crossing point is detected, the current zero crossing timing value Cnt is assigned to the MonCnt value, wherein the MonCnt value is the frequency count value between two zero crossing points, and the zero crossing timing value Cnt is cleared, and the state of the state machine enters the first state.

[0010] Furthermore, the state machine in different states is operated separately to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained based on the m frequency count values, m≥4, and also includes: when the state machine is in the first state, it is determined whether the current MonCnt value is within the maximum and minimum value range obtained by the previous frequency count value. If so, the current MonCnt value and the previous three frequency count values ​​are stored, that is, four valid frequency count values, and the state of the state machine enters the second state.

[0011] Furthermore, the state machines in different states are operated separately to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained based on the m frequency count values, m≥4, and also include: when the state machine is in the first state, it is determined whether the current MonCnt value is within the maximum and minimum value range obtained by the previous frequency count value; if not, the current MonCnt value is discarded, and the state of the state machine enters the fourth state.

[0012] Furthermore, when the state machine is in the second state, the four stored valid frequency count values ​​are added to obtain a frequency value, and at the same time, the state of the state machine enters the third state.

[0013] Furthermore, when the state machine is in the third state, a counting average value MonCnt_aver between two zero crossing points is calculated based on the frequency value, and a system frequency and a sampling interrupt timing are calculated according to the counting average MonCnt_aver, and the state of the state machine enters the fourth state.

[0014] Furthermore, based on the system frequency, the maximum and minimum values ​​of the frequency count are calculated for use in determining the next valid range of the frequency count value, specifically including: when the state machine is in the fourth state, the maximum and minimum values ​​of the current frequency count value are calculated for use in determining the next valid range of the frequency count value, and then the state machine returns to the idle state to wait for the next positive zero crossing of the system voltage.

[0015] Furthermore, after setting the state machine with multiple states and before operating the state machines in different states respectively, it includes: adding 1 to the zero-crossing timing variable Cnt each time entering the detection, so as to detect the count between two zero-crossing points and calculate the system frequency accordingly.

[0016] In addition, the present invention also proposes a hardware phase-locking device for implementing the hardware phase-locking method as described above, comprising: an FPGA, a voltage detection module and a frequency calculation module; the FPGA is used to implement a state machine and the state transition of the state machine; the voltage detection module is used to detect the positive zero-crossing point of the system voltage; the frequency calculation module is used to calculate the system frequency and the sampling interrupt timing according to the counting average value MonCnt_aver.

[0017] Furthermore, it also includes an abnormal value discarding module, which is used to discard the abnormal count value when an abnormal count value is detected.

[0018] Through the above technical solution, the present invention has the following beneficial effects:

[0019] By setting a state machine with multiple states; operating the state machines in different states respectively, obtaining m frequency count values, and obtaining the system frequency and sampling interrupt timing according to the m frequency count values, m≥4; and calculating the maximum and minimum values ​​of the frequency count based on the system frequency for judging the effective range of the next frequency count value. By optimizing the FPGA, the present invention can solve the problem of abnormal phase and frequency detection when the system voltage is deeply dropped or the zero crossing point is offset due to harmonics in the traditional hard phase lock, thereby being able to adapt to the changes in the power grid environment during the deep voltage drop and recovery process, and ensuring the stable operation of the equipment under extreme conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the impact of hardware synchronization filtering circuit in the prior art;

[0021] Figure 2 A schematic diagram of a voltage drop recovery phase detection anomaly in the prior art;

[0022] Figure 3 is a flow chart of a hardware phase locking method in one embodiment of the present invention;

[0023] Figure 4 A specific flow chart of a hardware phase-locking method in one embodiment of the present invention;

[0024] Figure 5 The hardware phase-locking operation waveform diagram in the hardware phase-locking method in one embodiment of the present invention. DETAILED DESCRIPTION

[0025] A hardware phase-locking method and device of the present invention will be described below in conjunction with a schematic diagram, wherein a preferred embodiment of the present invention is shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0026] The serial numbers of the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0027] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0028] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0029] With the rapid development of new energy technologies, the power system has higher and higher requirements for power quality. As a key device connecting new energy and the power grid, the control accuracy of the grid-connected inverter directly affects the power quality and system stability. In the control process of the grid-connected inverter, it is necessary to accurately obtain the frequency and phase information of the system voltage to achieve precise control of current reference components such as active current, reactive current, negative sequence current and harmonic current.

[0030] At present, the frequency detection of hardware phase-locked is mainly detected by counting the duration of adjacent zero-crossing points. Generally, the system voltage is relatively stable, so the frequency detection is relatively normal. However, when the voltage drops deeply, at the time of occurrence and recovery, the filtering on the hardware synchronization will cause the zero-crossing point to shift, thereby affecting the correct detection of frequency and phase, resulting in abnormal reference current.

[0031] For example, in Figure 1In the hardware synchronous filter circuit influence diagram shown in the figure, the delay of the filter circuit will cause the zero crossing point to shift when the voltage drops and recovers. Figure 2 As shown in the figure, in the actual measurement of a cascaded SVG (Static Var Generator), an abnormal system voltage phase calculation occurred during the process of recovering from low voltage to normal voltage, thereby affecting the normal reference and output current. Figure 2 A is the system voltage waveform, B is the phase waveform, C is the reference current waveform, and D is the output current waveform. In addition, Figure 2 5.00V, 5.00V (with an inverted arrow on the left, indicating that the channel signal is inverted for the convenience of observation), 1.00V and 1.00V represent the voltage values ​​represented by the two horizontal dashed lines of each channel. RMS represents the effective value of the four channel signals; Z20.0ms represents the time span represented by the two vertical dashed lines; 140000s represents the position of the cursor (not shown in the figure for the sake of simplicity); -2.16V represents the trigger level of the waveform.

[0032] In order to solve the above problems, the present invention proposes an improved hardware phase-locking method. This method improves the frequency and phase detection accuracy in the case of deep voltage drop or harmonic interference by optimizing FPGA software, thereby ensuring the normality of reference and output currents and improving the control performance and power quality of the grid-connected inverter.

[0033] like Figure 3-Figure 4 As shown, the embodiment of the present invention proposes a hardware phase locking method, which specifically includes the following steps:

[0034] S1. Set a state machine with multiple states;

[0035] S2. respectively operate the state machines in different states to obtain m frequency count values, and obtain the system frequency and sampling interrupt timing according to the m frequency count values, m≥4; and

[0036] S3. Based on the system frequency, the maximum value and the minimum value of the frequency count are calculated for use in determining the effective range of the frequency count value next time.

[0037] This embodiment is specifically implemented in FPGA (Field Programmable Gate Array), and the process is performed once at each rising edge of the external crystal oscillator, for example, at a frequency of 50M, it is performed once every 20ns. Therefore, this embodiment, through the combination of step S1, step S2 and step S3, that is, mainly through the method of modifying the FPGA software, and the modification is easy and the cost is low, can solve the problem of abnormal phase and frequency detection when the system voltage is offset due to a deep drop or harmonics causing the zero crossing point to shift in the traditional hard phase lock.

[0038] This embodiment takes four frequency count values ​​as an example, which can make the calculated system frequency more accurate. Those skilled in the art will appreciate that the number of frequency count values ​​can be multiple, and the more frequency count values ​​there are, the more accurate the calculation result will be, but it will lead to a longer update delay. Therefore, this embodiment preferably takes four frequency count values ​​as an example to avoid increasing the update delay.

[0039] In step S1, the setting of a state machine (CntState) with multiple states specifically includes: setting a state machine in the FPGA, the state machine having at least five states, the at least five states including an idle state (idle), a first state (state1), a second state (state2), a third state (state3) and a fourth state (state4). The state setting of the state machine can be manually selected and set according to actual needs. For example, the fifth state and the sixth state can also be set according to actual needs. Except in the case of interference or abnormal conditions, this embodiment does not need to enter the fifth state or the sixth state. If interference or abnormal conditions occur, this implementation will initialize it to the idle state, that is, the idle state. How to enter a new state and the specific implementation logic can be set according to actual needs, and the logic of the first state to the fourth state of this embodiment can also be referred to.

[0040] In this embodiment, after setting the state machine with multiple states, the state machines in different states are operated separately, including: each time entering the detection, the zero-crossing timing variable Cnt is first increased by 1 to detect the count between two zero-crossing points and calculate the system frequency accordingly.

[0041] In step S2, the state machines in different states are operated respectively to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained according to the m frequency count values, m≥4, specifically including: when the state machine is in an idle state, the positive zero crossing point of the system voltage is detected; if the zero crossing point is detected, the current zero crossing timing value Cnt is assigned to the MonCnt value, wherein the MonCnt value is the frequency count value between the two zero crossing points, and the zero crossing timing value Cnt is cleared, and the state of the state machine enters the first state. If the zero crossing point is not detected, the current process is terminated, and the state of the state machine remains unchanged.

[0042] In this embodiment, the state machines in different states are operated separately to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained based on the m frequency count values, m≥4, and also include: when the state machine is in the first state, it is determined whether the current MonCnt value is within the maximum and minimum value range obtained by the previous frequency count value (that is, the previous MonCnt value, the value appearing before the current MonCnt value), and if so, the current MonCnt value and the previous three frequency count values ​​are stored, that is, four valid frequency count values, and the state of the state machine enters the second state.

[0043] Among them, the MonCnt value (i.e., frequency count value) is obtained multiple times. Only when the current MonCnt value is within the maximum and minimum value range of the previous MonCnt value can it be regarded as a valid frequency count value and can be stored. Therefore, the four frequency count values ​​refer to the four consecutive valid frequency count values ​​before the voltage crosses the zero point this time; whether the current frequency count value is valid is determined by the maximum and minimum value range obtained by the previous frequency count value (the frequency count value may be invalid).

[0044] Furthermore, the state machines in different states are operated separately to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained based on the m frequency count values, m≥4, and also include: when the state machine is in the first state, it is determined whether the current MonCnt value is within the maximum and minimum value range obtained by the previous frequency count value. If not, the current MonCnt value is discarded (discarded by the abnormal value discarding module), and the state of the state machine enters the fourth state.

[0045] In this embodiment, when the state machine is in the second state, the four stored valid frequency count values ​​are added to obtain a frequency value, and the state of the state machine enters the third state.

[0046] In this embodiment, the state machine is in the third state, and the counting average value MonCnt_aver between two zero crossing points is calculated based on the frequency value, that is, the average value of the four valid frequency count values ​​is calculated, and the system frequency and sampling interrupt timing are calculated according to the counting average MonCnt_aver, and at the same time, the state of the state machine enters the fourth state.

[0047] In step S3, the maximum and minimum values ​​of the frequency count are calculated based on the system frequency for use in determining the next valid range of the frequency count value, specifically including: when the state machine is in the fourth state, the maximum and minimum values ​​of the current frequency count value are calculated for use in determining the next valid range of the frequency count value, and then the state machine returns to the idle state to wait for the next positive zero crossing of the system voltage.

[0048] Therefore, compared with the traditional hardware phase-locked, this embodiment has the following two main optimizations: first, the average value of four consecutive zero-crossing timings is taken to reduce the deviation fluctuation of a single count, making the frequency calculation and interrupt timing more stable; second, the occasional abnormal count value is discarded to avoid the impact caused by deep drops or harmonics.

[0049] In addition, this embodiment also proposes a hardware phase locking device for implementing the hardware phase locking method as described above, including: an FPGA arranged on a designated device (eg, a grid-connected inverter), a voltage detection module, and a frequency calculation module.

[0050] Specifically, the FPGA is used to implement the state machine and the state transition of the state machine; the voltage detection module is used to detect the positive zero-crossing point of the system voltage; and the frequency calculation module is used to calculate the system frequency and sampling interrupt timing according to the counting average value MonCnt_aver.

[0051] Furthermore, this embodiment also includes an abnormal value discarding module, which is used to discard the abnormal count value when an abnormal count value is detected.

[0052] In this embodiment, a cascaded SVG (Static Var Generator) is taken as an example. In addition to being applied to the cascaded SVG, this embodiment can also be applied to grid-connected converters such as PCS (Power Conversion System) and photovoltaic inverters that need to be connected to the power grid.

[0053] First, assume that the grid frequency is 50.05Hz and the FPGA crystal oscillator is 50MHz. The count value between two zero-crossing points is MonCnt, and the average value MonCnt_aver calculated by taking four consecutive values ​​is about 999000; the control program samples 80 points per cycle, so the interval count of the interrupt count is 12487. Secondly, before a voltage drop, the count MonCnt count is 999055, so the maximum and minimum values ​​of the current frequency are 1000055 and 998055 respectively. Due to the influence of sampling filtering, the count MonCnt delay of the first zero-crossing point of the voltage drop is 1020408. Because it exceeds the current frequency range, the count value is discarded and not used for average value calculation; but the maximum and minimum values ​​of the current frequency are updated to 1021408 and 1019408 respectively. Then, the second zero-crossing count MonCnt is reduced to 980392. Since it is still not within the current maximum and minimum frequency range, the count value is still discarded, and the maximum and minimum values ​​of the current frequency are updated to 981392 and 979392 respectively. The third zero-crossing count MonCnt is 999050. Since it is not within the current maximum and minimum frequency range, it is still discarded. At the same time, the maximum and minimum values ​​of the current frequency are updated to 1000050 and 998050 respectively. Then, the fourth zero-crossing count MonCnt is 999048. Since this number is within the maximum and minimum frequency range, it can be used as a valid frequency count value for calculating the frequency average value. The maximum and minimum values ​​of the current frequency are updated to 1000048 and 998048 respectively. By analogy, continue to take the zero-crossing count MonCnt, and obtain multiple valid frequency count values, store the multiple valid frequency count values ​​and the fourth zero-crossing count MonCnt, and perform subsequent average value calculations to obtain the system frequency and sampling interrupt timing.

[0054] After that, the voltage sampling enters a stable and normal stage. The above method can filter out a certain large frequency fluctuation caused by voltage drop or interference, making the device run more smoothly.

[0055] also, Figure 5 The figure shows the measured waveform of a cascaded SVG after adopting this method. Figure 5 A is the system voltage waveform, B is the phase waveform, C is the reference current waveform, and D is the output current waveform. Figure 2 Compared with the waveform shown in Figure 1, when the system voltage phase is restored from low voltage to normal voltage, there is no abnormality in the corresponding reference current and output current, and the waveform transition is smooth. Figure 55.00V, 5.00V (with an inverted arrow on the left, indicating that the channel signal is inverted for observation convenience), 1.00V and 1.00V represent the voltage values ​​represented by the two horizontal dashed lines of each channel. RMS represents the effective value of the four channel signals; 100ms represents the time span represented by the two vertical dashed lines; -432.000ms represents the cursor position (not shown in the figure for simplicity); -2.16V represents the trigger level of the waveform.

[0056] In summary, the hardware phase-locking method and device proposed in the present invention have the following advantages:

[0057] By setting a state machine with multiple states; operating the state machines in different states respectively, obtaining m frequency count values, and obtaining the system frequency and sampling interrupt timing according to the m frequency count values, m≥4; and calculating the maximum and minimum values ​​of the frequency count based on the system frequency for judging the effective range of the next frequency count value. By optimizing the FPGA, the present invention can solve the problem of abnormal phase and frequency detection when the system voltage is deeply dropped or the zero crossing point is offset due to harmonics in the traditional hard phase lock, thereby being able to adapt to the changes in the power grid environment during the deep voltage drop and recovery process, and ensuring the stable operation of the equipment under extreme conditions.

[0058] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A hardware phase-locking method, characterized in that: The details include: Set up a state machine with multiple states; The state machines in different states are operated respectively to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained according to the m frequency count values, where m≥4; as well as Based on the system frequency, the maximum value and the minimum value of the frequency count are calculated for use in determining the effective range of the frequency count value next time.

2. The hardware phase-locking method according to claim 1, characterized in that: The setting of a state machine with multiple states specifically includes: setting a state machine in the FPGA, the state machine has at least five states, and the at least five states include an idle state, a first state, a second state, a third state and a fourth state.

3. The hardware phase-locking method according to claim 2, characterized in that: The state machines in different states are operated respectively to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained according to the m frequency count values, where m≥4, and specifically include: when the state machine is in an idle state, the positive zero crossing point of the system voltage is detected; if the zero crossing point is detected, the current zero crossing timing value Cnt is assigned to the MonCnt value, wherein the MonCnt value is the frequency count value between two zero crossing points, and the zero crossing timing value Cnt is cleared, and the state of the state machine enters the first state.

4. The hardware phase-locking method according to claim 3, characterized in that: The state machines in different states are operated respectively to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained according to the m frequency count values, m≥4, and also include: when the state machine is in the first state, it is determined whether the current MonCnt value is within the maximum and minimum value range obtained by the previous frequency count value, and if so, the current MonCnt value and the previous three frequency count values ​​are stored, that is, four valid frequency count values, and the state of the state machine enters the second state.

5. The hardware phase-locking method according to claim 4, characterized in that: The state machines in different states are operated respectively to obtain m frequency count values, and the system frequency and sampling interrupt timing are obtained according to the m frequency count values, m≥4, and also include: when the state machine is in the first state, it is determined whether the current MonCnt value is within the maximum and minimum value range obtained by the previous frequency count value; if not, the current MonCnt value is discarded, and the state of the state machine enters the fourth state.

6. The hardware phase-locking method according to claim 5, characterized in that: When the state machine is in the second state, the four stored valid frequency count values ​​are added to obtain a frequency value, and the state of the state machine enters the third state.

7. The hardware phase locking method according to claim 6, characterized in that: When the state machine is in the third state, the counting average value MonCnt_aver between two zero crossing points is calculated based on the frequency value, and the system frequency and sampling interrupt timing are calculated according to the counting average value MonCnt_aver, and the state of the state machine enters the fourth state.

8. The hardware phase-locking method according to claim 7, characterized in that: The method of calculating the maximum and minimum values ​​of the frequency count based on the system frequency for determining the next valid range of the frequency count value specifically includes: when the state machine is in the fourth state, calculating the maximum and minimum values ​​of the current frequency count value for determining the next valid range of the frequency count value, and then returning the state machine to the idle state to wait for the next positive zero crossing of the system voltage.

9. The hardware phase locking method according to claim 8, characterized in that: After setting the state machine with multiple states and before operating the state machines in different states respectively, it includes: adding 1 to the zero-crossing timing variable Cnt each time entering the detection, so as to detect the count between two zero-crossing points and calculate the system frequency accordingly.

10. A hardware phase locking device, used to implement the hardware phase locking method according to any one of claims 1 to 9, characterized in that: It includes: FPGA, voltage detection module and frequency calculation module; the FPGA is used to realize the state machine and the state conversion of the state machine; the voltage detection module is used to detect the positive zero crossing point of the system voltage; the frequency calculation module is used to calculate the system frequency and sampling interrupt timing according to the counting average value MonCnt_aver.

11. The hardware phase-locking device according to claim 10, characterized in that: It also includes an abnormal value discarding module, which is used to discard the abnormal count value when an abnormal count value is detected.

Images