Complete cycle time delay compensation method and unit applied to antenna array signal synthesis

Abstract

The invention discloses a whole-cycle time delay compensation method and unit applied to antenna array signal synthesis, and the method comprises the steps: obtaining the compensation whole-cycle number of each antenna in an antenna array according to the time delay, needing to be compensated, of each antenna in the antenna array for receiving a signal; and by taking a system clock period as a unit and combining the compensation integer number of the antennas in the antenna array, performing integer time delay compensation on the signals received by the antennas in the antenna array. According to the invention, the time delay of the signal can be effectively compensated, so that the antenna array can efficiently complete signal synthesis.

Description

Technical Field

[0001] The present invention relates to the field of antenna array technology, and in particular to an integer delay compensation method and unit applied to antenna array signal synthesis. Background Art

[0002] Deep space exploration has important application value in modern astronomy, space geodesy, space technology and other fields. Since the target of deep space exploration is far away, the signal transmitted from the deep space target to the ground observation station is very weak. In order to ensure that the ground antenna can receive the data of deep space exploration, the receiving antenna generally adopts two technical solutions. One is to build a large-aperture antenna. Another technical solution is to build multiple small-aperture antennas and synthesize the signals received by these small-aperture antennas into a receiving signal equivalent to a large-aperture antenna through the method of antenna array. Since small-aperture antenna arrays have the characteristics of low construction cost, simple equipment maintenance and flexible use, they are increasingly valued in deep space exploration technology and have become a hot area in deep space exploration technology in recent years.

[0003] In antenna array systems, a key issue is how to synthesize the signals received by each antenna in the array into one signal. Since the delays of the signals received by each antenna in the antenna array system vary greatly, if only the phase compensation method is used to synthesize the signal, the synthesized signal will be distorted, causing problems in the back-end signal processing. Therefore, when the antenna array is performing signal synthesis, the delay of each antenna signal must be compensated. Summary of the invention

[0004] In view of this, the present invention provides a whole-cycle delay compensation method and unit applied to antenna array signal synthesis, which can effectively compensate for the signal delay, so as to facilitate the antenna array to efficiently complete signal synthesis.

[0005] The present invention discloses a whole cycle delay compensation method applied to antenna array signal synthesis, which comprises:

[0006] According to the delay that needs to be compensated for the signal received by each antenna in the antenna array, the compensation integer number of each antenna in the antenna array is obtained; taking the system clock period as a unit and combining the compensation integer number of each antenna in the antenna array, the integer delay compensation is performed on the signal received by each antenna in the antenna array.

[0007] Furthermore, obtaining the number of compensated integer cycles of each antenna in the antenna array according to the time delay required to be compensated for receiving a signal by each antenna in the antenna array includes:

[0008] The ratio of the time delay required to compensate for the signal received by each antenna in the antenna array to the system clock period is rounded up, and the rounded result is the number of compensation cycles for each antenna in the antenna array.

[0009] Furthermore, the method for obtaining the time delay required to be compensated for receiving a signal by each antenna in the antenna array includes:

[0010] The total delay of receiving signals by each antenna in the antenna array is obtained, and the maximum value is selected from all the total delays obtained. The maximum value is subtracted from the total delays of all antennas in the antenna array. The obtained differences are the delays to be compensated for the corresponding antennas. The total delay is the sum of the spatial delay and the delay of the device itself.

[0011] Furthermore, the step of performing integer delay compensation on a signal received by each antenna in the antenna array in units of a system clock cycle and a compensation integer number of each antenna in the antenna array includes:

[0012] Determine the number of system clock cycles for delaying the received signal of each antenna according to the maximum value of the compensation delay required for the received signal of each antenna in the antenna array;

[0013] The signals received by each antenna in the antenna array are delayed by p times the system clock cycle. According to the number of compensated integer cycles of each antenna, one signal is selected from the delayed signals for output, thus completing the integer delay compensation for the antenna received signal.

[0014] Furthermore, the step of determining the number of system clock cycles for delaying the received signal of each antenna according to the maximum value of the compensation delay required for the received signal of each antenna in the antenna array includes:

[0015] The ratio of the maximum value of the delay compensation required for each antenna receiving signal in the antenna array to the system clock cycle is rounded, and the rounded result is summed with the preset value. The summed result is the number of system clock cycles for delaying the signal received by each antenna.

[0016] Furthermore, the maximum value of the delay compensation required for each antenna in the antenna array to receive the signal is the sum of the maximum relative spatial delay difference of each antenna in the antenna array and the maximum device relative delay difference of each antenna in the antenna array.

[0017] Furthermore, the method for obtaining the maximum relative spatial delay difference of each antenna of the antenna array is:

[0018] According to the minimum elevation angle of the antenna, the maximum value of the distance between any two antennas in the antenna array and the speed of light, the maximum relative spatial delay difference of each antenna in the antenna array is obtained.

[0019] Further, selecting a signal to output from the delayed signals according to the number of compensation cycles of each antenna includes:

[0020] For each antenna in the antenna array, if p corresponding to the delayed signal is equal to the number of compensated integer cycles, the delayed signal is output as a signal after integer delay compensation.

[0021] The present invention also discloses an integer delay compensation unit applied to antenna array signal synthesis, which is used to implement any of the integer delay compensation methods applied to antenna array signal synthesis as described above, including a delay memory and an integer delay compensation selection switch connected in sequence; the delay memory includes a plurality of storage units connected in series in sequence, and the output of each storage unit is connected to the integer delay compensation selection switch.

[0022] Furthermore, the storage unit is used to delay the signal received by each antenna in the antenna array input thereto by one system clock cycle; the first storage unit among a plurality of sequentially connected storage units is used to receive the signal received by each antenna in the antenna array; the integer delay compensation selection switch is used to select a signal output from the delayed signal according to the number of compensation integer cycles of each antenna, thereby completing the integer delay compensation for the antenna received signal.

[0023] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0024] 1. The present invention solves the problem of delay compensation for antenna array signal synthesis. The present invention converts the delay value to be compensated for each antenna receiving signal into the number of whole cycles of the system clock by adopting a normalized delay processing algorithm, and completes the whole cycle delay compensation for each antenna receiving signal of the antenna array according to the method provided by the present invention. The method provided by the present invention can ensure the delay compensation requirements for the synthesis of antenna array receiving signals, solving a key problem in the design of array antenna systems.

[0025] 2. Simple implementation, less resource occupation, and reduced system design cost. The present invention does not require complex circuits, and the implementation method is relatively simple. The present invention only uses the original equipment of the system without adding additional equipment, and realizes the full-cycle delay compensation function of each antenna receiving signal through a software algorithm, which is convenient for automatic operation and reduces the system design cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0027] Figure 1 It is a schematic diagram of the antenna array system receiving the signal and processing it.

[0028] Figure 2 It is a principle block diagram of array signal synthesis of antenna array system.

[0029] Figure 3 It is a principle block diagram of a signal integer delay compensation unit of an antenna array system.

[0030] Figure 4 It is a principle block diagram of the delay memory of the signal integer delay compensation unit of the antenna array system.

[0031] Figure 5 It is a flow chart of integer delay compensation applied to signal synthesis of antenna array system. DETAILED DESCRIPTION

[0032] The present invention is further described in conjunction with the accompanying drawings and embodiments, and the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present invention.

[0033] The present invention provides an embodiment of a method for compensating an integer delay applied to antenna array signal synthesis, which includes:

[0034] According to the delay that needs to be compensated for the signal received by each antenna in the antenna array, the compensation integer number of each antenna in the antenna array is obtained; taking the system clock period as a unit and combining the compensation integer number of each antenna in the antenna array, the integer delay compensation is performed on the signal received by each antenna in the antenna array.

[0035] In this embodiment, obtaining the number of compensated integer cycles of each antenna in the antenna array according to the delay required to be compensated for receiving a signal by each antenna in the antenna array includes:

[0036] The ratio of the time delay required to compensate for the signal received by each antenna in the antenna array to the system clock period is rounded up, and the rounded result is the number of compensation cycles for each antenna in the antenna array.

[0037] In this embodiment, a method for obtaining a delay required to be compensated for a signal received by each antenna in the antenna array includes:

[0038] The total delay of receiving signals by each antenna in the antenna array is obtained, and the maximum value is selected from all the total delays obtained. The maximum value is subtracted from the total delays of all antennas in the antenna array. The obtained differences are the delays to be compensated for the corresponding antennas. The total delay is the sum of the spatial delay and the delay of the device itself.

[0039] In this embodiment, the whole cycle delay compensation for the signal received by each antenna in the antenna array is performed in units of system clock cycles and in combination with the compensation whole cycle number of each antenna in the antenna array, including:

[0040] Determine the number of system clock cycles for delaying the received signal of each antenna according to the maximum value of the compensation delay required for the received signal of each antenna in the antenna array;

[0041] The signals received by each antenna in the antenna array are delayed by p times the system clock cycle. According to the number of compensated integer cycles of each antenna, one signal is selected from the delayed signals for output, thus completing the integer delay compensation for the antenna received signal.

[0042] In this embodiment, the step of determining the number of system clock cycles for delaying the received signal of each antenna according to the maximum value of the compensation delay required for the received signal of each antenna in the antenna array includes:

[0043] The ratio of the maximum value of the delay compensation required for each antenna receiving signal in the antenna array to the system clock cycle is rounded, and the rounded result is summed with the preset value. The summed result is the number of system clock cycles for delaying the signal received by each antenna.

[0044] In this embodiment, the maximum value of the compensation delay required for each antenna in the antenna array to receive the signal is the sum of the maximum relative spatial delay difference of each antenna in the antenna array and the maximum device relative delay difference of each antenna in the antenna array.

[0045] In this embodiment, the method for obtaining the maximum relative spatial delay difference of each antenna in the antenna array is:

[0046] According to the minimum elevation angle of the antenna, the maximum value of the distance between any two antennas in the antenna array and the speed of light, the maximum relative spatial delay difference of each antenna in the antenna array is obtained.

[0047] In this embodiment, selecting a signal to output from the delayed signals according to the number of compensation cycles of each antenna includes:

[0048] For each antenna in the antenna array, if p corresponding to the delayed signal is equal to the number of compensated integer cycles, the delayed signal is output as a signal after integer delay compensation.

[0049] The present invention also provides an embodiment of an integer delay compensation unit applied to antenna array signal synthesis, which is used to implement the integer delay compensation method applied to antenna array signal synthesis described in the above embodiment, and includes a delay memory and an integer delay compensation selection switch connected in sequence; the delay memory includes a plurality of storage units connected in series in sequence, and the output of each storage unit is connected to the integer delay compensation selection switch.

[0050] In this embodiment, the storage unit is used to delay the signal received by each antenna in the antenna array input thereto by one system clock cycle; the first storage unit among multiple sequentially connected storage units is used to receive the signal received by each antenna in the antenna array; the integer delay compensation selection switch is used to select a signal output from the delayed signal according to the number of compensation integer cycles of each antenna, thereby completing the integer delay compensation for the antenna received signal.

[0051] For ease of understanding, the present invention provides a more specific embodiment:

[0052] See also Figure 1 ,like Figure 1 As shown in the figure, the antenna array consists of antennas A1, A2, ... to An. n is the total number of antennas in the antenna array. When receiving the target signal, due to the different paths from the signal to each antenna of the antenna array and the differences between each antenna, the delay of each received signal is different. Assuming that the target transmitted signal is s(t), the signals received by antennas A1, A2, ..., Ak, ..., An are s(t-t1), s(t-t2), ..., s(tt n ), where t1, t2, …, t n They are the sum of the spatial delay of the signals received by antennas A1, A2, …, Ak, …, An and the device delay of the device itself. The spatial delay can be calculated through the position information of the antenna and the target, and the device delay of the antenna itself can be obtained by calibrating the antenna.

[0053] From the principle of signal synthesis, signal synthesis can be completed by adjusting the signal delays received by each antenna to be consistent, that is:

[0054]

[0055] Among them, t max for t1, t2, …, t k ,…,t n The maximum value in t max =max(t1,t2,…,t k ,…,t n ), formula (1) is the basic formula for antenna array signal synthesis.

[0056] According to formula (1), let Δt1 = t max -t1,Δt2=t max -t2,…,Δt k =t max -t k ,…,Δt n =t max -t n, are the time delays that need to be compensated for the signals received by antennas A1, A2, …, Ak, …, An, that is, the time delays that need to be compensated theoretically when the signals received by each antenna are synthesized.

[0057] Although the best array signal synthesis can be obtained theoretically according to the basic formula (1) for antenna array signal synthesis, it is impossible to accurately process the delay of the signals of each antenna according to formula (1) in real devices. In view of this, a processing method for whole-cycle delay compensation is proposed, that is, according to the small clock cycle T processed by the device, the delay difference of the signals received by each antenna of the antenna array is adjusted to be less than T. On this basis, the signal synthesis of the antenna array can be completed by adjusting the phase of each antenna signal.

[0058] See also Figure 2 ,like Figure 2 As shown, the signals received by antennas A1, A2, ..., Ak, ..., An are respectively subjected to digital A / D sampling processing, and the digitized signals are sent to the same FPGA mathematical signal processing chip for signal processing: first, the sampling signal of each antenna is first sent to the signal whole cycle delay compensation unit to complete the whole cycle delay compensation processing; then, the signal after the whole cycle delay compensation processing is sent to the signal synthesis unit to complete the signal synthesis.

[0059] Here, the signal whole cycle delay compensation unit is to compensate the integer multiple time delay of T in the unit of system clock period T, that is, to compensate m for antenna k k T time delay, that is, the signal compensation algorithm for antenna k is as follows:

[0060] s k (t) = s(tt k -m k ·T)

[0061] Among them, t k is the delay of antenna k receiving the signal; m k is an integer greater than or equal to 0, which is the compensation cycle number of antenna k, m k The calculation is based on the following algorithm:

[0062]

[0063] Among them, Δt k is the delay required to compensate for the received signal of antenna k; T is the system clock period.

[0064] Next, the signal after delay compensation is synthesized according to a conventional method of synthesizing a phase-controlled signal, and finally the array signal is synthesized.

[0065] See also Figure 3 and Figure 4 ,like Figure 3 As shown in the figure, the signal whole cycle delay compensation unit includes a delay memory and a whole cycle delay compensation selection switch. The delay memory includes n ′ It is composed of n series storage units, which transmit the signal s(t) received by the antenna in series according to the control of the system clock. ′ storage units, and simultaneously converts the input signal into n ′ delayed signals s(tT),s(t-2T),…,s(t-kT),…,s(tn ′ T) is sent to the full-cycle delay compensation selection switch, and the compensation full-cycle number m is calculated. k , through the whole cycle delay compensation selection switch, from n ′ The delay storage unit corresponds to n ′ Among the delayed signals, select k The delay signal corresponding to the equal delay is output. For example, if m k If it is 3, then the whole cycle delay compensation selection switch is changed from n ′ Select s(t-3T) from the delayed signals and output it.

[0066] The maximum storage number n of the delay memory designed for the system ′ The value is chosen and calculated according to the following algorithm:

[0067]

[0068] Where T is the system clock period; Δt max The maximum value of the compensation delay required for each antenna to receive the signal when the antenna array is working, that is, Δt max =max(Δt1,Δt2,…,Δt k ,…,Δt n ). Calculate Δt according to the following algorithm: max :

[0069] Δt max =Δ space t max +Δ Equipment t max

[0070] Among them, Δ space t max is the maximum relative spatial delay difference of each antenna in the antenna array; Δ device t max is the maximum relative delay difference of each antenna in the antenna array. ΔDevice t max It can be obtained by calibrating each antenna in the antenna array; Δ space t max It can be obtained according to the following algorithm

[0071]

[0072] Among them, Lmax is the maximum baseline length of the antenna array, that is, the maximum distance between two antennas in the antenna array; θ is the minimum elevation angle of the antenna; c is the speed of light.

[0073] For example, the maximum relative delay difference of a certain antenna array obtained by calibration is Δdevice t max = 20ns, the maximum baseline length of the linear array is L max = 100 meters, the minimum elevation angle of the antenna is θ = 5 degrees, the system clock frequency is 500MHz, that is, the system clock period is 2ns. According to the above formula, the maximum relative spatial delay difference of each antenna in the antenna array can be calculated as: Δ spatial t max =33.206ns, so the maximum value of the delay that the line array needs to compensate is Δt max =53.206ns. The maximum number of storage units in the delay memory designed for this antenna array is n ′ =27.

[0074] The working principle of delay memory is as follows Figure 4 As shown, the delay memory contains n ′ There are a total of 3 storage units connected in series, where storage unit 1 receives the signal s(t) sent from the antenna. ′ Each serial storage unit is stimulated by the system clock, that is, at each rising edge of the system clock, the storage unit will send the stored data to the next level storage unit and output it to the outside, and then update the data of the storage unit, and store the data sent by the previous level storage unit (or the data sent by the antenna) in the storage unit. ′ The output data is s(tT) to s(tn ′ T).

[0075] See also Figure 5 The steps of the whole cycle delay compensation of the antenna array are as follows: first, the signals received by each antenna of the antenna array are sampled by digital A / D, and then the sampled digitized signals are sent to the FPGA for array signal synthesis, and then the whole cycle delay compensation is performed on the digital signals received by each antenna respectively, and finally the signals that have completed the whole cycle delay compensation are synthesized.

[0076] Among them, the maximum number of delay storage units n of the delay memory of the whole cycle delay compensation unit of each antenna receiving signal ′ According to the maximum baseline length L of the antenna array max and the maximum relative delay difference of each antenna in the antenna array Δdevice t max And designed according to the given algorithm. Each antenna receives the target signal according to the delay t kAnd the system clock period T and calculate the compensation integer number of each antenna according to a given algorithm, and use it to control the integer delay compensation unit of each signal to complete.

[0077] Finally, the signals of all antennas in the antenna array after the full-cycle delay compensation are synthesized to complete the signal synthesis of the entire antenna array.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for compensating an integer delay applied to antenna array signal synthesis, characterized in that: include: According to the time delay required to be compensated for receiving signals by each antenna in the antenna array, the number of compensated integer cycles of each antenna in the antenna array is obtained; Taking the system clock cycle as a unit and combining the compensation integer number of each antenna in the antenna array, integer delay compensation is performed on the signal received by each antenna in the antenna array.

2. The method for compensating for integer delay applied to antenna array signal synthesis according to claim 1, characterized in that: The step of obtaining the number of compensated integer cycles of each antenna in the antenna array according to the time delay required to be compensated for receiving a signal by each antenna in the antenna array includes: The ratio of the time delay required to compensate for the signal received by each antenna in the antenna array to the system clock period is rounded up, and the rounded result is the number of compensation cycles for each antenna in the antenna array.

3. The method for compensating for integer delay applied to antenna array signal synthesis according to claim 1 or 2, characterized in that: The method for obtaining the time delay required to be compensated for receiving a signal by each antenna in the antenna array includes: The total delay of receiving signals by each antenna in the antenna array is obtained, and the maximum value is selected from all the total delays obtained. The maximum value is subtracted from the total delays of all antennas in the antenna array. The obtained differences are the delays to be compensated for the corresponding antennas. The total delay is the sum of the spatial delay and the delay of the device itself.

4. The method for compensating for integer delay applied to antenna array signal synthesis according to claim 1, characterized in that: The method of performing integer delay compensation on a signal received by each antenna in the antenna array in units of a system clock cycle and a compensation integer number of each antenna in the antenna array includes: Determine the number of system clock cycles for delaying the received signal of each antenna according to the maximum value of the compensation delay required for the received signal of each antenna in the antenna array; The signals received by each antenna in the antenna array are delayed by p times the system clock cycle. According to the number of compensated integer cycles of each antenna, one signal is selected from the delayed signals for output, thus completing the integer delay compensation for the antenna received signal.

5. The method for compensating for integer delay applied to antenna array signal synthesis according to claim 4, characterized in that: The step of determining the number of system clock cycles for delaying the received signal of each antenna according to the maximum value of the compensation delay required for the received signal of each antenna in the antenna array comprises: The ratio of the maximum value of the delay compensation required for each antenna receiving signal in the antenna array to the system clock cycle is rounded, and the rounded result is summed with the preset value. The summed result is the number of system clock cycles for delaying the signal received by each antenna.

6. The method for compensating for integer delay applied to antenna array signal synthesis according to claim 4, characterized in that: The maximum value of the compensation delay required for each antenna in the antenna array to receive the signal is the sum of the maximum relative spatial delay difference of each antenna in the antenna array and the maximum device relative delay difference of each antenna in the antenna array.

7. The method for compensating for integer delay applied to antenna array signal synthesis according to claim 6, characterized in that: The method for obtaining the maximum relative spatial delay difference of each antenna of the antenna array is: According to the minimum elevation angle of the antenna, the maximum value of the distance between any two antennas in the antenna array and the speed of light, the maximum relative spatial delay difference of each antenna in the antenna array is obtained.

8. The method for compensating for integer delay applied to antenna array signal synthesis according to claim 4, characterized in that: The step of selecting a signal to output from the delayed signals according to the number of compensation cycles of each antenna includes: For each antenna in the antenna array, if p corresponding to the delayed signal is equal to the number of compensated integer cycles, the delayed signal is output as a signal after integer delay compensation.

9. An integer delay compensation unit applied to antenna array signal synthesis, used to implement the integer delay compensation method applied to antenna array signal synthesis according to any one of claims 1 to 8, characterized in that: It includes a delay memory and a whole cycle delay compensation selection switch connected in sequence; the delay memory includes a plurality of storage units connected in series in sequence, and the output of each storage unit is connected to the whole cycle delay compensation selection switch.

10. The integer delay compensation unit for antenna array signal synthesis according to claim 9, characterized in that: The storage unit is used to delay the signal received by each antenna in the antenna array input thereto by one system clock cycle; the first storage unit among the plurality of sequentially connected storage units is used to receive the signal received by each antenna in the antenna array; The integer delay compensation selection switch is used to select a signal output from the delayed signals according to the compensation integer number of each antenna, that is, to complete the integer delay compensation of the antenna receiving signal.

Images