Vehicle-mounted sensor data reinjection time synchronization method based on FPGA

Abstract

The invention belongs to the field of automotive electronics, and relates to a vehicle-mounted sensor data reinjection time synchronization method based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: when a system is initially operated, each daughter card sends a timestamp of a first data packet to the main card; the main card gathers timestamp information and adopts the earliest timestamp as the sending start time of each daughter card; the main card determines the actual clock frequency of the daughter card and adjusts the timing length of the timer; the main card and the daughter cards realize clock synchronization calibration through multi-stage calibration and periodic calibration; according to the method, the parallel processing and accurate calibration mechanism of the FPGA is utilized, high-precision time synchronization of multi-sensor data is achieved, the method is suitable for a vehicle-mounted sensor system with the high time precision requirement, and the performance and reliability of a data reinjection system are remarkably improved.

Description

Technical Field

[0001] The invention belongs to the field of automotive electronics, and in particular relates to a vehicle-mounted sensor data re-injection time synchronization method based on FPGA. Background Art

[0002] Before realizing intelligent driving, it is essential to conduct comprehensive vehicle safety testing and simulation. One of the key links is to test and simulate the vehicle using on-board sensor back-injection equipment. These devices can capture various data when the vehicle is running and transmit this data back to the test center or server for analysis and evaluation. Therefore, it is crucial to develop an efficient and reliable automotive data back-injection system.

[0003] In the data collection process, both offline data collected on the road and hardware-in-the-loop (HIL) simulation data are generated by different sensors or simulation algorithms, resulting in strong temporal heterogeneity of the data. Camera video data, ultrasonic radar, lidar and other data are often collected based on different clock sources. This temporal heterogeneity poses a great challenge to the time synchronization of data when conducting automobile safety driving tests and intelligent driving simulations.

[0004] In order to obtain accurate results during testing and simulation, the data streams of different sensors need to be time synchronized. The accuracy of time synchronization directly determines the test and simulation performance during back injection. If the time synchronization is inaccurate, it may cause data inconsistency, thus affecting the reliability of the test results. Therefore, it is crucial to extract the timestamps of the data streams of each channel and perform high-precision time synchronization. Summary of the invention

[0005] In order to solve the problems existing in the above prior art, the present invention proposes a vehicle-mounted sensor data injection time synchronization method based on FPGA, which includes: constructing a vehicle-mounted sensor injection system, which includes an FPGA daughter card and an FPGA main card; the FPGA daughter card realizes the functions of sensor data reception, timing time calculation, sensor data storage and data timing transmission; the FPGA main card completes the system initial time determination, maintenance of the global reference clock, and daughter card time calibration functions;

[0006] When the system is running, each FPGA sub-card sends the timestamp of the first data packet received to the FPGA main card. The main card summarizes the timestamps of each sub-card and uses the earliest timestamp of each sub-card as the initial sending time and returns it to each sub-card.

[0007] Determine the actual frequency of the daughter card clock through the clock comparison method, and adjust the timing length of the daughter card timer;

[0008] The sub-card receives sensor data packets in a fixed frame format, calculates the timestamp difference between adjacent data packets, and determines whether the timestamp difference is incorrect. If the timestamp difference is incorrect, the data packet sequence is disordered and the data packet is discarded; if the timestamp difference is correct, the data packet is sent to the main card on a regular basis;

[0009] Multi-level calibration is used between the main card and the sub-card to achieve clock calibration.

[0010] Beneficial effects of the present invention:

[0011] The present invention utilizes the parallel processing capability and high-precision clock synchronization mechanism of FPGA to ensure high-precision time synchronization of multi-sensor data and improve the performance and reliability of the data injection system. The method is particularly suitable for intelligent driving testing and simulation environments and can effectively improve the overall efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a flow chart of the FPGA-based vehicle-mounted sensor data injection time synchronization method of the present invention;

[0013] Figure 2 It is a schematic diagram of the sensor data packet frame structure of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] A method for FPGA-based on-vehicle sensor data injection time synchronization, such as Figure 1 As shown, the method includes: the FPGA daughter card realizes the functions of sensor data reception, timing time calculation, sensor data storage and data timing transmission; the FPGA main card completes the system initial time determination, maintenance of the global reference clock, and daughter card time calibration;

[0016] The main card uses a weighted average algorithm to determine the system initial time. The sub-card receives the sensor data packet and extracts the timestamp information in the sensor data packet; extracts the timestamp of the first received data packet and transmits the extracted timestamp information to the main card. Different sensors have different weight values, and the main card determines the system initial time through weighted average.

[0017] The main card and the sub-card use multi-level calibration to calibrate the clock. When the sensor sub-card works for the first time, the main card performs a global calibration. The main card performs periodic calibration at preset intervals. For sensors with high time accuracy, the main card monitors the time difference between sensors in real time, and immediately triggers a local calibration for sensors that deviate from the global reference time to resynchronize the data time of the sensor.

[0018] In a single daughter card, the daughter card receives sensor data packets in a fixed frame format and determines whether the timestamp difference is within a reasonable range by calculating the timestamp difference between adjacent data packets. If the timestamp of a data packet differs too much from the timestamps of the previous and next data packets, the daughter card may consider that the data packet is out of order or has a timestamp error and process the data packet.

[0019] In this embodiment, the frame header identifier is used to identify the start of the frame; the frame check code is used to check the integrity and correctness of the data frame; the sensor type is used to identify the type of sensor, such as camera, ultrasonic radar, laser radar, etc.; the sensor configuration is used to identify the specific configuration parameters of the sensor; the sensor channel number is used to distinguish different sensor channels; the data packet timestamp is used to record the time point when the data packet is generated; the sensor data is used to record the data generated by the sensor path sampling or simulation; the frame end identifier is used to identify the end of the frame. The frame structure is as follows: Figure 2 shown.

[0020] In this embodiment, the data packet receiving and processing steps are specifically as follows: different sub-cards receive the data packets serially, detect the frame header and frame tail identifiers, extract and cache the sensor type Stype, sensor configuration information Smess, data packet timestamp information T_send, and channel number N_ID in the data packet according to the frame structure.

[0021] Furthermore, the initial time synchronization step of the system is as follows: the FPGA main card summarizes the earliest timestamp information between each sub-card as the initial sending time, and the sub-card sensor uses relative time for timing sending.

[0022] The clock frequency of the main card is f a , determine the actual frequency f of the daughter card clock by clock comparison method b In a fixed time interval T, the master card clock counts N a , the clock count of the daughter card is N b , then the actual frequency of the daughter card clock is f b It can be calculated by the following formula:

[0023]

[0024] Through this calculation method, the actual frequency of the daughter card clock can be accurately determined and used to calculate the number of timing times.

[0025] Furthermore, clock synchronization is achieved between the main card and the sub-card through multi-level calibration, and periodic calibration is performed regularly during system operation.

[0026] S1: When the system is initially working, the subcard calculates the weighted average timestamp based on the main card and performs a global clock calibration.

[0027] S2: The main card sends a calibration signal to each sub-card at a preset interval. The calibration cycle is short for video sensors and radar sensors with high time accuracy, and long for ultrasonic sensors with low time accuracy.

[0028] S3: The master card can monitor the time differences between sensors in real time. Once it finds that the timer timestamp of a sensor starts to deviate from the global reference time, that is, exceeds the set threshold, it immediately triggers a local calibration to resynchronize the data time of the sensor;

[0029] Specifically, the subcard sends multiple sensor channel data in parallel. Each subcard opens a buffer BRAM for each channel. Each buffer BRAM can cache a maximum of 150 data packets of the channel, and a sending timer is set for each channel.

[0030] Each channel data packet calculates whether the time is reasonable based on the timestamp. The data packet after the timing calculation is stored in the BRAM corresponding to each sensor, including the timing duration, sensor data, and the channel wr_index of the number of data packets written. When a new data packet is written to each channel, the wr_index corresponding to the channel is incremented automatically.

[0031] The position of the data packet sent, rd_index, is incremented each time the data packet is sent. Each channel uses a first-in, first-out mechanism to send data packets.

[0032] Each sensor channel sends data packets according to first-in-first-out. Specifically, the wr_index and rd_index increment range is 0-149. When wr_index and rd_index increase to 149, after writing a new data packet, wr_inedx and rd_index become 0; the number of data packets to be read in the BRAM is calculated. When there are more than or equal to 148 data packets in the buffer BRAM, the data packet processing at the front end of the data stream is stopped, that is, data is stopped from being sent to the BRAM of each sensor channel; when wr_index is greater than rd_index, the number of data packets to be read in the BRAM is: numpack = wr_index-rd_index; when wr_index is less than rd_index, the number of data packets to be read in the BRAM is: numpack = wr_index+150-rd_index.

[0033] Determine whether the timestamp of the data packet of each channel is reasonable. For ultrasonic sensors that are not sensitive to time accuracy, perform time error correction and record the difference between the last 10 time increments. For incorrect timestamps, modify them to the last sending time plus the increment time. Specifically:

[0034] S1: Record the incremental difference ΔT of the last 10 timestamps i =T i -T i-1 ,i=1,2,3,…,10;

[0035] S2: Calculate the average of the time difference

[0036] S3: When the timestamp T of a data packet is detected err In case of error, the timestamp is modified to the last sending time T 10 Add average increment time ΔT avg , T err_correct =T 10 +ΔT avg ;

[0037] S4: The timestamp of the next data packet with an incorrect timestamp is not modified, it is sent according to the current timestamp, and the average of the time differences is recalculated.

[0038] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A vehicle-mounted sensor data injection time synchronization method based on FPGA, characterized in that: include: Construct a vehicle-mounted sensor back-injection system, which includes an FPGA daughter card and an FPGA main card; the FPGA daughter card realizes the functions of sensor data reception, timing time calculation, sensor data storage, and data timing transmission; the FPGA main card completes the system initial time determination, maintenance of the global reference clock, and daughter card time calibration; When the system is running, each FPGA sub-card sends the timestamp of the first data packet received to the FPGA main card. The main card summarizes the timestamps of each sub-card and uses the earliest timestamp of each sub-card as the initial sending time and returns it to each sub-card. Determine the actual frequency of the daughter card clock through the clock comparison method, and adjust the timing length of the daughter card timer; The daughter card receives sensor data packets in a fixed frame format, calculates the timestamp difference between adjacent data packets, and determines whether the timestamp difference is incorrect. If the timestamp difference is incorrect, the data packet sequence is disordered and the data packet is discarded. If the timestamp difference is correct, the data packet is sent to the master card on time; Multi-level calibration is used between the main card and the sub-card to achieve clock calibration.

2. According to the FPGA-based vehicle sensor data injection time synchronization method of claim 1, it is characterized in that: Determining the actual frequency of the daughter card clock by the clock comparison method includes: obtaining the clock frequency f of the main card a , get the master card's clock count N within a fixed time interval T a and the daughter card clock count is N b ; Calculate the actual frequency of the daughter card clock according to the main card clock frequency, the main card clock count and the daughter card clock count.

3. The FPGA-based vehicle sensor data injection time synchronization method according to claim 1 is characterized in that: The timestamp information in the sensor data packet includes: detecting the frame header and frame tail identifiers of the sensor data packet, extracting and caching the sensor type, sensor configuration information, data packet timestamp information T_send, and channel number N_ID in the data packet according to the frame structure.

4. The FPGA-based vehicle sensor data injection time synchronization method according to claim 1 is characterized in that: Determining whether the timestamp difference is incorrect includes: S1, record the timestamp T of the last data packet of channel i i,last_send ; S2. Get the timestamp T of the data packet sent by the current channel i i,now_send , judge T i,now_send Is it greater than T i,last_send , if yes, then send the data packet, otherwise it is considered that the sensor data packet of channel i in the data packet does not need to be sent; S3. Calculate the timestamp difference ΔT=T i,now_send -T i,last_send ; S4. Set a threshold to determine whether the timestamp difference ΔT is greater than the threshold. If the data packet is out of sequence or has a timestamp error, the subcard marks the data packet as abnormal and processes the abnormal data packet.

5. The method for FPGA-based on-vehicle sensor data injection time synchronization according to claim 1, characterized in that: Processing of abnormal data packets includes: Step 1: Record the incremental difference ΔT of the last 10 timestamps i =T i -T i-1 ,i=1,2,3,…,10; Step 2: Calculate the average of the time difference Step 3: When the timestamp T of the data packet is detected err In case of error, the timestamp is modified to the last sending time T 10 Add average increment time ΔT avg , T err_correct =T 10 +ΔT avg ; Step 4: For the next data packet with an incorrect timestamp, send it according to the current timestamp and start recalculating the mean of the time difference.

6. The FPGA-based vehicle sensor data injection time synchronization method according to claim 1, characterized in that: Each sensor channel of the daughter card uses the BRAM resources of the FPGA to cache the transmitted data packets and adopts the FIFO mechanism to send the data packets.

7. The FPGA-based vehicle sensor data injection time synchronization method according to claim 1, characterized in that: Multi-level calibration includes: global calibration, periodic calibration and local calibration.

8. The FPGA-based vehicle sensor data injection time synchronization method according to claim 7, characterized in that: The specific steps for multi-level calibration are: Step 1: When the system is initially working, the sub-card calculates the initial timing timestamp based on the main card and performs a global clock calibration; Step 2: The main card sends a calibration signal to each sub-card once at a preset interval; Step 3: The main card monitors the time difference between each sensor in real time. When the sensor's timer timestamp deviates from the global reference time, that is, exceeds the set threshold, a local calibration is performed to resynchronize the sensor's data time.

9. The FPGA-based vehicle sensor data injection time synchronization method according to claim 7, characterized in that: The periodic calibration cycle is: judge the time accuracy of the sensor. When the time accuracy of the sensor is high, set the calibration cycle to T1; when the time accuracy of the sensor is low, set the calibration cycle to T2, and T1 <T2。

Images