Passive clock synchronization method and system for distributed relay protection equipment

Abstract

The invention relates to the technical field of power systems, and provides a passive clock synchronization method and system for distributed relay protection equipment, and the method comprises the steps: calculating the communication channel delay between a host and a slave, and executing the next step when the channel delay calculation is correct; checking the time of the host and the slave to synchronize the time of each slave; calculating the sampling beat time difference of the host and the slave; the sampling rhythm of the slave is adjusted, so that the sampling rhythms of the slave and the host are consistent in real time, and passive clock synchronization of the host and the slave is completed. According to the scheme of the invention, the passive clock synchronization method has the following advantages: the distance between the host and the slave is not limited, as long as the data transmission delay between the host and the slave is fixed or measurable; meanwhile, clock synchronization and beat synchronization of equipment in a local area are realized; the frequency is stable in the equipment beat adjusting process, and the synchronization precision between equipment is high; accidental data interruption does not affect sampling beat synchronization and time synchronization between devices.

Description

Technical Field

[0001] The present invention relates to the technical field of power systems, and in particular to a passive clock synchronization method and system for distributed relay protection equipment. Background Art

[0002] The reliable operation of the power system is the basis for the normal operation of modern society. However, the reliability of the power system depends largely on the precise time and beat synchronization between the various components in the system. In the operation of modern power grids, there are many complex automation equipment and protection equipment, which require a common time reference point in order to accurately execute data sampling and protection control commands, as well as to record various key events in detail. At the same time, the progress of clock synchronization technology has not only greatly improved the monitoring capability of the power grid, so that the operating status of the power system can be monitored and analyzed in real time, but also optimized the allocation of power resources, making the power supply more efficient and reasonable. However, the clock synchronization source is often interfered by external factors, causing the system to lose the synchronization source signal. Therefore, passive synchronization technology will enhance the stability of the entire power system, so that the system can maintain a good operating state when facing various external clock source interferences, and reduce the probability of failure.

[0003] There are two main methods for adjusting the beat of passive synchronization of sampling data between traditional devices:

[0004] Synchronization error first beat compensation method: This method compensates all synchronization errors in the first beat of the timing signal received. Its advantage is fast beat adjustment, but its disadvantage is that the first beat cycle adjustment is too large, and the beat frequency jumps every time the timing is synchronized, which is not conducive to the operation of the back-end protection algorithm.

[0005] Synchronous error step-by-step compensation method: This method calculates the time data for each beat to be compensated after receiving the first beat of the timing signal, and adjusts each beat based on this compensation data in the later period. Its advantage is that the adjusted beat frequency is stable, but its disadvantage is that the compensation data is usually not an integer multiple of the beat frequency, and the beat adjustment of each timing cycle has overshoot, so the beat adjustment accuracy is low. Summary of the invention

[0006] The purpose of the present invention is to solve at least one technical problem in the background technology and to provide a passive clock synchronization method and system for distributed relay protection equipment.

[0007] To achieve the above object, the present invention provides a passive clock synchronization method for distributed relay protection equipment, comprising:

[0008] Calculate the communication channel delay between the host and the slave. When the channel delay calculation is correct, proceed to the next step.

[0009] Check the time of the master and slaves to synchronize the time of each slave;

[0010] Calculate the sampling beat time difference between the host and the slave;

[0011] Adjust the sampling rhythm of the slave to make the sampling rhythm of the slave consistent with that of the host in real time, and complete the passive clock synchronization of the host and slave.

[0012] According to one aspect of the present invention, the communication channel delay between the computing host and the slave is:

[0013] Before the sampling beat is synchronized, the host m1 Send a frame of information to the slave at any time, which includes the current time stamp of the host and the calculated channel delay t d The slave device receives the command and then delays t m The time will be the current time stamp and delay time t m The information is sent back to the host. Since the information transmission path is the same, the transmission delay between the host and the slave is the same. The time when the host receives the returned information is t r2 , calculate the channel delay t as follows d ;

[0014]

[0015] Host delay t` m Then the calculated result t d and delay t` m Send it to the slave; after receiving the information sent by the master again, the slave calculates the channel delay t` in the same way as the master d .

[0016] According to one aspect of the present invention, the channel delay is calculated correctly as follows:

[0017] Will t` d t transmitted by host computer d When the difference between the two is smaller than the empirical data A, it is determined that the communication process is correct and the channel delay calculation is correct.

[0018] According to one aspect of the present invention, the time of the master and slaves is checked to synchronize the time of each slave as follows:

[0019] The system uses the absolute time of the host as the standard to calibrate the time of each slave. During the calculation and measurement of channel delay, the host transmits its own absolute time to the peer slave. The slave uses the absolute time of the host and the channel delay t d Modify its own time to achieve time synchronization of each slave.

[0020] According to one aspect of the present invention, the computing host and slave sampling beat time difference is:

[0021] The beat time is based on the host time. The host is at the current beat time t mj will include the channel delay t d A frame of information including the beat adjustment command is sent to the slave, and the slave receives the information based on the time t r3 and t d First, we can determine t mj The corresponding beat time t on this side si , and then calculate the sampling beat time difference Δt between the host and the slave according to the following formula:

[0022] Δt=t si -t mj =t si -(t r3 -t d );

[0023] Among them, t si For mj The closest slave beat time, Δt>0 means the master beat is ahead of the slave, Δt<0 means the master beat is behind the slave.

[0024] According to one aspect of the present invention, the step of adjusting the slave sampling rhythm comprises:

[0025] When the slave is not synchronized, the system beat frequency of the slave is f, which is generated by the internal crystal oscillator clock. A pulse is generated every Ts count value: T S =T1 / f, T1 is the frequency of the device crystal oscillator;

[0026] In 1 second, the sampling beat time difference Δt is evenly distributed to f beats, x digital quantities are adjusted in each beat, and x+1 digital quantities are adjusted in each z beats. After the number of beats for adjusting x+1 digital quantities reaches y, only x digital quantities are adjusted in each beat, and x+1 digital quantities are no longer adjusted. The calculation formulas for x, y, and z are:

[0027]

[0028] The slave repeats the previous step every 1 second to adjust the sampling rhythm.

[0029] According to one aspect of the present invention, when the synchronization time difference between the master and slave is less than 1us, that is, when |Δt| is less than the digital constant C, the T2 value is recorded and updated to the T1 value. When the data channel is accidentally interrupted, the beat pulse can be combined with the updated T1 value according to the formula T S =T1 / f is generated, and the whole second digital quantity T2 after the beat adjustment in synchronization can be expressed as: T2=T1-Δt.

[0030] Furthermore, to achieve the above object, the present invention also provides a passive clock synchronization system for distributed relay protection equipment, comprising:

[0031] The channel delay measurement module calculates the communication channel delay between the host and the slave. When the channel delay calculation is correct, the next step is executed;

[0032] The slave time synchronization module checks the time of the master and slaves to synchronize the time of each slave;

[0033] The time difference calculation module calculates the sampling beat time difference between the host and the slave;

[0034] The passive clock synchronization module adjusts the sampling rhythm of the slave to make the sampling rhythm of the slave consistent with that of the host in real time, thus completing the passive clock synchronization of the host and the slave.

[0035] Furthermore, to achieve the above-mentioned purpose, the present invention also provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the passive clock synchronization method for distributed relay protection equipment as described above is implemented.

[0036] Furthermore, to achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the passive clock synchronization method for distributed relay protection equipment as described above is implemented.

[0037] According to the solution of the present invention, a high-precision passive clock synchronization method for distributed relay protection equipment is proposed, which aims to solve the problem that traditional relay protection equipment cannot ensure time and sampling rhythm synchronization after the external synchronization source is lost and the timekeeping phase is exited.

[0038] According to the solution of the present invention, the passive clock synchronization method of the present invention combines the two methods of data channel synchronization and accurate and uniform full compensation of beats, and includes two synchronization functions of sampling beats and time. The present invention calculates the data transmission delay and the sampling beat time difference between the master and slave machines through the sending and arrival time of data between the master and slave machines in the channel. Each slave machine then uses the accurate and uniform full compensation method of beats to adjust the sampling beat, reduce the sampling beat time difference between the master and slave machines, and realize the sampling beat synchronization between devices. At the same time, each slave machine can synchronize itself according to the absolute time of the master machine and the channel transmission delay to realize the time synchronization of the equipment.

[0039] According to the solution of the present invention, the passive clock synchronization method of the present invention has the following advantages:

[0040] There is no distance limit between the host and the slave. The devices can be a few meters to tens of kilometers apart, as long as the data transmission delay between the host and the slave is fixed or measurable;

[0041] At the same time, realize the clock synchronization and beat synchronization of local equipment;

[0042] The frequency is stable during the equipment beat adjustment process, and the synchronization accuracy between devices is high;

[0043] Occasional data interruptions do not affect the sampling rhythm synchronization and time synchronization between devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A flowchart schematically showing a passive clock synchronization method for a distributed relay protection device according to an embodiment of the present invention;

[0045] Figure 2 A schematic diagram showing a passive clock synchronization principle block diagram according to an embodiment of the present invention;

[0046] Figure 3 Schematically showing a data channel delay measurement principle diagram according to an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of a sampling beat time difference measurement principle according to an embodiment of the present invention is shown;

[0048] Figure 5 The diagram schematically shows a sampling beat synchronization adjustment diagram according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention will now be discussed with reference to exemplary embodiments. It should be understood that the embodiments discussed are only to enable those skilled in the art to better understand and thus implement the present invention, rather than implying any limitation on the scope of the present invention.

[0050] As used herein, the term “including” and variations thereof are to be interpreted as open-ended terms meaning “including, but not limited to.” The term “based on” is to be interpreted as “based, at least in part, on.” The terms “one embodiment” and “an embodiment” are to be interpreted as “at least one embodiment.”

[0051] Figure 1 The flowchart schematically shows a passive clock synchronization method for distributed relay protection equipment according to an embodiment of the present invention. Figure 1 As shown, in this embodiment, the passive clock synchronization method for distributed relay protection equipment includes:

[0052] Calculate the communication channel delay between the host and the slave. When the channel delay calculation is correct, proceed to the next step.

[0053] Check the time of the master and slaves to synchronize the time of each slave;

[0054] After the time of each slave is synchronized, the sampling beat time difference between the master and slave is calculated;

[0055] Adjust the sampling rhythm of the slave to make the sampling rhythm of the slave consistent with that of the host in real time, and complete the passive clock synchronization of the host and slave.

[0056] Further, Figure 2 The following schematically shows a block diagram of a passive clock synchronization principle according to an embodiment of the present invention. Figure 2 As shown, in this embodiment, in order to achieve passive clock synchronization between devices, a data channel synchronization method must first be used. In this embodiment, the data channel synchronization method is essentially a data channel delay measurement, which provides data support for its subsequent sampling beat time adjustment. Figure 3 As shown, the inherent sampling beat frequency of the host and the slave is the same, and the beat interval is T s , controlled by a crystal oscillator. m1 ,t m2 ,t m3 is the time scale corresponding to the host beat time point, t s1 ,t s2 ,t s3 It is the time stamp corresponding to the slave machine's beat moment.

[0057] Based on this, the steps of data channel delay measurement include:

[0058] Calculate the communication channel delay between the master and slave:

[0059] Before the sampling beat is synchronized, the host m1 Send a frame of information to the slave at any time, which includes the current time stamp of the host and the calculated channel delay t d The slave device receives the command and then delays t m The time will be the current time stamp and delay time t m The information is sent back to the host. Since the information transmission path is the same, the transmission delay between the host and the slave is the same. The time when the host receives the returned information is t r2 , calculate the channel delay t as follows d ;

[0060]

[0061] Host delay t` m Then the calculated result t d and delay t` mSend it to the slave; after receiving the information sent by the master again, the slave calculates the channel delay t` in the same way as the master d .

[0062] Determine whether the channel delay calculation is correct:

[0063] Will t` d t transmitted by host computer d When the difference between the two is less than the empirical data A (taking a 100MHz crystal oscillator as an example, to meet the 1us synchronization accuracy, A is taken as 100), it is determined that the communication process is correct and the channel delay calculation is correct, then the subsequent beat adjustment process will begin, otherwise the above process will be automatically repeated.

[0064] Further, according to an embodiment of the present invention, the time of the master and the slaves is checked so that the time of each slave is synchronized as follows:

[0065] The system uses the absolute time of the host as the standard to calibrate the time of each slave. During the calculation and measurement of channel delay, the host transmits its own absolute time to the peer slave. The slave uses the absolute time of the host and the channel delay t d Modify its own time to achieve time synchronization of each slave.

[0066] Further, according to an embodiment of the present invention, the sampling beat time difference between the host and the slave is calculated as:

[0067] like Figure 4 As shown in the figure, the beat time is based on the host time. The host is at the current beat time t mj will include the channel delay t d A frame of information including the beat adjustment command is sent to the slave, and the slave receives the information based on the time t r3 and t d First, we can determine t mj The corresponding beat time t on this side si , and then calculate the sampling beat time difference Δt between the host and the slave according to the following formula:

[0068] Δt=t si -t mj =t si -(t r3 -t d );

[0069] Among them, t si For mj The closest slave beat time, Δt>0 means the master beat is ahead of the slave, Δt<0 means the master beat is behind the slave. In order to synchronize the master and slave sampling beats, the slave will make a precise and uniform full compensation adjustment of the beat starting from the next beat.

[0070] Further, according to an embodiment of the present invention, the beat accurate uniform full compensation adjustment method adopts the time difference average amortization adjustment method, which divides the sampling beat time difference Δt of the master and slave equally into one second for adjustment, so that the beat interval time changes slightly, and fundamentally avoids the beat frequency mutation problem in the synchronization process. In this embodiment, specifically adjusting the sampling beat of the slave includes:

[0071] like Figure 5 As shown, when the slave is not synchronized, the slave system beat frequency is f, which is generated by the internal crystal oscillator clock, and a pulse is generated every Ts count value: T S =T1 / f, T1 is the frequency of the device crystal oscillator;

[0072] Furthermore, based on the above data channel synchronization method, the sampling beat time difference between the master and slave is obtained as Δt (assuming Δt>0). The sampling beat time difference Δt is evenly distributed to f beats within 1 second, as follows: Figure 5 As shown, x digital quantities are adjusted in each beat, x+1 digital quantities are adjusted in each z beats, and after the number of beats for adjusting x+1 digital quantities reaches y, only x digital quantities are adjusted in each beat, and x+1 digital quantities are no longer adjusted. The calculation formulas for x, y, and z are:

[0073]

[0074] The slave repeats the previous step every 1 second to adjust the sampling rhythm.

[0075] In passive clock synchronization technology, the host sampling beat remains relatively independent, and the slave adjusts in real time according to the host sampling beat. In order to ensure that the clocks on both sides are always consistent and the sampling beat time is consistent in real time, both sides need to perform time calibration and sampling beat synchronization control regularly.

[0076] Further, according to an embodiment of the present invention, when the synchronization time difference between the master and the slave is less than 1us, that is, when |Δt| is less than the digital constant C, the T2 value is recorded and updated to the T1 value. When the data channel is accidentally interrupted, the beat pulse can be combined with the updated T1 value according to the formula T S =T1 / f is generated, and the whole second digital quantity T2 after the beat adjustment in synchronization can be expressed as: T2=T1-Δt.

[0077] According to the above scheme of the present invention, the present invention proposes a high-precision passive clock synchronization method for distributed relay protection equipment, which aims to solve the problem that traditional relay protection equipment cannot ensure time and sampling rhythm synchronization after the external synchronization source is lost and the timekeeping phase is exited.

[0078] According to the above scheme of the present invention, the passive clock synchronization method of the present invention combines the two methods of data channel synchronization and accurate and uniform full compensation of beats, and includes two synchronization functions of sampling beats and time. The present invention calculates the data transmission delay and the sampling beat time difference between the master and slave machines through the sending and arrival time of the data between the master and the slave in the channel. Each slave machine then uses the accurate and uniform full compensation method of beats to adjust the sampling beat, reduce the sampling beat time difference between the master and the slave, and realize the sampling beat synchronization between the devices. At the same time, each slave machine can synchronize itself according to the absolute time of the master machine and the transmission delay of the channel to realize the time synchronization of the equipment.

[0079] According to the above solution of the present invention, the passive clock synchronization method of the present invention has the following advantages:

[0080] There is no distance limit between the host and the slave. The devices can be a few meters to tens of kilometers apart, as long as the data transmission delay between the host and the slave is fixed or measurable;

[0081] At the same time, realize the clock synchronization and beat synchronization of local equipment;

[0082] The frequency is stable during the equipment beat adjustment process, and the synchronization accuracy between devices is high;

[0083] Occasional data interruptions do not affect the sampling rhythm synchronization and time synchronization between devices.

[0084] Furthermore, to achieve the above object, the present invention also provides a passive clock synchronization system for distributed relay protection equipment, comprising:

[0085] The channel delay measurement module calculates the communication channel delay between the host and the slave. When the channel delay calculation is correct, the next step is executed;

[0086] The slave time synchronization module checks the time of the master and slaves to synchronize the time of each slave;

[0087] The time difference calculation module calculates the sampling beat time difference between the host and the slave;

[0088] The passive clock synchronization module adjusts the sampling rhythm of the slave to make the sampling rhythm of the slave consistent with that of the host in real time, thus completing the passive clock synchronization of the host and the slave.

[0089] Furthermore, if Figure 2 As shown, in this embodiment, in order to achieve passive clock synchronization between devices, a data channel synchronization method must first be used. In this embodiment, the data channel synchronization method is essentially a data channel delay measurement, which provides data support for its subsequent sampling beat time adjustment. Figure 3 As shown, the inherent sampling beat frequency of the host and the slave is the same, and the beat interval is T s , controlled by a crystal oscillator.m1 ,t m2 ,t m3 is the time scale corresponding to the host beat time point, t s1 ,t s2 ,t s3 is the time stamp corresponding to the slave clock moment. Based on this, the steps of data channel delay measurement include:

[0090] Calculate the communication channel delay between the master and slave:

[0091] Before the sampling beat is synchronized, the host m1 Send a frame of information to the slave at any time, which includes the current time stamp of the host and the calculated channel delay t d The slave device receives the command and then delays t m The time will be the current time stamp and delay time t m The information is sent back to the host. Since the information transmission path is the same, the transmission delay between the host and the slave is the same. The time when the host receives the returned information is t r2 , calculate the channel delay t as follows d ;

[0092]

[0093] Host delay t` m Then the calculated result t d and delay t` m Send it to the slave; after receiving the information sent by the master again, the slave calculates the channel delay t` in the same way as the master d .

[0094] Determine whether the channel delay calculation is correct:

[0095] Will t` d t transmitted by host computer d When the difference between the two is less than the empirical data A (taking a 100MHz crystal oscillator as an example, to meet the 1us synchronization accuracy, A is taken as 100), it is determined that the communication process is correct and the channel delay calculation is correct, then the subsequent beat adjustment process will begin, otherwise the above process will be automatically repeated.

[0096] Further, according to an embodiment of the present invention, the time of the master and the slaves is checked so that the time of each slave is synchronized as follows:

[0097] The system uses the absolute time of the host as the standard to calibrate the time of each slave. During the calculation and measurement of channel delay, the host transmits its own absolute time to the peer slave. The slave uses the absolute time of the host and the channel delay t d Modify its own time to achieve time synchronization of each slave.

[0098] Further, according to an embodiment of the present invention, the sampling beat time difference between the host and the slave is calculated as:

[0099] like Figure 4 As shown in the figure, the beat time is based on the host time. The host is at the current beat time t mj will include the channel delay t d A frame of information including the beat adjustment command is sent to the slave, and the slave receives the information based on the time t r3 and t d First, we can determine t mj The corresponding beat time t on this side si , and then calculate the sampling beat time difference Δt between the host and the slave according to the following formula:

[0100] Δt=t si -t mj =t si -(t r3 -t d );

[0101] Among them, t si For mj The closest slave beat time, Δt>0 means the master beat is ahead of the slave, Δt<0 means the master beat is behind the slave. In order to synchronize the master and slave sampling beats, the slave will make a precise and uniform full compensation adjustment of the beat starting from the next beat.

[0102] Further, according to an embodiment of the present invention, the beat accurate uniform full compensation adjustment method adopts the time difference average amortization adjustment method, which divides the sampling beat time difference Δt of the master and slave equally into one second for adjustment, so that the beat interval time changes slightly, and fundamentally avoids the beat frequency mutation problem in the synchronization process. In this embodiment, specifically adjusting the sampling beat of the slave includes:

[0103] like Figure 5 As shown, when the slave is not synchronized, the slave system beat frequency is f, which is generated by the internal crystal oscillator clock, and a pulse is generated every Ts count value: T S =T1 / f, T1 is the frequency of the device crystal oscillator;

[0104] Furthermore, based on the above data channel synchronization method, the sampling beat time difference between the master and slave is obtained as Δt (assuming Δt>0). The sampling beat time difference Δt is evenly distributed to f beats within 1 second, as follows: Figure 5 As shown, x digital quantities are adjusted in each beat, x+1 digital quantities are adjusted in each z beats, and after the number of beats for adjusting x+1 digital quantities reaches y, only x digital quantities are adjusted in each beat, and x+1 digital quantities are no longer adjusted. The calculation formulas for x, y, and z are:

[0105]

[0106] The slave repeats the previous step every 1 second to adjust the sampling rhythm.

[0107] In passive clock synchronization technology, the host sampling beat remains relatively independent, and the slave adjusts in real time according to the host sampling beat. In order to ensure that the clocks on both sides are always consistent and the sampling beat time is consistent in real time, both sides need to perform time calibration and sampling beat synchronization control regularly.

[0108] Further, according to an embodiment of the present invention, when the synchronization time difference between the master and the slave is less than 1us, that is, when |Δt| is less than the digital constant C, the T2 value is recorded and updated to the T1 value. When the data channel is accidentally interrupted, the beat pulse can be combined with the updated T1 value according to the formula T S =T1 / f is generated, and the whole second digital quantity T2 after the beat adjustment in synchronization can be expressed as: T2=T1-Δt.

[0109] According to the above scheme of the present invention, the present invention proposes a high-precision passive clock synchronization method for distributed relay protection equipment, which aims to solve the problem that traditional relay protection equipment cannot ensure time and sampling rhythm synchronization after the external synchronization source is lost and the timekeeping phase is exited.

[0110] According to the above scheme of the present invention, the passive clock synchronization method of the present invention combines the two methods of data channel synchronization and accurate and uniform full compensation of beats, and includes two synchronization functions of sampling beats and time. The present invention calculates the data transmission delay and the sampling beat time difference between the master and slave machines through the sending and arrival time of the data between the master and the slave in the channel. Each slave machine then uses the accurate and uniform full compensation method of beats to adjust the sampling beat, reduce the sampling beat time difference between the master and the slave, and realize the sampling beat synchronization between the devices. At the same time, each slave machine can synchronize itself according to the absolute time of the master machine and the transmission delay of the channel to realize the time synchronization of the equipment.

[0111] According to the above solution of the present invention, the passive clock synchronization method of the present invention has the following advantages:

[0112] There is no distance limit between the host and the slave. The devices can be a few meters to tens of kilometers apart, as long as the data transmission delay between the host and the slave is fixed or measurable;

[0113] At the same time, realize the clock synchronization and beat synchronization of local equipment;

[0114] The frequency is stable during the equipment beat adjustment process, and the synchronization accuracy between devices is high;

[0115] Occasional data interruptions do not affect the sampling rhythm synchronization and time synchronization between devices.

[0116] Furthermore, to achieve the above objectives, the present invention also provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the passive clock synchronization method for distributed relay protection equipment as described above is implemented.

[0117] Furthermore, to achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the passive clock synchronization method for distributed relay protection equipment as described above is implemented.

[0118] Those skilled in the art will appreciate that the modules and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0119] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and equipment can refer to the corresponding processes in the aforementioned method implementation methods, and will not be repeated here.

[0120] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0121] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0122] In addition, each functional module in the embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0123] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the energy-saving signal sending / receiving method of each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical disks.

[0124] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

[0125] It should be understood that the size of the serial numbers of each step in the content of the invention and the implementation methods of the present invention does not absolutely mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present invention.

Claims

1. A passive clock synchronization method for distributed relay protection equipment, characterized in that: include: Calculate the communication channel delay between the host and the slave. When the channel delay calculation is correct, proceed to the next step. Check the time of the master and slaves to synchronize the time of each slave; Calculate the sampling beat time difference between the host and the slave; Adjust the sampling rhythm of the slave to make the sampling rhythm of the slave consistent with that of the host in real time, and complete the passive clock synchronization of the host and slave.

2. The passive clock synchronization method for distributed relay protection equipment according to claim 1, characterized in that: The communication channel delay between the computing host and the slave is: Before the sampling beat is synchronized, the host m1 Send a frame of information to the slave at any time, which includes the current time stamp of the host and the calculated channel delay t d The slave device receives the command and then delays t m The time will be the current time stamp and delay time t m The information is sent back to the host. Since the information transmission path is the same, the transmission delay between the host and the slave is the same. The time when the host receives the returned information is t r2 , calculate the channel delay t as follows d ; Host delay t` m Then the calculated result t d and delay t` m Send it to the slave; after receiving the information sent by the master again, the slave calculates the channel delay t` in the same way as the master d .

3. The passive clock synchronization method for distributed relay protection equipment according to claim 2, characterized in that: The channel delay is calculated correctly as follows: Will t` d t transmitted by host computer d When the difference between the two is smaller than the empirical data A, it is determined that the communication process is correct and the channel delay calculation is correct.

4. The passive clock synchronization method for distributed relay protection equipment according to claim 1, characterized in that: The time of the master and slaves is checked to synchronize the time of each slave: The system uses the absolute time of the host as the standard to calibrate the time of each slave. During the calculation and measurement of channel delay, the host transmits its own absolute time to the peer slave. The slave uses the absolute time of the host and the channel delay t d Modify its own time to achieve time synchronization of each slave.

5. The passive clock synchronization method for distributed relay protection equipment according to claim 1, characterized in that: The calculation host and slave sampling beat time difference is: The beat time is based on the host time. The host is at the current beat time t mj will include the channel delay t d A frame of information including the beat adjustment command is sent to the slave, and the slave receives the information based on the time t r3 and t d First, we can determine t mj The corresponding beat time t on this side si , and then calculate the sampling beat time difference Δt between the host and the slave according to the following formula: Δt=t si -t mj =t si -(t r3 -t d ); Among them, t si For mj The closest slave beat time, Δt>0 means the master beat is ahead of the slave, Δt<0 means the master beat is behind the slave.

6. The passive clock synchronization method for distributed relay protection equipment according to any one of claims 1 to 5, characterized in that: The step of adjusting the slave sampling rhythm comprises: When the slave is not synchronized, the system beat frequency of the slave is f, which is generated by the internal crystal oscillator clock. s One count value generates one pulse: T S =T1 / f, T1 is the frequency of the device crystal oscillator; In 1 second, the sampling beat time difference Δt is evenly distributed to f beats, x digital quantities are adjusted in each beat, and x+1 digital quantities are adjusted in each z beats. After the number of beats for adjusting x+1 digital quantities reaches y, only x digital quantities are adjusted in each beat, and x+1 digital quantities are no longer adjusted. The calculation formulas for x, y, and z are: The slave repeats the previous step every 1 second to adjust the sampling rhythm.

7. The passive clock synchronization method for distributed relay protection equipment according to claim 6, characterized in that: When the synchronization time difference between the master and slave is less than 1us, that is, |Δt| is less than the digital constant C, the T2 value is recorded and updated to the T1 value. When the data channel is interrupted occasionally, the beat pulse can be combined with the updated T1 value according to the formula T S =T1 / f is generated, and the whole second digital quantity T2 after the beat adjustment in synchronization can be expressed as: T2=T1-Δt.

8. A passive clock synchronization system for distributed relay protection equipment, characterized in that: include: The channel delay measurement module calculates the communication channel delay between the host and the slave. When the channel delay calculation is correct, the next step is executed; The slave time synchronization module checks the time of the master and slaves to synchronize the time of each slave; The time difference calculation module calculates the sampling beat time difference between the host and the slave; The passive clock synchronization module adjusts the sampling rhythm of the slave to make the sampling rhythm of the slave consistent with that of the host in real time, thus completing the passive clock synchronization of the host and the slave.

9. An electronic device, characterized in that The invention comprises a processor, a memory and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the passive clock synchronization method for distributed relay protection equipment as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the passive clock synchronization method for a distributed relay protection device according to any one of claims 1 to 7 is implemented.

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