Video decoding system

Abstract

The invention relates to a video decoding system. The system comprises: a video decoder for decoding a code stream into decoded image blocks; a video postprocessor, wherein the video postprocessor is connected with the video decoder; and the video postprocessor is used for processing the decoded image block and sending the processed decoded image block to a target module. By adopting the method, memory access can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of video decoding, and in particular to a video decoding system. Background Art

[0002] With the official release of the H.264 / AVC video compression protocol in 2003 and its widespread commercial use, the storage and dissemination costs of video content have been reduced, and video content has flourished in multimedia applications. In recent years, compression standards such as HEVC / AVS2 / AV1 have been proposed one after another, and the commonly used video resolution has developed from HD and UHD to 4k, 8k and even 16k. In future applications, immersive viewing is an important development direction of video, and video resolution and frame rate are important indicators of immersive viewing. As video resolution and frame rate increase, the memory access bandwidth per unit time also increases, and bandwidth has become an important bottleneck affecting video playback performance.

[0003] At present, most hardware implementation methods are: the video decoder decodes the video and writes the decoding result to the memory; the video post-processor reads the decoded image in the memory, performs scaling and format conversion, and writes the post-processing result to the memory; the target output module reads the post-processed image from the memory in the order required by itself, and processes it by itself.

[0004] The above process involves a large amount of image reading and writing. The video decoder, video post-processor and target module all require higher bandwidth, which will lead to competition for memory bandwidth. Summary of the invention

[0005] Based on this, it is necessary to provide a video decoding system that can reduce memory access in response to the above technical problems.

[0006] In a first aspect, the present application provides a video decoding system, the system comprising:

[0007] A video decoder, used for decoding a bitstream into a decoded image block;

[0008] A video post-processor is connected to the video decoder; the video post-processor is used to process the decoded image block and send the processed decoded image block to a target module.

[0009] In one of the optional embodiments, the system further comprises:

[0010] A direct-connect processor, wherein the input interface of the direct-connect processor is connected to the output interface of the video decoder, and the output interface of the direct-connect processor is connected to the input interface of the video post-processor; the direct-connect processor is used to receive the decoded image blocks output by the video decoder, and send the decoded image blocks required by the video post-processor to the video post-processor.

[0011] In one of the optional embodiments, the directly connected processor includes:

[0012] A target cache module, used for caching basic image information output by the video decoder;

[0013] The video decoder further comprises a data reading interface, and the video decoder is used to read the loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the basic information of the image from the target cache module through the data reading interface.

[0014] In one of the optional embodiments, the direct-connect processor further includes:

[0015] A controller, the controller is used to read the loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the image basic information from the target cache module based on the data read request sent by the data read interface of the video decoder, and return the read loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the image basic information to the video decoder; store the decoded image block in the target cache module; and read the decoded image block required by the video post-processor from the target cache module, and send the read decoded image block to the video post-processor.

[0016] In one of the optional embodiments, the video decoder is further configured to store the decoded image block into a memory when it is determined that the decoded image block obtained by decoding is a reference frame image block.

[0017] In one of the optional embodiments, the video post-processor includes:

[0018] An image scaling module, used for scaling the decoded image blocks;

[0019] A color space conversion module, used for performing color space conversion on the scaled decoded image block;

[0020] An image splicing module, used for splicing the decoded image blocks after color space conversion;

[0021] Output cache module, used to cache the stitched post-processed images.

[0022] In one of the optional embodiments, the image stitching module is further used to obtain a background image from a memory, and stitch the background image with each of the decoded image blocks after color space conversion.

[0023] In one of the optional embodiments, the video post-processor is further used to send the processed decoded image to the target module based on the output order of the target module.

[0024] In one of the optional embodiments, the number of the video decoders and the directly connected processors is greater than or equal to 2, and each of the video decoders is connected to one of the directly connected processors;

[0025] Each of the direct-connected processors is also connected to at least two of the video post-processors, and each of the video post-processors is respectively connected to a target module.

[0026] In one of the optional embodiments, the number of the video decoders and the directly connected processors is greater than or equal to 2, and each of the video decoders is connected to one of the directly connected processors;

[0027] Each of the direct-connect processors is connected to the same video post-processor.

[0028] The above-mentioned video decoding system includes a video decoder and a video post-processor. The video decoder is used to decode the code stream into a decoded image block, and the video post-processor is connected to the video decoder; the video post-processor is used to process the decoded image block and send the processed decoded image to the target module. In this way, the video post-processor is directly connected to the video decoder, so that the video decoding result can be directly converted into the output required by the target module. There is no need to store the decoded image block in the memory, which saves the bandwidth spent on reading and writing the decoded image block through the memory, thereby avoiding the access delay when the bandwidth is insufficient. Problems such as delay can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] FIG1 is a block diagram of a typical video decoder in conventional technology;

[0031] FIG. 2 is a schematic diagram of a method for implementing hardware video decoding and playback in conventional technology;

[0032] FIG3 is a schematic diagram of a video decoding system in one embodiment;

[0033] FIG4 is a diagram of data interaction between a video decoder and a direct-connect processor in HEVC decoding in one embodiment;

[0034] FIG5 is a block diagram of a video post-processor in one embodiment;

[0035] FIG. 6 is a schematic diagram showing a video decoder connected to multiple video post-processors and multiple video decoders connected to one video post-processor in one embodiment. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] Please refer to Figure 1, which is a typical framework diagram of a video decoder in traditional technology. The input bitstream is entropy decoded to obtain the prediction mode and residual coefficients. Intra-frame / inter-frame prediction is performed according to the prediction mode to obtain the prediction value. The residual coefficient is inversely quantized and inversely transformed to obtain the residual value. The two are added to obtain the reconstructed value, and then the image is decoded through loop filtering. During the decoding process, the bitstream is read from the memory, and the decoded image is written to the decoded image buffer (located in the memory). In addition, some temporary variables of the intermediate process are stored in the memory, such as the motion vector history data required for inter-frame prediction, the upper neighbor of the intra-frame prediction, and the upper boundary temporary data of the loop filter.

[0038] The resolution and output format in the bitstream are specified by the encoder, and the decoder only completes the decompression process of the bitstream. In the actual playback process, the size of the playback window can be freely specified by the user. It is possible to play multiple videos on the screen at the same time, or the video can be played in picture-in-picture mode. In order to generate the screen image, the hardware post-processor and software program need to do the corresponding processing. For example, the decoded image is 4096x2160 resolution, but the user's playback window is 3840x2048; or 4k and 8k images are decoded at the same time and played on the screen at 1080p; or the video source is in YUV format, but it needs to be played in RGB format. In addition, the video image needs to be spliced ​​with the screen background to obtain a complete screen image.

[0039] In addition, as video applications become more and more widespread, the output of video decoding is also used in scenarios such as video format transcoding and AI processor input. The target modules for video output are diverse, and the requirements for video format, size, output order, etc. are also different.

[0040] As shown in FIG. 2 , FIG. 2 is a schematic diagram of a method for implementing hardware video decoding-playback in the conventional technology. As shown in FIG. 2 , the hardware video decoding output is completed by three parts:

[0041] Video decoder: used to decode the code stream defined by video compression standards such as H.264 / HEVC / AVS2 / AV1 into a pixel matrix in YUV format.

[0042] Video post-processor: responsible for post-processing of decoded output images, including scaling, stitching, data format conversion (such as NV12 to ARGB), etc.

[0043] Target module: The target module where the video post-processor outputs the image, which can be a display device, video transcoder, AI processor, etc.

[0044] As shown by the solid arrow, the video decoder is responsible for decompressing the video code stream and writing the decoded image to the memory; the video post-processor reads the decoded image from the memory and performs post-processing, and writes the post-processed output image to the memory; the target module reads the post-processed image from the memory according to its own input definition. In addition, the video decoder and video post-processor also have memory access based on their own algorithms (the video decoder takes HEVC as an example), such as the storage and acquisition of the upper neighbor in the decoder frame, and the acquisition of the screen background image by the post-processor, as shown by the dotted arrow.

[0045] As can be seen from Figure 2, some data in the memory are written first and then read, which causes a waste of memory bandwidth. In order to solve this problem, in combination with Figure 3, the present application provides a video decoding system, which includes a video decoder and a video post-processor, wherein the video post-processor is connected to the video decoder, the video decoder is used to decode the code stream into a decoded image block, the video post-processor is used to process the decoded image block, and send the processed decoded image block to the target module.

[0046] The decoded image blocks output by the video decoder are directly input to the video post-processor without being stored in the memory. This can reduce the memory bandwidth of the video post-processor for reading the decoded image blocks. Similarly, it can also save the bandwidth of writing the decoded image to the memory.

[0047] Another point that needs to be explained is that if the decoded image corresponding to the decoded image block is a reference image, the decoded image needs to be written into the memory. In this case, the write bandwidth of writing the decoded image block into the memory cannot be saved, but at least the memory bandwidth of the video post-processor reading the decoded image block from the memory can be saved.

[0048] In addition, since the video postprocessor sends the processed decoded image blocks to the target module, there is no need for the video postprocessor to first store the processed decoded image blocks in the memory and then the target module reads them from the memory. Therefore, the write memory bandwidth of the video postprocessor writing the processed decoded image blocks to the memory and the read memory bandwidth of the target module reading the processed decoded image blocks from the memory are saved.

[0049] In summary, the video postprocessor is directly connected to the video decoder, so that the video decoding result can be directly converted into the output required by the target module. There is no need to store the decoded image blocks in the memory, which saves the bandwidth spent on reading and writing decoded image blocks through the memory, thereby avoiding problems such as access delay when the bandwidth is insufficient.

[0050] In one of the optional embodiments, the system also includes: a direct-connected processor, the input interface of the direct-connected processor is connected to the output interface of the video decoder, and the output interface of the direct-connected processor is connected to the input interface of the video post-processor; the direct-connected processor is used to receive the decoded image blocks output by the video decoder, and send the decoded image blocks required by the video post-processor to the video post-processor.

[0051] A direct processor is added between the video decoder and the post-processor. The output of the video decoder is input into the direct processor in block order (see the rectangular box mark of the decoded image block in Figure 3). The direct processor packs the pixel values ​​of the area required by the video post-processor and sends them to the video post-processor. After the video post-processor completes the post-processing of the input block, it sends it to the target module in the order required by the target module (see the rectangular box mark of the post-processed image block in Figure 3). In this way, the decoded image block can be directly sent to the target module without passing through the memory, thus saving the reading and writing of the memory.

[0052] In addition to the basic modules specified by the compression algorithm, the video decoder also includes an output interface to the direct-connected processor, which is used to output basic image layer information (width, height, decoding block size, loop filter settings) and block unit information (the coordinates of the decoded image block in the decoded image and its pixel value matrix), so that the decoded data is output to the direct-connected processor according to the decoded image block. The video decoder also includes an interface for reading the upper neighbors of the loop filter from the direct-connected processor. In this way, the decoded image block can be first input to the direct-connected processor, and then the direct-connected processor inputs it to the video post-processor. The entire process does not pass through the memory, which can save memory read and write bandwidth.

[0053] In one of the optional embodiments, the video decoder is further configured to store the decoded image block into a memory when determining that the decoded image block obtained by decoding is a reference frame image block.

[0054] If the current decoded frame is marked as a reference frame, the decoded image must be written to the image cache and used as a reference image for subsequent frames, so the write bandwidth cannot always be saved. Only when the decoded frame is not a reference frame, the corresponding decoded image block is directly output to the direct-connected processor without being written to the memory. At this time, the corresponding memory bandwidth for reading and writing memory can be saved, which not only avoids the video decoder from writing to the memory, but also avoids the video post-processor from reading the decoded image frame from the memory.

[0055] In one of the optional embodiments, the direct-connected processor includes: a target cache module for caching basic image information output by a video decoder; the video decoder also includes a data reading interface, and the video decoder is used to read loop filtering upper neighbor data and intra-frame prediction upper neighbor data in the basic image information from the target cache module through the data reading interface.

[0056] Among them, the data such as the upper neighbor of the loop filter is stored in the target cache module of the direct-connected processor, so that the video decoder can directly read the data such as the upper neighbor of the loop filter from the direct-connected processor without reading from the memory, which saves the memory read and write bandwidth. That is, if the upper neighbor data of the loop filter is stored in the target cache module of the direct-connected processor, it can save the bandwidth of temporarily storing the unfiltered pixel points of the upper neighbor in the decoded image, and reading from the decoded image after the decoding unit at the same horizontal position in the next row completes the decoding, and updating the decoded image. In addition, the upper neighbor data of the intra-frame prediction. It has the same value as the last row of data of the upper neighbor of the loop filter, and can be shared.

[0057] In one of the optional embodiments, the direct-connected processor also includes: a controller, which is used to read the loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the image basic information from the target cache module based on the data read request sent by the data read interface of the video decoder, and return the read loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the image basic information to the video decoder; store the decoded image blocks in the target cache module; and read the decoded image blocks required by the video post-processor from the target cache module, and send the read decoded image blocks to the video post-processor.

[0058] Continuing with FIG. 3 , the direct-connect processor may include a target cache module and a controller. The target cache module is used to store pixel values ​​within a decoding range. It stores pixel values ​​of adjacent blocks, including a current block, a left adjacent block, and an upper neighbor row.

[0059] The controller stores the decoded image block in the target cache module, reads the pixel value from the target cache module and sends it to the video post-processor according to the decoded image block. In addition, the controller also processes the video decoder's request to read the neighbor on the loop filter.

[0060] For ease of understanding, video sequences are divided into frames, slices, macroblocks (MB) or coding tree units (CTUs), coding units, prediction blocks, and transform blocks from high to low levels. For each video sequence, the division of coding units, prediction blocks, and transform blocks is not fixed, but the size of MB / CTU for each video sequence is fixed. All operations before loop filtering can be completed according to MB / CTU, but loop filtering will affect the boundaries of MB / CTU.

[0061] Taking the HEVC decoding shown in Figure 4 as an example, the black solid line is the CTU boundary, and the dotted line is the boundary of the decoding completion block. After a CTU is decoded, its reconstructed pixels can be obtained, but its bottom 4 rows and rightmost 4 columns may be updated by loop filtering, which depends on the encoding mode of the current CTU and the encoding mode and pixel value of its right, bottom, and lower right CTUs. Therefore, only when its right, bottom, and lower right CTUs are completed can the final decoded pixel value of the current CTU be obtained. The pixel area that can be determined by the current CTU has an offset of (-4,-4) for the current CTU position. For example, in Figure 4, if the current decoding completes CTU5, the decoded output values ​​of A1 and B1 and the reconstructed value of A2 can be obtained, but the final decoded value of A2 can only be obtained after CTU9 is decoded.

[0062] Therefore, the area that the video decoder inputs to the direct-connected processor is an extended and offset area based on the CTU. In the previous example, after the decoding of CTU5 is completed, the video decoder outputs three areas, A1, B1, and B2, to the direct-connected processor. The direct-connected processor stores A1 and B1 in the cache and sends them to the video post-processor for post-processing, and temporarily stores A2 in the cache of the direct-connected processor. When decoding the next row of CTU, when the decoding of CTU9 is completed, the video decoder obtains A2 from the direct-connected processor and updates it. A2 and B2 are stored in the cache as the decoded output values ​​and sent to the video post-processor for post-processing.

[0063] In one of the optional embodiments, the video post-processor includes: an image scaling module for scaling the decoded image blocks; a color space conversion module for performing color space conversion on the scaled decoded image blocks; an image stitching module for stitching the decoded image blocks after the color space conversion; and an output cache module for caching the stitched post-processed image.

[0064] The input of the video post-processor includes basic information of the image layer (width, height, post-processing block size) and block unit information (coordinates of the input block in the decoded image and its pixel value matrix). The video post-processor contains an image scaling module, a color conversion module, an image stitching module, and an output buffer module, so that it can output in the pixel format and order specified by the output module.

[0065] Specifically, as shown in Figure 5, Figure 5 is a framework diagram of a video post-processor in one embodiment, which includes common post-processing operations required for video decoding images. The post-processed image generated after the input image is scaled, the color space converted, and the image is spliced ​​can be directly used by the target module.

[0066] In the image scaling stage, in order to ensure the image effect, the commonly used scaling algorithm usually needs to perform multi-tap filter interpolation on each point of the output image at the corresponding position of the original image. For example, the Bi-Cubic algorithm requires pixel values ​​of 2 rows (columns) on the left and right and on the top and bottom. In the direct connection algorithm of this embodiment, the left neighbor is continuous with the current processing block in the decoding order and can be directly obtained; the upper neighbor is located at the bottom of the upper neighbor block of the current processing block; the right and lower neighbor blocks cannot be obtained, and the interpolation of the two rightmost rows and the two bottom rows of the current decoding completion block needs to be postponed to the next CTU / next row of CTU decoding completion processing, as shown in the shaded part of Figure 4. Therefore, the direct connection processor also needs to cache the 4 rows of upper neighbors in the vertical direction of the decoding completion block. Taking the completion of CTU5 decoding as an example, the position of the point where the post-processing value can be calculated is inside the small dotted box, and the direct connection processor needs to prepare all the data in the large dotted box to send to the video post-processor.

[0067] In one of the optional embodiments, the video post-processor is further configured to send the processed decoded image to the target module based on the output order of the target module.

[0068] Specifically, the post-processed image generated after image scaling, color space conversion, and image stitching is stored in the output control and cache module, and output in the order required by the output target module, saving the read and write bandwidth of the post-processed image in the memory.

[0069] In one of the optional embodiments, when there is only one video post-processor and one video is processed, the background image can be stored in the memory, and the image stitching module is also used to obtain the background image from the memory and stitch the background image and the decoded image blocks after color space conversion.

[0070] Take HEVC decoding of 1080p, YUV420 format 8-bit image, and post-processing output of 1080p, ARGB format 8-bit image as an example.

[0071] The memory access bandwidth improvement of this application is shown in Table 1. This application can save the read and write bandwidth of the neighbor data on the loop filter equivalent to 20% of the original single-frame image data volume in the decoding stage, and save all the post-processor read bandwidth from the decoder to the post-processing stage, as well as all the read and write bandwidth from the post-processor to the target module.

[0072] Table 1 Memory access bandwidth improvement

[0073]

[0074] The bandwidth calculation assumes that the CTU height is 16, 70% of the CTU horizontal boundaries require loop filtering, and 30% of them have their upper boundary values ​​changed by loop filtering.

[0075] The cache size required by this application is shown in Table 2. If 1920x1080, 16x16 CTU, and 2x horizontal and vertical scaling are supported, the required cache size is about 200kB. A larger magnification requires a larger cache.

[0076] Table 2 Cache size required for this application

[0077]

[0078] Taking into account the cost of caching and the adaptability of the video decoder and video post-processor directly connected to the system, as well as the asynchronous processing needs of the video decoder, video post-processor, and target module, this application also supports writing part or all of the data to the memory, reducing the cache size of the entire system at the cost of a portion of the bandwidth.

[0079] Among them, in this application, at least part of the following memory read and write bandwidth can be saved based on the above video decoding system:

[0080] Decoded image blocks: If the pixel values ​​of the video decoder are directly passed to the video postprocessor in the output order of the video decoder, the read bandwidth of the video postprocessor for the decoded image can be saved (similarly, the write bandwidth of the video decoder to write the decoded image blocks to the memory can also be saved. However, due to the limitations of the compression standard, if the current decoded frame is marked as a reference frame, the decoded image must be written to the image cache and used as a reference image for subsequent frames, so the write bandwidth cannot always be saved).

[0081] Upper neighbor data of loop filtering: If the upper neighbor data of loop filtering is stored in the cache, it can save the bandwidth of temporarily storing the upper neighbor unfiltered pixel points in the decoded image, and reading from the decoded image after the decoding unit of the same horizontal position in the next line completes decoding, and updating the decoded image. In addition, the upper neighbor data of intra-frame prediction. It has the same value as the last row of the upper neighbor data of loop filtering, and can be shared.

[0082] Screen background (also known as background image): If the screen output content is composed of the outputs of multiple video decoders, the output of each module can be directly connected to the video post-processor without going through memory conversion.

[0083] Post-processed images: The video post-processor can output images in the order required by the target module and send them directly to the target module without first sending them to the memory.

[0084] In one of the optional embodiments, the number of video decoders and directly connected processors is greater than or equal to 2, and each video decoder is connected to a directly connected processor; each directly connected processor is also connected to at least two video post-processors, and each video post-processor is respectively connected to a target module.

[0085] In one of the optional embodiments, the number of video decoders and directly connected processors is greater than or equal to 2, and each video decoder is connected to a directly connected processor; each directly connected processor is connected to the same video post-processor.

[0086] Specifically, in combination with FIG. 6 , FIG. 6 is a schematic diagram of one video decoder connected to multiple video post-processors and multiple video decoders connected to one video post-processor in one embodiment.

[0087] In this embodiment, it supports the case where one video decoder is connected to multiple post-processors and multiple video decoders / other sources are connected to one video post-processor, and it can support the direct transmission of multiple images without completing the splicing of code streams through memory access. As shown in Figure 6, each video decoder is connected to a direct processor, each video post-processor is connected to a target module, and the data of a direct processor can be sent to multiple video post-processors for video post-processing, and a video post-processor can also obtain data from multiple direct processors to splice multiple code streams.

[0088] When the content output on the screen is composed of the outputs of multiple video decoders, the output of each video decoder can be directly connected to the video post-processor without going through memory conversion, thereby saving the memory read and write bandwidth of the background image.

[0089] In summary, the present application directly connects the video decoder to the post-processor so that the video decoding result can be directly converted into the output required by the target module. A direct-connected processor is added between the video decoder and the video post-processor so that the video decoder can transmit image data to the video post-processor in blocks, saving the bandwidth of the video post-processor reading the memory; a cache is added to the direct-connected processor, and adjacent pixels, especially the upper neighbor values, are saved to the cache, so that the video post-processor can obtain the necessary adjacent pixel data when doing post-processing, avoiding the block effect caused by discontinuous block boundaries. The temporary data of the upper boundary of the loop filter is stored in the cache of the direct-connected processor, which saves the bandwidth of the loop filter upper boundary data through memory temporary storage and reading, saves the read and write bandwidth of the intra-frame prediction upper boundary, and simplifies the design of the direct-connected processor (the direct-connected processor does not need to obtain which loop filter upper boundaries are updated, and can send the image decoding blocks to the post-processor according to a uniform size). Color space conversion and output order conversion are supported in the video post-processor. The output of the video post-processor supports linear ARGB output and can be directly connected to a variety of target output modules.

[0090] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0091] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0092] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A video decoding system, characterized in that: The system comprises: A video decoder, used for decoding a bitstream into a decoded image block; A video post-processor is connected to the video decoder; the video post-processor is used to process the decoded image block and send the processed decoded image block to a target module.

2. The system according to claim 1, characterized in that The system further comprises: A direct-connect processor, wherein the input interface of the direct-connect processor is connected to the output interface of the video decoder, and the output interface of the direct-connect processor is connected to the input interface of the video post-processor; the direct-connect processor is used to receive the decoded image blocks output by the video decoder, and send the decoded image blocks required by the video post-processor to the video post-processor.

3. The system according to claim 2, characterized in that The directly connected processor comprises: A target cache module, used for caching basic image information output by the video decoder; The video decoder further comprises a data reading interface, and the video decoder is used to read the loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the basic information of the image from the target cache module through the data reading interface.

4. The system according to claim 3, characterized in that The directly connected processor also includes: A controller, the controller is used to read the loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the image basic information from the target cache module based on the data read request sent by the data read interface of the video decoder, and return the read loop filtering upper neighbor data and the intra-frame prediction upper neighbor data in the image basic information to the video decoder; store the decoded image block in the target cache module; and read the decoded image block required by the video post-processor from the target cache module, and send the read decoded image block to the video post-processor.

5. The system according to claim 1, characterized in that The video decoder is further configured to store the decoded image block in a memory when it is determined that the decoded image block obtained by decoding is a reference frame image block.

6. The system according to claim 1, characterized in that The video post-processor comprises: An image scaling module, used for scaling the decoded image blocks; A color space conversion module, used for performing color space conversion on the scaled decoded image block; An image splicing module, used for splicing the decoded image blocks after color space conversion; Output cache module, used to cache the stitched post-processed images.

7. The system according to claim 6, characterized in that The image splicing module is also used to obtain a background image from the memory, and splice the background image with each of the decoded image blocks after color space conversion.

8. The system according to any one of claims 1 to 7, characterized in that: The video post-processor is further configured to send the processed decoded image to the target module based on the output order of the target module.

9. The system according to any one of claims 2 to 7, characterized in that: The number of the video decoders and the directly connected processors is greater than or equal to 2, and each of the video decoders is connected to one of the directly connected processors; Each of the direct-connected processors is also connected to at least two of the video post-processors, and each of the video post-processors is respectively connected to a target module.

10. The system according to any one of claims 2 to 7, characterized in that: The number of the video decoders and the directly connected processors is greater than or equal to 2, and each of the video decoders is connected to one of the directly connected processors; Each of the direct-connect processors is connected to the same video post-processor.

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