Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and is applied to the technical field of semiconductors. According to the semiconductor device and the manufacturing method thereof, the semiconductor device with the height difference between the multiple lower electrodes in the vertical direction is formed in the mode that the partial height of at least one lower electrode in the multiple lower electrodes on the substrate is removed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor memory device and a manufacturing method thereof. Background Art

[0002] As various electronic products develop towards miniaturization, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the DRAM cell with only a planar gate structure under the current mainstream development trend. Generally speaking, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage component to receive voltage signals from the bit line and the word line. However, due to the limitations of process technology, the existing DRAM cell with a recessed gate structure still has many defects, and further improvements are needed to effectively improve the performance and reliability of the relevant memory components. Summary of the invention

[0003] The object of the present invention is to provide a method for preparing a semiconductor structure to improve the performance and reliability of semiconductor devices.

[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, which may at least include:

[0005] providing a substrate including a first region and a second region;

[0006] Forming a stacked structure layer located on the first region and the second region, the stacked structure layer comprising a supporting stacked layer and a first mask layer stacked from bottom to top;

[0007] forming a through hole in the first region, wherein the through hole penetrates the stacked structure layer;

[0008] forming a lower electrode located on the inner surface of the through hole and extending laterally to cover the first mask layer in the second region;

[0009] forming a second mask layer on the lower electrode in the first region and the second region;

[0010] The second mask layer, a portion of the lower electrode and a portion of the first mask layer on the second region are removed so that top surfaces of the lower electrodes on both side walls of at least one through hole adjacent to the second region are at different levels.

[0011] Optionally, the step of removing the lower electrode on the second region may include:

[0012] Forming a first photoresist layer having a first opening on the second mask layer, wherein the first opening exposes a portion of a top surface of the second mask layer on the first region and a top surface of the second mask layer on the second region;

[0013] Using the first photoresist layer as a mask, the second mask layer, part of the lower electrode and part of the first mask layer corresponding to the first opening are removed to expose the support stack layer on the second region and the lower electrode on the sidewall of the through hole adjacent thereto.

[0014] Optionally, after removing the lower electrode on the second region, the method may further include:

[0015] The first photoresist layer on the first region and the second mask layer thereunder are removed to expose the lower electrode on the first region.

[0016] Optionally, the through hole adjacent to the supporting stack layer on the second zone has a first side wall and a second side wall relative to each other, the lower electrode located on the first side wall is in direct contact with the stack structure layer on the first zone, and the lower electrode located on the second side wall is in direct contact with the supporting stack layer on the second zone.

[0017] Optionally, a top surface of the lower electrode located on the first side wall is higher than a top surface of the lower electrode located on the second side wall.

[0018] Optionally, the supporting stack layer may include a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer stacked in sequence from bottom to top.

[0019] Optionally, after removing the second mask layer on the first area, the method may further include:

[0020] The lower electrode on the supporting stack layer between adjacent through holes and the first mask layer thereunder are removed.

[0021] Optionally, in the step of removing the lower electrode on the supporting stack layer between adjacent through holes and the first mask layer thereunder, a portion of the height of the lower electrode on the second side wall of the through hole adjacent to the supporting stack layer on the second region is also removed synchronously.

[0022] Optionally, after removing the second mask layer on the first area, the method may further include:

[0023] forming a third mask layer on the first region and the second region;

[0024] A second photoresist layer having a second opening is formed on the third mask layer on the first region, wherein the second opening exposes a portion of a top surface of the third mask layer in the first region.

[0025] Optionally, after removing the second mask layer on the first area, the method may further include:

[0026] Using the second photoresist layer as a mask, the third mask layer and the first supporting layer and the second supporting layer in the supporting stack layer corresponding to the second opening are removed.

[0027] Optionally, after removing the second mask layer on the first area, the method may further include:

[0028] The second sacrificial layer and the first sacrificial layer in the support stack layer in the first region and the second region are removed.

[0029] Optionally, after removing the second mask layer, the lower electrode and the first mask layer on the second region, the method may further include:

[0030] A metal oxide layer is formed on the lower electrode, and an upper electrode is formed on the metal oxide.

[0031] In the second aspect, based on the same inventive concept, the present invention further provides a semiconductor device, which may at least include:

[0032] a substrate, comprising a first region and a second region;

[0033] A support structure, comprising a first support structure located in the first area and a second support structure located in the second area, wherein the second support structure is longer than the first support structure;

[0034] A plurality of lower electrodes are located on the first region of the substrate, and at least a portion of the top surface of the lower electrodes in contact with the second supporting structure on the second region is lower than the top surfaces of the remaining lower electrodes.

[0035] Optionally, the semiconductor device may further include:

[0036] a metal oxide layer, located on the plurality of lower electrodes;

[0037] The upper electrode is located on the metal oxide layer.

[0038] Optionally, the lower electrode in contact with the second supporting structure on the second region has a first side wall and a second side wall opposite to each other, the second side wall contacts the second supporting structure, and the top surface of the lower electrode on the first side wall is higher than the top surface of the lower electrode on the second side wall.

[0039] Optionally, the lower electrode in contact with the second supporting structure on the second region may be located on the same side as all other lower electrodes.

[0040] Optionally, the lower electrode comprises a cylindrical or columnar shape.

[0041] In a third aspect, based on the same inventive concept, the present invention further provides a semiconductor device, which may at least include:

[0042] substrate;

[0043] A plurality of lower electrodes are located on the substrate, wherein at least a portion of a top surface of one of the lower electrodes is lower than all other lower electrodes and is located on the same side of all the lower electrodes.

[0044] Optionally, the semiconductor device may further include:

[0045] a metal oxide layer, located on the plurality of lower electrodes;

[0046] The upper electrode is located on the metal oxide layer.

[0047] Optionally, the lower electrode has a first side wall and a second side wall opposite to each other, the second side wall is located on a side away from the rest of the lower electrodes, and a top surface of the lower electrode on the first side wall is higher than a top surface of the lower electrode on the second side wall.

[0048] In the present invention, when removing the second mask layer and the first mask layer stacked in the second area, part of the height of the lower electrode on the side wall of at least one through hole adjacent to the second area is simultaneously removed, so that the top surface of at least one of the multiple lower electrodes included in the formed semiconductor device is lower than the top surfaces of the remaining lower electrodes, that is, there is a height difference in the vertical direction between the lower electrodes in the formed semiconductor device, thereby improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0050] Figure 1 A flowchart of a method for preparing a semiconductor memory provided in one embodiment of the present invention;

[0051] Figure 2 to Figure 11 A schematic diagram of the structure of a method for manufacturing a semiconductor device provided in one embodiment of the present invention during the manufacturing process;

[0052] Fig.12 The use provided in one embodiment of the present invention Figure 1A schematic diagram of the evolving structure of a semiconductor device manufactured by the method for manufacturing a semiconductor device shown.

[0053] Wherein, the accompanying drawings are marked as follows:

[0054] 100-substrate, 101-first area of ​​the substrate, 102-second area of ​​the substrate, 251-stacked structure layer, 110 / 110' / 110"-support stack layer, 110-support stack layer, 111-first sacrificial layer, 112-first supporting layer, 113-second sacrificial layer, 114-second supporting layer, 120-first mask layer, OP-through hole, 130-lower electrode, 140-second mask layer, 150-first photoresist layer, OP1-through hole adjacent to the supporting stack layer on the second area, 160-third mask layer, 131 / 131'-lower electrode on the first side wall of through hole OP1, 132 / 132'-lower electrode on the second side wall of through hole OP1, H1 / H2-height difference of the lower electrode between the first side wall and the second side wall, 170-second photoresist layer, 180-metal oxide layer, 190-upper electrode, CAP-capacitor.

[0055] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0056] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0057] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0058] For ease of understanding, a horizontal direction and a vertical direction are defined below, wherein the horizontal direction is a direction parallel to the surface of the substrate 100 ; and the vertical direction is a direction perpendicular to the surface of the substrate 100 .

[0059] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention. Figure 1 As shown, the method for manufacturing a semiconductor device provided in this embodiment at least includes the following steps:

[0060] Step S101, providing a substrate, including a first area and a second area;

[0061] Step S102, forming a stacked structure layer located on the first region and the second region, the stacked structure layer comprising a supporting stacked layer and a first mask layer stacked from bottom to top;

[0062] Step S103, forming a through hole located in the first region, and the through hole penetrates the stacked structure layer;

[0063] Step S104, forming a lower electrode located on the inner surface of the through hole and extending laterally to cover the first mask layer in the second region;

[0064] Step S1015, forming a second mask layer on the lower electrode in the first region and the second region;

[0065] Step S106 , removing the second mask layer, a portion of the lower electrode and a portion of the first mask layer on the second region, so that top surfaces of the lower electrode on both side walls of at least one through hole adjacent to the second region are at different levels.

[0066] In order to enable a person skilled in the art to which the present invention belongs to easily understand the method for manufacturing a semiconductor device in the embodiment of the present invention, the method for manufacturing a semiconductor device proposed by the present invention will be further described below in conjunction with various structural schematic diagrams of the manufacturing method during the preparation process. Figure 2 to Figure 12 It is a structural schematic diagram of the manufacturing method of the semiconductor device provided in an embodiment of the present invention during the manufacturing process.

[0067] Execute the above step S101: Please refer to Figure 2, a substrate 100 is provided, the substrate 100 includes a first region 101, for example, a storage region (cell region) of a semiconductor memory, and a second region 102, for example, a peripheral region (periphery region) of the semiconductor memory. In one embodiment, the substrate 100 is any suitable substrate material known in the art, for example, a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate composed of other suitable materials, etc., but not limited thereto. The substrate 100 may be formed with components such as a bit line structure, a sidewall structure, a contact structure, and a connection pad structure (not shown), but not limited thereto.

[0068] Execute the above step S102: Please continue to refer to Figure 2 , a stacked structure layer 251 is formed on the surface of the substrate 100 by using at least one of deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.; wherein the stacked structure layer 251 includes a support stacked layer 110 and a first mask layer 120 stacked in sequence from bottom to top. In one embodiment, the support stacked layer 110 may include a first sacrificial layer 111, a first support layer 112, a second sacrificial layer 113, and a second support layer 114 stacked in sequence from bottom to top, so as to achieve a more solid support effect on the lower electrode by setting a plurality of support layers, but the present invention is not limited thereto. Wherein, the first sacrificial layer 111 and the second sacrificial layer 113 may respectively include a single layer or multiple layers of oxide material, such as silicon oxide, boro-phospho-silicate-glass (BPSG) or other sacrificial materials having a desired etching selectivity ratio with the material of the support layer, but the present invention is not limited thereto. The first support layer 112 and the second support layer 114 may be silicon carbon nitride (SiCN); the material of the first mask layer 120 may include silicon oxide, amorphous silicon, polysilicon or a combination thereof, but is not limited thereto.

[0069] Execute the above step S103: Please continue to refer to Figure 2 , a plurality of through holes OP spaced apart from each other in the horizontal direction are formed in the stacked structure layer 251 in the first region 101 of the substrate 100 by using at least one of an etching process such as dry etching or wet etching, that is, the through holes OP penetrate the first mask layer 120 and the supporting stack layer 110, and the bottom thereof is exposed to the substrate 100, but not limited thereto. After the through holes OP are formed by etching, the top surface of the portion of the first mask layer 120 located on the first region 101 may be lower than the top surface of the portion of the first mask layer 120 located on the second region 102.

[0070] Execute the above step S104: Please refer to Figure 3, a conductive material layer of the lower electrode 130 is formed by using at least one of the above deposition processes, and the conductive material layer of the lower electrode 130 is specifically located on the inner surface of the through hole OP, the top surface of the first mask layer 120 in the first area 101 exposed between adjacent through holes OP, and the top surface of the first mask layer 120 in the second area 102. At this time, the conductive material layer of the lower electrode 130 does not fill the through hole OP located on the first area 101; in one embodiment, the material of the conductive material layer of the lower electrode 130 may include doped silicon, tungsten, copper, titanium nitride or others, but is not limited thereto.

[0071] Execute the above step S105: Please refer to Figure 4 , a second mask layer 140 is formed on the first area 101 and the second area 102 of the substrate 100 by using at least one of the above deposition processes; the second mask layer 140 fills the gaps between the adjacent through holes OP of the first area 101, and extends horizontally in the horizontal direction to cover the top surface of the lower electrode 130 between the adjacent through holes OP and the top surface of the lower electrode 130 located on the second area 102, that is, the second mask layer 140 buries the film layer structures on the first area 101 and the second area 102, and due to the height difference of the stacked structure layer 251 in the first area 101 and the second area 102, the junction of the first area 101 and the second area 102 is stepped. In one embodiment, the material of the second mask layer 140 can be the same as the material of the first mask layer 120, for example, both are silicon oxide, or different, for example, the material of the first mask layer 120 is silicon oxide, and the material of the second mask layer 140 is polysilicon, but it is not limited to this.

[0072] Execute the above step S106: Please refer to Figure 5 and Figure 6 , a first photoresist layer 150 may be formed on the second mask layer 140 in the first region 101; wherein the first photoresist layer 150 has an opening (hereinafter referred to as the first opening for the sake of distinction), and the first opening exposes a portion of the top surface of the second mask layer 140 on the first region 101 and the entire top surface of the second mask layer 140 on the second region 102. Then, the first photoresist layer 150 having the first opening may be used as a mask to remove a portion of the second mask layer 140 and a portion of the lower electrode 130 on the first region 101 corresponding to the first opening, and all of the second mask layer 140 and all of the first mask layer 120 on the second region 102 in a vertical direction, so as to expose the support stack layer 110 on the second region 102, and the lower electrode 130 on the sidewall of the through hole OP adjacent thereto and located on the first region 101, thereby forming a structure as shown in FIG. Figure 5Next, the first photoresist layer 150 on the first region 101 and the remaining second mask layer 140' thereunder are further removed to expose the lower electrode 130 on the first region 101, forming a structure as shown in FIG. Figure 6 The structure shown.

[0073] Thus, the through hole OP (eg, Figure 6 As shown in the figure, the top surfaces of the lower electrodes on the two side walls of the through hole OP1 (hereinafter referred to as OP1) are at different horizontal heights; specifically, the through hole OP1 adjacent to the supporting stack layer 251 on the second area 102 has a first side wall and a second side wall relative to each other. Exemplarily, for the sake of convenience in distinction, the side wall of the through hole OP1 close to the first area 101 may be referred to as the first side wall (that is, the first side wall is in direct contact with the stack structure layer 251 on the first area 101), and the side wall of the through hole OP1 close to the second area 102 may be referred to as the second side wall (that is, the second side wall is in direct contact with the supporting stack layer 110 on the second area 102), and then the lower electrode 130 located on the first side wall of the through hole OP1 is identified by the reference numeral 131, and the lower electrode 130 located on the second side wall of the through hole OP1 is identified by the reference numeral 132, as shown in the figure. Figure 6 Obviously, in the process of removing the second mask layer 140 and the first mask layer 120 on the second region 102 in step S106 in the embodiment of the present invention, part of the height of the lower electrode 130 on the second side wall of the through hole OP1 is also removed synchronously, so that the top surface of the lower electrode 132 remaining on the second side wall of the through hole OP1 after etching is lower than the top surface of the lower electrode 131 on the first side wall of the through hole OP1 opposite to the second side wall, that is, there is a height difference H1 between the two in the vertical direction, and also the top surfaces of part of the multiple lower electrodes included in the finally formed semiconductor device have a height difference.

[0074] It should be understood that in the embodiment of the present invention, only in the drawings, a through hole OP located on the first region 101 in the semiconductor device is set as a through hole OP1 with different top surfaces of the lower electrodes on the two side walls, while in other embodiments of the present invention, multiple through holes OP on the first region 101 can also be set as the through holes OP1 with different top surfaces of the lower electrodes on the side walls (i.e., at different heights).

[0075] Continue to step S106: Please refer to Figure 7, after removing part of the lower electrode 130 on the second area 102 to form a structure with a height difference between the lower electrodes on the two side walls in the through hole OP1, the lower electrode 130 on the support stack layer 110 between the adjacent through holes OP on the first area 101 and the first mask layer 120 thereunder may be further removed downwardly in the vertical direction, so that the top surface of the lower electrode 130 on the two side walls of the through hole OP on the first area 101 is lower than the top surface of the support stack layer 110 between the adjacent through holes OP. In one embodiment, in the step of removing the lower electrode 130 on the support stack layer 110 between the adjacent through holes OP on the first area 101 and the first mask layer 120 thereunder, a part of the height of the lower electrode 131 on the first side wall and the lower electrode 132 on the second side wall of the through hole OP1 adjacent to the support stack layer 110 on the second area 102 may be simultaneously removed, so that the height difference between the lower electrodes on the two side walls of the through hole OP1 is reduced (along the vertical direction), for example by Figure 6 H1 shown is reduced to Figure 7 H2 shown, that is, H1>H2>0, but not limited to this; it should be understood that for the sake of distinction, in the embodiment of the present invention, the lower electrode remaining on the first side wall of the through hole OP1 after executing this step is marked with the reference numeral 131', and the lower electrode remaining on the second side wall of the through hole OP1 is marked with the reference numeral 132'.

[0076] Continue to step S106: Please refer to Figure 8 , a third mask layer 160 that buries the corresponding film structures and a second photoresist layer 170 located on the top surface of the third mask layer 160 on the first area 101 can be further formed on the first area 101 and the second area 102 of the substrate 100 by a deposition process. At this time, the second photoresist layer 170 has at least one second opening, such as Figure 8 The two second openings are shown to expose a portion of the top surface of the third mask layer 160 in the first region 101. In one embodiment, a second opening in the second photoresist layer 170 exposes the support stack layer 110 located between two adjacent through holes OP in the first region 101 to prepare for the subsequent removal of a portion of the film layer in the support stack layer 110.

[0077] Continue to step S106: Please refer to Fig. 9 , and combined with Figure 8, the second photoresist layer 170 can be used as a mask, and an etching process such as wet etching can be used to first remove the third mask layer 160 and the second support layer 114 and part of the second sacrificial layer 113 in the support stack layer 110 corresponding to at least one second opening in the second photoresist layer 170 downward. In one embodiment, in this step, the second support layer 114 is partially removed, and the second sacrificial layer 113 is completely removed, and the position where the second support layer 114 is removed is aligned with the second opening in the second photoresist layer 170, but the present invention is not limited thereto. It should be understood that, for the sake of distinction, the support stack layer obtained after executing this step in the embodiment of the present invention is marked with the reference numeral 110'.

[0078] Continue to step S106: Please refer to Fig.10 , and combined with Figure 8 and Fig. 9 , the second photoresist layer 170 can be used as a mask, and an etching process such as wet etching can be used to further remove part of the first supporting layer 112 and the entire first sacrificial layer 111 in the supporting stack layer 110' on the first area 101 and the second area 102, and the supporting stack layer obtained after etching in this step is marked with a reference numeral 110"; then the second photoresist layer 170 and the remaining third mask layer 160 are removed. It should be understood that since the second photoresist layer 170 in the embodiment of the present invention has a second opening, the second supporting layer 114 and the first supporting layer 112 in the supporting stack layer 110 located at the second opening will be removed accordingly during the above two etching and removal steps performed on the supporting stack layer 110, but the present invention is not limited thereto.

[0079] Continue to step S106: Please refer to Fig.11 or Fig.12Further, at least one of the above deposition processes can be used to form a metal oxide layer 180 on the lower electrode 130 in the through hole OP of the first region 101, and an upper electrode 190 filling the remaining area of ​​the through hole OP is formed on the metal oxide layer 180, that is, a capacitor CP composed of the lower electrode 130, the metal oxide layer 180 and the upper electrode 190 is formed. In one embodiment, the metal oxide layer 180 may include a high dielectric constant material layer, such as TaOO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)OO, Sr(Zr,Ti)O, a combination of the above materials, or other suitable dielectric materials, and the material of the upper electrode 190 may include titanium nitride, tantalum nitride, SiGe, a combination of the above materials, or other suitable conductive materials, but is not limited thereto. In addition, the upper electrode 190 will also fill the areas corresponding to the first sacrificial layer 111, the second sacrificial layer 113, the first supporting layer 112 and the second supporting layer 114 that have been removed from the supporting stack layer 110", and extend laterally on the top surface of the supporting stack layer 110" exposed on the first area 101 and the second area 102.

[0080] It should be noted that the above is based on Figures 2 to 11 In the steps of the method for manufacturing the semiconductor device shown in FIG. 1 , the lower electrode 130 or the lower electrode 131′ / 131″ and the lower electrode 132′ / 132″ located on the inner surface of the through hole OP or OP1 in the first region 101 in the entire process are all cylindrical in shape. In other embodiments, the lower electrode 130 or the lower electrode 131′ / 131″ and the lower electrode 132′ / 132″ located on the inner surface of the through hole OP or OP1 in the first region 101 in the entire process may also be columnar in shape, such as Fig.12 shown.

[0081] Based on this, for different shapes of the lower electrode 130 included in the capacitor CAP, the embodiments of the present invention provide the following respectively: Fig.11 The structure of the semiconductor device shown in FIG. Fig.12 The structure of the semiconductor device shown in FIG. Fig.11 and Fig.12 The structures of the semiconductor devices shown are all different in the shape of the lower electrode 130 , while other corresponding manufacturing processes are the same, but the present invention is not limited thereto.

[0082] To summarize, in the present invention, when removing the second mask layer and the first mask layer stacked in the second zone, a portion of the height of the lower electrode on the side wall of at least one through hole adjacent to the second zone is simultaneously removed, so that the top surface of at least one of the multiple lower electrodes included in the formed semiconductor device is lower than the top surfaces of the remaining lower electrodes, that is, there is a height difference in the vertical direction between the lower electrodes in the formed semiconductor device, thereby improving the performance and reliability of the semiconductor device.

[0083] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0084] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate including a first region and a second region; Forming a stacked structure layer located on the first region and the second region, the stacked structure layer comprising a supporting stacked layer and a first mask layer stacked from bottom to top; forming a through hole in the first region, wherein the through hole penetrates the stacked structure layer; forming a lower electrode located on the inner surface of the through hole and extending laterally to cover the first mask layer in the second region; forming a second mask layer on the lower electrode in the first region and the second region; The second mask layer, a portion of the lower electrode and a portion of the first mask layer on the second region are removed so that top surfaces of the lower electrodes on both side walls of at least one through hole adjacent to the second region are at different levels.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of removing the lower electrode on the second region comprises: Forming a first photoresist layer having a first opening on the second mask layer, wherein the first opening exposes a portion of a top surface of the second mask layer on the first region and a top surface of the second mask layer on the second region; Using the first photoresist layer as a mask, the second mask layer, part of the lower electrode and part of the first mask layer corresponding to the first opening are removed to expose the support stack layer on the second region and the lower electrode on the sidewall of the through hole adjacent thereto.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: After removing the lower electrode on the second region, the method further comprises: The first photoresist layer on the first region and the second mask layer thereunder are removed to expose the lower electrode on the first region.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The through hole adjacent to the supporting stack layer on the second zone has a first side wall and a second side wall opposite to each other, the lower electrode on the first side wall is in direct contact with the stack structure layer on the first zone, and the lower electrode on the second side wall is in direct contact with the supporting stack layer on the second zone.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: A top surface of the lower electrode located on the first side wall is higher than a top surface of the lower electrode located on the second side wall.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The supporting stacked layer includes a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer which are sequentially stacked from bottom to top.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: After removing the second mask layer on the first area, the method further includes: The lower electrode on the supporting stack layer between adjacent through holes and the first mask layer thereunder are removed.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: In the step of removing the lower electrode on the supporting stack layer between adjacent through holes and the first mask layer thereunder, a portion of the height of the lower electrode on the second side wall of the through hole adjacent to the supporting stack layer on the second region is also removed synchronously.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: After removing the second mask layer on the first area, the method further includes: forming a third mask layer on the first region and the second region; A second photoresist layer having a second opening is formed on the third mask layer on the first region, wherein the second opening exposes a portion of a top surface of the third mask layer in the first region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: After removing the second mask layer on the first area, the method further includes: Using the second photoresist layer as a mask, the third mask layer and the first supporting layer and the second supporting layer in the supporting stack layer corresponding to the second opening are removed.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: After removing the second mask layer on the first area, the method further includes: The second sacrificial layer and the first sacrificial layer in the support stack layer in the first region and the second region are removed.

12. The method for manufacturing a semiconductor device according to claim 1, wherein: After removing the second mask layer, the lower electrode and the first mask layer on the second region, the method further includes: A metal oxide layer is formed on the lower electrode, and an upper electrode is formed on the metal oxide.

13. A semiconductor device, characterized in that: include: a substrate, comprising a first region and a second region; A support structure, comprising a first support structure located in the first area and a second support structure located in the second area, wherein the second support structure is longer than the first support structure; A plurality of lower electrodes are located on the first region of the substrate, and at least a portion of the top surface of the lower electrodes in contact with the second supporting structure on the second region is lower than the top surfaces of the remaining lower electrodes.

14. The semiconductor device according to claim 13, wherein: Also includes: a metal oxide layer, located on the plurality of lower electrodes; The upper electrode is located on the metal oxide layer.

15. The semiconductor device according to claim 13, wherein: The lower electrode in contact with the second supporting structure on the second region has opposite first and second side walls, the second side wall contacts the second supporting structure, and the top surface of the lower electrode on the first side wall is higher than the top surface of the lower electrode on the second side wall.

16. The semiconductor device according to claim 13, wherein: The lower electrode in contact with the second supporting structure on the second region is located on the same side as all other lower electrodes.

17. The semiconductor device according to claim 13, wherein: The lower electrode includes a cylindrical shape or a columnar shape.

18. A semiconductor device, characterized in that: include: substrate; A plurality of lower electrodes are located on the substrate, wherein at least a portion of a top surface of one of the lower electrodes is lower than all other lower electrodes and is located on the same side of all the lower electrodes.

19. The semiconductor device according to claim 18, wherein: Also includes: a metal oxide layer, located on the plurality of lower electrodes; The upper electrode is located on the metal oxide layer.

20. The semiconductor device according to claim 18, wherein The lower electrode has a first side wall and a second side wall opposite to each other. The second side wall is located on a side away from the rest of the lower electrodes. The top surface of the lower electrode on the first side wall is higher than the top surface of the lower electrode on the second side wall.

Images