Flash memory and manufacturing method thereof

Abstract

The invention provides a flash memory and a manufacturing method thereof, and the method comprises the steps: providing a substrate, sequentially forming a dielectric layer, a floating gate layer, an interlayer insulating layer, a control gate layer and a sacrificial layer on the substrate, and forming a first side wall on the side wall of the sacrificial layer in a hole; etching the control gate layer and the interlayer insulating layer until the floating gate layer is exposed; the formed second side wall covers the interlayer insulating layer, the control gate layer and the side wall of the first side wall; etching the floating gate layer and the dielectric layer along the second side wall to expose the substrate; the formed third side wall at least covers the side wall of the floating gate layer; etching the substrate exposed by the third side wall to form a groove; the word line oxide layer covers the surface of the groove, the dielectric layer, the side wall of the floating gate layer and the side wall of the second side wall; and forming a word line. By increasing etching of substrate silicon at the bottom of a word line, a groove is formed, namely a word line channel is formed, the length of the word line channel is increased, and the turn-off capacity of the word line is improved. Under the condition that the area of the device is not increased, the turn-off capability of the word line is adjusted through the etching amount of the substrate silicon.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a flash memory and a manufacturing method thereof. Background Art

[0002] Flash memory is an integrated circuit storage device that is widely used in electronic products such as portable computers, mobile phones, and digital music players because it has the function of electrically erasable storage of information and the stored information will not be lost after power failure.

[0003] As the area of ​​flash memory cells continues to shrink, the critical dimension at the bottom of the word line is also shrinking accordingly. The shrinking critical dimension at the bottom of the word line weakens the ability to shut down the word line, which leads to an increase in programming-related failures. Programming failures are caused by, for example, the chip's read current after a programming operation is too high and does not meet the judgment standard for state "0". Summary of the invention

[0004] The purpose of the present invention is to provide a flash memory and a method for manufacturing the same. The flash memory structure of the present invention forms a groove by increasing the etching of the substrate silicon at the bottom of the word line, that is, forming a word line channel, and increasing the length of the word line channel, thereby improving the word line shutdown capability. Without increasing the device area, the word line shutdown capability is adjusted by the etching amount of the substrate silicon.

[0005] The present invention provides a method for manufacturing a flash memory, comprising:

[0006] A substrate is provided, and a dielectric layer, a floating gate layer, an interlayer insulating layer, a control gate layer, and a sacrificial layer with an opening are stacked in sequence on the substrate, and a first sidewall is formed on the surface of the control gate layer in the opening; the control gate layer and the interlayer insulating layer are etched along the interval between the first sidewalls until the surface of the floating gate layer is exposed; a second sidewall is formed, and the second sidewall covers the sidewalls of the interlayer insulating layer, the control gate layer, and the first sidewall; the floating gate layer and the dielectric layer are etched along the second sidewall to expose the substrate;

[0007] forming a third spacer, wherein the third spacer at least covers a sidewall of the floating gate layer;

[0008] Etching the substrate exposed by the third sidewall to form a groove; removing the third sidewall;

[0009] forming a word line oxide layer, wherein the word line oxide layer covers the surface of the trench, the sidewall surfaces of the dielectric layer and the floating gate layer, the second sidewall spacer, and the sidewall surface of the first sidewall spacer;

[0010] The space surrounded by the word line oxide layer is filled with polysilicon to form a word line.

[0011] Furthermore, the shape of the groove includes: a semicircular shape, an inverted trapezoidal shape, and a U shape.

[0012] Furthermore, the material of the third sidewall spacer includes: an oxide layer; and the process of forming the third sidewall spacer includes: plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

[0013] Furthermore, the process of forming the groove includes: wet etching or dry etching.

[0014] Furthermore, the material of the word line oxide layer includes silicon oxide; and the process of forming the word line oxide layer includes plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

[0015] Furthermore, after forming the word line, the manufacturing method further includes:

[0016] The sacrificial layer is removed by etching, and the control gate layer, the interlayer insulating layer, the floating gate layer and the dielectric layer exposed by the sacrificial layer are sequentially dry-etched with reference to the first side wall, so that after etching, the control gate layer forms two separated control gates, and the floating gate layer forms two separated floating gates.

[0017] Furthermore, the material of the sacrificial layer includes silicon nitride, silicon oxynitride or high-k material, and the method for forming the sacrificial layer includes one of atomic layer deposition, chemical vapor deposition and plasma enhanced chemical vapor deposition processes.

[0018] The present invention also provides a flash memory, comprising:

[0019] A substrate, on which a stacked dielectric layer, a floating gate, an interlayer insulating layer, a control gate and a first sidewall are sequentially formed on both sides of the opening; a trench is formed in the substrate below the opening;

[0020] a second sidewall spacer, wherein the second sidewall spacer covers the interlayer insulating layer, the control gate and the sidewall of the first sidewall spacer in the opening;

[0021] A word line oxide layer, wherein the word line oxide layer covers the surface of the trench, the dielectric layer and the side wall surface of the floating gate, and the side wall surface of the second side wall and the first side wall;

[0022] A word line fills a space surrounded by the word line oxide layer.

[0023] Furthermore, the interlayer insulating layer comprises a stacked structure of silicon dioxide layer-silicon nitride layer-silicon dioxide layer.

[0024] Furthermore, the floating gate, the control gate and the word line are all made of polysilicon.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] The invention provides a flash memory and a manufacturing method thereof. The manufacturing method comprises: providing a substrate, sequentially forming a stacked dielectric layer, a floating gate layer, an interlayer insulating layer, a control gate layer and a sacrificial layer with an opening on the substrate, forming a first side wall on the side wall of the sacrificial layer in the opening; etching the control gate layer and the interlayer insulating layer along the interval between the first side walls until the surface of the floating gate layer is exposed; forming a second side wall, the second side wall covering the side wall of the interlayer insulating layer, the control gate layer and the first side wall; etching the floating gate layer and the dielectric layer along the second side wall to expose the substrate; forming a third side wall, the third side wall at least covering the side wall of the floating gate layer; etching the substrate exposed by the third side wall to form a groove; removing the third side wall; forming a word line oxide layer, the word line oxide layer covering the surface of the groove, the side wall surface of the dielectric layer and the floating gate layer, the second side wall and the side wall surface of the first side wall; and filling the space surrounded by the word line oxide layer with polysilicon to form a word line. The flash memory structure of the present invention forms a groove by increasing the etching of the substrate silicon at the bottom of the word line, that is, forming a word line channel, increasing the length of the word line channel, thereby improving the word line shutdown capability. Without increasing the device area, the word line shutdown capability is adjusted by the etching amount of the substrate silicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The present invention is a flowchart of a method for manufacturing a flash memory according to an embodiment of the present invention.

[0028] Figures 2 to 7 Schematic diagram of each step of a method for manufacturing a flash memory according to an embodiment of the present invention.

[0029] Figure 8 This is a schematic diagram comparing the word line threshold voltage Vt before and after the flash memory improvement.

[0030] Fig. 9 This is a schematic diagram comparing the voltage Vdp before and after the flash memory improvement.

[0031] The reference numerals are as follows:

[0032] 10-substrate; 11-dielectric layer; 12-floating gate layer; 120-floating gate; 13-interlayer insulating layer; 14-control gate layer; 140-control gate; 15-sacrificial layer; 16-first sidewall; 17-second sidewall; 18-third sidewall; 19-word line oxide layer; 20-word line. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0034] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0035] The embodiment of the present invention provides a method for manufacturing a flash memory, such as Figure 1 As shown, including:

[0036] Step S1, providing a substrate, sequentially forming a stacked dielectric layer, a floating gate layer, an interlayer insulating layer, a control gate layer and a sacrificial layer with an opening on the substrate, forming a first sidewall on the sidewall of the sacrificial layer in the opening; etching the control gate layer and the interlayer insulating layer along the interval between the first sidewalls until the surface of the floating gate layer is exposed; forming a second sidewall, the second sidewall covering the sidewalls of the interlayer insulating layer, the control gate layer and the first sidewall; etching the floating gate layer and the dielectric layer along the second sidewall to expose the substrate;

[0037] Step S2, forming a third spacer, wherein the third spacer at least covers the side wall of the floating gate layer;

[0038] Step S3, etching the substrate exposed by the third sidewall to form a groove; removing the third sidewall;

[0039] Step S4, forming a word line oxide layer, the word line oxide layer covers the surface of the trench, the sidewall surfaces of the dielectric layer and the floating gate layer, the second sidewall spacer and the sidewall surface of the first sidewall spacer;

[0040] Step S5, filling the space surrounded by the word line oxide layer with polysilicon to form a word line.

[0041] Combine the following Figures 2 to 7 The steps of the method for manufacturing a flash memory according to an embodiment of the present invention are described in detail.

[0042] Please refer to Figure 2A substrate 10 is provided, on which a dielectric layer 11, a floating gate layer 12, an interlayer insulating layer 13, a control gate layer 14 and a sacrificial layer 15 are sequentially formed. The material of the dielectric layer 11 is an oxide, for example, silicon dioxide, and can be formed by a thermal oxidation process. The material of the floating gate layer 12 is polysilicon, and the material of the control gate layer 14 is polysilicon; the floating gate layer 12 and the control gate layer 14 can be formed by chemical vapor deposition (CVDP) or low pressure chemical vapor deposition (LPCVDP) processes. The interlayer insulating layer 13 can be an ONO layer, that is, a stacked structure of silicon dioxide layer-silicon nitride layer-silicon dioxide layer, and the formation method can be a deposition method. The sacrificial layer 15 can be silicon nitride, silicon oxynitride or other high-k materials, and the formation method can be atomic layer deposition (ALD), chemical vapor deposition (CVDP), plasma enhanced chemical vapor deposition (PECVDP) and other processes.

[0043] Next, the sacrificial layer 15 has an opening, and a first sidewall 16 is formed on the sidewall of the sacrificial layer 15 in the opening. The material of the first sidewall 16 is an oxide, such as silicon dioxide, and the material of the sacrificial layer 15 is a nitride, such as silicon nitride. The control gate layer 14 and the interlayer insulating layer 13 are etched along the space between the first sidewalls 16 until the surface of the floating gate layer 12 is exposed. A second sidewall 17 is formed by etching the remaining sidewalls of the interlayer insulating layer 13, the control gate layer 14, and the first sidewall 16. The material of the second sidewall 17 can be an oxide layer and a nitride layer. The floating gate layer 12 and the dielectric layer 11 are etched along the second sidewall 17 to expose the substrate 10.

[0044] Next, please refer to Figure 3 , forming a third spacer 18, the third spacer 18 at least covers the sidewall surface of the remaining floating gate layer 12, and can also extend to cover the sidewall surface of the second spacer 17 and the dielectric layer 11. The material of the third spacer 18 is, for example, an oxide layer, which can be formed by plasma enhanced chemical vapor deposition (PECVDP) or low pressure chemical vapor deposition (LPCVDP).

[0045] Next, please refer to Figure 4 , etching the substrate 10 exposed by the third sidewall 18 to form a groove V. The process steps for forming the groove V may be wet etching or dry etching. The shape of the groove V is, for example, a semicircular, an inverted trapezoidal, a U-shaped, or other regular or irregular shapes. The flash memory structure forms a word line channel by increasing the etching of the substrate silicon at the bottom of the word line, increasing the word line channel length, and increasing the word line turn-on voltage, thereby improving the word line shutdown capability. Without increasing the device area, the word line shutdown capability is adjusted by the etching amount of the substrate silicon. Next, remove the third sidewall.

[0046] Next, please refer to Figure 5, forming a word line oxide layer 19, which covers the surface of the trench, the sidewall surfaces of the dielectric layer 11 and the floating gate layer 12, the second sidewall spacer 17, and the sidewall surfaces of the first sidewall spacer 16. The material of the word line oxide layer 19 is, for example, silicon oxide, and the formation method thereof can be plasma enhanced chemical vapor deposition (PECVDP) or low pressure chemical vapor deposition (LPCVDP).

[0047] Next, please refer to Figure 6 The space surrounded by the word line oxide layer 19 is filled with polysilicon to form the word line 20. The process of forming the polysilicon is, for example, a chemical vapor deposition process, and then a chemical mechanical polishing process is used to flatten the polysilicon to form the word line 20. A protective layer (not shown) is formed on the word line 20.

[0048] Next, please refer to Figure 6 and Figure 7 The sacrificial layer 15 is removed by etching. The control gate layer 14, the interlayer insulating layer 13, the floating gate layer 12 and the dielectric layer 11 are sequentially dry-etched with reference to the first sidewall 16, so that the control gate layer 14 forms two separate control gates 140, and the floating gate layer 12 forms two separate floating gates 120.

[0049] Figure 8 This is a comparison diagram of the word line threshold voltage Vt before and after the flash memory improvement. Please refer to Figure 8 , the word line of flash memory A before improvement is only located above the substrate, the critical dimension at the bottom of the word line is small, the word line channel is short, and the corresponding word line threshold voltage Vt is low, resulting in more programming failures. The word lines of the improved flash memory B and flash memory C are partially located above the substrate, and partially extend into the trench of the substrate. The trench depth of flash memory B is 150 angstroms, and the trench depth of flash memory C is 200 angstroms. The word line threshold voltage Vt of the improved flash memory B and flash memory C is greater than the word line threshold voltage Vt of flash memory A before improvement; and the word line threshold voltage Vt of the improved flash memory C is greater than the word line threshold voltage of the improved flash memory B. The word lines of the improved flash memory B and flash memory C also extend into the trench of the substrate, increasing the word line channel length, increasing the word line threshold voltage Vt, and reducing programming failures.

[0050] Fig. 9 This is a comparison diagram of the voltage Vdp before and after the flash memory is improved. The voltage Vdp refers to the lowest voltage corresponding to the minimum current Idp injected into the drain when the bit is successfully programmed. Please refer to Fig. 9, the word line of flash memory A before improvement is only located above the substrate, the key dimension at the bottom of the word line is small, the word line channel is short, and the corresponding voltage Vdp is large, that is, a higher threshold voltage Vdp is required to achieve programming. The word lines of the improved flash memory B and flash memory C are partially located above the substrate, and partially extend into the trench of the substrate. The trench depth of flash memory B is 150 angstroms, and the trench depth of flash memory C is 200 angstroms. The voltage Vdp of the improved flash memory B and flash memory C are both lower than the voltage Vdp of flash memory A before improvement; and the voltage Vdp of the improved flash memory C is lower than the voltage Vdp of the improved flash memory B, that is, after improvement, as the trench etching depth increases, the voltage Vdp decreases. The word lines of the improved flash memory B and flash memory C also extend into the trench of the substrate, which reduces the voltage Vdp, and the drain end does not need too much voltage to be programmed, and the programming capability is improved.

[0051] The split-gate flash memory cell formed by the method of this embodiment effectively increases the word line channel length of the device under the same lithography scale by extending the word line 20 and embedding it into the substrate 10; and under the general trend of continuous reduction in device size, the split-gate flash memory cell structure of this embodiment can reduce the area of ​​a single flash memory cell and improve the density of the device. Furthermore, the operating voltage of the device can also be reduced, and the device performance of the split-gate flash memory cell can be improved.

[0052] An embodiment of the present invention provides a flash memory, such as Figure 7 As shown, including:

[0053] A substrate 10, on which a dielectric layer 11, a floating gate 120, an interlayer insulating layer 13, a control gate 140 and a first spacer 16 are stacked in sequence on both sides of the opening; a trench is formed in the substrate below the opening;

[0054] A second spacer 17, the second spacer 17 covers the interlayer insulating layer 13, the control gate 140 and the sidewall of the first spacer 16 in the opening;

[0055] A word line oxide layer 19, the word line oxide layer 19 covers the surface of the trench, the sidewall surfaces of the dielectric layer 11 and the floating gate 120, and the sidewall surfaces of the second spacer 17 and the first spacer 16;

[0056] The word line 20 fills the space surrounded by the word line oxide layer 19 .

[0057] The interlayer insulating layer 13 includes a stacked structure of a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer. The floating gate 120, the control gate 140, and the word line 20 are all made of polysilicon.

[0058] In summary, the present invention provides a flash memory and a manufacturing method thereof, the manufacturing method comprising: providing a substrate, sequentially forming a stacked dielectric layer, a floating gate layer, an interlayer insulating layer, a control gate layer and a sacrificial layer with an opening on the substrate, forming a first sidewall on the sidewall of the sacrificial layer in the opening; etching the control gate layer and the interlayer insulating layer along the interval between the first sidewalls until the surface of the floating gate layer is exposed; forming a second sidewall, the second sidewall covers the sidewalls of the interlayer insulating layer, the control gate layer and the first sidewall; etching the floating gate layer and the dielectric layer along the second sidewall to expose the substrate; forming a third sidewall, the third sidewall at least covers the sidewall of the floating gate layer; etching the substrate exposed by the third sidewall to form a groove; removing the third sidewall; forming a word line oxide layer, the word line oxide layer covers the surface of the groove, the sidewall surface of the dielectric layer and the floating gate layer, the second sidewall and the sidewall surface of the first sidewall; using polysilicon to fill the space surrounded by the word line oxide layer to form a word line. The flash memory structure of the present invention forms a groove by increasing the etching of the substrate silicon at the bottom of the word line, that is, forming a word line channel, increasing the length of the word line channel, thereby improving the word line shutdown capability. Without increasing the device area, the word line shutdown capability is adjusted by the etching amount of the substrate silicon.

[0059] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0060] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a flash memory, characterized in that: include: Providing a substrate, sequentially forming a stacked dielectric layer, a floating gate layer, an interlayer insulating layer, a control gate layer and a sacrificial layer with an opening on the substrate, forming a first sidewall on the surface of the control gate layer in the opening; etching the control gate layer and the interlayer insulating layer along the interval between the first sidewalls until the surface of the floating gate layer is exposed; forming a second spacer, wherein the second spacer covers the interlayer insulating layer, the control gate layer and the sidewall of the first spacer; Etching the floating gate layer and the dielectric layer along the second sidewall to expose the substrate; forming a third spacer, wherein the third spacer at least covers a sidewall of the floating gate layer; Etching the substrate exposed by the third sidewall to form a groove; removing the third side wall; forming a word line oxide layer, wherein the word line oxide layer covers the surface of the trench, the sidewall surfaces of the dielectric layer and the floating gate layer, the second sidewall spacer, and the sidewall surface of the first sidewall spacer; The space surrounded by the word line oxide layer is filled with polysilicon to form a word line.

2. The method for manufacturing a flash memory according to claim 1, wherein: The shape of the groove includes: a semicircular shape, an inverted trapezoidal shape, and a U shape.

3. The method for manufacturing a flash memory according to claim 1, wherein: The material of the third sidewall spacer includes: an oxide layer; the process of forming the third sidewall spacer includes: plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

4. The method for manufacturing a flash memory according to claim 1, wherein: The process of forming the groove includes: wet etching or dry etching.

5. The method for manufacturing a flash memory according to claim 1, wherein: The material of the word line oxide layer includes silicon oxide; the process of forming the word line oxide layer includes plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

6. The method for manufacturing a flash memory according to claim 1, wherein: After forming the word line, the manufacturing method further includes: The sacrificial layer is removed by etching, and the control gate layer, the interlayer insulating layer, the floating gate layer and the dielectric layer exposed by the sacrificial layer are sequentially dry-etched with reference to the first side wall, so that after etching, the control gate layer forms two separated control gates, and the floating gate layer forms two separated floating gates.

7. The method for manufacturing a flash memory according to claim 1, wherein: The material of the sacrificial layer includes silicon nitride, silicon oxynitride or high-k material, and the method for forming the sacrificial layer includes one of atomic layer deposition, chemical vapor deposition and plasma enhanced chemical vapor deposition processes.

8. A flash memory, characterized in that: include: A substrate, on which a stacked dielectric layer, a floating gate, an interlayer insulating layer, a control gate and a first sidewall are sequentially formed on both sides of the opening; A groove is formed in the substrate below the opening; a second sidewall spacer, wherein the second sidewall spacer covers the interlayer insulating layer, the control gate and the sidewall of the first sidewall spacer in the opening; A word line oxide layer, wherein the word line oxide layer covers the surface of the trench, the dielectric layer and the side wall surface of the floating gate, and the side wall surface of the second side wall and the first side wall; A word line fills a space surrounded by the word line oxide layer.

9. The flash memory according to claim 8, wherein: The interlayer insulating layer comprises a stacked structure of a silicon dioxide layer, a silicon nitride layer and a silicon dioxide layer.

10. The flash memory according to claim 8, wherein: The floating gate, the control gate and the word line are all made of polysilicon.

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