Magnetic memory element

Abstract

The invention discloses a magnetic memory element which comprises a magnetic tunnel junction stack and a cover layer. The magnetic tunnel junction stack includes a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer. The capping layer is disposed on the magnetic tunnel junction stack and includes a metal underlayer in direct contact with the free layer, an oxide capping layer on the metal underlayer, and a metal protective layer on the oxide capping layer.

Description

Technical Field

[0001] The invention relates to a magnetic memory element, in particular to a magnetoresistive random access memory with a cap layer of a multi-layer structure. Background Art

[0002] Magnetoresistive random access memory (MRAM) is a new type of memory that has received great attention in recent years. It integrates the advantages of various current memories, such as access speed comparable to static random access memory (SRAM), non-volatility and low power consumption of flash memory (flash), and high density and durability of dynamic random access memory (DRAM). It can also be integrated with current semiconductor back-end manufacturing processes, so it has the potential to become the main memory used in semiconductor chips.

[0003] The magnetoresistive random access memory includes a memory stack structure disposed between upper and lower interconnect structures, including a magnetic tunneling junction (MTJ). Unlike conventional memory, which stores data by storing charges, the operation of the magnetoresistive random access memory is to control the magnetization direction of the magnetic tunneling junction by applying an external magnetic field to the magnetic tunneling junction to obtain different tunneling magnetoresistances (TMR) to store digital data. How to improve the thermal stability of the device, the reliability of the data and extend the data retention time is the focus of improving the performance of the magnetoresistive memory. Summary of the invention

[0004] The present invention provides a magnetic memory element, whose stacked structure can generate stronger perpendicular magnetic anisotropy (PMA) and higher magnetic moment density and tunneling magnetoresistance (TMR), and can reduce the problem of tunneling magnetoresistance (TMR) instability caused by impurities diffusing into the magnetic tunneling junction stack, thereby having improved thermal stability, data reliability and extended data retention time.

[0005] According to an embodiment of the present invention, a magnetic memory element is provided, which includes a magnetic tunneling junction stack and a cap layer, wherein the magnetic tunneling junction stack includes a reference layer, a tunneling barrier layer located on the reference layer, and a free layer located on the tunneling barrier layer. The cap layer is disposed on the magnetic tunneling junction stack and includes a metal bottom layer directly contacting the free layer, an oxide cap layer located on the metal bottom layer, and a metal protection layer located on the oxide cap layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 4 FIG. 4 is a cross-sectional view of a magnetic memory element during fabrication according to an embodiment of the present invention.

[0007] Main component symbols

[0008] 10 Base

[0009] 12 Dielectric layer

[0010] 14 Internal connection structure

[0011] 16 Dielectric layer

[0012] 18 Internal connection structure

[0013] 20 Magnetic Tunnel Junction Stack

[0014] 22 Seed layer

[0015] 24 Reference Layer

[0016] 25 Fixed layer

[0017] 26 Tunneling barrier layer

[0018] 28 Free Tiers

[0019] 32 Metal Base

[0020] 34 Oxide capping layer

[0021] 36 Metal protective layer

[0022] 40 Hard mask layer

[0023] 42 protective layer

[0024] 44 Interlayer dielectric layer

[0025] 46 Internal connection structure

[0026] 36a First metal layer

[0027] 36b Second metal layer

[0028] 36c Third metal layer

[0029] CAP Capping Layer

[0030] MC Storage Unit

[0031] P1 Annealing Process

[0032] P2 Patterning Process DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the following is a detailed description of preferred embodiments in conjunction with the attached drawings. The attached drawings are schematic diagrams and are not drawn to scale, and the same or similar features are usually described with the same figure numbers. The embodiments and drawings described herein are for reference and illustration only and are not intended to limit the present invention. The scope of the present invention is defined by the claims. Those with equivalent meanings to the claims of the present invention should also fall within the scope of the present invention.

[0034] Figures 1 to 4 The figure shows the steps of a method for manufacturing a magnetic memory element according to an embodiment of the present invention. Figure 1 First, a substrate 10 is provided, such as a silicon substrate, a silicon-on-insulator substrate, a III-V semiconductor substrate, etc., but not limited thereto. The substrate 10 may include fabricated semiconductor elements, such as transistors, capacitors, resistors, inductors, etc., which are not shown in the drawings for simplicity.

[0035] The substrate 10 may be provided with at least one dielectric layer and an interconnect structure formed in the dielectric layer, such as Figure 1 As shown, the substrate 10 may be provided with a dielectric layer 12, an interconnect structure 14 (e.g., a metal interconnect structure) formed in the dielectric layer 12, another dielectric layer 16 disposed on the dielectric layer 12, and an interconnect structure 18 (e.g., a contact plug) formed in the dielectric layer 16 and directly contacting the interconnect structure 14. The dielectric layer 12 and the dielectric layer 16 may each include silicon oxide (SiO 2 ) or a low-k dielectric material, wherein the low-k dielectric material is, for example, fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on silicon glass (spin-on glass), porous low-k dielectric material or organic polymer dielectric material, but not limited thereto. The interconnect structure 14 and the interconnect structure 18 may include a conductive metal material or a metal compound, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but not limited thereto.

[0036] Please refer to Figure 2. Next, a stacked structure is formed on the substrate 10, which includes a bottom electrode layer BE, a magnetic tunneling junction (MTJ) stack 20, a cap layer CAP, and a hard mask layer 40 in order from bottom to top (from close to the substrate 10 to far away from the substrate 10). Then, the stacked structure is subjected to an annealing process P1 to promote material crystallization, improve interface quality, and determine the magnetization direction of the magnetic tunneling junction stack 20. According to one embodiment of the present invention, the temperature of the annealing process P1 may be between about 350° C. and 450° C., and the time may be between about 30 minutes and 5 hours, but is not limited thereto.

[0037] The bottom electrode layer BE is disposed on the dielectric layer 16 and directly contacts the interconnect structure 18. The bottom electrode layer BE may include a conductive metal material or a metal compound, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof, but is not limited thereto.

[0038] The magnetic tunneling junction stack 20 has a multi-layer structure, including a seed layer 22 at the bottom, and a reference layer 24 , a fixed layer 25 , a tunneling barrier layer 26 , and a free layer 28 sequentially formed on the seed layer 22 .

[0039] The seed layer 22 is used to adjust the crystallization direction of the thin film formed thereon and improve the quality of the interface. The seed layer 22 may have a single-layer or multi-layer structure, and the materials suitable for each layer may include magnesium oxide (MgO), cobalt iron boron (CoFeB), cobalt chromium (CoCr), cobalt tantalum (CoTa), cobalt titanium (CoTi), cobalt vanadium (CoV), tantalum (Ta), iridium (Ir), hafnium (Hf), tungsten (W), molybdenum (Mo), ruthenium (Ru), platinum (Pt), palladium (Pd), nickel chromium (NiCr), nickel tantalum (NiTa), nickel titanium (NiTi), nickel vanadium (NiV), tantalum nitride (TaN), or a combination of the above materials, but not limited thereto.

[0040] The reference layer 24 is used to fix or limit the magnetization direction of the adjacent layer, and mainly includes anti-ferromagnetic (AFM) materials, such as platinum manganese (PtMn), iridium manganese (IrMn), platinum iridium (PtIr) and other materials or a combination thereof, but is not limited thereto.

[0041] The fixed layer 25 and the free layer 28 include ferromagnetic materials, for example, they may include iron (Fe), cobalt (Co), nickel (Ni), iron nickel (FeNi), iron cobalt (FeCo), cobalt nickel (CoNi), iron boron (FeB), iron platinum (FePt), iron palladium (FePd), cobalt iron boron (CoFeB) and other materials or combinations thereof, but are not limited thereto. According to an embodiment of the present invention, the fixed layer 25 and the free layer 28 include cobalt iron boron (CoFeB). The magnetization direction of the fixed layer 25 is fixed by the reference layer 24, and the magnetization direction of the free layer 28 can be flipped by an external magnetic field and is parallel or anti-parallel to the magnetization direction of the fixed layer 25, thereby obtaining tunneling magnetoresistance (TMR) in low resistance state and high resistance state. The ratio of the difference between the resistance value of the high resistance state and the resistance value of the low resistance state to the resistance value of the low resistance state is the tunneling magnetoresistance change rate (TMR ratio), and a higher tunneling magnetoresistance change rate can provide a larger read margin, thereby improving the data reading speed and reliability of the element.

[0042] The tunneling barrier layer 26 is sandwiched between the fixed layer 25 and the free layer 28, and may include metal oxide materials, such as magnesium oxide (MgO), aluminum oxide (AlO), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (TaO), molybdenum oxide (MoO), titanium oxide (TiO), tungsten oxide (WO) and other materials or combinations thereof, but is not limited thereto. According to an embodiment of the present invention, the tunneling barrier layer 26 includes magnesium oxide (MgO), and its interface with the fixed layer 25 and the free layer 28 can produce a strong perpendicular magnetic anisotropy (PMA) and a high magnetic moment density and tunneling magnetoresistance change rate (TMR ratio), which helps to improve the thermal stability of the element, improve the reliability of data, and extend the data retention time. The reference layer 24, the fixed layer 25, the tunneling barrier layer 26 and the free layer 28 can be a single layer or a multi-layer structure, and the thickness of each layer is approximately between a few angstroms. to tens of nanometers (nm).

[0043] The cap layer CAP is directly disposed on the magnetic tunneling junction stack 20, and includes a metal bottom layer 32, an oxide cap layer 34, and a metal protection layer 36. The oxide cap layer 34 includes a metal oxide material, such as magnesium oxide (MgO), aluminum oxide (AlO), nickel oxide (NiO), gadolinium oxide (GdO), tantalum oxide (TaO), molybdenum oxide (MoO), titanium oxide (TiO), tungsten oxide (WO) and the like or a combination thereof, but is not limited thereto. According to one embodiment of the present invention, the oxide cap layer 34 includes magnesium oxide (MgO) or tantalum oxide (TaO), or a combination thereof, to obtain a stronger perpendicular magnetic anisotropy (PMA) and a higher tunneling magnetoresistance change ratio (TMR ratio). According to one embodiment of the present invention, the thickness of the oxide cap layer 34 is preferably controlled to be between about 3 and 10 angstroms to obtain the best technical effect.

[0044] The metal bottom layer 32 is between the oxide cap layer 34 and the free layer 28 and is in direct contact with the free layer 28. The metal bottom layer 32 includes a heavy metal material with stronger spin orbit coupling (SOC) and lower electronegativity, such as but not limited to tantalum (Ta), tungsten (W), hafnium (Hf), molybdenum (Mo), or a combination of the above materials, so as to further strengthen the perpendicular magnetic anisotropy (PMA) of the interface between the oxide cap layer 34 and the free layer 28 and improve the tunneling magnetoresistance ratio (TMR ratio). Preferably, the material of the metal bottom layer 32 includes tantalum (Ta), which can also absorb excess boron (B) elements of the free layer 28 during the annealing process P1 to help the crystallization of the free layer 28. In addition, the metal bottom layer 32 also helps to block impurities (such as elements from the metal protection layer 36 and / or the hard mask layer 40) from diffusing into the magnetic tunneling junction stack 20. According to an embodiment of the present invention, the thickness of the metal bottom layer 32 is preferably controlled to be between about 3 and 5 angstroms to obtain the best technical effect.

[0045] The material of the metal protection layer 36 includes a metal with excellent electrical conductivity and can protect the stacked layer below from being oxidized. Preferably, the main material of the metal protection layer 36 is ruthenium (Ru). Ruthenium (Ru) can react with oxygen to form a dense ruthenium oxide (RuO) on the surface, effectively blocking oxygen from continuing to penetrate and oxidize the material layer below, and ruthenium oxide (RuO) still has excellent electrical conductivity and will not cause abnormal tunneling magnetoresistance (TMR). In some embodiments, the portion of the metal protection layer 36 close to the surface of the oxide cap layer 34 also includes a metal material that is easier to react with unoxidized ruthenium (Ru) to form an alloy, such as but not limited to vanadium (V), manganese (Mn), zinc (Zn), molybdenum (Mo), tantalum (Ta), tungsten (W), rhenium (Re), and osmium (Os), so as to prevent the unoxidized ruthenium (Ru) from diffusing downward to the magnetic tunneling junction stack 20 and affecting the tunneling magnetoresistance (TMR).

[0046] For example, if Figure 2 As shown, the metal protection layer 36 is a composite layer continuously stacked by a first metal layer 36a, a second metal layer 36b and a third metal layer 36c, wherein the materials of the first metal layer 36a and the third metal layer 36c preferably include ruthenium (Ru), and the material of the second metal layer 36b preferably includes tantalum (Ta). The first metal layer 36a (also referred to as the bottom ruthenium layer) is in direct contact with the surface of the oxide cap layer 34, and the thickness is between about 3 and 10 angstroms. The third metal layer 36c (also referred to as the top ruthenium layer) is in direct contact with the hard mask layer 40, and the thickness can be between 2 and 10 times the thickness of the bottom ruthenium layer 36a, for example, between about 10 and 100 angstroms. The second metal layer 36b (also referred to as the middle tantalum layer) is between the bottom ruthenium layer 36a and the top ruthenium layer 36c, and the thickness is between about 3 and 10 angstroms. The hard mask layer 40 is disposed on the metal protection layer 36 and is in direct contact with the third metal layer 36c of the metal protection layer 36. The material of the hard mask layer 40 may include a conductive metal material or a metal compound, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), but is not limited thereto. According to one embodiment of the present invention, the hard mask layer 40 includes titanium nitride (TiN). The hard mask layer 40 may be formed in the patterning process P2 (refer to Figure 3 ) as an etching barrier to protect the structure below it, which helps to obtain a memory cell MC with a more vertical sidewall (reference Figure 3 ), and also serves as the top electrode of the memory cell MC.

[0047] Please refer to Figure 3Next, a patterning process P2 (e.g., photolithography and etching process) is performed to remove the redundant bottom electrode layer BE, the magnetic tunneling junction stack 20, the dielectric cap layer 30, the cap layer CAP and the hard mask layer 40 to obtain the memory cells MC. The memory cells MC are respectively disposed on the interconnection structure 18, and the bottom electrode layer BE contacts and is electrically connected to the interconnection structure 18.

[0048] Please refer to Figure 4 Next, a protective layer 42 is formed on the substrate 10 to conformally cover the surface of the dielectric layer 16 and the top surface and sidewalls of the memory cells MC, and then an interlayer dielectric layer 44 is formed on the protective layer 42 to fully cover the memory cells MC and fill the gaps between the memory cells MC. The protective layer 42 may include an insulating material such as silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbide nitride (SiCN), but is not limited thereto. The interlayer dielectric layer 44 may include silicon oxide (SiO 2 ) or a low-k dielectric material, wherein the low-k dielectric material may include, but is not limited to, fluorinated silica glass (FSG), carbon silicon oxide (SiCOH), spin-on silicon glass (spin-on glass), a porous low-k dielectric material or an organic polymer dielectric material. Next, an interconnect structure 46 is formed, which passes through the interlayer dielectric layer 42 and the protection layer 42 directly above the memory cell MC, and contacts and electrically connects to the hard mask layer 40 (as a top electrode) of the memory cell MC. The interconnect structure 46 may include a conductive metal material or a metal compound, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), but is not limited to these.

[0049] Please continue to refer to Figure 4. The magnetic memory element provided by the present invention has a stacked structure of a memory cell MC which includes a bottom electrode layer BE, a magnetic tunneling junction stack 20, a cap layer CAP, and a hard mask layer 40 in order from bottom to top (from the direction close to the substrate 10 to the direction away from the substrate 10). Specifically, the magnetic tunneling junction stack 20 includes a seed layer 22, a reference layer 24, a fixed layer 25, a tunneling barrier layer 26, and a free layer 28 in order from bottom to top. The cap layer CAP includes a metal bottom layer 32, an oxide cap layer 34, and a metal protection layer 36 in order from bottom to top. The metal bottom layer 32 is sandwiched between the free layer 28 and the oxide cap layer 34, and the bottom surface and the top surface are directly in contact with the free layer 28 and the oxide cap layer 34, respectively. Preferably, the material of the metal bottom layer 32 mainly includes tantalum (Ta), the material of the oxide cap layer 34 mainly includes magnesium oxide (MgO), tantalum oxide (TaO), or a combination thereof, and the metal protection layer 36 is a composite layer including ruthenium (Ru) and tantalum (Ta). Such a configuration can produce stronger perpendicular magnetic anisotropy (PMA) and more stable tunneling magnetoresistance (TMR), resulting in significant improvements in the thermal stability, data reliability, and data retention time of the device.

[0050] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A magnetic memory element, comprising: Magnetic tunnel junction, including: Reference layer; a tunneling barrier layer located on the reference layer; and a free layer located on the tunnel barrier layer; and A cap layer is disposed on the magnetic tunnel junction and includes: A metal bottom layer directly contacts the free layer; an oxide capping layer disposed on the metal base layer; and The metal protection layer is located on the oxide cap layer. 2 . The magnetic memory device as claimed in claim 1 , wherein the tunnel barrier layer comprises magnesium oxide (MgO). 3 . The magnetic memory element of claim 1 , wherein the reference layer and the free layer each comprise cobalt iron boron (CoFeB).

4. The magnetic memory device as claimed in claim 1, wherein the metal bottom layer comprises tantalum (Ta). 5 . The magnetic memory device as claimed in claim 1 , wherein the oxide capping layer comprises magnesium oxide (MgO), tantalum oxide (TaO), or a combination thereof.

6. The magnetic memory device as claimed in claim 1, wherein the thickness of the metal bottom layer is between 3 and 5 angstroms. 7 . The magnetic memory device as claimed in claim 1 , wherein the thickness of the oxide capping layer is between 3 and 10 angstroms. 8 . The magnetic memory element as claimed in claim 1 , wherein the metal protection layer is a composite layer composed of ruthenium (Ru) and tantalum (Ta).

9. The magnetic memory element of claim 1, wherein the metal protection layer comprises a bottom ruthenium layer, a middle tantalum layer on the bottom ruthenium layer, and a top ruthenium layer on the middle tantalum layer, wherein the bottom ruthenium layer directly contacts the oxide capping layer.

10. The magnetic memory device of claim 1, wherein the thickness of the top ruthenium layer is greater than the thickness of the bottom ruthenium layer and the middle tantalum layer. 11 . The magnetic memory element as claimed in claim 1 , further comprising a hard mask layer located on the cap layer and directly contacting the metal protection layer.

12. The magnetic memory element of claim 11, wherein the hard mask layer comprises titanium nitride (TiN).

Images