Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a method for manufacturing the same. The display panel includes an array substrate, a cathode layer, a light-emitting device layer, and an anode layer. The array substrate includes a substrate and a transistor, wherein the transistor is disposed on the substrate, the cathode layer is disposed on a side of the array substrate facing away from the transistor, the light-emitting device layer is disposed on a side of the cathode layer facing away from the array substrate, and the anode layer is disposed on a light-emitting side of the light-emitting device layer. The anode layer is electrically connected to the transistor through an opening in the cathode layer, and the thickness of the anode layer is less than that of the cathode layer. By disposing the cathode layer on one side of the array substrate and the anode layer on the light-emitting side of the light-emitting device layer, and disposing the anode layer on a thickness less than that of the cathode layer, the sheet resistance of the cathode layer can be effectively reduced, thereby achieving the effect of reducing voltage drop, which is beneficial for improving the brightness uniformity of the display panel and reducing power consumption.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for manufacturing the same. Background Art

[0002] In related art, the organic light-emitting diodes in display panels use a top-emission structure, which is beneficial for improving the aperture ratio. However, the cathode layer of a top-emission display panel is located on top of the light-emitting device, and the cathode layer has a high sheet resistance, resulting in a large voltage drop across the display panel, affecting the brightness uniformity and power consumption of the display panel. Summary of the Invention

[0003] In view of this, the present application provides a display panel and a manufacturing method thereof, so as to improve the problem of large voltage drop of a display panel adopting a top emission structure.

[0004] The technical solutions adopted by this application to solve the above technical problems are:

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0006] An array substrate, the array substrate comprising a substrate and transistors, wherein the transistors are arranged on the substrate;

[0007] a cathode layer, provided on a side of the array substrate facing away from the transistor;

[0008] a light emitting device layer, provided on a side of the cathode layer facing away from the array substrate;

[0009] An anode layer is provided on the light-emitting side of the light-emitting device layer, and the anode layer is electrically connected to the transistor through the opening in the cathode layer. The thickness of the anode layer is smaller than that of the cathode layer.

[0010] Optionally, a conductive metal layer is provided in the array substrate, the conductive metal layer is provided on the side of the transistor facing the cathode layer and the conductive metal layer is overlapped with the source of the transistor, and the anode layer is overlapped with the conductive metal layer through an opening in the cathode layer.

[0011] Optionally, the array substrate includes a planarization layer, which is arranged on the side of the transistor facing the cathode layer and covers the conductive metal layer. The planarization layer is provided with a second overlapping hole for exposing a portion of the conductive metal layer, and the anode layer is overlapped with the conductive metal layer through the opening in the cathode layer and the second overlapping hole.

[0012] Optionally, the conductive metal layer includes a first conductive portion, the cathode layer is provided with a through hole, the through hole is connected to the second overlapping hole, and the anode layer is overlapped with the first conductive portion through the through hole and the second overlapping hole.

[0013] Optionally, the conductive metal layer further includes a second conductive portion, which is spaced apart from the first conductive portion. The planarization layer is provided with a first overlapping hole, which exposes the second conductive portion. The cathode layer is overlapped with the second conductive portion through the first overlapping hole.

[0014] Optionally, the planarization layer further defines a third overlapping hole, through which the second conductive portion is overlapped with the transistor, and a maximum aperture of the third overlapping hole is greater than or equal to a maximum aperture of the first overlapping hole.

[0015] Optionally, a dam layer is provided on the side of the planarization layer facing away from the transistor, the dam layer covers the cathode layer and forms a first hollow portion and a second hollow portion, the first hollow portion exposes part of the cathode layer, the light-emitting device layer is provided in the first hollow portion, and the second hollow portion is connected to the second overlapping hole.

[0016] Optionally, a portion of the dam layer used to form the second hollow portion is located in the opening of the cathode layer, so that the cathode layer and the anode layer are isolated from each other by a portion of the dam layer.

[0017] In a second aspect, an embodiment of the present application provides a method for manufacturing a display panel, comprising:

[0018] preparing an array substrate, the array substrate comprising a substrate and transistors, wherein the transistors are arranged on the substrate;

[0019] forming a cathode layer on a side of the array substrate facing away from the transistor;

[0020] forming a light emitting device layer on a side of the cathode layer facing away from the array substrate;

[0021] An anode layer is formed on the light-emitting side of the light-emitting device layer. The anode layer extends into the array substrate through the opening in the cathode layer and is electrically connected to the transistor. The thickness of the anode layer is smaller than that of the cathode layer.

[0022] Optionally, the array substrate includes a conductive metal layer, the conductive metal layer is overlapped with the source electrode of the transistor, and the step of forming a cathode layer on one side of the array substrate includes:

[0023] A first overlapping hole is formed on a side of the array substrate facing away from the transistor, wherein the first overlapping hole exposes a portion of the conductive metal layer;

[0024] Depositing a metal layer on a side of the array substrate facing away from the transistor by physical vapor deposition, wherein the metal layer extends into the first overlapping hole and overlaps the conductive metal layer;

[0025] The metal layer is patterned to form a cathode layer with through holes.

[0026] In summary, due to the adoption of the above technical solution, this application has at least the following beneficial effects:

[0027] The embodiments of the present application provide a display panel and a method for preparing the same. By arranging a cathode layer on one side of an array substrate and an anode layer on the light-emitting side of a light-emitting device layer, and the thickness of the anode layer is less than the thickness of the cathode layer, the sheet resistance of the cathode layer can be effectively reduced, thereby achieving the effect of reducing the voltage drop, which is beneficial to improving the brightness uniformity of the display panel and reducing power consumption. In detail, in a traditional top-emitting structure, the cathode layer is generally located above the anode layer and the cathode layer is located on the light-emitting side of the light-emitting device layer, resulting in the cathode layer needing to ensure both good light transmittance and good electrical conductivity. Therefore, the cathode layer is generally made of magnesium-silver alloy, indium tin oxide, or some transparent conductive polymers. These materials must be thin layers to be both conductive and not affect the light transmittance. Generally, the thickness of the cathode layer will be less than the thickness of the anode layer, making the cathode layer a thin layer design. Such a thin layer design of the cathode layer will inevitably increase the sheet resistance, resulting in a higher voltage drop of the cathode layer. The present application eliminates the need for the cathode layer to be light-transmitting by arranging the cathode layer below the light-emitting device layer and the anode layer above the light-emitting device layer (the light-emitting side of the light-emitting device layer). Then, by making the thickness of the anode layer smaller than the thickness of the cathode layer, since the cathode layer does not need to consider the transmittance, the thickness of the cathode layer can be set large enough to reduce the sheet resistance and thereby achieve the purpose of reducing the voltage drop. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0029] Figure 2 for Figure 1 A schematic diagram of an organic light emitting diode composed of a light emitting device layer, an anode layer, and a cathode layer in a provided display panel;

[0030] Figure 3 A schematic diagram of a partial wiring layout of a display panel provided in an embodiment of the present application;

[0031] Figure 4A flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of a portion of a process for preparing a display panel provided in an embodiment of the present application;

[0033] Figure 6 To continue Figure 5 A schematic diagram of another part of the preparation process of the provided display panel is provided.

[0034] Description of reference numerals:

[0035] 1. Array substrate; 11. Glass substrate; 12. Buffer layer; 13. First gate insulating layer; 14. Second gate insulating layer; 15. Interlayer dielectric layer; 16. Passivation layer; 17. Planarization layer; 171. First planarization layer; 1711. Third overlap hole; 172. Second planarization layer; 173. Third planarization layer; 18. Transistor; 181. Active layer; 182. First gate; 183. Second gate; 184. Source; 185. Drain; 19. Conductive metal layer; 191. First conductive portion; 192. Second conductive portion; 2. Cathode layer; 21. Through hole; 3. Light-emitting device layer; 31. Electron injection layer; 32. Light-emitting layer; 33. Hole transport layer; 34. Hole injection layer; 4. Anode layer; 5. Dam; 6. Encapsulation layer. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0037] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0038] In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0039] See Figure 1 and Figure 3 An embodiment of the present application provides a display panel, which includes an array substrate 1, a cathode layer 2, a light-emitting device layer 3 and an anode layer 4.

[0040] The array substrate 1 includes a substrate and a transistor 18. The transistor 18 is provided on the substrate, which is a glass substrate 11. A cathode layer 2 is provided on the side of the array substrate 1 facing away from the transistor 18. A light-emitting device layer 3 is provided on the side of the cathode layer 2 facing away from the array substrate 1. An anode layer 4 is provided on the light-emitting side of the light-emitting device layer 3. The anode layer 4 is electrically connected to the transistor 18 through an opening in the cathode layer 2. The thickness of the anode layer 4 is less than that of the cathode layer 2.

[0041] It should be noted that, based on the formula for sheet resistance and the formula for voltage drop, the formula for voltage drop can be derived (the formula for sheet resistance, the formula for voltage drop, and the formula for voltage drop are all existing formulas). According to the formula for voltage drop, it can be seen that the magnitude of the voltage drop is related to the current passing through the conductor, the resistivity of the conductor itself, the length of the conductor, and the cross-sectional area of ​​the conductor. Specifically, the voltage drop is directly proportional to the current, resistivity, and length, and inversely proportional to the cross-sectional area of ​​the conductor. In the technical solution of the present application, the cross-sectional area of ​​the conductor is equivalent to the thickness of the cathode layer 2, so the voltage drop of the cathode layer 2 is inversely proportional to the thickness of the cathode layer 2.

[0042] The technical solution provided in this application effectively reduces the sheet resistance of cathode layer 2 by positioning cathode layer 2 on one side of array substrate 1 and anode layer 4 on the light-emitting side of light-emitting device layer 3, with the thickness of anode layer 4 being smaller than that of cathode layer 2. This effectively reduces the sheet resistance of cathode layer 2, thereby reducing voltage drop, thereby improving brightness uniformity of the display panel and reducing power consumption. Specifically, in a traditional top-emitting structure, cathode layer 2 is generally positioned above anode layer 4 and on the light-emitting side of light-emitting device layer 3. This requires cathode layer 2 to ensure both good light transmittance and good electrical conductivity. Therefore, cathode layer 2 is generally made of magnesium-silver alloy, indium tin oxide, or some transparent conductive polymers. These materials must be thin to be both conductive and non-destructive in light transmittance. Generally, the thickness of cathode layer 2 is smaller than that of anode layer 4, resulting in a thin cathode layer design. Since the voltage drop and sheet resistance of cathode layer 2 are both inversely proportional to the thickness of cathode layer 2, such a thin cathode layer design inevitably increases the sheet resistance, resulting in a higher voltage drop in cathode layer 2. The present application eliminates the need for the cathode layer 2 to be light-transmitting by arranging the cathode layer 2 below the light-emitting device layer 3 and the anode layer 4 above the light-emitting device layer 3 (the light-emitting side of the light-emitting device layer 3). Then, by making the thickness of the anode layer 4 smaller than the thickness of the cathode layer 2, since the cathode layer 2 does not need to consider the transmittance, the thickness of the cathode layer 2 can be set to be large enough. Since the thickness of the cathode layer 2 is greater than the thickness of the anode layer 4, compared with the traditional cathode layer 2 having a thickness less than the anode layer 4, the thickness of the cathode layer 2 is increased. According to the voltage drop formula, it can be seen that the sheet resistance of the cathode layer 2 is reduced, thereby achieving the purpose of reducing the voltage drop.

[0043] See Figure 2In some embodiments, the light-emitting device layer 3 includes an electron injection layer 31 , a light-emitting layer 32 , a hole transport layer 33 , and a hole injection layer 34 .

[0044] The electron injection layer 31 is located on the side of the cathode layer 2 facing away from the array substrate 1, facilitating the injection of electrons from the cathode into the light-emitting layer 32. Specifically, the electron injection layer 31 improves the electron injection efficiency by lowering the electron injection barrier and is typically made of a low-work-function material. The light-emitting layer 32 is located on the side of the electron injection layer 31 facing away from the array substrate 1 and is used to emit light. Specifically, electrons and holes recombine in this layer to generate photons. The hole transport layer 33 is located on the side of the light-emitting layer 32 facing away from the array substrate 1 and is used to transport holes injected from the anode to the light-emitting layer 32. Specifically, the hole transport layer 33 is typically made of an organic material with a high hole transport rate to improve device efficiency. The hole injection layer 34 is located on the side of the hole transport layer 33 facing away from the array substrate 1 and is used to improve the efficiency of hole injection from the anode into the hole transport layer 33. The anode layer 4 is located on the side of the hole injection layer 34 facing away from the array substrate 1.

[0045] Furthermore, an encapsulation layer 6 may be provided on the side of the anode layer 4 facing away from the array substrate 1 to protect the light emitting device layer 3 from external moisture, oxygen and physical damage. The encapsulation layer 6 is usually made of an inorganic material or a mixed organic and inorganic material.

[0046] See Figure 1 In some embodiments, the array substrate 1 includes a conductive metal layer 19, which is provided on the side of the transistor 18 facing the cathode layer 2 and is overlapped with the source 184 of the transistor 18. The anode layer 4 passes through the cathode layer 2 and is overlapped with the conductive metal layer 19. In a traditional organic light-emitting diode structure, when current is conducted from the anode layer 4 to the cathode layer 2, it passes through multiple contact interfaces (for example, from the anode to the organic layer, and then to the cathode). At these interfaces, contact resistance will cause a decrease in current conduction efficiency. In this embodiment, by adding a conductive metal layer 19 to the array substrate 1 and directly overlapping the layer with the source 184 of the transistor 18 and the anode layer 4, the contact resistance between these interfaces is reduced. The anode layer 4 is directly connected to the transistor 18 through the conductive metal layer 19, which can significantly reduce the resistance in the overall circuit. The reduction in contact resistance improves the current conduction efficiency, thereby reducing the voltage drop and making the current distribution more uniform.

[0047] Furthermore, the conductive metal layer 19 includes a first conductive portion 191, the cathode layer 2 is provided with a through hole 21, and the anode layer 4 is overlapped with the first conductive portion 191 through the through hole 21. A plurality of transistors 18 are formed on the array substrate 1 of the display panel. Each transistor 18 consists of a source 184, a drain 185 and a gate, and these transistors 18 control the operation of the pixel. A layer of metal material (such as aluminum or copper) is deposited above the transistor 18 of the array substrate 1 and patterned into a conductive metal layer 19. The overlapping layer includes at least one first conductive portion 191, which is located on a side close to the source 184 of the transistor 18. A cathode layer 2 is formed above the array substrate 1, and the cathode layer 2 covers the upper surface of the conductive metal layer 19. In order to achieve electrical connection, a through hole 21 is provided on the cathode layer 2, so that the first conductive portion 191 of the conductive metal layer 19 is partially exposed. The anode layer 4 is deposited on the side of the cathode layer 2 facing away from the array substrate 1, and part of the material of the anode layer 4 is electrically connected to the first conductive portion 191 of the conductive metal layer 19 through the through hole 21 of the cathode layer 2. By providing the through hole 21 in the cathode layer 2 and directly connecting the anode layer 4 to the first conductive portion 191 of the conductive metal layer 19, the number of intermediate layers and possible contact points are reduced, effectively reducing the contact resistance problem caused by multi-layer stacking, and ensuring a more stable electrical connection. In traditional designs, the current between the anode layer 4 and the cathode layer 2 must pass through multiple interfaces, resulting in a large voltage drop. In this embodiment, the anode layer 4 is directly connected to the conductive metal layer 19 through the through hole 21, shortening the current path and reducing the resistance encountered by the current during transmission. In addition, after the anode layer 4 is directly connected to the conductive metal layer 19, the current can be conducted more efficiently, reducing local heat accumulation.

[0048] Furthermore, the conductive metal layer 19 also includes a second conductive portion 192, which is spaced apart from the first conductive portion 191, and the cathode layer 2 overlaps the second conductive portion 192. By patterning the conductive metal layer 19 into two spaced apart conductive portions, the first conductive portion 191 can overlap the anode layer 4, and the second conductive portion 192 can overlap the cathode layer 2. This allows both the anode layer 4 and the cathode layer 2 to be connected to the transistor 18 through the conductive metal layer 19 without interfering with each other.

[0049] See Figure 1 In some embodiments, the array substrate 1 includes a glass substrate 11, a buffer layer 12, a first gate insulating layer 13, a second gate insulating layer 14, an interlayer dielectric layer 15, a passivation layer 16, a planarization layer 17, a conductive metal layer 19, and a transistor 18. The transistor 18 further includes an active layer 181, a source electrode 184, a drain electrode 185, a first gate electrode 182, and a second gate electrode 183. The planarization layer 17 further includes a first planarization layer 171, a second planarization layer 172, and a third planarization layer 173.

[0050] Among them, the planarization layer 17 is arranged on the side of the transistor 18 facing the cathode layer 2 and covers the conductive metal layer 19. The planarization layer 17 is provided with a second overlapping hole for exposing part of the conductive metal layer 19. The anode layer 2 is overlapped with the conductive metal layer 19 through the opening in the cathode layer 2 and the second overlapping hole.

[0051] Along the light-emitting direction, the glass substrate 11, buffer layer 12, first gate insulating layer 13, second gate insulating layer 14, interlayer dielectric layer 15, passivation layer 16, first planarization layer 171, second planarization layer 172, and third planarization layer 173 are stacked in sequence. An active layer 181 is formed on the side of the buffer layer 12 facing away from the glass substrate 11. The first gate insulating layer 13 covers the active layer 181 and defines two first through-holes spaced apart to expose the two ends of the active layer 181. A first gate 182 is provided on the side of the first gate insulating layer 13 facing away from the glass substrate 11. The second gate insulating layer 14 covers the first gate 182. A second gate 183 is provided on the side of the second gate insulating layer 14 facing away from the glass substrate 11. The interlayer dielectric layer 15 covers the second gate 183. The source electrode 184 and the drain electrode 185 are both located on the side of the interlayer dielectric layer 15 facing away from the substrate. The source electrode 184 penetrates the interlayer dielectric layer 15 and the second gate insulating layer 14 and extends into the first through-hole to overlap one end of the active layer 181. The drain electrode 185 penetrates the interlayer dielectric layer 15 and the second gate insulating layer 14 and extends into the other first through-hole to overlap the other end of the active layer 181. The conductive metal layer 19 is disposed on the first planarization layer 171 and extends through the first planarization layer 171 into the passivation layer 16, so that the conductive metal layer 19 can overlap the source electrode 184. Two second through-holes are defined in the second planarization layer 172, exposing the first conductive portion 191 and the second conductive portion 192 of the conductive metal layer 19. The third planarization layer 173 has two third through-holes, one of which is aligned with and connected to one of the second through-holes. The second through hole and the third through hole connected to each other constitute a lap hole, namely a first lap hole and a second lap hole, wherein the second lap hole is connected to the through hole 21, so that the anode can overlap with the second conductive portion 192 in the conductive metal layer 19 through the through hole 21 and the through hole group. The cathode layer 2 is overlapped with the second conductive portion 192 through the first lap hole.

[0052] In some embodiments, the cathode layer 2 is a reflective metal layer, which can be made of a metal material with excellent reflective properties, such as aluminum, silver or its alloys, and the thickness of the cathode layer 2 is controlled between 1200nm and 1800nm. This thickness range is achieved through physical vapor deposition technology to ensure that the cathode layer 2 has both good conductivity and excellent reflective properties. The reflective metal layer of the cathode layer 2 reduces light loss by reflecting photons in the light-emitting device layer 3. This reflective layer will reflect photons that fail to pass directly through the anode layer 4 back to the light-emitting device layer 3, re-enter the anode layer 4 and emit outward, thereby improving the overall luminous efficiency. When the thickness of the cathode layer 2 is in the range of 1200nm to 1800nm, it can provide sufficient thickness to ensure low resistance while maintaining good reflectivity. Lower resistance reduces the loss during current conduction, thereby reducing the voltage drop and further improving the current conduction efficiency of the display panel.

[0053] Furthermore, the planarization layer 17 is also provided with a third overlapping hole 1711. Specifically, the third overlapping hole 1711 is formed by penetrating the first planarization layer 171 and extending to open a portion of the passivation layer 16. That is, a countersunk hole is formed on the passivation layer 16 and is aligned with the through hole penetrating the first planarization layer 171. The countersunk hole and the through hole together constitute the third overlapping hole 1711. The second conductive portion 192 is overlapped with the transistor 18 through the third overlapping hole 1711. The maximum aperture of the third overlapping hole 1711 is greater than or equal to the maximum aperture of the first overlapping hole. Through such a setting, compared with the traditional structure in which the cathode is set at the top and overlaps with the metal conductive portion, the third overlapping hole 1711 is significantly smaller, which helps to achieve a narrow frame effect for the display panel.

[0054] In some embodiments, the light emitting direction of the light emitting device layer 3 is from the light emitting device layer 3 toward the anode layer 4, so that the display panel is a top-emitting structure, and the cathode layer 2 and the anode layer 4 are respectively arranged on both sides of the light emitting device layer 3, and the cathode layer 2 is arranged below the anode layer 4, so that there is no need to consider the transmittance of the cathode layer 2. Compared with the bottom-emitting structure, the top-emitting structure is not limited by the limitations of the circuit routing, and thus has a larger aperture ratio. By combining the cathode layer 2 arranged below the anode layer 4, and the thickness range of 1200nm to 1800nm, the cathode layer 2 has sufficient thickness, thereby improving the problem of large voltage drop in the top-emitting structure.

[0055] In some embodiments, a dam layer is provided on the side of the third planarization layer 173 facing away from the glass substrate 11. The dam layer covers the cathode layer 2 and forms a first hollow portion and a second hollow portion. The first hollow portion exposes a portion of the cathode layer. The light-emitting device layer 3 is provided within the first hollow portion, and the second hollow portion communicates with the second overlap hole. After patterning, the dam layer forms a plurality of spaced dams 5. Adjacent dams 5 define a first hollow portion for accommodating the light-emitting device layer 3 and a second hollow portion for allowing the anode layer 4 to pass through the through hole 21. The anode layer 4 is provided on the side of the dams 5 facing away from the glass substrate 11 and extends through the dams 5 into the second overlap hole, overlapping the second conductive portion 192.

[0056] Furthermore, a portion of the dam layer, which is used to form the second hollow portion, is located within the opening (through-hole 21) of the cathode layer 2, thereby isolating the cathode layer 2 from the anode layer 4 via a portion of the dam layer. Specifically, a portion of the dam 5 is located within the through-hole 21 and serves as the inner wall of the second hollow portion. When the anode layer 4 passes through the through-hole 21, it actually passes through the second hollow portion. The anode layer 4 is isolated from the cathode layer 2 by the dam 5, preventing a short circuit between the anode layer 4 and the cathode layer 2 when the anode layer 4 is connected to the transistor 18.

[0057] Please also see Figures 4 to 6 , an embodiment of the present application further provides a method for preparing a display panel, comprising:

[0058] S1. Prepare an array substrate, which includes a substrate and transistors, wherein the transistors are arranged on the substrate.

[0059] On the display panel substrate, thin film deposition and photolithography techniques are used to form multiple transistors 18. These transistors 18 consist of a source 184, a drain 185, and a gate electrode, and are responsible for driving each pixel in the display panel. Transistors 18 are integrated into the array substrate 1 using standard semiconductor manufacturing processes (such as low-temperature polysilicon or oxide semiconductor technology). This step ensures that each pixel can be independently controlled.

[0060] The steps for preparing the array substrate 1 include:

[0061] forming a buffer layer 12 on a glass substrate 11;

[0062] An active layer 181 is formed on a side of the buffer layer 12 facing away from the glass substrate 11;

[0063] A first gate insulating layer 13 is formed on a side of the buffer layer 12 facing away from the glass substrate 11 , and the first gate insulating layer 13 covers the active layer 181 ;

[0064] A first gate electrode 182 is formed on a side of the first gate insulating layer 13 facing away from the glass substrate 11;

[0065] A second gate insulating layer 14 is formed on a side of the first gate insulating layer 13 facing away from the glass substrate 11 , and the second gate insulating layer 14 covers the first gate 182 ;

[0066] A second gate 183 is formed on a side of the second gate insulating layer 14 facing away from the glass substrate 11 , and the first gate 182 and the second gate 183 are arranged in alignment;

[0067] An interlayer dielectric layer 15 is formed on a side of the second gate insulating layer 14 facing away from the glass substrate 11 , and the interlayer dielectric layer 15 covers the second gate 183 ;

[0068] The interlayer dielectric layer 15, the second gate insulating layer 14 and the first gate insulating layer 13 are etched to form two first through holes, which are respectively located on both sides of the first gate 182 and expose both ends of the active layer 181;

[0069] A metal layer is formed on a side of the interlayer dielectric layer 15 facing away from the glass substrate 11, and the metal layer is patterned to form a source electrode 184 and a drain electrode 185 of the transistor 18. The source electrode 184 extends into a first through hole and overlaps one end of the active layer 181. The drain electrode 185 extends into another first through hole and overlaps the other end of the active layer 181.

[0070] A passivation layer 16 is formed on a side of the interlayer dielectric layer 15 facing away from the glass substrate 11 , and the passivation layer 16 covers the source electrode 184 and the drain electrode 185 ;

[0071] A first planarization layer 171 is formed on a side of the passivation layer 16 facing away from the glass substrate 11 and the first planarization layer 171 is etched to form two second through holes, wherein the second through holes expose the source electrode 184 and a portion of the unpatterned metal layer;

[0072] A conductive metal layer 19 is formed on a side of the first planarization layer 171 facing away from the glass substrate 11, and the conductive metal layer 19 is patterned to form a first conductive portion 191 and a second conductive portion 192. The first conductive portion 191 and the second conductive portion 192 are respectively connected to the source electrode 184 and the unpatterned portion of the metal layer through the second through hole.

[0073] A second planarizing layer 172 and a third planarizing layer 173 are stacked in sequence on the side of the first planarizing layer 171 facing away from the glass substrate 11, and the second planarizing layer 172 and the third planarizing layer 173 are etched to form a first overlapping hole and a second overlapping hole. The first overlapping hole exposes the first conductive portion 191, and the second overlapping hole exposes the second conductive portion 192.

[0074] S2. Forming a cathode layer on a side of the array substrate facing away from the transistor.

[0075] A cathode layer 2 is deposited on the surface of the array substrate 1 using physical vapor deposition technology. The cathode layer 2 is typically made of a reflective metal material (such as aluminum or silver) with a thickness between 1200nm and 1800nm ​​to ensure good conductivity and effective light reflection.

[0076] The step of forming the cathode layer 2 on one side of the array substrate further includes:

[0077] A first overlapping hole is formed on a side of the array substrate facing away from the transistor, wherein a portion of the conductive metal layer is exposed through the first overlapping hole;

[0078] Depositing a metal layer on a side of the array substrate facing away from the transistor by physical vapor deposition, wherein the metal layer extends into the first overlapping hole and overlaps the conductive metal layer;

[0079] The metal layer is patterned to form a cathode layer with through holes.

[0080] Above the planarization layer 17, a metal layer is deposited by a physical vapor deposition process. The metal layer is usually made of a highly reflective and conductive metal material (such as aluminum or silver). During the deposition process, the metal layer not only covers the entire planarization layer 17, but also extends to the inside of the first overlapping hole previously patterned, and is electrically connected to the conductive metal layer 19 at the bottom. The deposited metal layer is patterned by photolithography and etching processes to form a cathode layer 2 of a specific shape. The cathode layer 2 is provided with through holes 21 in specific areas, which are used to connect the anode layer 4 to the lower electrode. The metal layer deposited by the physical vapor deposition process can extend to the first overlapping hole and contact the conductive metal layer 19, which not only forms the main part of the cathode layer 2, but also ensures good electrical connection between the cathode layer 2 and the conductive metal layer 19. This process reduces the problem of increased resistance due to poor contact, especially in the case of large current conduction, and can significantly improve the stability and reliability of the connection. Since the cathode layer 2 is deposited and patterned through a physical vapor deposition process, and extends into the first overlapping hole, tightly bonding with the conductive metal layer 19 at the bottom, this structural design can improve the mechanical bonding strength between the entire cathode layer 2 and the substrate, and reduce the delamination or peeling phenomenon that may be caused during subsequent processing (such as interlayer stress, temperature changes, etc.).

[0081] The step of opening a first overlapping hole on a side of the array substrate facing away from the transistor, wherein the first overlapping hole exposes a portion of the conductive metal layer, specifically includes:

[0082] A first planarization layer 171 is formed on a side of the passivation layer 16 facing away from the glass substrate 11 and the first planarization layer 171 is etched to form two second through holes, wherein the second through holes expose the source electrode 184 and a portion of the unpatterned metal layer;

[0083] A conductive metal layer 19 is formed on a side of the first planarization layer 171 facing away from the glass substrate 11, and the conductive metal layer 19 is patterned to form a first conductive portion 191 and a second conductive portion 192. The first conductive portion 191 and the second conductive portion 192 are respectively connected to the source electrode 184 and the unpatterned portion of the metal layer through the second through hole.

[0084] A second planarizing layer 172 and a third planarizing layer 173 are stacked in sequence on the side of the first planarizing layer 171 facing away from the glass substrate 11, and the second planarizing layer 172 and the third planarizing layer 173 are etched to form a first overlapping hole and a second overlapping hole. The first overlapping hole exposes the first conductive portion 191, and the second overlapping hole exposes the second conductive portion 192.

[0085] S3. Forming a light-emitting device layer on a side of the cathode layer facing away from the array substrate.

[0086] A light-emitting device layer 3 is formed above the cathode layer 2 using organic vapor deposition or inkjet printing techniques. This layer typically consists of multiple organic layers, including a hole injection layer 34, a light-emitting layer 32, and an electron injection layer 31. The materials and thicknesses of these organic layers are precisely controlled to ensure excellent luminous efficiency and color rendering. The structure of the light-emitting device layer 3 ensures that current is efficiently injected into the light-emitting material, generating efficient light output.

[0087] The step of forming the light emitting device layer 3 on the side of the cathode layer 2 facing away from the array substrate 1 further includes:

[0088] An electron injection layer 31 is formed on a side of the cathode layer 2 facing away from the array substrate 1 .

[0089] An electron injection layer 31 is formed on the cathode layer 2 by organic vapor deposition or other appropriate techniques. The electron injection layer 31 is composed of a low-work function material (such as a lithium-doped organic material) and is used to efficiently inject electrons into the light-emitting layer 32. The material and thickness of the electron injection layer 31 are optimized to ensure efficient electron injection into the light-emitting layer 32.

[0090] A light emitting layer 32 is formed on a side of the electron injection layer 31 facing away from the array substrate 1 .

[0091] A light-emitting layer 32 is formed above the electron injection layer 31. The light-emitting layer 32 is typically made of an organic light-emitting material, such as a fluorescent material or a phosphorescent material. The light-emitting layer 32 emits light through the recombination of electrons and holes, thereby achieving light output from the display panel.

[0092] A hole transport layer 33 is formed on a side of the light emitting layer 32 facing away from the array substrate 1 .

[0093] A hole transport layer 33 is deposited on the light emitting layer 32 to effectively conduct holes to the light emitting layer 32 and recombine with electrons in the light emitting layer 32. The hole transport layer 33 is generally made of a material with high hole mobility to improve light emitting efficiency and stability.

[0094] A hole injection layer 34 is formed on a side of the hole transport layer 33 facing away from the array substrate 1 , and the anode layer 4 is provided on a side of the hole injection layer 34 facing away from the array substrate 1 .

[0095] A hole injection layer 34 is formed on the hole transport layer 33. Its primary function is to inject holes from the anode layer 4 into the hole transport layer 33. The hole injection layer 34 is made of a high-work-function material to ensure that holes can smoothly enter the hole transport layer 33 from the anode. An anode layer 4 is formed on the side of the hole injection layer 34 facing away from the array substrate 1. The anode layer 4 is typically made of a transparent conductive material to ensure that light can effectively transmit to the outside and complete the circuit.

[0096] Between the step of forming the cathode layer 2 on one side of the array substrate 1 and the step of forming the light emitting device layer 3 on the side of the cathode layer 2 facing away from the array substrate 1, the method further includes:

[0097] A dam layer is formed on the third planarization layer 173. The dam layer covers the cathode layer 2 and is patterned to form a plurality of spaced dams 5. Each dam 5 only covers a portion of the cathode layer 2, thereby exposing the cathode layer 2 between two adjacent dams 5. The space between the two spaced dams 5 accommodates the light-emitting device layer 3. The dams 5 are provided with connecting through-holes that align and communicate with the second overlapping holes. These connecting through-holes allow the anode to extend into the second overlapping holes and overlap the second conductive portion 192. The dam layer can have a double-layer structure, a multi-layer structure, or a single-layer structure, without limitation.

[0098] S4. Form an anode layer on the light-emitting side of the light-emitting device layer. The anode layer extends into the array substrate through the opening in the cathode layer and is electrically connected to the transistor. The thickness of the anode layer is smaller than that of the cathode layer.

[0099] An anode layer 4 is deposited on the light-emitting side of the light-emitting device layer 3. This anode layer 4 is made of a transparent conductive material (such as ITO or IGZO), ensuring that light can be effectively transmitted through the anode layer 4 to the outside world. The anode layer 4 extends directly through the pre-set through-hole 21 in the cathode layer 2 to the array substrate 1 below, and is electrically connected to the source 184 or drain 185 of the transistor 18. This step ensures an effective connection between the anode layer 4 and the underlying drive circuitry, ensuring smooth current conduction.

[0100] Regarding the technical solution of the method for preparing the display panel provided in the present application, although it has one more preparation process compared to the traditional preparation method, it can improve the problems of limited aperture ratio and excessive voltage drop. The display panel prepared by this preparation method can effectively reduce the sheet resistance of the cathode layer 2 by arranging the cathode layer 2 on one side of the array substrate 1 and arranging the anode layer 4 on the light-emitting side of the light-emitting device layer 3, and the thickness of the anode layer 4 is less than the thickness of the cathode layer 2, thereby achieving the effect of reducing the voltage drop, which is beneficial to improving the brightness uniformity of the display panel and reducing power consumption. In detail, in the traditional top emission structure, the cathode layer 2 is generally located above the anode layer 4 and the cathode layer 2 is located on the light-emitting side of the light-emitting device layer 3, resulting in the cathode layer 2 needing to ensure both good light transmittance and good electrical conductivity. Therefore, the cathode layer 2 is generally made of magnesium silver alloy, indium tin oxide, or some transparent conductive polymers. These materials must be thin layers to be both conductive and not affect the light transmittance. Generally, the thickness of the cathode layer 2 is smaller than that of the anode layer 4, making the cathode layer 2 a thin layer design. Such a thin layer design of the cathode layer 2 will inevitably increase the sheet resistance, thereby resulting in a higher voltage drop in the cathode layer 2. However, the present application eliminates the need for the cathode layer 2 to be light-transmissive by arranging the cathode layer 2 below the light-emitting device layer 3 and the anode layer 4 above the light-emitting device layer 3 (on the light-emitting side of the light-emitting device layer 3). Then, by making the thickness of the anode layer 4 smaller than that of the cathode layer 2, since the cathode layer 2 does not need to consider the transmittance, the thickness of the cathode layer 2 can be set to be large enough, thereby reducing the sheet resistance and then achieving the purpose of reducing the voltage drop.

[0101] At the same time, this application uses specific terms to describe the embodiments of this application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "one embodiment," "an embodiment," or "an alternative embodiment" mentioned twice or multiple times in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application may be appropriately combined.

[0102] Similarly, it should be noted that, in order to simplify the description of the present disclosure and thus facilitate understanding of one or more embodiments of the present disclosure, the foregoing description of the embodiments of the present disclosure sometimes combines multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not mean that the present disclosure requires more features than those recited in the claims. In fact, the features of the embodiments may be fewer than the total features of the individual embodiments disclosed above.

Claims

1. A display panel, characterized in that: include: An array substrate, the array substrate comprising a substrate and transistors, wherein the transistors are arranged on the substrate; a cathode layer, provided on a side of the array substrate facing away from the transistor; a light emitting device layer, provided on a side of the cathode layer facing away from the array substrate; an anode layer, provided on a light-emitting side of the light-emitting device layer, and electrically connected to the transistor through an opening in the cathode layer, wherein the thickness of the anode layer is smaller than that of the cathode layer; The array substrate includes a conductive metal layer, the conductive metal layer is provided on a side of the transistor facing the cathode layer and the conductive metal layer overlaps the source electrode of the transistor, and the anode layer overlaps the conductive metal layer through an opening in the cathode layer; The array substrate includes a planarization layer, the planarization layer is provided on a side of the transistor facing the cathode layer and covers the conductive metal layer, the planarization layer is provided with a second overlapping hole for exposing a portion of the conductive metal layer, and the anode layer is overlapped with the conductive metal layer through the opening in the cathode layer and the second overlapping hole; The conductive metal layer includes a first conductive portion, the cathode layer is provided with a through hole, the through hole is connected to the second overlapping hole, and the anode layer is overlapped with the first conductive portion through the through hole and the second overlapping hole; The conductive metal layer further includes a second conductive portion, the second conductive portion is spaced apart from the first conductive portion, the planarization layer is provided with a first overlapping hole, the first overlapping hole exposes the second conductive portion, and the cathode layer overlaps the second conductive portion through the first overlapping hole; The planarization layer is further provided with a third overlapping hole, through which the second conductive portion is overlapped with the transistor, and a maximum aperture of the third overlapping hole is greater than or equal to a maximum aperture of the first overlapping hole.

2. The display panel according to claim 1, wherein A dam layer is provided on the side of the planarization layer facing away from the transistor, and the dam layer covers the cathode layer and forms a first hollow portion and a second hollow portion. The first hollow portion exposes part of the cathode layer, and the light-emitting device layer is provided in the first hollow portion. The second hollow portion is connected to the second overlapping hole.

3. The display panel according to claim 2, wherein: A portion of the dam layer used to form the second hollow portion is located in the opening of the cathode layer, so that the cathode layer and the anode layer are isolated from each other by the portion of the dam layer.

4. A method for preparing a display panel, characterized in that: include: preparing an array substrate, the array substrate comprising a substrate and transistors, wherein the transistors are arranged on the substrate; forming a cathode layer on a side of the array substrate facing away from the transistor; forming a light emitting device layer on a side of the cathode layer facing away from the array substrate; forming an anode layer on a light-emitting side of the light-emitting device layer, wherein the anode layer extends into the array substrate through the opening in the cathode layer and is electrically connected to the transistor, and the thickness of the anode layer is smaller than the thickness of the cathode layer; The array substrate includes a conductive metal layer, the conductive metal layer is provided on a side of the transistor facing the cathode layer and the conductive metal layer overlaps the source electrode of the transistor, and the anode layer overlaps the conductive metal layer through an opening in the cathode layer; The array substrate includes a planarization layer, the planarization layer is provided on a side of the transistor facing the cathode layer and covers the conductive metal layer, the planarization layer is provided with a second overlapping hole for exposing a portion of the conductive metal layer, and the anode layer is overlapped with the conductive metal layer through the opening in the cathode layer and the second overlapping hole; The conductive metal layer includes a first conductive portion, the cathode layer is provided with a through hole, the through hole is connected to the second overlapping hole, and the anode layer is overlapped with the first conductive portion through the through hole and the second overlapping hole; The conductive metal layer further includes a second conductive portion, the second conductive portion is spaced apart from the first conductive portion, the planarization layer is provided with a first overlapping hole, the first overlapping hole exposes the second conductive portion, and the cathode layer overlaps the second conductive portion through the first overlapping hole; The planarization layer is further provided with a third overlapping hole, through which the second conductive portion is overlapped with the transistor, and a maximum aperture of the third overlapping hole is greater than or equal to a maximum aperture of the first overlapping hole.

5. The preparation method according to claim 4, wherein The step of forming a cathode layer on one side of the array substrate includes: A first overlapping hole is formed on a side of the array substrate facing away from the transistor, wherein the first overlapping hole exposes a portion of the conductive metal layer; Depositing a metal layer on a side of the array substrate facing away from the transistor by physical vapor deposition, wherein the metal layer extends into the first overlapping hole and overlaps the conductive metal layer; The metal layer is patterned to form a cathode layer with through holes.

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