Scheduling method and related device

Abstract

The embodiment of the invention provides a scheduling method and a related device. The virtual machine system comprises a host, the host creates a plurality of virtual machines according to acquired virtual machine configuration information, the plurality of virtual machines share computing power of a processor, and the processor allocates a time slice for each virtual machine in the plurality of virtual machines according to received first configuration information from the host, the first configuration information is used for indicating the computing power proportion of each virtual machine in the multiple virtual machines, and the larger the computing power proportion is, the more the time slices are distributed to the virtual machine. The computing power requirement of each virtual machine can be met, and the reasonability of time slice distribution in each virtual machine is ensured. The embodiment provided by the invention can be applied to intelligent computing equipment such as an intelligent automobile or a new energy automobile.

Description

Scheduling method and related device Technical Field

[0001] The present application relates to the field of information technology, and in particular to a scheduling method and related devices. Background Art

[0002] Artificial intelligence (AI) is the theory, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, to perceive the environment, acquire knowledge, and use that knowledge to make decisions. In other words, AI is a branch of computer science that seeks to understand the essence of intelligence and develop new intelligent machines that can respond in a manner similar to human intelligence. AI also studies the design principles and implementation methods of various intelligent machines, enabling them to possess the capabilities of perception, reasoning, and decision-making. Research in the field of AI includes robotics, natural language processing, computer vision, decision-making and reasoning, human-computer interaction, recommendation and search, and basic AI theory.

[0003] However, the computing resources of smart cars or other smart terminals are limited, which brings challenges to the practical application of artificial intelligence.

[0004] Summary of the Invention

[0005] The present application provides a scheduling method and related devices, which meet the computing power requirements of each virtual machine and ensure the rationality of time slice allocation in each virtual machine.

[0006] In a first aspect, the present application provides a scheduling method, which is applied to a virtual machine system, wherein the virtual machine system includes multiple virtual machines, and the multiple virtual machines share the computing power of a processor. The method includes: the processor allocates a time slice to each of the multiple virtual machines according to first configuration information, and the first configuration information is used to indicate the computing power ratio of each virtual machine in the multiple virtual machines; when the time slice exists in the first virtual machine among the multiple virtual machines and a first task is being executed, a second task arrives, the processor stops executing the first task and schedules the execution of the second task, and the priority of the execution sequence to which the second task belongs is higher than the priority of the execution sequence to which the first task belongs.

[0007] In this method, the processor allocates time slices to each virtual machine in the virtual machine system according to the computing power ratio of each virtual machine in multiple virtual machines. The virtual machine with a larger computing power ratio is allocated more time slices, thereby realizing the sharing of processor computing power by multiple virtual machines and meeting the computing power requirements of each virtual machine; and when a high-priority task arrives, it is executed first, which can ensure the real-time execution of the high-priority task.

[0008] In one possible implementation, the first virtual machine among the multiple virtual machines includes n execution sequences, where n is an integer greater than or equal to 0; the method also includes: the processor allocates the time slices to s execution sequences among the n execution sequences according to the first configuration information and the second configuration information, the second configuration information is used to indicate the priority of the n execution sequences in the first virtual machine, and s is an integer less than or equal to n.

[0009] In this implementation, the first virtual machine is any one of multiple virtual machines in the virtual machine system. The first virtual machine includes n execution sequences. The processor allocates time slices to s execution sequences among the n execution sequences according to the priorities of the n execution sequences in the first virtual machine. The higher the priority of the s execution sequences, the more time slices are allocated to them, thereby realizing the two-level allocation of time slices, meeting the computing power requirements of each execution sequence in the first virtual machine, and ensuring the rationality of allocating time slices to each execution sequence.

[0010] In one possible implementation, the priority of the execution sequence in the first virtual machine includes a normal type priority and a real-time type priority, and the real-time type priority is higher than the normal type priority; wherein the priority of the s execution sequences is the normal type priority.

[0011] In this implementation, the priority of the execution sequence in the first virtual machine includes a normal type priority and a real-time type priority. The processor allocates time slices only to the execution sequence with a normal type priority among the n execution sequences according to the priorities of the n execution sequences in the first virtual machine. The execution sequence with a real-time type priority is scheduled according to actual needs. As long as the first virtual machine has a time slice, the execution sequence with a real-time type priority can be scheduled, thereby ensuring the real-time nature of real-time services.

[0012] In a possible implementation, the method further includes: the processor allocating the time slice to each virtual machine according to the first configuration information and third configuration information, wherein the third configuration information is used to indicate the period length of the time slice allocated by the processor to the multiple virtual machines.

[0013] In this implementation, the processor allocates time slices to multiple virtual machines in the virtual machine system according to the period indicated by the third configuration information, thereby meeting the computing power requirements of each virtual machine and ensuring that various services in the virtual machine can be completed on time and as needed.

[0014] In a possible implementation, the processor allocates time slices for the multiple virtual machines with a period length greater than or equal to a period length of an execution period of an execution sequence with a real-time priority.

[0015] In this implementation, the processor allocates time slices to multiple virtual machines in the virtual machine system with a period length greater than or equal to the period length of the execution period of the execution sequence with a real-time type priority, so that when the real-time task in the virtual machine is completed, time slices are reallocated to multiple virtual machines, thereby ensuring the real-time nature of the real-time task.

[0016] In a possible implementation manner, the method further includes: the processor receiving the first configuration information.

[0017] In one possible implementation, the method further includes: when a time slice and x first execution sequences and q second execution sequences to be executed exist in a first virtual machine among the multiple virtual machines, the processor preferentially schedules tasks in the q second execution sequences, the priority of the first execution sequence is a normal priority, the priority of the second execution sequence is a real-time priority, and x and q are integers greater than or equal to 0. In this implementation, when the first virtual machine includes both execution sequences with a normal priority and execution sequences with a real-time priority, the processor preferentially schedules tasks in the execution sequence with a real-time priority, thereby ensuring the real-time nature of real-time tasks.

[0018] In one possible implementation, the processor prioritizes scheduling tasks in the q second execution sequences, including: the real-time type priorities in the q second execution sequences also include a first real-time priority and a second real-time priority, and the priority of the first real-time priority is higher than the second real-time priority; the processor prioritizes scheduling tasks of the first real-time priority in the q second execution sequences.

[0019] In this implementation, when there are multiple execution sequences with real-time priority to be executed in the first virtual machine, the processor prioritizes scheduling tasks in the execution sequence with a higher real-time priority level. In many cases, when executing tasks in the execution sequence with a lower real-time priority level, the execution results of tasks in the execution sequence with a higher real-time priority level are needed. Therefore, prioritizing the execution of tasks in the execution sequence with a higher real-time priority level helps to ensure the real-time nature of real-time tasks and improves the execution efficiency of real-time tasks.

[0020] In a possible implementation, the first task belongs to any one of the x first execution sequences, and the second task belongs to any one of the q second execution sequences.

[0021] In this implementation, in the first virtual machine, when a task of normal priority is being executed, if a task of real-time priority arrives, the processor stops scheduling the task of normal priority and starts scheduling the task of real-time priority, thereby ensuring the real-time nature of the real-time task.

[0022] In one possible implementation, if there is a time slice allocation ratio in the x first execution sequences, then after the execution of the tasks in the q second execution sequences is completed, the processor allocates the remaining time slices to the x first execution sequences according to the time slice allocation ratio, and the remaining time slices are the difference between the sum of the time slices allocated by the processor to the x first execution sequences and the time slices used for the execution of the tasks in the q second execution sequences.

[0023] In this implementation, when the real-time priority task is completed, the processor allocates the remaining time slices to the ordinary priority execution sequence according to the original time slice allocation ratio, so that the time slices of the ordinary priority execution sequence still meet the time slice allocation ratio.

[0024] In a possible implementation, the first task and the second task belong to different execution sequences among the q second execution sequences, and the priority of the execution sequence to which the second task belongs is higher than the priority of the execution sequence to which the first task belongs.

[0025] In this implementation, in the first virtual machine, when a task with a low real-time priority level is being executed, if a task with a high real-time priority level arrives, the processor stops scheduling the task with the low real-time priority level and starts scheduling the task with the high real-time priority level, thereby ensuring that the tasks with the real-time priority level in the first virtual machine can be executed in descending order of priority level, ensuring the real-time nature of the real-time tasks and improving the execution efficiency of the real-time tasks.

[0026] In one possible implementation, the method further includes: the processor obtaining the total execution time and the current execution time of the first task; the processor calculating the remaining execution time of the first task based on the total execution time of the first task and the current execution time; when the remaining execution time of the first task is less than a preset threshold, the processor executes the first task.

[0027] In this implementation, in the first virtual machine, the first task is being executed and the second task arrives. Before the processor triggers task switching, it first calculates the remaining execution time of the first task based on the total execution time of the first task and the current execution time. When the remaining execution time of the first task is less than the preset threshold, the processor still executes the first task to ensure that the current first task is completed, so as to save system resources and improve the execution efficiency of the business.

[0028] In a possible implementation, the method further includes: the processor obtains the total execution time and the current execution time of the first task; the processor calculates the remaining execution time of the first task based on the total execution time of the first task and the current execution time; when the remaining execution time of the first task is less than the product of the preset switching backup time of the first task and a preset multiple, the processor executes the first task.

[0029] In this implementation, in the first virtual machine, the first task is being executed and the second task arrives. Before the processor triggers task switching, it first calculates the remaining execution time of the first task based on the total execution time of the first task and the current execution time. When the remaining execution time of the first task is less than the product of the preset switching backup time of the first task and the preset multiple, the processor still executes the first task to ensure that the current first task is completed, so as to save system resources and improve the execution efficiency of the business.

[0030] In one possible implementation, the method further includes: the processor obtaining the total execution time and the current execution time of the first task; the processor calculating the remaining execution time of the first task based on the total execution time of the first task and the current execution time; when the remaining execution time of the first task is greater than or equal to a preset threshold, the processor stops executing the first task.

[0031] In this implementation, in the first virtual machine, the first task is being executed and the second task arrives. Before the processor triggers task switching, it first calculates the remaining execution time of the first task based on the total execution time of the first task and the current execution time. When the remaining execution time of the first task is greater than or equal to the preset threshold, the processor stops executing the first task and starts executing the second task to ensure the real-time performance of the high-priority second task, thereby improving the execution efficiency of the business.

[0032] In a possible implementation, after the processor stops scheduling the first task, the method further includes: storing execution information of the first task in a backup memory unit.

[0033] In this implementation, after the processor stops scheduling the first task, the execution information of the first task is stored in the backup memory unit. When the processor schedules the first task again, the execution information of the first task is retrieved from the backup memory unit and the first task is continued to be executed, thereby improving the execution efficiency of the first task.

[0034] In a possible implementation, the execution information of the first task includes one or more of the following information: data in a general register, a special register, an internal cache memory, or a buffer of a logic operation unit that executes the first task.

[0035] In this implementation, when the processor stops scheduling the first task, the data in the general registers, special registers, internal cache memory, and buffer of the logic operation unit executing the first task is stored in the backup memory unit, thereby retaining sufficient data for re-executing the first task and improving the execution efficiency of the first task.

[0036] In one possible implementation, the number of backup memory units in the processor satisfies the following relationship: L=e*g, where L represents the number of backup memory units in the processor, e represents the number of logical operation units in the processor, and g represents the number of real-time priority levels.

[0037] In this implementation, the number of backup memory units in the processor is equal to the product of the number of logical operation units in the processor and the number of real-time priority levels. Compared with setting a backup memory unit for each execution sequence in the virtual machine system, it greatly saves memory space.

[0038] In a possible implementation, the method further includes: when the second task is completed, the processor executing the unfinished first task.

[0039] In this implementation, when a real-time task or a task with a higher priority is completed, the preempted task is processed first instead of executing a new task, ensuring that the preempted task is executed first.

[0040] In one possible implementation, the method further includes: when there is no time slice in the first virtual machine and there is an execution sequence to be executed, the processor schedules other virtual machines with time slices other than the first virtual machine to execute tasks of the execution sequence in the first virtual machine.

[0041] In this implementation, when the first virtual machine has no time slice but has tasks to be executed, the processor schedules other idle virtual machines to execute the tasks, thereby improving the business processing efficiency of the virtual machine system and maximizing the utilization of the processor computing power.

[0042] In a possible implementation, the method further includes: the processor allocating, according to the first configuration information, a time slice for each virtual machine that satisfies the following relationship:

[0043] Y=1000*1000 / t*m*p

[0044] Among them, Y represents the time slice allocated to each virtual machine; t represents the scheduling period, in each of which the processor allocates the time slice to each virtual machine; m represents the number of logical operation units in the processor; and p represents the computing power ratio of each virtual machine.

[0045] In a second aspect, the present application provides a scheduling method applied to a virtual machine system, wherein the virtual machine system includes a host, and the method includes: the host obtains virtual machine configuration information, wherein the virtual machine configuration information is used to indicate the creation of multiple virtual machines, and the virtual machine configuration information includes the computing power ratio of each virtual machine in the multiple virtual machines; the host creates the multiple virtual machines according to the virtual machine configuration information, and the multiple virtual machines share the computing power of the processor; the host sends first configuration information to the processor, and the first configuration information is used to indicate the computing power ratio of each virtual machine in the multiple virtual machines.

[0046] In this method, a virtual machine system includes a host, which creates multiple virtual machines based on the obtained virtual machine configuration information. The multiple created virtual machines jointly complete the tasks in the virtual machine system, and send first configuration information to the processor to instruct the processor to create multiple virtual machines based on the computing power ratio of each virtual machine in the multiple virtual machines, thereby improving the rationality of creating multiple virtual machines, saving resources of the virtual machine system, and improving the execution efficiency of the virtual machine system.

[0047] In one possible implementation, the method further includes: the host obtaining multiple models; the host creating n execution sequences for the first virtual machine among the multiple virtual machines based on the first model among the multiple models, where n is an integer greater than or equal to 0; the host configuring a priority for each of the n execution sequences; and sending second configuration information to the processor, where the second configuration information is used to indicate the priority of the n execution sequences in the first virtual machine.

[0048] In this implementation, the host creates n execution sequences for the first virtual machine based on the first model among the multiple models obtained, configures a priority for each of the n execution sequences, and sends second configuration information to the processor to indicate the priority of the n execution sequences in the first virtual machine. The n execution sequences can be processed in parallel, and each of the n execution sequences can be executed in descending order of priority level, thereby improving the execution efficiency of the first model and ensuring the real-time requirements of the first model.

[0049] In a possible implementation, the priority includes a common type priority and a real-time type priority, and the real-time type priority is higher than the common type priority.

[0050] In one possible implementation, the virtual machine configuration information also includes the period length of the time slices allocated to the multiple virtual machines; the method also includes: the host sends third configuration information to the processor, and the third configuration information is used to indicate the period length of the time slices allocated to the multiple virtual machines.

[0051] In this implementation, the host sends third configuration information to the processor to indicate the period for allocating time slices to multiple virtual machines in the virtual machine system, thereby meeting the computing power requirements of each virtual machine and ensuring that various services in the virtual machine can be completed on time and as needed.

[0052] In a possible implementation, the period of allocating time slices to the multiple virtual machines is greater than or equal to the execution period of an execution sequence with a real-time priority.

[0053] In this implementation, the period of time slices allocated to multiple virtual machines in the virtual machine system is greater than or equal to the execution period of the execution sequence with a real-time priority type, so that when the real-time task in the virtual machine is completed, time slices are reallocated to multiple virtual machines, thereby ensuring the real-time nature of the real-time task.

[0054] In a third aspect, the present application provides a scheduling device, which is applied to a virtual machine system, wherein the virtual machine system includes multiple virtual machines, and the multiple virtual machines share the computing power of a processor. The device includes: an allocation module, which is used to allocate a time slice to each of the multiple virtual machines according to first configuration information, and the first configuration information is used to indicate the computing power ratio of each virtual machine in the multiple virtual machines; an execution module, which is used to stop executing the first task and schedule the execution of the second task when the time slice exists in the first virtual machine among the multiple virtual machines and the first task is being executed. The priority of the execution sequence to which the second task belongs is higher than the priority of the execution sequence to which the first task belongs.

[0055] In one possible implementation, the first virtual machine among the multiple virtual machines includes n execution sequences, where n is an integer greater than or equal to 0; the device also includes: the allocation module is also used to allocate the time slices to s execution sequences among the n execution sequences based on the first configuration information and the second configuration information, and the second configuration information is used to indicate the priority of the n execution sequences in the first virtual machine, and s is an integer less than or equal to n.

[0056] In one possible implementation, the priority of the execution sequence in the first virtual machine includes a normal type priority and a real-time type priority, and the real-time type priority is higher than the normal type priority; wherein the priority of the s execution sequences is the normal type priority.

[0057] In a possible implementation, the allocation module is further used to allocate the time slice to each virtual machine according to the first configuration information and third configuration information, and the third configuration information is used to indicate the period length of the time slice allocated by the processor to the multiple virtual machines.

[0058] In a possible implementation, the processor allocates time slices for the multiple virtual machines with a period length greater than or equal to a period length of an execution period of an execution sequence with a real-time priority.

[0059] In a possible implementation, the apparatus further includes: a receiving module, configured for the processor to receive the first configuration information.

[0060] In one possible implementation, the device also includes: a scheduling module, which is used to prioritize scheduling tasks in the q second execution sequences when there are time slices and x first execution sequences and q second execution sequences to be executed in the first virtual machine among the multiple virtual machines, the priority of the first execution sequence is a normal type priority, the priority of the second execution sequence is a real-time type priority, and x and q are integers greater than or equal to 0.

[0061] In one possible implementation, the scheduling module is specifically used to: the real-time type priorities in the q second execution sequences also include a first real-time priority and a second real-time priority, and the priority of the first real-time priority is higher than the second real-time priority; the scheduling module preferentially schedules tasks with the first real-time priority in the q second execution sequences.

[0062] In a possible implementation, the first task belongs to any one of the x first execution sequences, and the second task belongs to any one of the q second execution sequences.

[0063] In one possible implementation, if there is a time slice allocation ratio in the x first execution sequences, then after the execution of the tasks in the q second execution sequences is completed, the allocation module is also used to allocate the remaining time slices to the x first execution sequences according to the time slice allocation ratio, and the remaining time slices are the difference between the sum of the time slices allocated by the processor to the x first execution sequences and the time slices used for the execution of the tasks in the q second execution sequences.

[0064] In a possible implementation, the first task and the second task belong to different execution sequences among the q second execution sequences, and the priority of the execution sequence to which the second task belongs is higher than the priority of the execution sequence to which the first task belongs.

[0065] In one possible implementation, the device also includes: an acquisition module for acquiring the total execution time and the current execution time of the first task; a calculation module for calculating the remaining execution time of the first task based on the total execution time of the first task and the current execution time; when the remaining execution time of the first task is less than a preset threshold, the execution module is also used to execute the first task.

[0066] In one possible implementation, the acquisition module is also used to obtain the total execution time and the current execution time of the first task; the calculation module is also used to calculate the remaining execution time of the first task based on the total execution time of the first task and the current execution time; when the remaining execution time of the first task is less than the product of the preset switching backup time of the first task and a preset multiple, the execution module is also used to execute the first task.

[0067] In one possible implementation, the acquisition module is also used to obtain the total execution time and the current execution time of the first task; the calculation module is also used to calculate the remaining execution time of the first task based on the total execution time of the first task and the current execution time; when the remaining execution time of the first task is greater than or equal to a preset threshold, the execution module is also used to stop executing the first task.

[0068] In a possible implementation, after the processor stops scheduling the first task, the device further includes: a storage module, configured to store execution information of the first task in a backup memory unit.

[0069] In a possible implementation, the execution information of the first task includes one or more of the following information: data in a general register, a special register, an internal cache memory, or a buffer of a logic operation unit that executes the first task.

[0070] In one possible implementation, the number of backup memory units in the processor satisfies the following relationship: L=e*g, where L represents the number of backup memory units in the processor, e represents the number of logical operation units in the processor, and g represents the number of real-time priority levels.

[0071] In a possible implementation, the execution module is further configured to enable the processor to execute the unfinished first task when the second task is completed.

[0072] In one possible implementation, the scheduling module is further used to schedule other virtual machines with time slices other than the first virtual machine to execute tasks of the execution sequence in the first virtual machine when there is no time slice in the first virtual machine and there is an execution sequence to be executed.

[0073] In a possible implementation, the time slice allocated by the processor to each virtual machine according to the first configuration information satisfies the following relationship:

[0074] Y=1000*1000 / t*m*p

[0075] Among them, Y represents the time slice allocated to each virtual machine; t represents the scheduling period, in each of which the processor allocates the time slice to each virtual machine; m represents the number of logical operation units in the processor; and p represents the computing power ratio of each virtual machine.

[0076] The beneficial effects of the third aspect and various possible implementations of the third aspect can be found in the beneficial effects of the first aspect and various possible implementations of the first aspect, and will not be repeated here.

[0077] In a fourth aspect, the present application provides a scheduling device, which is applied to a virtual machine system, wherein the virtual machine system includes a host, and the device includes: an acquisition module, used to obtain virtual machine configuration information, wherein the virtual machine configuration information is used to indicate the creation of multiple virtual machines, and the virtual machine configuration information includes the computing power ratio of each virtual machine in the multiple virtual machines; a creation module, used to create the multiple virtual machines according to the virtual machine configuration information, and the multiple virtual machines share the computing power of the processor; a sending module, used to send first configuration information to the processor, wherein the first configuration information is used to indicate the computing power ratio of each virtual machine in the multiple virtual machines.

[0078] In one possible implementation, the acquisition module is also used to acquire multiple models; the creation module is also used to create n execution sequences for the first virtual machine among the multiple virtual machines based on the first model among the multiple models, where n is an integer greater than or equal to 0; the configuration module is used to configure the priority for each of the n execution sequences; and the sending module is used to send second configuration information to the processor, where the second configuration information is used to indicate the priority of the n execution sequences in the first virtual machine.

[0079] In a possible implementation, the priority includes a common type priority and a real-time type priority, and the real-time type priority is higher than the common type priority.

[0080] In one possible implementation, the virtual machine configuration information also includes the period length of the time slices allocated to the multiple virtual machines; the sending module is also used to send third configuration information to the processor, and the third configuration information is used to indicate the period length of the time slices allocated to the multiple virtual machines.

[0081] In a possible implementation, the period of allocating time slices to the multiple virtual machines is greater than or equal to the execution period of an execution sequence with a real-time priority.

[0082] The beneficial effects of the fourth aspect and various possible implementations of the fourth aspect can be found in the beneficial effects of the second aspect and various possible implementations of the second aspect, and will not be repeated here.

[0083] In a fifth aspect, the present application provides a scheduling device. The device may include a processor coupled to a memory. The memory is configured to store program code, and the processor is configured to execute the program code in the memory to implement the method of the first aspect, the second aspect, or any implementation thereof.

[0084] Optionally, the device may further include the memory.

[0085] In a sixth aspect, the present application provides a chip comprising at least one processor and a communication interface, wherein the communication interface and the at least one processor are interconnected via a line, and the at least one processor is used to run a computer program or instruction to execute the method described in the first aspect or the second aspect or any possible implementation thereof.

[0086] In a seventh aspect, the present application provides a chip system, which includes multiple chips as in the sixth aspect.

[0087] In an eighth aspect, the present application provides a computer-readable medium storing program code for execution by a device, wherein the program code includes instructions for executing the method described in the first aspect or the second aspect or any possible implementation thereof.

[0088] In a ninth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method as described in the first aspect or the second aspect or any possible implementation thereof.

[0089] In the tenth aspect, the present application provides a computing device comprising at least one processor and a communication interface, wherein the communication interface and the at least one processor are interconnected via a line, the communication interface communicates with a target system, and the at least one processor is used to run a computer program or instruction to execute the method described in the first aspect or the second aspect or any possible implementation thereof.

[0090] In the eleventh aspect, the present application provides a computing system comprising at least one processor and a communication interface, wherein the communication interface and the at least one processor are interconnected via a line, the communication interface communicates with a target system, and the at least one processor is used to run a computer program or instruction to execute the method described in the first aspect or the second aspect or any possible implementation thereof.

[0091] In a twelfth aspect, the present application provides a vehicle, comprising the chip as described in the sixth aspect or the scheduling device as described in the fifth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] FIG1 is a schematic diagram of a system architecture provided in an embodiment of the present application;

[0093] FIG2 is a flow chart of a scheduling method provided in an embodiment of the present application;

[0094] FIG3 is a flow chart of configuring a scheduling period according to an embodiment of the present application;

[0095] FIG4 is a flow chart of a scheduling method provided in one embodiment of the present application;

[0096] FIG5 is a schematic diagram of a process of creating multiple virtual machines on a host according to an embodiment of the present application;

[0097] FIG6 is a schematic diagram of a process for creating an execution sequence according to an embodiment of the present application;

[0098] FIG7 is a schematic diagram of priority preemption provided by one embodiment of the present application;

[0099] FIG8 is a schematic diagram of a backup memory unit provided by one embodiment of the present application;

[0100] FIG9 is a schematic structural diagram of a scheduling device according to an embodiment of the present application;

[0101] FIG10 is a schematic structural diagram of a scheduling device according to another embodiment of the present application;

[0102] FIG11 is a schematic structural diagram of a scheduling device according to another embodiment of the present application. DETAILED DESCRIPTION

[0103] The following will describe the technical solutions in the embodiments of this application in conjunction with the drawings in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0104] Many AI application scenarios involve a variety of different businesses. The Central Car Computer (CCC) architecture enables the virtualization of multiple partitions with varying security levels on a powerful underlying hardware platform for different businesses. These partitions share hardware with computing power. Partitions can also be called containers or virtual machines (VMs), and computing power can be simply referred to as computing power. Hardware with computing power can include processors such as neural network processing units (NPUs) and graphics processing units (GPUs).

[0105] Taking autonomous driving as an example, this area encompasses services such as planning and control, predictive planning, perception fusion, 360-degree surround view management, driver monitoring systems (DMS), entertainment systems, and cockpit-related functions. These services have varying requirements for computing power and real-time performance.

[0106] For example, services such as planning and control, predictive planning, and perception fusion have high requirements for both computing power and real-time performance; DMS requires high computing power but not real-time performance; and cockpit-related services have computing power requirements that are related to actual functions but not real-time performance.

[0107] FIG1 is a schematic diagram of a system architecture provided by an embodiment of the present application. As shown in FIG1 , a virtual machine system 100 includes a host 110 and a processor 120 .

[0108] The host 110 may include multiple virtual machines (VM1, VM2, ..., VMn) and a hypervisor 111. Each of the multiple virtual machines includes an application (APP), a memory management (runtime), and a virtual processor driver. The hypervisor 111 may include a processor driver and a central processing unit (CPU). The processor driver may provide the hypervisor 111 with a driver function for the processor 120. For example, the processor driver may provide the hypervisor 111 with an interface for setting the virtual machine computing power ratio and the virtual machine resource scheduling period. The runtime may be deployed in the APP and may provide the user-mode driver function (such as an application programming interface (API)) of the processor 120. The APP loads the AI ​​model into the processor 120 by calling the API provided by the runtime, and drives the processor 120 to execute the AI ​​model and obtain the execution result of the AI ​​model.

[0109] The processor 120 may be a dedicated neural network processor (AI chip), such as an NPU or GPU. The processor 120 may include a controller 121 and multiple logic operation units. The controller 121 is used to receive the AI ​​model sent by the host 110, schedule the execution of the AI ​​model, obtain the execution result of the AI ​​model, and report the execution result of the AI ​​model to the host 110. The logic operation unit is used to execute the task in the AI ​​model sent by the controller 121 (the execution unit in the execution sequence) and return the execution result of the task to the controller 121.

[0110] For example, the AI ​​model can be a computational graph structure. Before the APP sends the AI ​​model to the processor 120, it converts the AI ​​model of the computational graph structure into an execution sequence structure for the processor 120. One AI model corresponds to one or more execution sequences (multiple execution sequences can increase parallelism), and each execution sequence has multiple execution units (i.e., AI tasks). An execution unit (AI task) can also be divided into multiple blocks. The number of blocks is generally equal to the number of cores of the logical operation unit in the processor 120. Each logical operation unit executes one block at a time. Therefore, for an AI task, the controller 121 can schedule it to execute on multiple logical operation units at the same time. Only after all AI tasks of all execution sequences of the AI ​​model are completed can the APP obtain the complete calculation result. The APP can load the AI ​​model to the processor 120 and execute it multiple times at a time, or it can send the AI ​​tasks of the AI ​​model to the processor 120 for execution multiple times. Regardless of the execution method, the processor 120 sees that the AI ​​tasks in the execution sequence need to be executed. Therefore, the processor 120 concurrently schedules the AI ​​model, that is, concurrently schedules the execution sequence.

[0111] For example, the controller 121 may only send one block of an execution unit to the logic operation unit at a time. After the logic operation unit completes execution, the controller 121 sends the next block to the logic operation unit.

[0112] It should be understood that the system architecture shown in FIG1 is merely an example of a virtual machine system provided herein. In other embodiments of the present invention, virtual machine system 100 may include more or fewer components than shown, or may combine or separate certain components, or may have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware, and this application does not limit this.

[0113] Taking autonomous driving as an example, the perception, prediction, and planning involved in autonomous driving are real-time tasks, requiring the corresponding AI models to execute as quickly as possible. AI model execution is a typical parallel computing process. AI tasks (operators) can be divided into multiple blocks, allowing them to be executed simultaneously on multiple logical units (LAUs). This increases computational parallelism, improves execution efficiency, and shortens execution time.

[0114] Furthermore, the execution of AI models for perception, prediction, and planning services follows a time sequence: perception results feed into prediction and planning, and prediction results feed into planning. Therefore, if all the processor's logical units are dedicated to real-time services during the execution of AI models for perception, prediction, and planning services, the execution time of the AI ​​models for real-time services can be minimized, thereby ensuring the real-time nature of the services.

[0115] Therefore, instead of isolating a certain number of logical operation units for each virtual machine, all virtual machines in the virtual machine system share all the logical operation units of the processor, which can minimize the running time of real-time services.

[0116] All virtual machines have configured computing power specifications. To ensure the accuracy of partitioned computing power usage, each virtual machine needs to be allocated a time slice for using the processor's logical operation unit. The controller in the processor controls the business usage time slice of each virtual machine, and the use of the time slice reflects the computing power configuration specifications of each virtual machine.

[0117] Since non-real-time services also require computing power allocation and AI models to execute, the proportion of computing power allocated to non-real-time services must also be guaranteed. Therefore, the processor controller must ensure that the time slices allocated to each virtual machine using the processor cannot be too small. In other words, the processor controller's scheduling cycle (each scheduling cycle allocates a time slice to each virtual machine) cannot be too short.

[0118] Therefore, how to allocate computing power to these partitions or schedule computing power for these partitions to meet the computing power and real-time requirements of various businesses has become an urgent problem to be solved.

[0119] Based on the above description, the present application proposes a scheduling method. FIG2 is a schematic diagram of the execution sequence of a scheduling method according to an embodiment of the present application. As shown in FIG2, the method includes at least S201 to S205. The method shown in FIG2 can be applied to the virtual machine system 100 shown in FIG1.

[0120] S201, the host obtains virtual machine configuration information, where the virtual machine configuration information is used to instruct the creation of multiple virtual machines. The virtual machine configuration information includes a computing power ratio of each of the multiple virtual machines.

[0121] As an example, the host in this embodiment may be the host 110 in FIG. 1 .

[0122] In a possible implementation, the host obtains virtual machine configuration information through a virtual machine manager, and the processor driver provides an interface for the virtual machine manager to configure the virtual machine configuration information.

[0123] As an example, the virtual machine manager in this embodiment may be the virtual machine manager 111 in FIG. 1 , and the processor driver in this embodiment may be the processor driver in the virtual machine manager 111 in FIG. 1 .

[0124] Exemplarily, the virtual machine configuration information may include information such as the number of virtual machines in the virtual machine system, the computing power ratio of each virtual machine in the multiple virtual machines, and the cycle for resource scheduling for the multiple virtual machines.

[0125] S202: The host creates multiple virtual machines according to the virtual machine configuration information, and the multiple virtual machines share the computing power of the processor.

[0126] In a possible implementation, the host creates multiple virtual machines according to the number of virtual machines in the virtual machine indicated by the virtual machine configuration information, and the multiple virtual machines share the computing power of the processor.

[0127] In another possible implementation, a host obtains multiple models, creates n execution sequences ("execution sequences") for a first virtual machine among the multiple virtual machines based on a first model among the multiple models, where n is an integer greater than or equal to 0, and configures a priority for each of the n execution sequences. The priority may include a normal priority and a real-time priority, with the real-time priority being higher than the normal priority.

[0128] It should be noted that the first model is any one of the multiple models obtained by the host, and the first virtual machine is any one of the multiple virtual machines in the virtual machine system.

[0129] S203: The host sends first configuration information to the processor, where the first configuration information is used to indicate a computing power ratio of each virtual machine in the multiple virtual machines.

[0130] In one possible implementation, the host sends first configuration information to the processor, where the first configuration information is used to indicate the computing power ratio of each virtual machine among multiple virtual machines, so that the processor allocates a time slice to each virtual machine based on the computing power ratio of each virtual machine among the multiple virtual machines indicated in the first configuration information.

[0131] Optionally, the computing power ratio of each virtual machine in the multiple virtual machines is the available computing power ratio of each virtual machine set by the NPU. For example, there are five virtual machines in the NPU: VM1, VM2, VM3, VM4 and VM5. VM1, VM2, VM3, VM4 and VM5 use 25%, 50%, 10% and 15% of the total computing power of the NPU respectively. The computing power ratio of each virtual machine can be set separately, and the total computing power ratio is less than or equal to 100%.

[0132] In another possible implementation, the host sends second configuration information to the processor, where the second configuration information is used to indicate the priorities of the n execution sequences in the first virtual machine, so that the processor allocates time slices to the n execution sequences according to the priorities of the n execution sequences in the first virtual machine indicated by the second configuration information.

[0133] The n execution sequences are execution sequences to be executed in the first virtual machine.

[0134] In another possible implementation, the virtual machine configuration information obtained by the host also includes the period length for allocating time slices to multiple virtual machines. The host can also send third configuration information to the processor, where the third configuration information is used to indicate the period length for allocating time slices to multiple virtual machines in the virtual machine system, so that the processor allocates time slices to multiple virtual machines in the virtual machine system according to the period indicated by the third configuration information.

[0135] As an example, the period length of the time slices allocated to the multiple virtual machines is greater than or equal to the execution period of the execution sequence with a real-time priority.

[0136] Optionally, the period length for allocating time slices to multiple virtual machines is also called a scheduling period.

[0137] In other words, the scheduling cycle should be no less than the cycle of real-time priority services. Within a computing power time slice allocation cycle, real-time priority services can be scheduled first, followed by normal priority services. If the cycle is too short, real-time priority services can easily use up their allocated time slices. Normal priority services also have time slices and can execute AI models. Real-time priority services will only have time slices in the next cycle, resulting in delayed delivery of real-time priority services.

[0138] Exemplarily, the configuration flow chart of the scheduling cycle is shown in FIG3 . The virtual machine manager sends the scheduling cycle to the NPU driver, and the NPU driver sends the scheduling cycle to the NPU controller. The NPU controller saves the scheduling cycle for subsequent use.

[0139] S204: The processor allocates a time slice to each virtual machine according to the first configuration information, where the first configuration information is used to indicate a computing power ratio of each virtual machine among the multiple virtual machines.

[0140] In a possible implementation, the processor allocates a time slice to each virtual machine in the virtual machine system according to the computing power ratio of the virtual machine indicated by the first configuration information, and a virtual machine with a larger computing power ratio is allocated more time slices.

[0141] In another possible implementation, the first virtual machine in the virtual machine system includes n execution sequences, where n is an integer greater than or equal to 0; the processor receives second configuration information and allocates time slices to s execution sequences among the n execution sequences based on the received first configuration information and second configuration information, wherein an execution sequence with a higher priority among the s execution sequences is allocated more time slices, and s is an integer less than or equal to n.

[0142] As an example, the priorities of the s execution sequences assigned to time slices are all ordinary type priorities. According to the first configuration information and the second configuration information, the processor only allocates time slices to the execution sequences with ordinary type priorities. The execution sequences with real-time type priorities among the n execution sequences are not allocated time slices. However, when the first virtual machine has a time slice, the processor can schedule tasks in the execution sequences with real-time type priorities.

[0143] In a possible implementation, the processor receives the third configuration information, and allocates a time slice to each virtual machine in the virtual machine system according to a period length for allocating time slices to the multiple virtual machines indicated by the third configuration information.

[0144] As an example, the processor allocates a time slice to each virtual machine in the virtual machine system based on the first configuration information according to the cycle length indicated by the third configuration information.

[0145] Exemplarily, the time slice allocated by the processor to the first virtual machine in the virtual machine system satisfies the following relationship:

[0146] Y=1000*1000 / t*m*p

[0147] Among them, Y represents the time slice allocated to each virtual machine; t represents the scheduling period, in each scheduling period, the processor allocates a time slice to each virtual machine; m represents the number of logical operation units in the processor; and p represents the computing power ratio of each virtual machine.

[0148] As another example, the processor allocates time slices to execution sequences of normal priority in the first virtual machine based on the first configuration information and the second configuration information according to the period indicated by the third configuration information.

[0149] Exemplarily, the normal priority class is divided into multiple levels, and the processor allocates time slices to execution sequences of different normal priority classes in the first virtual machine based on the first configuration information and the second configuration information according to the period indicated by the third configuration information. For example, the normal priority class execution sequences in the first virtual machine can be divided into four levels, and the ratio of time slices allocated to these four levels from high to low is 10:8:4:2:1, where execution sequences with a higher priority class ratio are allocated more time slices.

[0150] After the processor allocates a time slice to the first virtual machine, the processor schedules tasks in the first virtual machine.

[0151] S205, there is a time slice in the first virtual machine among multiple virtual machines, and when the first task is being executed, a second task arrives, the execution of the first task is stopped, and the second task is scheduled for execution, and the priority of the execution sequence to which the second task belongs is higher than the priority of the execution sequence to which the first task belongs.

[0152] In one possible implementation, when there is a time slice in the first virtual machine among multiple virtual machines, and there are x first execution sequences and q second execution sequences to be executed, the processor prioritizes scheduling tasks in the q second execution sequences, the priority of the first execution sequence is a normal type priority, and the priority of the second execution sequence is a real-time type priority, and x and q are integers greater than or equal to 0.

[0153] As an example, the real-time type priorities in the q second execution sequences also include a first real-time priority and a second real-time priority. The first real-time priority has a higher priority than the second real-time priority, and the processor prioritizes scheduling tasks with the first real-time priority in the q second execution sequences.

[0154] In one possible implementation, in a first virtual machine, when a first task is being executed, a second task arrives, and the first task belongs to any one of x first execution sequences, and the second task belongs to any one of q second execution sequences. Then, the processor stops executing the first task and schedules execution of the second task.

[0155] In one possible implementation, if there is a time slice allocation ratio in the x first execution sequences, such as 10:8:4:2:1, then after the tasks in the q second execution sequences are executed, the processor allocates the remaining time slices to the x first execution sequences according to the time slice allocation ratio, and the remaining time slices are the difference between the sum of the time slices allocated by the processor to the x first execution sequences and the time slices used to execute the tasks in the q second execution sequences.

[0156] That is to say, when the real-time priority task is completed, the processor allocates the remaining time slices to the execution sequence of the normal priority according to the original time slice allocation ratio, so that the time slices of the normal priority execution sequence still meet the time slice allocation ratio.

[0157] In another possible implementation, in the first virtual machine, when the first task is being executed, a second task arrives, the first task and the second task belong to different execution sequences among q second execution sequences, and the priority of the execution sequence to which the second task belongs is higher than the priority of the execution sequence to which the first task belongs, then the processor stops executing the first task and schedules the execution of the second task.

[0158] As an example, for the two possible implementation methods mentioned above, before the processor stops scheduling the first task, the processor obtains the total execution time and the current execution time of the first task, calculates the remaining execution time of the first task, and when the remaining execution time of the first task is less than a preset threshold, the processor executes the first task.

[0159] Optionally, the preset threshold includes a switching backup time.

[0160] That is to say, in the first virtual machine, the first task is being executed and the second task arrives. Before the processor triggers task switching, it first calculates the remaining execution time of the first task based on the total execution time of the first task and the current execution time. When the remaining execution time of the first task is less than the preset threshold, the processor still executes the first task to ensure that the current first task is completed, so as to save system resources and improve the execution efficiency of the business.

[0161] As another example, before the processor stops scheduling the first task, the processor obtains the total execution time and the current execution time of the first task, calculates the remaining execution time of the first task, and when the remaining execution time of the first task is less than the product of the preset switching backup time of the first task and a preset multiple, the processor executes the first task.

[0162] Among them, the switching backup time can be configured to the NPU controller by the NPU driver. The switching backup time of the logical operation unit is different when the number of cores and the operating frequency are different, and are all configured to the NPU controller by the NPU driver; the preset multiples are configured in advance.

[0163] That is to say, in the first virtual machine, the first task is being executed and the second task arrives. Before the processor triggers task switching, it first calculates the remaining execution time of the first task based on the total execution time of the first task and the current execution time. When the remaining execution time of the first task is less than the product of the preset switching backup time of the first task and the preset multiple, the processor still executes the first task to ensure that the current first task is completed, so as to save system resources and improve the execution efficiency of the business.

[0164] As another example, before the processor stops scheduling the first task, the processor obtains the total execution time and the current execution time of the first task, calculates the remaining execution time of the first task, and when the remaining execution time of the first task is greater than or equal to a preset threshold, the processor stops executing the first task.

[0165] That is to say, in the first virtual machine, the first task is being executed and the second task arrives. Before the processor triggers task switching, it first calculates the remaining execution time of the first task based on the total execution time of the first task and the current execution time. When the remaining execution time of the first task is greater than or equal to the preset threshold, the processor stops executing the first task and starts executing the second task to ensure the real-time performance of the high-priority second task, thereby improving the execution efficiency of the business.

[0166] Optionally, the preset threshold includes a switching backup time.

[0167] As an example, after the processor stops scheduling the first task, execution information of the first task is stored in the backup memory unit. The execution information of the first task may include data in general registers, special registers, internal cache memory, buffers, etc. of the logic operation unit that executes the first task.

[0168] As an example, the number of backup memory units in the processor satisfies the following relationship:

[0169] L=e*g

[0170] Wherein, L represents the number of backup memory units in the processor, e represents the number of logic operation units in the processor, and g represents the number of levels of real-time type priority.

[0171] In another possible implementation, when there is no time slice in the first virtual machine and there is an execution sequence to be executed, the processor schedules other virtual machines with time slices other than the first virtual machine to execute tasks of the execution sequence in the first virtual machine.

[0172] That is to say, when the first virtual machine has no time slice but has tasks to be executed, the processor can schedule other virtual machines with available time slices or remaining time slices to execute tasks, thereby improving the business processing efficiency of the virtual machine system and maximizing the utilization of processor computing power.

[0173] Optionally, when the second task is completed, the processor executes the unfinished first task, that is, when the real-time task or the higher priority task is completed, the preempted task is processed first instead of executing the new task, to ensure that the preempted task is executed first.

[0174] For example, when a task of a normal priority level is preempted and all tasks in the real-time execution sequence are scheduled, the execution of the preempted task is resumed first. This is because if a new task is executed instead of continuing the previously interrupted task, when preemption occurs again, the corresponding memory space has already backed up the scene information, and there is no memory space to back up the scene information of this task.

[0175] In the technical solution provided by the present application, the processor allocates time slices to each virtual machine in the virtual machine system according to the computing power ratio of each virtual machine among multiple virtual machines. The virtual machine with a larger computing power ratio is allocated more time slices, thereby realizing the sharing of processor computing power by multiple virtual machines and meeting the computing power requirements of each virtual machine. At the same time, the rationality of time slice allocation in each virtual machine is guaranteed, and when a high-priority task arrives, it is executed first, which can ensure the real-time execution of high-priority tasks.

[0176] The following takes the processor in the virtual machine system as an NPU as an example to introduce the scheduling method provided by this application.

[0177] Figure 4 is a flow chart of a scheduling method according to an embodiment of the present application. As shown in Figure 4 , the method includes at least S401 to S407. The method shown in Figure 4 can be applied to the virtual machine system 100 shown in Figure 1 .

[0178] S401: The host obtains virtual machine configuration information.

[0179] It should be noted that S401 may refer to S201 and will not be described in detail here.

[0180] S402: The host creates multiple virtual machines according to the virtual machine configuration information.

[0181] In a possible implementation, the virtual machine configuration information obtained by the host includes information such as the number of created virtual machines and the computing power ratio of each of the multiple created virtual machines.

[0182] As an example, the flowchart of the host creating multiple virtual machines is shown in Figure 5. The virtual machine manager (hypervisor) in the host creates multiple virtual machines according to the virtual machine configuration information. The hypervisor calls the interface of the NPU driver (NPU driver) and informs the NPU driver of the virtual machine identifier (identity document, ID) and computing power ratio of each newly added virtual machine. The NPU driver informs the virtual NPU driver (vNPU driver) in the virtual machine of the virtual machine ID. The vNPU driver saves the virtual machine ID information. The NPU driver configures the virtual machine ID and computing power ratio to the NPU controller, and the NPU controller saves information such as the virtual machine ID and computing power ratio.

[0183] S403: The host obtains the target model.

[0184] In a possible implementation, an APP in any virtual machine in the virtual machine system obtains the target model and loads the target model.

[0185] As an example, the target model may be an AI model.

[0186] S404: The host creates multiple execution sequences according to the target model.

[0187] In a possible implementation, when an APP in any virtual machine in the virtual machine system loads a target model, multiple execution sequences (execution sequences) need to be created.

[0188] As an example, Figure 6 is a flowchart of creating an execution sequence provided by an embodiment of the present application. As shown in Figure 6, the virtual machine manager calls the memory management (runtime) interface to create an execution sequence and configures a priority for the created execution sequence. The memory management calls the interface of the virtual NPU driver in the virtual machine to apply for an execution sequence ID. The virtual NPU driver applies for an execution sequence ID from the NPU driver in the host. The virtual NPU driver also sends the virtual machine ID to the NPU driver. The NPU driver assigns an execution sequence ID to the virtual machine corresponding to the virtual machine ID and returns it to the virtual NPU driver. The NPU driver simultaneously configures the virtual machine ID and the execution sequence ID to the NPU controller. The NPU controller saves the virtual machine ID and execution sequence ID information, so the NPU controller has information about the execution sequence IDs of each virtual machine.

[0189] Furthermore, apps are unaware of whether they are running on a VM or a host. The memory management interface provided to apps is the same, as is the execution sequence priority definition. Execution sequence priority can be categorized into real-time and normal priorities, which can be further subdivided into multiple levels.

[0190] For example, real-time priorities can be divided into three levels: SP0, SP1, and SP2. The priority of SP0 is higher than that of SP1, which is higher than that of SP2. Ordinary priorities can be divided into four levels: WRR0, WRR1, WRR3, and WRR4. The priority of WRR0 is higher than that of WRR1, which is higher than that of WRR2, which is higher than that of WRR3, which is higher than that of WRR4. An execution sequence with a real-time priority level can preempt an execution sequence with an ordinary priority level. An execution sequence with a higher level of real-time priority can preempt an execution sequence with a lower level of real-time priority. A schematic diagram of priority preemption is shown in FIG7. An execution sequence with a priority of SP0 can preempt an execution sequence with a priority of SP1 and SP2, an execution sequence with a priority of SP1 can preempt an execution sequence with a priority of SP2, and the level of ordinary priority can be reflected in the size of the time slice.

[0191] S405: The host sends resource configuration information to the NPU.

[0192] Multiple virtual machines in the virtual machine system share the resources of the NPU. The resource configuration information sent by the host to the NPU is used to instruct the NPU to allocate resources to the multiple virtual machines.

[0193] As an example, the resource configuration information sent by the host to the NPU may include information such as the computing power ratio of each virtual machine in multiple virtual machines, the priority of the execution sequence in each virtual machine, and the cycle length for resource allocation to each virtual machine.

[0194] S406: The NPU allocates resources to the multiple virtual machines according to the resource configuration information.

[0195] In a possible implementation, in each resource allocation cycle indicated by the resource configuration information, the NPU controller allocates a time slice to each virtual machine.

[0196] As an example, the time slice allocated by the NPU controller to the first virtual machine can satisfy the formula Y = 1000 * 1000 / t * m * p, where Y represents the time slice allocated by the NPU to the first virtual machine, t represents the scheduling period, in each scheduling period, the processor allocates a time slice to the first virtual machine, m represents the number of logical operation units in the NPU, and p represents the computing power ratio of the first virtual machine. The unit of the time slice is microseconds (us), and the resource allocation period indicated by the resource configuration information can be 30 hertz (HZ).

[0197] In a possible implementation, the NPU controller allocates time slices to execution sequences of common priority levels according to the priorities of the execution sequences in the first virtual machine.

[0198] As an example, the ratio of time slices allocated to execution sequences of normal priority levels WRR0 to WRR4 in the first virtual machine may be 10:8:4:2:1. Since execution sequences of real-time priority levels can preempt time slices of execution sequences of normal priority levels, no time slices are allocated to execution sequences of real-time priority levels.

[0199] As an example, in any one of multiple virtual machines, when the execution sequence of real-time type priority is running, the NPU controller deducts the time slice of the execution sequence of ordinary type priority according to the time slice ratio of ordinary type priority. The total number of deducted time slices is the time slice used by the execution sequence of real-time type priority, so that the time slice of the execution sequence of ordinary type priority still meets the preset ratio.

[0200] In a possible implementation, after a resource allocation cycle ends, the NPU controller reallocates time slices to each virtual machine.

[0201] For example, if any VM does not use up its time slice in the previous resource allocation cycle, the remaining time slice will not be carried over to the next resource allocation cycle. If any VM uses up more time slices than the allocated specification, this is likely due to the execution time of the task in the last execution sequence. Since the task execution time is much shorter than the VM's time slice, the excess time slice will not be deducted from the next resource allocation cycle. Within the VM, unused time slices in normal priority execution sequences will not be carried over to the next resource allocation cycle. However, any excess time slices from the previous resource allocation cycle will be deducted from the next allocation.

[0202] S407: The NPU schedules tasks in multiple virtual machines.

[0203] In a possible implementation, an NPU controller in the NPU schedules tasks of an execution sequence in the virtual machine system.

[0204] As an example, the NPU controller first schedules the execution sequence of real-time type priority in the virtual machine with time slices and the execution sequence of normal type priority with time slices. If these execution sequences have no task scheduling, it schedules other execution sequences, for example, execution sequences without time slices.

[0205] As another example, when scheduling both real-time and normal priority execution sequences, each type of execution sequence is scheduled sequentially in the order of high real-time priority, low real-time priority, and normal priority. That is, after all high-priority real-time execution sequences are scheduled, low-priority real-time execution sequences are scheduled, followed by normal priority execution sequences.

[0206] As another example, when multiple execution sequences of equal priority are scheduled together, if the execution time of any execution sequence exceeds the preset time or the time slice of that execution sequence is exhausted, the NPU controller will schedule another execution sequence. In this case, the NPU controller will wait until the currently running task is completed before switching to another execution sequence, without switching the currently executing task / block midway.

[0207] In one possible implementation, when each block is executed, the NPU controller can obtain the time slice used for the block to run and deduct the time slice of the corresponding execution sequence and the virtual machine.

[0208] For example, if a normal-priority task is executing in a time-sliced ​​virtual machine and a task in a real-time priority execution sequence arrives, scheduling of the normal-priority task is stopped and scheduling of the real-time priority task is started. After the task in the real-time priority execution sequence in the virtual machine is scheduled, the time slice used by the real-time priority task is deducted from the time slice of the normal-priority execution sequence in the virtual machine.

[0209] For example, when a task arrives in the execution sequence of real-time type priority, if the logic operation unit is executing the block of the task of the normal type priority execution sequence; or when a task of the low-level real-time type priority execution sequence is executed, a task of the high-level real-time type priority execution sequence arrives, the NPU controller needs to interrupt the executing block and execute the block of the real-time (high) priority task instead. This process can be called preemption.

[0210] When the execution of a task or block in a sequence is interrupted, the NPU controller needs to back up the block's current running state. This state information can include general-purpose register information, special-purpose register information, internal cache memory, and cache information within the logic unit executing the block. The buffer and cache space within a logic unit is relatively large, so a similar amount of memory space is required to back up this information. The memory space that backs up all the state information of a logic unit (all general-purpose registers, special-purpose registers, buffers, and cache) is called a backup memory unit.

[0211] As an example, the number of backup memory units in the NPU can satisfy the relationship L=e*g, where L represents the number of backup memory units in the NPU, e represents the number of logic operation units in the NPU, and g represents the number of real-time priority levels.

[0212] For example, the real-time type priority has three levels, namely SP0, SP1 and SP2, and the value of g is 3.

[0213] For example, the number of backup memory units in each logical operation unit (LAU) is equal to the number of real-time priority levels. If there are three real-time priority levels, the number of backup memory units in each LAU in the NPU is three. Each backup memory block is used to store data from the LAU's general registers, special registers, internal cache, and buffers, i.e., on-site information about the LAU's execution blocks.

[0214] Optionally, Figure 8 is a schematic diagram of a backup memory unit provided in an embodiment of the present application. As shown in Figure 8, the NPU includes multiple logical operation units (logical operation unit 0 to logical operation unit 3), which are controlled by a controller. Each logical operation unit includes multiple internal cache memories (buffers) and multiple buffers (caches), etc. Backup memory units 0 to backup memory units 3 can back up all field information of a logical operation unit (all general registers, special registers, buffers, caches).

[0215] For example, when preemption occurs, the current information of the preempted block in the logical operation unit is backed up to the corresponding space. When an execution sequence with a normal priority is preempted by an execution sequence with a real-time priority of SP0 / 1 / 2, the current information is backed up in backup memory unit 2. If an execution sequence with a real-time priority of SP2 is preempted by an execution sequence with a real-time priority of SP0 / 1, the current information is backed up in backup memory unit 1. When an execution sequence with a real-time priority of SP1 is preempted by an execution sequence with a real-time priority of SP0, the current information is backed up in backup memory unit 0.

[0216] Exemplarily, the NPU driver allocates the total space of the backup memory unit according to the number of logical operation units in the NPU. When the NPU is started, the NPU driver configures the backup memory unit to the NPU controller.

[0217] As an example, when the logic operation unit is executing a task / block of normal priority or a task / block of low real-time priority, the NPU controller detects that a task has arrived in a real-time execution sequence or a high real-time priority execution sequence. The NPU controller then configures the control register of the logic operation unit to stop the logic operation unit from executing the current block. The logic operation unit stops executing each internal execution sequence waterline and sends a signal back to the NPU controller to inform the NPU controller that the current block has been stopped. The NPU controller configures the control register of the logic operation unit to enable the backup function of the logic operation unit. The logic operation unit starts memory tagging extension (MTE) and backs up data in registers, caches, and buffers to a designated backup memory unit. The logic operation unit sends a signal back to the NPU controller to inform the NPU controller that the backup is complete. The NPU controller records information about the stopped execution sequence, task, and block. The NPU controller configures the block of the real-time (high) priority task to the logic operation unit. The logic operation unit executes the block of the currently configured real-time priority task.

[0218] As an example, when both the preempted task and the task to be scheduled in the execution sequence queue have scheduling opportunities, the block of the preempted task is restored first.

[0219] For example, if a normal-priority task is preempted, the preempted task will be resumed after all tasks in the real-time-priority execution sequence have been scheduled. This is because if a new task is executed instead of the interrupted task, the corresponding memory space will have already backed up the current information when preemption occurs again, leaving no memory space to back up the current information of the new task.

[0220] Exemplarily, the preemption and recovery execution sequence process may include: the NPU controller configures the registers of the logic operation unit to enable the logic operation unit to start the on-site recovery function, the logic operation unit starts the MTE, and restores the data from the specified backup memory unit to the registers, cache and buffer. The logic operation unit sends a signal back to the NPU controller to inform the NPU controller that the recovery is complete. The NPU controller configures the logic operation unit to enable the logic operation unit to start executing the preempted block, that is, to continue executing the previously interrupted block from the currently recovered environment. At the same time, the NPU controller clears the stopped execution sequence, task, and block information recorded in the backup memory unit.

[0221] It should be noted that the block that was preempted in logical operation unit A can be resumed on logical operation unit B.

[0222] For example, preemption requires a backup and recovery environment, resulting in significant overhead. If the remaining execution time of a block is less than the backup time, allowing the block to complete execution is more beneficial for task scheduling and improves task execution efficiency rather than preempting it. Therefore, the NPU controller needs to know the total execution time and elapsed execution time of the currently executing task or block to determine how long the block will take to complete and whether preemption can be avoided. Therefore, it is necessary to increase task or block execution time statistics.

[0223] For example, a performance statistics counter t_cnt is added to each logic unit in the NPU to count the number of execution cycles of the block, and a space is added for each task to store the execution cycle number of the task / block. This execution cycle number is obtained based on the actual execution time of the block, so the execution cycle number is 0 when the model is loaded.

[0224] For example, when the logic unit starts executing a block, it sets the performance statistics counter t_cnt to 0. During execution, the logic unit increments t_cnt by 1 for each cycle. While the logic unit is executing the block, the NPU controller can read the number of cycles the block has executed. When the block finishes executing, the NPU controller can obtain the total number of cycles executed by the block.

[0225] For example, the NPU controller controls the scheduling of task / block execution. When the block execution ends, the NPU controller reads the t_cnt value of the logic operation unit, that is, the execution time of the block, and summarizes it to the position of the cyele number of the corresponding task in the execution queue. Therefore, the total execution cycle number of the task can be obtained. The total execution cycle number divided by the number of blocks can obtain the average execution time of the block.

[0226] If the frequency and core count of the NPU's logical operation unit (LAU) are adjusted, the number of task execution cycles will also change. Therefore, the NPU controller needs to recalculate the task's execution cycle count. The NPU controller only recalculates and updates the total number of task cycles when running an AI model for the first time or when the frequency and core count of the NPU's LAU are adjusted.

[0227] As an example, the NPU controller configures a preset threshold. If the remaining time of the currently executed block is less than the preset threshold, no preemption is performed. After the current block is executed, the block of the newly arrived task is executed.

[0228] For example, the preset threshold can be a multiple of the switchback time. If the remaining execution time of the currently executing block is less than a multiple of the preset switchback time, preemption is not performed. The switchback time can be configured by the NPU driver to the NPU controller. The switchback time of the logical operation unit varies when the number of cores and operating frequencies are different, and is also configured by the NPU driver to the NPU controller.

[0229] It's important to note that when a model is initially run, or when the number of cores in the logical operation unit (LAU) is adjusted, or when the operating frequency is adjusted, the task information in the model queue lacks the task execution statistics. Therefore, the controller does not consider preemption avoidance and directly preempts the task. After the model is executed once, the task execution statistics are available, and the NPU controller can then perform preemption avoidance.

[0230] In a possible implementation, when there is no task scheduling in an execution sequence of a real-time type priority or an execution sequence with a time slice in a virtual machine with a time slice, the NPU controller performs idle processing.

[0231] As an example, the NPU controller schedules a virtual machine with a time slice to execute all execution sequences in a virtual machine without a time slice and an execution sequence in which the virtual machine has a time slice but the execution sequence has no time slice. In the scheduling process, the priority of the execution sequence is not distinguished. Each execution sequence is executed for a preset time before other execution sequences are scheduled.

[0232] As an example, in the idle processing state, the time for executing tasks in the execution sequence does not occupy the time slice allocated by the virtual machine.

[0233] As an example, when a virtual machine with a time slice executes a task in an execution sequence in another virtual machine, if a task arrives in the execution sequence of the real-time type priority in the virtual machine, the scheduling of the current task is stopped and the task of the execution sequence of the real-time type priority that has arrived is started; if a task arrives in the execution sequence of the normal type priority, the execution of the virtual machine is scheduled to execute the task of the execution sequence of the normal type priority that has arrived after the current task is completed.

[0234] In a possible implementation, if a virtual machine has no time slice, but there is a task to be scheduled in the execution sequence of the real-time priority level in the virtual machine, it indicates that the resource allocation of the virtual machine is abnormal.

[0235] As an example, one situation in which abnormal virtual machine resource allocation occurs is that the execution sequences in the virtual machine are all real-time type priority or the number of real-time type priority execution sequences in the virtual machine is far greater than the number of ordinary type priority execution sequences, resulting in too little computing power allocated to the virtual machine. The solution is to increase the computing power ratio of the virtual machine.

[0236] As another example, before the NPU controller schedules the virtual machine to execute the task of the real-time priority execution sequence, the normal priority execution sequence has used up the time slice in the virtual machine, resulting in no time slice in the virtual machine to execute the real-time priority execution sequence. The solution may be to move the normal priority execution sequence to another virtual machine for execution or increase the computing power of the virtual machine.

[0237] The technical solution provided by this application enables each virtual machine in the virtual machine system to share the NPU computing power according to the configured NPU computing power ratio; real-time tasks are executed first, and real-time tasks can use all NPU logical operation units, thereby ensuring the real-time performance of real-time tasks; when the remaining execution time of the block of the currently executing task is less than the preset threshold, the NPU controller does not perform preemptive switching, thereby improving the utilization efficiency of the NPU and improving the real-time performance of real-time tasks.

[0238] Figure 9 is a schematic diagram of the scheduling device according to one embodiment of the present application. As shown in Figure 9, device 900 may include an allocation module 901, an execution module 902, a receiving module 903, a scheduling module 904, an acquisition module 905, a calculation module 906, and a storage module 907. Device 900 may be used to implement the operations performed by the processor in Figures 2 and 4.

[0239] Any module in the embodiments of the present application may be implemented in whole or in part by software and / or hardware.

[0240] In one implementation, the apparatus 900 may be used to implement the method shown in Figure 2. For example, the allocation module 901 is used to implement S204, and the execution module 902 is used to implement S205.

[0241] In another implementation, the apparatus 900 may further include a scheduling module, and the apparatus 900 in this implementation may be used to implement the method shown in Figure 4. For example, the allocation module 901 is used to implement S406, and the scheduling module is used to implement S407.

[0242] Figure 10 is a schematic structural diagram of a scheduling device according to another embodiment of the present application. As shown in Figure 10, the device 1000 may include an acquisition module 1001, a creation module 1002, a sending module 1003, and a configuration module 1004. The device 1000 may be used to implement the operations performed by the host in Figures 2 and 4.

[0243] Any module in the embodiments of the present application may be implemented in whole or in part by software and / or hardware.

[0244] In one implementation, the apparatus 1000 may be used to implement the method shown in Figure 2. For example, the acquisition module 1001 is used to implement S201, the creation module 1002 is used to implement S202, and the sending module 1003 is used to implement S203.

[0245] In another implementation, the apparatus 1000 may be used to implement the method shown in Figure 4. For example, the acquisition module 1001 is used to implement S401 and S403, the creation module 1002 is used to implement S402 and S404, and the sending module 1003 is used to implement S405.

[0246] FIG11 is a schematic diagram of the structure of a scheduling device provided in one embodiment of the present application. The device 1100 shown in FIG11 can be used to execute the method described in any of the above embodiments.

[0247] As shown in Figure 11 , the apparatus 1100 of this embodiment includes a memory 1101, a processor 1102, a communication interface 1103, and a bus 1104. The memory 1101, the processor 1102, and the communication interface 1103 are connected to each other via the bus 1104.

[0248] The memory 1101 may be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1101 may store a program. When the program stored in the memory 1101 is executed by the processor 1102, the processor 1102 may be configured to perform the steps of the method shown in FIG. 2 to FIG. 4 .

[0249] The processor 1102 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits to execute relevant programs to implement the scheduling method of the embodiment of the method of the present application.

[0250] The processor 1102 may also be an integrated circuit chip with signal processing capabilities. During implementation, each step of the method of each embodiment of the present application may be completed by hardware integrated logic circuits in the processor 1102 or software instructions.

[0251] The processor 1102 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The processor 1102 may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor.

[0252] The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 1101, and the processor 1102 reads the information in the memory 1101 and, in combination with its hardware, completes the functions required to be executed by each method in the embodiments of the present application. For example, the various steps / functions of the embodiments shown in Figures 2 to 4 can be executed.

[0253] The communication interface 1103 may use, but is not limited to, a transceiver or other transceiver device to implement communication between the apparatus 1100 and other devices or a communication network.

[0254] The bus 1104 may include a path for transmitting information between various components of the device 1100 (eg, the memory 1101 , the processor 1102 , and the communication interface 1103 ).

[0255] It should be understood that the device 1100 shown in the embodiment of the present application may be an electronic device, or may be a chip configured in the electronic device.

[0256] It should be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0257] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0258] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0259] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. A and B can be singular or plural. Furthermore, the character " / " as used herein generally indicates an "or" relationship between the associated objects, but it may also indicate an "and / or" relationship. For specific understanding, please refer to the context.

[0260] In this application, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0261] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0262] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0263] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0264] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0265] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0266] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0267] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk, or an optical disk.

[0268] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A scheduling method, characterized in that: Applied to a virtual machine system, the virtual machine system includes multiple virtual machines, and the multiple virtual machines share the computing power of a processor. The method includes: The processor allocates a time slice to each of the multiple virtual machines according to first configuration information, where the first configuration information is used to indicate a computing power ratio of each of the multiple virtual machines; The time slice exists in the first virtual machine among the multiple virtual machines, and when the first task is being executed, a second task arrives, the processor stops executing the first task, and schedules the execution of the second task, and the priority of the execution sequence to which the second task belongs is higher than the priority of the execution sequence to which the first task belongs.

2. The method according to claim 1, characterized in that A first virtual machine among the plurality of virtual machines includes n execution sequences, where n is an integer greater than or equal to 0; The method further comprises: The processor allocates the time slices to s execution sequences among the n execution sequences according to the first configuration information and the second configuration information, wherein the second configuration information is used to indicate the priority of the n execution sequences in the first virtual machine, and s is an integer less than or equal to n.

3. The method according to claim 2, characterized in that The priority of the execution sequence in the first virtual machine includes a normal priority and a real-time priority, and the real-time priority is higher than the normal priority; The priorities of the s execution sequences are common priorities.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: The processor allocates the time slice to each virtual machine according to the first configuration information and the third configuration information, where the third configuration information is used to indicate a period length of the time slices allocated by the processor to the multiple virtual machines.

5. The method according to claim 4, characterized in that The processor allocates time slices for the multiple virtual machines with a period length greater than or equal to a period length of an execution period of an execution sequence with a real-time priority.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The processor receives the first configuration information.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: When there is a time slice and x first execution sequences and q second execution sequences to be executed in the first virtual machine among the multiple virtual machines, the processor prioritizes scheduling tasks in the q second execution sequences, the priority of the first execution sequence is a normal type priority, the priority of the second execution sequence is a real-time type priority, and x and q are integers greater than or equal to 0.

8. The method according to claim 7, characterized in that The processor preferentially schedules the tasks in the q second execution sequences, including: The real-time priority levels in the q second execution sequences further include a first real-time priority level and a second real-time priority level, wherein the first real-time priority level is higher than the second real-time priority level; The processor preferentially schedules the tasks with the first real-time priority in the q second execution sequences.

9. The method according to claim 7 or 8, characterized in that The first task belongs to any one of the x first execution sequences, and the second task belongs to any one of the q second execution sequences.

10. The method according to claim 9, characterized in that If there is a time slice allocation ratio in the x first execution sequences, after the execution of the tasks in the q second execution sequences is completed, the processor allocates the remaining time slices to the x first execution sequences according to the time slice allocation ratio, and the remaining time slices are the difference between the sum of the time slices allocated by the processor to the x first execution sequences and the time slices used for the execution of the tasks in the q second execution sequences.

11. The method according to claim 7 or 8, characterized in that The first task and the second task belong to different execution sequences among the q second execution sequences, and a priority of the execution sequence to which the second task belongs is higher than a priority of the execution sequence to which the first task belongs.

12. The method according to any one of claims 9 to 11, characterized in that The method further comprises: The processor obtains the total execution time and current execution time of the first task; The processor calculates the remaining execution time of the first task according to the total execution time of the first task and the current execution time; When the remaining execution time of the first task is less than a preset threshold, the processor executes the first task.

13. The method according to any one of claims 9 to 11, characterized in that The method further comprises: The processor obtains the total execution time and current execution time of the first task; The processor calculates the remaining execution time of the first task according to the total execution time of the first task and the current execution time; When the remaining execution time of the first task is less than a product of a preset switching backup time of the first task and a preset multiple, the processor executes the first task.

14. The method according to any one of claims 9 to 11, characterized in that The method further comprises: The processor obtains the total execution time and current execution time of the first task; The processor calculates the remaining execution time of the first task according to the total execution time of the first task and the current execution time; When the remaining execution time of the first task is greater than or equal to a preset threshold, the processor stops executing the first task.

15. The method according to any one of claims 9 to 13, characterized in that The method further comprises: The execution information of the first task is stored in the backup memory unit.

16. The method according to claim 15, characterized in that The execution information of the first task includes one or more of the following information: data in a general register, a special register, an internal cache memory, or a buffer of a logic operation unit that executes the first task.

17. The method according to claim 15 or 16, characterized in that The number of backup memory units in the processor satisfies the following relationship: L=e*g Wherein, L represents the number of backup memory units in the processor, e represents the number of logic operation units in the processor, and g represents the number of priority levels of the real-time type.

18. The method according to any one of claims 1 to 17, characterized in that The method further comprises: When the second task is completed, the processor executes the unfinished first task.

19. The method according to any one of claims 7 to 18, characterized in that The method further comprises: When there is no time slice in the first virtual machine and there is an execution sequence to be executed, the processor schedules other virtual machines with time slices except the first virtual machine to execute tasks of the execution sequence in the first virtual machine.

20. The method according to any one of claims 1 to 19, characterized in that The time slice allocated by the processor to each virtual machine according to the first configuration information satisfies the following relationship: Y=1000*1000 / t*m*p Among them, Y represents the time slice allocated to each virtual machine; t represents the scheduling period, in each of which the processor allocates the time slice to each virtual machine; m represents the number of logical operation units in the processor; and p represents the computing power ratio of each virtual machine.

21. A scheduling method, characterized in that: Applied to a virtual machine system, the virtual machine system including a host, the method includes: The host obtains virtual machine configuration information, where the virtual machine configuration information is used to instruct creation of multiple virtual machines, and the virtual machine configuration information includes a computing power ratio of each of the multiple virtual machines; The host creates the multiple virtual machines according to the virtual machine configuration information, and the multiple virtual machines share the computing power of the processor; The host sends first configuration information to the processor, where the first configuration information is used to indicate a computing power ratio of each of the multiple virtual machines.

22. The method according to claim 21, characterized in that The method further comprises: The host obtains multiple models; The host creates n execution sequences for a first virtual machine among the multiple virtual machines according to a first model among the multiple models, where n is an integer greater than or equal to 0; The host configures a priority for each of the n execution sequences; Second configuration information is sent to the processor, where the second configuration information is used to indicate the priorities of n execution sequences in the first virtual machine.

23. The method according to claim 22, characterized in that The priority includes a common type priority and a real-time type priority, and the real-time type priority is higher than the common type priority.

24. The method according to any one of claims 21 to 23, characterized in that The virtual machine configuration information also includes a period length for allocating time slices to the multiple virtual machines; The method further comprises: The host sends third configuration information to the processor, where the third configuration information is used to indicate a period length for allocating time slices to the multiple virtual machines.

25. The method according to claim 24, characterized in that The period of allocating time slices to the multiple virtual machines is greater than or equal to the execution period of the execution sequence with a real-time priority.

26. A scheduling device, characterized in that: include: memory and processor; The memory is used to store program instructions; The processor is configured to call program instructions in the memory to execute the method according to any one of claims 1 to 20 or the method according to any one of claims 21 to 25.

27. A chip, characterized in that: The system comprises at least one processor and a communication interface, wherein the communication interface and the at least one processor are interconnected via a line, and the at least one processor is configured to run a computer program or instruction to execute the method according to any one of claims 1 to 20 or the method according to any one of claims 21 to 25.

28. A computer-readable medium, characterized in that The computer-readable medium stores a program code for computer execution, the program code including instructions for executing the method according to any one of claims 1 to 20 or the method according to any one of claims 21 to 25.

29. A computer program product, characterized in that The computer program product comprises instructions which, when executed, cause a computer to perform the method of any one of claims 1 to 20 or the method of any one of claims 21 to 25.

30. A vehicle, characterized in that: The vehicle includes the dispatching device according to claim 26 or the chip according to claim 27.

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