Signal amplification circuit

Abstract

Aspects of the present disclosure provide signal amplification. An example method generally includes amplifying a version of a first input signal using a power amplifier in a first state in which a bias voltage of the power amplifier is set to a first voltage based on a first tracking pattern; a first output signal of the power amplifier in a second state is obtained, and in the second state, the bias voltage is set to be a second voltage smaller than the first voltage; determining a pre-distortion associated with the power amplifier based at least in part on the obtained first output signal; applying the pre-distortion to the first input signal; and amplifying a version of the pre-distorted first input signal using the power amplifier in a third state in which the bias voltage is set to a third voltage based on a second tracking mode, where the third voltage is less than the first voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application Ser. No. 17 / 805,168, filed on Jun. 2, 2022, which is hereby incorporated by reference herein. Background Art Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to signal amplification circuits.

[0004] Related technologies

[0005] Electronic device technology has exploded in the past few years. For example, better communications, more powerful hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. In order to keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablet devices, laptop computers, etc.) have become more powerful and complex than ever before. As consumers demand longer device battery life, increasing the efficiency of electronic devices has become increasingly important. One technique for increasing battery life is to improve the efficiency of the power circuitry of the electronic device.

[0006] Integrated circuits (ICs) are often powered using various power supply circuits, such as a power supply that provides a constant output voltage (e.g., a voltage regulator, such as a low dropout regulator (LDO)) or a switch mode power supply (SMPS) that provides a variable voltage. The variable voltage output by the SMPS can facilitate efficient operation of the IC in terms of power consumption. The desired power supply output voltage can be adjusted based on various techniques including average power tracking (APT), continuous envelope tracking (CET), or discrete envelope tracking (DET).

[0007] In some cases, a wireless communication device may include an RF transceiver (also referred to as a radio frequency front end) for sending and / or receiving radio frequency (RF) signals. On the transmitting side, the RF transceiver may include an SMPS that supplies power to a power amplifier for amplifying the RF signal before transmission. Wireless communication devices are widely deployed to provide various communication services, such as telephone, video, data, messaging, broadcasting, and the like. Such wireless communication devices may send and / or receive RF signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, Wireless Local Area Network (WLAN) RAT (e.g., WiFi), etc. Summary of the invention

[0008] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable characteristics. Without limiting the scope of the present application as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," it will be understood how the features of the present disclosure provide the advantages of reducing power consumption and allowing online calibration.

[0009] Certain aspects of the present disclosure provide a method for signal amplification. The method generally includes: using a power amplifier in a first state to amplify a version of a first input signal, in which the bias voltage of the power amplifier is set to a first voltage based on a first tracking mode; obtaining a first output signal of the power amplifier in a second state, in which the bias voltage is set to a second voltage less than the first voltage; determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; applying the predistortion to the first input signal; and using the power amplifier in a third state to amplify a version of the predistorted first input signal, in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0010] Certain aspects of the present disclosure provide a method for signal amplification. The method generally includes: obtaining a first output signal of a power amplifier in a first state, in which a bias voltage is set to a first voltage less than a second voltage determined based on a first tracking mode; determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; applying the predistortion to a first input signal of the power amplifier; and amplifying a version of the predistorted first input signal using the power amplifier in a second state, in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0011] Certain aspects of the present disclosure provide a device for signal amplification. The device generally includes a power amplifier, a power supply coupled to the power amplifier, a memory including executable instructions, and a controller. The controller is coupled to the memory, the power amplifier, and the power supply. The controller is configured to execute the executable instructions and cause the device to: amplify a version of a first input signal using the power amplifier in a first state, in which the bias voltage of the power amplifier is set to a first voltage by the power supply based on a first tracking mode; obtain a first output signal of the power amplifier in a second state, in which the bias voltage is set to a second voltage by the power supply, wherein the second voltage is less than the first voltage; determine a predistortion associated with the power amplifier based at least in part on the obtained first output signal; apply the predistortion to the first input signal; and amplify a version of the predistorted first input signal using the power amplifier in a third state, in which the bias voltage is set to a third voltage by the power supply based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0012] Certain aspects of the present disclosure provide a device for signal amplification. The device generally includes a power amplifier, a power supply coupled to the power amplifier, a memory including executable instructions, and a controller. The controller is coupled to the memory, the power amplifier, and the power supply. The controller is configured to execute the executable instructions and cause the device to: obtain a first output signal of the power amplifier in a first state, in which the bias voltage is set to a first voltage less than a second voltage determined based on a first tracking mode; determine a predistortion associated with the power amplifier based at least in part on the obtained first output signal; apply the predistortion to a first input signal of the power amplifier; and amplify a version of the predistorted first input signal using the power amplifier in a second state, in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0013] Certain aspects of the present disclosure provide an apparatus for signal amplification. The apparatus generally includes: a component for amplifying a version of a first input signal using a power amplifier in a first state, in which the bias voltage of the power amplifier is set to a first voltage based on a first tracking mode; a component for obtaining a first output signal of the power amplifier in a second state, in which the bias voltage is set to a second voltage less than the first voltage; a component for determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; a component for applying the predistortion to the first input signal; and a component for amplifying a version of the predistorted first input signal using the power amplifier in a third state, in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0014] Certain aspects of the present disclosure provide an apparatus for signal amplification. The apparatus generally includes: a component for obtaining a first output signal of a power amplifier in a first state, in which a bias voltage is set to a first voltage less than a second voltage determined based on a first tracking mode; a component for determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; a component for applying the predistortion to a first input signal of the power amplifier; and a component for amplifying a version of the predistorted first input signal using the power amplifier in a second state, in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0015] To achieve the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0017] Figure 1 is a block diagram of an example RF transceiver.

[0018] Figure 2is a block diagram illustrating an example circuit for signal amplification.

[0019] Figure 3 is a flow chart illustrating example operations for signal amplification.

[0020] Figure 4 is an example of a bias voltage (V CC ) and the peak input voltage (V in ) is a diagram of an example of a relationship between .

[0021] Figure 5 The linearity metrics over time when no pre-distortion is applied during the feedback sampling phase, the power amplifier settings (e.g., bias voltage (V CC )) and a graph of an example of the peak input voltage of a power amplifier over time.

[0022] Figure 6 The example includes illustrating linearity metrics over time when predistortion is applied during the feedback sampling phase, power amplifier settings (e.g., bias voltage (V CC )) and a graph of an example of the peak input voltage of the power amplifier over time.

[0023] Figure 7 is a block diagram illustrating an example circuit for signal amplification.

[0024] Figure 8 is a flow chart of example operations for signal amplification.

[0025] Fig. 9 is a diagram of a wireless communication network including a wireless communication device having a signal amplification circuit.

[0026] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0027] Certain aspects of the present disclosure relate to signal amplification circuits and signal amplification methods.

[0028] A wireless communication device may include a transceiver (also referred to as a radio frequency front end (RFFE) circuit or RF transceiver circuit) for transmitting and / or receiving RF signals. The transceiver may include a power supply circuit to provide a variable supply voltage (e.g., V) to a power amplifier (PA) for power efficiency, such as by average power tracking (APT) or envelope tracking (ET). CC). It should be understood that the term "supply voltage" may refer to a bias voltage of the PA. Certain characteristics associated with the PA may be calibrated to achieve APT through pre-distortion, wherein the calibration may be performed by the manufacturer at the factory before the wireless communication device is deployed. For example, the input power of the PA, the output power of the PA, and the gain level of the transceiver circuit may be calibrated for different supply voltages and / or pre-distortion applied to the PA to achieve APT. The factory calibration may be static, which may not take into account changes in PA performance due to temperature and / or frequency changes. In some cases, the factory calibration may increase the cost of manufacturing the wireless communication device due to the increased time to perform the calibration.

[0029] Certain aspects of the present disclosure provide methods and apparatus for signal amplification that use online feedback to determine predistortion and bias voltage levels applied to a power amplifier. Online feedback may refer to information about certain operating conditions of a transceiver, such as an input voltage to a power amplifier, an output voltage of the power amplifier, a bias voltage of the power amplifier, and the like. As an example, at the beginning of a new transmission condition or shortly thereafter, the bias voltage may be reduced to operate the power amplifier in a particular compression for predistortion characterization capture. As used herein, the term "compression" generally relates to a reduction in a gain factor associated with an amplifier, usually expressed in decibels, of a signal peak relative to the gain of the lowest power in a modulated signal. The predistortion characterization capture may include capturing data under certain conditions (e.g., a power amplifier operating at a particular compression) to enable determination of predistortion parameters. For example, in some cases, the predistortion characterization capture may include a processor sampling an input signal and an output signal of a power amplifier operating at a particular compression. After the predistortion capture and while determining the predistortion, the power amplifier may operate at a low compression level with a higher bias voltage. When the predistortion parameters are determined, the bias voltage may be set to a level between the characterizing capture level and the low compression level.

[0030] The apparatus and methods described herein can reduce the bias voltage applied to the PA in APT mode based on feedback from the PA operating with or without predistortion. The feedback can be used to determine the predistortion that allows the bias voltage to be reduced. In some cases, the predistortion characterization can be reused for certain bias voltages or output powers. In some cases, the predistortion can be determined to meet certain performance metric(s), such as compression point, adjacent channel leakage ratio (ACLR), output power (e.g., Pout), etc.

[0031] The methods and apparatus for signal amplification described herein may provide various advantages. For example, the online feedback may enable the PA to be operated at a lower bias voltage without factory calibration, which would be desirable for wireless device manufacturers. The signal amplification described herein may provide increased power efficiency by operating the PA at a lower bias voltage. The predistortion may achieve desired PA performance, such as specific linearity, low adjacent channel leakage ratio (ACLR), and / or low error vector magnitude (EVM).

[0032] Example RF Transceiver

[0033] Figure 1 is a block diagram of an example RF transceiver circuit 100 according to certain aspects of the present disclosure. The RF transceiver circuit 100 includes at least one transmit (TX) path 102 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 106 and at least one receive (RX) path 104 (also referred to as a “receive chain”) for receiving signals via antenna 106. When TX path 102 and RX path 104 share antenna 106, these paths may be connected to the antenna via interface 108, which may include any of a variety of suitable RF devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0034] In the case of receiving an in-phase (I) or quadrature (Q) baseband analog signal from a digital-to-analog converter (DAC) 110, the TX path 102 may include a baseband filter (BBF) 112, a mixer 114, a driver amplifier (DA) 116, and a power amplifier (PA) 118. The BBF 112, the mixer 114, the DA 116, and the PA 118 may be included in a radio frequency integrated circuit (RFIC).

[0035] In certain aspects, the power supply 140 may provide a variable supply voltage to the PA 118 (and / or the DA 116) to facilitate efficient operation of the PA 118 (and / or the DA 116) in terms of power consumption. For example, the power supply 140 may include a switch mode power supply (SMPS) configured to operate in an APT mode and / or an ET mode. The supply voltage of the power supply 140 may be adjusted using various techniques including APT and / or ET.

[0036] The BBF 112 filters the baseband signal received from the DAC 110, and the mixer 114 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process produces sum and difference frequencies between the LO frequency and the frequency of the baseband signal of interest. The sum and difference frequencies are referred to as beat frequencies. The beat frequencies are typically in the RF range, so that the signal output by the mixer 114 is typically an RF signal, which may be amplified by the DA 116 and / or by the PA 118 before being transmitted through the antenna 106.

[0037] The RX path 104 may include a low noise amplifier (LNA) 124, a mixer 126, and a baseband filter (BBF) 128. The LNA 124, the mixer 126, and the BBF 128 may be included in an RFIC, which may be the same RFIC as the RFIC that includes the TX path components, or may be a different RFIC. An RF signal received via the antenna 106 may be amplified by the LNA 124, and the mixer 126 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 126 may be filtered by the BBF 128 before being converted by an analog-to-digital converter (ADC) 130 into a digital I or Q signal for digital signal processing.

[0038] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO frequency may be generated by the TX frequency synthesizer 120, which may be buffered (e.g., applied unity gain), attenuated, or amplified by the amplifier 122 before being mixed with the baseband signal in the mixer 114. Similarly, the receive LO frequency may be generated by the RX frequency synthesizer 132, which may be buffered or amplified by the amplifier 134 before being mixed with the RF signal in the mixer 126. For certain aspects, a single frequency synthesizer may be used for both the TX path 102 and the RX path 104.

[0039] The controller 136 may direct the operation of the RF transceiver circuit 100, such as transmitting signals via the TX path 102 and / or receiving signals via the RX path 104. In certain aspects, the controller 136 may perform operations further described herein to obtain feedback associated with the PA 118 and determine pre-distortion to allow for a reduced bias voltage of the PA 118. The controller 136 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The memory 138 may store data and program code for operating the RF transceiver circuit 100. The controller 136 and / or the memory 138 may include control logic (e.g., CMOS logic).

[0040] Although Figure 1 An RF transceiver is provided as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, but certain aspects related to signal amplification described herein may be used in a variety of other suitable electronic systems.

[0041] Example signal amplification

[0042] Figure 2 2 is a block diagram illustrating an example circuit 200 for signal amplification. The circuit 200 includes a power amplifier 202, a predistorter 204, a controller 206, and a power supply 208. The elements or components (e.g., the predistorter 204, the controller 206, and / or the power supply 208) included in the circuit 200 may be implemented in hardware, software, or a combination of both. For example, one or more of the elements or components included in the circuit 200 may be implemented in a circuit, a circuit component (e.g., a resistor, a transistor, a capacitor, an inductor, etc.), a storage block, a register, a processing block, and / or an instruction (e.g., software code) stored in a memory and executed on a processor. Figure 2 This is only one example of a signal amplification circuit, and other circuits including fewer, additional, or alternative elements or components may be consistent with the present disclosure. For example, additional or alternative elements or components may be arranged between the predistorter 204 and the power amplifier 202, as described herein. Figure 6 Further described.

[0043] Circuit 200 may be an example of circuitry used in a transceiver, such as circuitry associated with transmit chain 102 of RF transceiver circuit 100. For example, power amplifier 202 may represent power amplifier 118, controller 204 may represent controller 136, and power supply 208 may represent power supply 140.

[0044] The controller 206 provides a predistortion control signal 210 to the predistorter 204. The predistortion control signal 210 may indicate a particular predistortion to be applied to a first input signal 212 (e.g., a digital version of the input signal) using the predistorter 204. The predistortion control signal 210 may cause the predistorter 204 to apply the particular predistortion to the first input signal 212. For example, the predistortion control signal 210 may indicate one or more parameters associated with the particular predistortion. In some cases, the predistortion control signal 210 may indicate a set of parameters in a lookup table (LUT) that defines a plurality of predistortions. For example, the lookup table may be associated with various amplitude to amplitude modulation (AMAM) and / or amplitude to phase modulation (AMPM) compensations for predistortion. In some cases, the predistortion control signal 210 may indicate specific information that functionally defines the predistortion, such as indicating parameters of the predistortion based on one or more of a polynomial function, a Volterra model, a piecewise function, and the like.

[0045] A control input of the predistorter 204 may be coupled to the controller 206, and an output of the predistorter 204 may be coupled to an input of the power amplifier 202. The predistorter 204 may apply predistortion to the first input signal 212 and output a second input signal 214 conditioned by the predistortion. For example, the predistorter 204 may apply predistortion as specified by the predistortion control signal 210. The predistorter 204 may apply the predistortion in response to the predistortion control signal 210.

[0046] The power amplifier 202 may amplify a second input signal 214, which may be modified (e.g., predistorted) or not modified by the predistortion. The power amplifier 202 may increase the amplitude of the second input signal 214 for wireless transmission. The power amplifier 202 may output an amplified version of the second input signal 214, which may be referred to as an output signal 218. A power supply input of the power amplifier 202 may be coupled to a power supply 208. For example, the power amplifier 202 may provide a power supply via a power supply terminal 216 (e.g., V CC ) is coupled to power supply 208. The performance of power amplifier 202 may vary based on bias voltage 220 output by power supply 208, where bias voltage 220 may be applied to power supply terminal 216. For example, the magnitude of amplification provided by power amplifier 202 and / or the linearity of power amplifier 202 may vary based on the voltage level of bias voltage 220.

[0047] In some cases, the predistortion control signal 210 may indicate that predistortion at the predistorter 204 is disabled. For example, the predistorter 204 may refrain from applying predistortion to the first input signal 212 in response to the predistortion control signal 210. With predistortion disabled, the controller 206 may acquire samples of the output signal 218 and / or the second input signal 214 to determine the appropriate predistortion for the power amplifier 202 given the bias voltage 220 applied to the power amplifier 202, as further described herein. For example, when the bias voltage 220 is set to a lower voltage, the controller 206 may capture samples of the output signal 218 and / or the second input signal 214. In some cases, the controller 206 may acquire samples of the output signal 218 with predistortion applied to the first input signal 212. The controller 206 may sample the first input signal 212 , the second input signal 214 , and / or the output signal 218 when the predistorter 204 is applying predistortion or when the predistorter 204 is refraining from applying predistortion, as further described herein.

[0048] The power supply 208 may adjust the source voltage 222 to output the bias voltage 220 based on the power control signal 224 output by the controller 206. In some cases, the power supply 208 may include a direct current to direct current (DC to DC) converter, such as a switch mode power supply (SMPS). The power supply 208 may convert the source voltage 222 to a specific voltage level for the bias voltage 220. For example, the source voltage 222 may be provided by a battery, a power adapter, another power supply, and / or some other source.

[0049] The controller 206 is coupled to the power amplifier 202, the power supply 208, and the predistorter 204. The controller 206 controls the power supply 208 and the predistorter 204 based at least in part on a second input signal 214 and an output signal 218 of the power amplifier 202. The controller 206 may determine a predistortion of the predistorter 204 based on the output signal 218, the first input signal 212, and / or the second input signal 214. The predistortion may allow the power amplifier 202 to amplify the second input signal 214 using a reduced bias voltage 220, as further described herein.

[0050] The controller 206 may provide a power control signal 224 to the power supply 208, wherein the power control signal 224 may indicate a voltage level of the bias voltage 220. The power control signal 224 may cause the power supply 208 to output the bias voltage 220 at the voltage level indicated by the power control signal 224. For example, the power control signal 224 may indicate a code point or a bitmap associated with a particular voltage level of the bias voltage 220. In some cases, the power control signal 224 may have a voltage that is proportional to the voltage level of the bias voltage 220. The power supply 208 may obtain the power control signal 224 and determine the voltage level of the bias voltage 220 based on the power control signal 224. In some cases, the power supply 208 may adjust the voltage level of the bias voltage 220 in response to the power control signal 224.

[0051] Applying predistortion to the first input signal 212 may enable the power amplifier 202 to operate at a lower bias voltage while still producing an output signal 218 that meets one or more criteria. Examples of the one or more criteria include adjacent channel leakage ratio (ACLR), adjacent channel power ratio (ACPR), peak-to-average power ratio (PAPR), error vector magnitude (EVM), output power (e.g., Pout), receive band noise (RxBN), gain of the transmit chain, and / or one or more specified values ​​of the power of the transmit chain. For example, from a transmit point of view, the gain or power may be equivalent. For example, if the gain is known, then knowing the transmit signal generated by the baseband transmitter (e.g., the second input signal 214) may enable prediction of the output power of the device (e.g., the circuit 200).

[0052] In some aspects, the predistorter 204 and the controller 206 may be implemented in hardware, software, or a combination of both in the same processor. For example, the processor may determine the predistortion and apply the predistortion to the digital version of the first input signal 212. In such cases, the predistortion control signal 210 may not be used between the predistorter 204 and the controller 206. The predistortion control signal 210 may represent the predistortion control implemented by the processor configured to perform the functions of the predistorter 204 and the controller 206.

[0053] Figure 3 Flowchart illustrating example operations 300 for signal amplification. Operation 300 may be performed by a signal amplification circuit, such as circuit 200.

[0054] Operations 300 may optionally begin at block 302, where the circuit may operate a power amplifier (e.g., power amplifier 202) in a first state in which a bias voltage (e.g., bias voltage 220) of the power amplifier is set to a first voltage based on a tracking mode (e.g., APT). For example, when the bias voltage is adjusted according to the APT mode, the power amplifier may amplify an input signal for wireless transmission (e.g., predistorted second input signal 214).

[0055] At block 304, the circuit may determine whether the predistortion associated with the power amplifier has been characterized for online calibration. If the predistortion associated with the power amplifier has not been characterized for online calibration, then at block 302, the circuit will continue to operate the power amplifier in a first state based on the tracking mode.

[0056] If the predistortion associated with the power amplifier has been characterized for online calibration, then at block 306, the circuit may determine whether to reuse the predistortion. For example, the circuit may determine whether a previously determined predistortion (e.g., from a previous online calibration) satisfies a particular or certain reuse criterion. The circuit may apply the previously determined predistortion when the output power of the power amplifier for a current transmission matches the output power for a previous transmission. The particular or certain reuse criterion may take into account various performance characteristics of the current transmission and the previous transmission, such as changes in the peak input power of the input signal of the power amplifier, the output power of the power amplifier, the compression point of the amplifier, the gain of the power amplifier, the bias voltage of the power amplifier, the allocated signal bandwidth, the frequency position of the signal in the transmission band, etc. In some cases, operation 300 may optionally begin at block 306.

[0057] If the predistortion is not to be reused, the circuit may determine the predistortion based on feedback associated with the power amplifier. At block 308, the circuit may obtain feedback associated with the power amplifier in a second state, in which the bias voltage is set to a second voltage less than the first voltage. In some aspects, the controller 206 may obtain samples of the second input signal 214 and / or the output signal 218 to determine the predistortion associated with the power amplifier. The feedback may include at least the output signal of the power amplifier (e.g., output signal 218). The feedback may also include an input signal of the predistorter (e.g., first input signal 212) and / or an input signal of the power amplifier (e.g., second input signal 214). In some cases, when the circuit obtains the feedback at block 308, the predistorter may refrain from applying the predistortion to the input signal (e.g., first input signal 212). In some cases, when the circuit obtains the feedback at block 308, the predistortion may be applied to the input signal (e.g., first input signal 212). For example, the controller 206 may obtain the feedback to retrain a particular predistortion that is applied to the input signal for different bias voltages, peak input powers, and / or output powers. As an example, the circuit may use a previously determined or available predistortion when obtaining the feedback associated with the power amplifier.

[0058] At block 310, the circuit may resume operation of the power amplifier in a first state while the controller processes the feedback to determine the predistortion. For example, the power amplifier may amplify the input signal with the bias voltage set to the first voltage determined based on a tracking mode (e.g., APT).

[0059] At box 312, the circuit may apply the predistortion to the input signal and operate the power amplifier in a third state, in which the bias voltage is set to a third voltage that is less than the first voltage. In some cases, the third voltage may be greater than the second voltage and less than the first voltage. At box 312, the circuit may operate the power amplifier in the third state with predistortion until a retraining event occurs or a transmission allocation changes. When the retraining event is detected, the circuit may retrain the predistortion at box 308. The retraining event may include a timer (e.g., a 1000 millisecond timer) timeout or a change in transmission conditions. The change in transmission conditions may include a change in the operating temperature of the circuit, the peak input voltage of the power amplifier, the bias voltage of the power amplifier, or the output power of the power amplifier.

[0060] When a change in transmit allocation (and / or another event) is detected, the circuit may return to operating the power amplifier in the first state at block 302, in which the bias voltage is set according to the tracking mode (e.g., APT). The change in transmit allocation may include a change in transmit configuration, including parameters such as frequency resources, subcarrier spacing, bandwidth, modulation and coding scheme (MCS), transmit power, code rate, etc.

[0061] In some cases, the circuitry may perform the operations in blocks 302, 304, and / or 306 in specific events. For example, the circuitry may perform the operations in blocks 302, 304, and / or 306 in response to an initial establishment of a connection with a network entity (such as a base station) and / or a reconfiguration of the connection (e.g., handover). The circuitry may perform the operations in blocks 302, 304, and / or 306 when the circuitry is initially powered on or when the circuitry reconnects to a wireless network. In such cases, a new transmit allocation or a change in transmit allocation may trigger the circuitry to perform the operations in blocks 306 and / or 308. In some cases, in block 310, the power amplifier may operate in APT mode without predistortion.

[0062] In some cases, a lookup table associated with the output power of the power amplifier may be used to amplify the input signal. For example, the lookup table may provide various gains, power levels, and bias voltages for different output powers of the power amplifier. The lookup table may include different values ​​of output power associated with the bias voltage, one or more gains applied to a transmission chain (e.g., transmission path 102), and at least one of the one or more power levels applied to the transmission chain (e.g., Pout_1 and Pout_2 in Table 1). Table 1 is an example of a lookup table that can be used to set various gains, power levels, and bias voltages based on the output power of the power amplifier. Table 1 includes a first output power (Pout_1) associated with a first transmission chain gain (G1), a first transmission chain power level (P1), and a first bias voltage (Vcc_1), and a second output power (Pout_2) associated with a second transmission chain gain (G2), a second transmission chain power level (P2), and a second bias voltage (Vcc_2).

[0063] Tx chain gain Tx chain power level <![CDATA[Bias voltage (V CC )]]> <![CDATA[Output power (P out )]]> G1 P1 Vcc_1 Pout_1 G2 P2 Vcc_2 Pout_2

[0064] Table 1

[0065] In some aspects, the second voltage and / or the third voltage may be determined based on the output voltage of the power amplifier using one or more models of the bias voltage and the peak input voltage of the power amplifier. For example, the second voltage and / or the third voltage may be determined using a first model of the bias voltage relative to the output voltage of the power amplifier and a second model of the peak input voltage of the power amplifier relative to the output voltage. The first model may include a linear function of the bias voltage with respect to the output voltage, and the second model may include a polynomial function (e.g., a second-order function) of the peak input voltage with respect to the output voltage. The second voltage and / or the third voltage may be determined to operate the power amplifier at a specific compression point (e.g., within a 0.25 dB compression point). Compression (or gain compression) occurs when the input power of the amplifier increases to a level that reduces the gain of the amplifier and causes a nonlinear increase in output power. The compression point refers to a point where the (ideal) linear output power of the amplifier and the nonlinear (actual) output power differ by a specific amount (such as 1 dB for a 1 dB compression point or 0.25 dB for a 0.25 dB compression point).

[0066] Figure 4 is an example of a bias voltage (V) in volts (V) associated with a power amplifier (e.g., power amplifier 202). CC ) and the peak input voltage (V in ). For example, the peak input voltage may be the peak voltage of the second input signal 214. The first curve 402 may represent the relationship of the bias voltage to the peak input voltage when the power amplifier is operated in the APT mode, and the second curve 404 may represent the relationship of the bias voltage to the peak input voltage when the power amplifier is operated at a reduced voltage relative to the APT mode. For example, in response to setting the bias voltage to the first voltage 406 along the first curve 402 in the APT mode, the power amplifier may be operated along the second curve 404 set to the second voltage 408 or to the bias voltage of the third voltage 410, as described herein.

[0067] In this example, the circuit (e.g., circuit 200) may operate the power amplifier in a first state (e.g., at block 302 or block 310) in which the bias voltage is set to a first voltage 406 according to a tracking mode (e.g., APT). While obtaining feedback associated with the power amplifier (e.g., at block 308), the circuit may operate the power amplifier in a second state in which the bias voltage is set to a second voltage 408 that is less than the first voltage 406. While determining a predistortion associated with the power amplifier based on the feedback, the circuit may operate the power amplifier in the first state in which the bias voltage is set to a first voltage (406). In response to determining the predistortion (at block 312), the circuit may apply the determined predistortion and operate the power amplifier in a third state in which the bias voltage is set to a third voltage 410 that is less than the first voltage 406 and may be greater than the second voltage 408.

[0068] Figure 5 Included are graphs 500a, 500b, and 500c that respectively illustrate examples of linearity metrics over time, power amplifier settings over time, and peak input voltage of the power amplifier over time when no predistortion is applied during a feedback sampling phase (e.g., the third phase 502c). The linearity metric in graph 500a (labeled "Lin Metric") may represent RF performance of the circuit, such as ACLR, EVM, in-band emission (IBE), intermodulation distortion (IMD), etc. The power amplifier settings may represent certain settings (e.g., bias voltages) applied to various amplification circuits in a transceiver, such as a power amplifier (PA), a driver amplifier (DA), a pre-DA, a PA, and an auxiliary PA (e.g., a Doherty amplifier), etc. The peak input voltage of the power amplifier may represent various voltages, such as a peak input voltage (Vin), an envelope tracking voltage (Vet) associated with the input voltage, and / or an average voltage associated with the input voltage.

[0069] In this example, the signal amplification circuit (e.g., circuit 200) may operate in five phases, including a first phase 502a, a second phase 502b, a third phase 502c, a fourth phase 502d, and a fifth phase 502e. During the first phase 502a, the circuit (e.g., circuit 200) may use a previous transmission allocation, for example, to transmit at a specific transmission frequency, bandwidth, transmission power, MCS, etc. The peak input voltage applied to the power amplifier may be at a first input voltage 504c, and the bias voltage of the power amplifier may be set to a first bias voltage 504b. During the first phase 502a, the circuit may have a linearity metric (e.g., ACLR) at a first level 504a.

[0070] During the second phase 502b, the circuit may operate the power amplifier in a first state (e.g., at block 302 and / or block 310) in which the peak input voltage is applied to the second input voltage 506c and the bias voltage is set to the second bias voltage 506b according to a tracking mode (e.g., APT). During the second phase 502b, the circuit may have a linearity metric at a second level 506a. In some cases, the circuit may start the second phase 502b in response to a new transmit allocation, such as an uplink grant or a semi-persistent uplink grant.

[0071] During the third phase 502c, the circuit may acquire feedback associated with the power amplifier, wherein the feedback may include an output signal and / or an input signal of the power amplifier. A capture or sampling opportunity 514 may occur during the second phase 502b, wherein the capture opportunity 514 may include a time period during which the feedback for determining predistortion is sampled at the controller. The circuit may operate the power amplifier in a second state, in which the peak input voltage is applied to the third input voltage 508c, and the bias voltage is set to the third bias voltage 508b. The peak input voltage may be adjusted to be greater than the second input voltage 506c at the third input voltage 508c. The bias voltage may be adjusted to be less than the second bias voltage 506b at the third bias voltage 508b. The circuit may also suppress the application of predistortion to the input signal of the power amplifier. In such cases, the circuit may exhibit a linearity metric at the third level 508a greater than the second level 506a. For example, the third phase 502c may have a relatively short duration spanning a portion of a symbol to several symbols (eg, 10 symbols).In some cases, the third phase 502c may have a duration of 10 microseconds (μs) to 100 microseconds (μs).

[0072] During the fourth stage 502d, the circuit may determine the predistortion based on the feedback. For example, the controller may calculate the weights of a polynomial model of the predistortion (such as a Volterra series or a generalized memory polynomial, etc.). While determining the predistortion (e.g., via online calibration), the circuit may revert to operating the power amplifier in the first state, in which the bias voltage is set according to the tracking mode. For example, the bias voltage may be set to a fourth bias voltage 510b greater than the third bias voltage 508b. The peak input voltage may be applied at a fourth input voltage 510c that may be less than the third input voltage 508c. The circuit may exhibit the linearity metric at a level that is reduced relative to the level of the third stage 502c. During the fourth stage 502d, the linearity metric may be at a fourth level 510a that is less than the third level 508a. The fourth stage 502d may have a duration of 0.1 milliseconds (ms) to 10 milliseconds (ms).

[0073] In response to determining the predistortion, the circuit may apply the predistortion to the input signal and use the predistorted input signal to operate the power amplifier with a reduced bias voltage. For example, during the fifth stage 502e, the circuit may operate the power amplifier in a third state, in which the bias voltage is set to a fifth bias voltage 512b, which is less than the second bias voltage 506b and / or the fourth bias voltage 510b. The circuit may also exhibit the linearity metric at a level that is reduced relative to the level of the third stage 502c. During the fifth stage 502e, the linearity metric may be at a third level 510a. As an example, the difference between the linearity in the third stage 502c and the other stages 502b, 502d, and 502e may be greater than or equal to 2 decibels (dB). The reduced bias voltage used during the fifth stage 502e may allow for reduced power consumption and improved efficiency without factory calibration.

[0074] In some cases, the circuit may optionally operate in the first phase 502a and / or the second phase 502b before obtaining feedback during the third phase 502c. In some cases, the circuit may begin outputting transmissions with a new allocation at the third phase 502c without operating the power amplifier in the first state in the second phase 502b.

[0075] Figure 6 The linearity metric over time, the power amplifier settings (e.g., bias voltage (V) over time, and the power amplifier settings (e.g., bias voltage (V)) over time are respectively illustrated when pre-distortion is applied during the feedback sampling phase. CC )) and example graphs 600a, 600b and 600c of the peak input voltage of the power amplifier over time.

[0076] In this example, the circuit may apply predistortion to the input signal of the power amplifier during the third phase 502c. The circuit may exhibit the linearity metric at a third level 608a, which is greater than the second level 506a, but less than the third level 508a when predistortion is not applied. During the third phase 502c, the circuit may obtain feedback associated with the power amplifier, wherein the feedback may include the output signal and / or the input signal of the power amplifier. The circuit may obtain the feedback in a capture opportunity 614. The circuit may operate the power amplifier in the second state, in which the peak input voltage is applied to the third input voltage 608c, and the bias voltage is set to the third bias voltage 608b. The peak input voltage may be adjusted to be greater than the second input voltage 506c at the third input voltage 608c. The bias voltage may be adjusted to be less than the second bias voltage 506b at the third bias voltage 608b. During the first phase 502a, the second phase 502b, the fourth phase 502d and the fifth phase 502e, the circuit may be combined as described herein. Figure 5 Operate as described.

[0077] Figure 7 is a block diagram illustrating an example circuit 700 for signal amplification. The circuit 700 may represent an example circuit 700 for signal amplification. Figure 2 The example circuit 200 is described. In some aspects, operation 300 may be performed by circuit 700. Figure 2 In addition to the components described, circuit 700 may include antenna 106, modulator 726, DAC 728, transmit (TX) chain circuit 730, ADC 732, and battery 734. Battery 734 may be coupled to power supply 208, where the battery may output source voltage 222. Antenna 106 may be coupled to power amplifier 202, where power amplifier 202 may output output signal 218 for transmission via antenna 106.

[0078] The modulator 726 may be coupled to the predistorter 204, and the modulator 726 may generate the first input signal 212. The modulator 726 may perform digital modulation on the data stream. The modulator 726 may perform various digital processing on the data stream, such as scrambling, modulation (e.g., quadrature phase shift keying (QPSK) or quadrature amplitude modulation (QAM)), layer mapping, and / or spatial processing (e.g., precoding). In some cases, the modulator 726 may encode the data stream across multiple carrier frequencies (e.g., via orthogonal frequency division multiplexing (OFDM)). The modulator 726 may be implemented in a modem or integrated with the modem.

[0079] The DAC 728 may be coupled to the predistorter 204 and to the transmit chain circuit 730. The DAC 728 may convert the digital version of the second input signal 214a into an analog version of the second input signal 214b.

[0080] In this example, when analog conversion occurs after predistortion, the predistortion may be applied to a digital version of the first input signal 212. Digital predistortion (DPD) may be performed by the predistorter 204. The controller 206 may also obtain a digital version of the second input signal 214a and / or a digital version of the first input signal 212 for predistortion processing as described herein.

[0081] The transmission chain circuit 730 may be coupled to the DAC 728 and to the power amplifier 202. The transmission chain circuit 730 may output an RF version of the second input signal 214c. The transmission chain circuit 730 may include a BBF, a mixer, and a driver amplifier, for example, as described herein in conjunction with Figure 1 As described. The BBF may filter a baseband signal from an analog version of the second input signal 214b. The mixer may up-convert the baseband frequency of the second input signal to a higher RF frequency, and the driver amplifier may amplify the up-converted version of the second input signal. As described herein, the circuit 700 may apply a specific gain and / or a specific power level across the transmission chain circuit depending on the target output power and / or bias voltage 220 of the power amplifier 202. For example, the circuit 700 may apply one or more gains to the BBF, the mixer, and / or the driver amplifier based on the target output power and / or bias voltage 220 of the power amplifier 202. In some aspects, the circuit may use a lookup table (e.g., Table 1) to determine the gain and / or power level applied to a specific circuit in the transmission chain.

[0082] ADC 732 may be coupled to power amplifier 202 and to controller 206. ADC 732 may convert an analog version of output signal 218a to a digital version of output signal 218b. ADC 732 may output the digital version of output signal 218b to controller 206 for predistortion processing described herein.

[0083] Figure 8 is a flow chart of example operations 800 for signal amplification. Operations 800 may be performed by a signal amplification circuit, such as circuits 200 or 700.

[0084] Operation 800 may optionally begin at box 802, where the circuit may amplify a version (e.g., an analog version) of a first input signal (e.g., second input signal 214) using a power amplifier (e.g., power amplifier 202) in a first state, in which a bias voltage of the power amplifier is set to a first voltage (e.g., first voltage 406) based on a first tracking mode (e.g., APT).

[0085] At block 804, the circuit may obtain feedback associated with the power amplifier in a second state, in which the bias voltage is set to a second voltage (e.g., second voltage 408) that is less than the first voltage. Obtaining the feedback may be referred to as performing a signal training capture, in which the circuit obtains samples of, for example, an input signal to the power amplifier, an input signal to a predistorter, and / or an output signal of the power amplifier. As used herein, the term "feedback associated with the power amplifier" may include information associated with an output of a transmission chain, wherein the information may include one or more gains associated with the transmission chain, one or more power levels associated with the transmission chain, a bias voltage, an output power, an output voltage, a peak input voltage, and the like. For example, the feedback may include a first output signal of the power amplifier (e.g., output signal 218), an input signal to a predistorter (e.g., first input signal 212), and / or the first input signal. In some cases, the circuit may operate the power amplifier in the second state without predistorting the first input signal, for example, for full online calibration of the predistortion. In some cases, the circuit may operate the power amplifier in the second state while predistorting the first input signal, e.g., to retrain the predistortion. In some aspects, the circuit may obtain the feedback associated with the power amplifier during an acquisition opportunity, e.g., in conjunction with Figure 5 and Figure 6 The acquisition opportunity may include a portion of a symbol or one or more symbols, for example, a fraction of a symbol to ten symbols.

[0086] At block 806, the circuit may determine a predistortion associated with the power amplifier based at least in part on the obtained feedback. In some aspects, while determining the predistortion, the circuit may revert to operating the power amplifier in the first state. For example, the circuit may amplify the version of the first input signal using the power amplifier in the first state while determining the predistortion. In some cases, the circuit may apply a default predistortion while operating the power amplifier in the first state. As described herein in conjunction with Figure 5 and Figure 6As described, resuming the power amplifier to operate in the first state may allow the circuit to operate with a suitable ACLR while the circuit determines the predistortion. The circuit may determine the predistortion associated with the power amplifier.

[0087] At block 808, the circuit may apply the predistortion to the first input signal. In some cases, the circuit may apply the predistortion to the first input signal as digital predistortion.

[0088] At block 810, the circuit may amplify a version (e.g., an analog version) of the predistorted first input signal using a power amplifier in a third state in which the bias voltage is set to a third voltage (e.g., third voltage 410) based on a second tracking mode (e.g., APT). The third voltage may be less than the first voltage, and in some cases, the third voltage may be greater than the second voltage. In response to determining the predistortion, the circuit may apply the predistortion to the first input signal at block 808 and at block 810, for example, as described herein in conjunction with Figure 5 and Figure 6 The predistorted first input signal is amplified using a power amplifier during the fifth stage 502e. The reduced bias voltage used at block 810 may allow for reduced power consumption and improved efficiency without factory calibration of the predistortion.

[0089] In some aspects, the voltages of the second state and the third state may be determined such that the voltage levels allow the circuit to meet a particular performance metric. In some cases, the circuit may operate the power amplifier in the second state and the third state at a compression point that meets a threshold (e.g., a threshold within a 0.25 dB compression point or within a 0.25 dB difference). That is, the compression point associated with the power amplifier in the second state and the third state may meet the threshold. The amount of compression in the signal peak, referred to as the compression point (CP), may be the same or within a particular threshold in a signal training capture (e.g., at block 804) compared to the signal amplification in the third state (e.g., at block 810). The compression may be within a 0.25 dB difference between the capture and the reduced bias voltage operation (e.g., at block 810).

[0090] In some cases, the power amplifier operating in the second state and the third state may satisfy a metric associated with the output power of the power amplifier. The circuit may maintain the transmit power (e.g., the output power of the power amplifier) ​​within a threshold from the target transmit power. For example, during pre-distortion training (e.g., at block 804 and / or block 806) and signal amplification in the third state (e.g., at block 810), the transmit power may be maintained within a range of + / -0.5 dB from the target transmit power. In some aspects, the metric includes at least one of the following: a change in the output power (e.g., ΔPout) relative to the output power during the first state, a first difference between the output power during the second state and the target output power of the power amplifier, and a second difference between the output power during the third state and the target output power. For certain aspects, the second state and the third state of the power amplifier may satisfy the metric associated with the output power of the power amplifier when the output power during the second state and the third state is within a power range (e.g., + / - 0.5dB) from the target output power of the power amplifier.

[0091] In some aspects, the circuit can determine the second voltage and / or the third voltage based on the output voltage of the power amplifier using one or more models of the bias voltage and the peak input voltage of the power amplifier, for example, as described herein in conjunction with Figure 3 In particular, the circuit may use the one or more models to determine the second voltage and / or the third voltage without iterating multiple test voltages on the bias voltage to determine a voltage that satisfies a particular metric. In some cases, the circuit may apply the predistortion to the first signal after a single iteration of the acquisition at box 804 and the determination at box 806. The single iteration may refer to performing an online predistortion calibration / characterization using a bias voltage that is set only to the second voltage at box 804 and a bias voltage that is set only to the third voltage at box 810, without multiple iterations of an adjusted voltage for the bias voltage. In some cases, the circuit may acquire a first output signal of the power amplifier in the second state, in which the bias voltage is set to the second voltage only for a specific duration (e.g., the duration of the capture opportunity). The circuit can amplify the predistorted version of the first input signal using the power amplifier in the third state, in which the bias voltage is set to the third voltage only for a specific duration (e.g., 1000 ms) or in response to an event (e.g., a change in operating conditions). For example, the second voltage and / or the third voltage can be a single constant voltage without using multiple test voltages.

[0092] For certain aspects, the tracking mode for the bias voltage may include an APT mode.For example, at least one of the first tracking mode or the second tracking mode includes an average power tracking mode.

[0093] In some aspects, the amplification of the input signal may be performed based on a lookup table (e.g., Table 1) associated with the output power of the power amplifier. For example, the circuit may amplify a version of the first input signal based at least in part on a value stored in a lookup table associated with the output power of the power amplifier. The lookup table may include different values ​​of the output power associated with at least one of the bias voltage, one or more gains applied to the transmission chain, and one or more power levels applied to the transmission chain. In some cases, the bias voltage may be determined based on an entry or value in the lookup table, and the bias voltage may be used to power an amplifier that amplifies the input signal (e.g., at block 802).

[0094] For certain aspects, the circuit may retrain (e.g., recalibrate, recharacterize, or redetermine) a predistortion, such as the predistortion determined at block 806. The circuit may redetermine the predistortion in response to satisfying one or more criteria (e.g., when a timer expires or a characteristic associated with the power amplifier changes). The circuit may obtain additional feedback associated with the power amplifier in the second state or in the third state in response to satisfying the one or more criteria. The additional feedback may include a second output signal of the power amplifier and / or a second input signal of the power amplifier, wherein the second output signal and / or the second input signal may be signals that are different in time relative to the first input signal and the first output signal. The circuit may determine the predistortion associated with the power amplifier based at least in part on the additional feedback, wherein the predistortion may be updated compared to the predistortion determined at block 806.

[0095] The one or more criteria may be satisfied when a timer times out or a change in a characteristic associated with the power amplifier reaches a threshold. The timer may run from when a previous predistortion was determined, and the timeout of the timer may indicate retraining the predistortion (e.g., after 1000 milliseconds from when the previous predistortion was determined). The circuit may retrain the predistortion in response to various changes in characteristics associated with the power amplifier, such as a change in operating temperature (e.g., a change in temperature bins), a change in frequency (e.g., a change in carrier frequency), a change in modulation scheme (e.g., a change from QPSK to QAM, or vice versa), a change in output (e.g., transmit) power, etc. A temperature bin may refer to a specific temperature range, wherein a change in the temperature bin may indicate a specific change in temperature.

[0096] In certain aspects, the circuit may reuse the predistortion determined at block 808 for, e.g., other transmit allocations, bias voltages, peak input voltages, output powers, and the like. For example, the circuit may reuse the predistortion for a new power target (e.g., a different transmit power). The circuit may apply the predistortion to the second input signal in response to satisfying one or more criteria for reusing the predistortion, and the circuit may amplify the predistorted version of the second input signal using the power amplifier in the third state or in a fourth state in which the bias voltage is set to a fourth voltage. That is, the circuit may reuse the predistortion determined at block 808 in response to satisfying a certain criterion or criteria (e.g., a new or different transmit allocation, a different bias voltage, a different peak input voltage, and / or a different output power). The fourth voltage may be associated with an APT voltage that is different from the first voltage, for example, as described herein in conjunction with Figure 4 The one or more criteria for reusing the predistortion may include various changes associated with the characteristics of the power amplifier and / or the transmit allocation. For example, when the difference between the first output power associated with the first input signal and the second output power associated with the second input signal is within a threshold value (e.g., 0.5 dB), the one or more criteria for reusing the predistortion may be met.

[0097] In certain aspects, operations 800 may begin at block 804 without an initial transmission in the first state. The circuit may obtain the feedback at block 804, determine the predistortion at block 806 while operating the power amplifier in the first state, apply the predistortion at block 808, and amplify the signal using the power amplifier in the third state at block 810. For example, the predistortion characterization capture at block 804 may begin at the start of a new transmission. In such cases, the first state may be a logic state determined by the circuitry used to implement the second state and the third state.

[0098] Example Wireless Communication Network

[0099] In certain aspects, the signal amplification circuits and / or methods may be used in certain wireless communication devices in a wireless network. Fig. 9 is a diagram of a wireless communication network 900 including a wireless communication device 902 having a wireless transceiver 996, such as Figure 1 In some aspects, wireless transceiver 996 may include a signal amplification circuit such as circuit 200 or 700.

[0100] In the wireless communication network 900, a wireless communication device 902 communicates with a base station 904 via a wireless link 906. As shown, the wireless communication device 902 is depicted as a smart phone. However, the wireless communication device 902 can be implemented as any suitable computing or other electronic device, such as a cellular base station, a broadband router, an access point, a cellular or mobile phone, a gaming device, a navigation device, a media device, a laptop computer, a desktop computer, a tablet computer, a server computer, a network attached storage (NAS) device, a smart appliance, a vehicle-based communication system, an Internet of Things (IoT) device, a sensor or security device, an asset tracker, etc.

[0101] The base station 904 communicates with the wireless communication device 902 via a wireless link 906, which can be implemented as any suitable type of wireless link. Although depicted as a base station tower of a cellular radio network, the base station 904 can represent or be implemented as another device, such as a satellite, a terrestrial broadcast tower, an access point, a peer device, a mesh network node, a fiber optic line, another electronic device substantially as described above, etc. Therefore, the wireless communication device 902 can communicate with the base station 904 or another device via a wired connection, a wireless connection, or a combination thereof. The wireless link 906 may include a downlink of data or control information communicated from the base station 904 to the wireless communication device 902, and an uplink of other data or control information communicated from the wireless communication device 902 to the base station 904. The wireless link 906 may use any suitable communication protocol or standard (such as 3rd Generation Partnership Project Long Term Evolution (3GPP LTE), 3GPP New Radio Fifth Generation (NR 5G), IEEE 802.11 (WiFi), IEEE802.16 (WiMAX), Bluetooth TM etc.) to achieve this.

[0102] The wireless communication device 902 includes a processor 908 and a memory 910. The memory 910 may be part of or form part of a computer-readable storage medium. The processor 908 may include any type of processor configured to execute processor-executable instructions (e.g., code) stored by the memory 910, such as an application processor or a multi-core processor. The memory 910 is configured to store instructions (e.g., computer-executable code) that, when executed by the processor 908, cause the processor 908 to perform operations in conjunction with the processor 908. Figure 3 and Figure 8The operations 300 and / or operations 800 described herein or any aspects related thereto. The memory 910 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., disk or tape), etc. In the context of the present disclosure, the memory 910 is implemented to store instructions 912, data 914, and other information of the wireless communication device 902, and therefore, when configured as a computer-readable storage medium or a portion thereof, the memory 910 does not include a transient propagation signal or carrier wave. That is, the memory 910 may include a non-transitory computer-readable medium (e.g., a tangible medium).

[0103] The wireless communication device 902 may also include input / output ports 916. The I / O ports 916 enable data exchange or interaction with other devices, networks, or users or components of the device.

[0104] The wireless communication device 902 may also include a signal processor (SPC) 918, such as, for example, a digital signal processor (DSP). The signal processor 918 may function similarly to the processor 908 and may be capable of executing instructions and / or processing information in conjunction with the memory 910.

[0105] For communication purposes, the wireless communication device 902 also includes a modem 920, a wireless transceiver 922, and an antenna (not shown). The wireless transceiver 922 provides connectivity to a corresponding network and other wireless communication devices connected thereto using radio frequency (RF) wireless signals, and may include Figure 1 The RF transceiver 100 and / or Figure 2 and Figure 7 The signal amplification circuit 200 or 700 of the wireless transceiver 922 can facilitate communication over any suitable type of wireless network, such as a wireless local area network (WLAN), a peer-to-peer (P2P) network, a mesh network, a cellular network, a wireless wide area network (WWAN), a navigation network (e.g., the Global Positioning System (GPS) or another Global Navigation Satellite System (GNSS) in North America), and / or a wireless personal area network (WPAN).

[0106] The various operations of the above methods may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. For example, the means for amplifying may include a power amplifier (e.g., power amplifier 202). The means for obtaining feedback and / or determining predistortion may include a controller or processor (e.g., controller 206). The means for applying predistortion may include a processor and / or a predistorter (e.g., predistorter 204).

[0107] Based on the present disclosure, it should be understood that the signal amplification circuit and the method of signal amplification described herein provide various advantages. The signal amplification circuit and the method of signal amplification described herein allow for increased power efficiency and reduced power consumption, for example, by operating the power amplifier at a lower bias voltage. Online feedback and calibration can enable the power amplifier to be operated at a lower bias voltage without factory calibration of the predistortion, which will be desired by wireless device manufacturers. The predistortion can achieve desired power amplifier performance, such as specific linearity, low adjacent channel leakage ratio (ACLR), and / or low error vector magnitude (EVM).

[0108] Example aspects

[0109] In addition to the above-mentioned various aspects, specific combinations of the various aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0110] Aspect 1: A method for signal amplification, the method comprising: using a power amplifier in a first state to amplify a version of a first input signal, in the first state, the bias voltage of the power amplifier is set to a first voltage based on a first tracking mode; obtaining a first output signal of the power amplifier in a second state, in the second state, the bias voltage is set to a second voltage less than the first voltage; determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; applying the predistortion to the first input signal; and using the power amplifier in a third state to amplify a version of the predistorted first input signal, in the third state, the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0111] Aspect 2: The method of aspect 1, wherein a compression point associated with the power amplifier in the second state and the third state satisfies a threshold.

[0112] Aspect 3: The method according to aspect 1 or 2, wherein applying the predistortion to the first input signal comprises: applying the predistortion to the first signal after a single iteration of the obtaining and the determining.

[0113] Aspect 4: A method according to any one of Aspects 1 to 3, wherein: obtaining the first output signal includes: obtaining the first output signal of the power amplifier in the second state, in which the bias voltage is set only to the second voltage; and amplifying the version of the predistorted first input signal includes: using the power amplifier in the third state to amplify the version of the predistorted first input signal, in which the bias voltage is set only to the third voltage.

[0114] Aspect 5: The method according to any one of aspects 1 to 4, wherein at least one of the first tracking mode or the second tracking mode comprises an average power tracking mode.

[0115] Aspect 6: The method according to any one of aspects 1 to 5, wherein amplifying the version of the first input signal comprises: amplifying the version of the first input signal based at least in part on a lookup table associated with an output power of the power amplifier.

[0116] Aspect 7: The method according to aspect 6, wherein the lookup table includes different values ​​of the output power associated with at least one of the bias voltage, one or more gains applied to the transmission chain, and one or more power levels applied to the transmission chain.

[0117] Aspect 8: The method according to any one of aspects 1 to 7, wherein determining the predistortion comprises: while determining the predistortion, amplifying the version of the first input signal using the power amplifier in the first state.

[0118] Aspect 9: The method according to any one of aspects 1 to 8, wherein acquiring the first output signal of the power amplifier comprises: acquiring the first output signal of the power amplifier in a capture opportunity.

[0119] Aspect 10: The method according to aspect 9, wherein the acquisition opportunity includes a fraction of one symbol to ten symbols.

[0120] Aspect 11: The method according to any one of aspects 1 to 10, wherein the second state and the third state of the power amplifier satisfy a metric associated with the output power of the power amplifier.

[0121] Aspect 12: A method according to Aspect 11, wherein the metric includes at least one of the following items: a change in the output power relative to the output power during the first state, a first difference between the output power during the second state and a target output power of the power amplifier, and a second difference between the output power during the third state and the target output power.

[0122] Aspect 13: A method according to Aspect 11 or 12, wherein the second state and the third state of the power amplifier satisfy the metric associated with the output power of the power amplifier when the output power during the second state and the third state is within a power range from a target output power of the power amplifier.

[0123] Aspect 14: The method according to any one of Aspects 1 to 13, further comprising: in response to satisfying one or more criteria, acquiring a second output signal of the power amplifier in the second state or the third state.

[0124] Aspect 15: The method according to aspect 14, wherein the one or more criteria are met when a timer times out or a characteristic change associated with the power amplifier reaches a threshold.

[0125] Aspect 16: According to the method described in any one of Aspects 1 to 15, the method further includes: applying the predistortion to a second input signal in response to satisfying one or more criteria; and amplifying the predistorted version of the second input signal using the power amplifier in the third state or in the fourth state, wherein the bias voltage is set to a fourth voltage in the fourth state.

[0126] Aspect 17: The method according to aspect 16, wherein the one or more criteria are satisfied when a difference between a first output power associated with the first input signal and a second output power associated with the second input signal is within a threshold.

[0127] Aspect 18: The method according to any one of aspects 1 to 17, wherein applying the predistortion comprises: applying the predistortion to the first input signal as digital predistortion.

[0128] Aspect 19: A method for signal amplification, the method comprising: obtaining a first output signal of a power amplifier in a first state, in which the bias voltage is set to a first voltage that is less than a second voltage determined based on a first tracking mode; determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; applying the predistortion to a first input signal of the power amplifier; and amplifying a version of the predistorted first input signal using the power amplifier in a second state, in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0129] Aspect 20: A method according to Aspect 19, wherein determining the pre-distortion includes: while determining the pre-distortion, amplifying the version of the first input signal using the power amplifier in the third state, in which the bias voltage is set to the second voltage.

[0130] Aspect 21: A device for signal amplification, the device comprising: a power amplifier; a power supply coupled to the power amplifier; a memory comprising executable instructions; and a controller coupled to the memory, the power amplifier and the power supply, wherein the controller is configured to execute the executable instructions and cause the device to: amplify a version of a first input signal using the power amplifier in a first state, in which the bias voltage of the power amplifier is set to a first voltage through the power supply based on a first tracking mode; obtain a first output signal of the power amplifier in a second state, in which the bias voltage is set to a second voltage through the power supply, wherein the second voltage is less than the first voltage; determine a predistortion associated with the power amplifier based at least in part on the obtained first output signal; apply the predistortion to the first input signal; and amplify a version of the predistorted first input signal using the power amplifier in a third state, in which the bias voltage is set to a third voltage through the power supply based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0131] Aspect 22: The apparatus of aspect 21, wherein a compression point associated with the power amplifier in the second state and the third state satisfies a threshold.

[0132] Aspect 23: An apparatus according to Aspect 21 or 22, wherein in order to apply the predistortion to the first input signal, the controller is also configured to execute the executable instructions and cause the apparatus to apply the predistortion to the first signal after a single iteration of the acquiring and the determining.

[0133] Aspect 24: An apparatus according to any one of Aspects 21 to 23, wherein: in order to obtain the first output signal, the controller is also configured to execute the executable instructions, and causes the apparatus to obtain the first output signal of the power amplifier in the second state, in which the bias voltage is set only to the second voltage; and in order to amplify the version of the predistorted first input signal, the controller is also configured to execute the executable instructions, and causes the apparatus to use the power amplifier in the third state to amplify the version of the predistorted first input signal, in which the bias voltage is set only to the third voltage.

[0134] Aspect 25: The apparatus according to any one of aspects 21 to 24, wherein at least one of the first tracking mode or the second tracking mode comprises an average power tracking mode.

[0135] Aspect 26: An apparatus according to any one of Aspects 21 to 25, wherein in order to amplify the version of the first input signal, the controller is also configured to execute the executable instructions and cause the apparatus to amplify the version of the first input signal at least partially based on a lookup table associated with the output power of the power amplifier.

[0136] Aspect 27: An apparatus according to any one of Aspects 21 to 26, wherein, in order to determine the pre-distortion, the controller is also configured to execute the executable instructions and enable the apparatus to amplify the version of the first input signal using the power amplifier in the first state while determining the pre-distortion.

[0137] Aspect 28: The apparatus according to any one of aspects 21 to 27, wherein the second state and the third state of the power amplifier satisfy a metric associated with the output power of the power amplifier.

[0138] Aspect 29: An apparatus according to any one of Aspects 21 to 28, wherein the controller is further configured to execute the executable instructions and cause the apparatus to obtain a second output signal of the power amplifier in the second state or the third state in response to satisfying one or more criteria.

[0139] Aspect 30: A device for signal amplification, the device comprising: a power amplifier; a power supply coupled to the power amplifier; a memory comprising executable instructions; and a controller coupled to the memory, the power amplifier and the power supply, wherein the controller is configured to execute the executable instructions and cause the device to: obtain a first output signal of the power amplifier in a first state, in which the bias voltage is set to a first voltage less than a second voltage determined based on a first tracking mode; determine a predistortion associated with the power amplifier based at least in part on the obtained first output signal; apply the predistortion to a first input signal of the power amplifier; and amplify a version of the predistorted first input signal using the power amplifier in a second state, in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

[0140] Aspect 31: A device comprising: a memory comprising computer-executable instructions; and one or more processors configured to execute the computer-executable instructions and cause the processing system to perform a method according to any one of Aspects 1 to 20.

[0141] Aspect 32: An apparatus comprising means for performing the method according to any one of aspects 1 to 20.

[0142] Aspect 33: A non-transitory computer-readable medium comprising computer-executable instructions, which, when executed by one or more processors of a processing system, cause the processing system to perform a method according to any one of aspects 1 to 20.

[0143] Aspect 34: A computer program product embodied on a computer-readable storage medium, the computer program product comprising code for executing the method according to any one of aspects 1 to 20.

[0144] Additional considerations

[0145] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. The examples discussed herein are not limited to the scope, applicability or aspects set forth in the claims. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. For example, without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Each example may ignore, replace or add each process or component as appropriate. For example, the described method may be performed in an order different from the order described, and various actions may be added, omitted or combined. In addition, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functions, or structures and functions that are supplemented or substituted for the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims.

[0146] The various illustrative logic blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or executed using a general purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, a system on a chip (SoC), or any other such configuration.

[0147] As used herein, a signal may refer to a detectable physical quantity or pulse (such as voltage, current, or magnetic field strength over time) by which a message or information may be transmitted. A signal may carry information that can be used for observation.

[0148] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0149] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, a database, or another data structure), ascertaining, etc. Also, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. In addition, "determining" may include resolving, selecting, choosing, establishing, etc.

[0150] The method disclosed herein includes one or more actions for implementing the method. The method actions can be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions can be modified without departing from the scope of the claims. In addition, the various operations of the method described above can be performed by any appropriate component that can perform the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors.

[0151] The following claims are not intended to be limited to the various aspects shown herein, but should be granted the full scope consistent with the language of the claims. Within the claims, unless otherwise specified, references to elements in the singular form are not intended to mean "one and only one", but "one or more". Unless otherwise specified, the term "some" refers to one or more. Any claim element is not interpreted according to the provisions of 35 U.S.C. § 112 (f) unless the element is explicitly stated using the phrase "member for...". All structural and functional equivalents of the elements of the various aspects described throughout the present disclosure that are known or will be known later to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims.

Claims

1. A method for signal amplification, the method comprising: amplifying a version of a first input signal using a power amplifier in a first state in which a bias voltage of the power amplifier is set to a first voltage based on a first tracking mode; Acquire a first output signal of the power amplifier in a second state, in which the bias voltage is set to a second voltage that is less than the first voltage; determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; applying the predistortion to the first input signal; as well as The predistorted version of the first input signal is amplified using the power amplifier in a third state in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage. 2 . The method of claim 1 , wherein a compression point associated with the power amplifier in the second state and the third state satisfies a threshold.

3. The method of claim 1 , wherein applying the predistortion to the first input signal comprises: The predistortion is applied to the first signal after a single iteration of the acquiring and the determining.

4. The method according to claim 1, wherein: Acquiring the first output signal includes: acquiring the first output signal of the power amplifier in the second state, in which the bias voltage is set to only the second voltage; and Amplifying the version of the predistorted first input signal includes amplifying the version of the predistorted first input signal using the power amplifier in the third state in which the bias voltage is set only to the third voltage. The method of claim 1 , wherein at least one of the first tracking mode or the second tracking mode comprises an average power tracking mode.

6. The method of claim 1 , wherein amplifying the version of the first input signal comprises: The version of the first input signal is amplified based at least in part on a lookup table associated with an output power of the power amplifier.

7. The method of claim 6, wherein the lookup table comprises different values ​​of the output power associated with at least one of the bias voltage, one or more gains applied to a transmit chain, and one or more power levels applied to the transmit chain.

8. The method of claim 1 , wherein determining the predistortion comprises: While determining the predistortion, the version of the first input signal is amplified using the power amplifier in the first state.

9. The method according to claim 1, wherein obtaining the first output signal of the power amplifier comprises: The first output signal of the power amplifier is acquired in a capture opportunity.

10. The method of claim 9, wherein the acquisition opportunity comprises a fraction of one symbol to ten symbols.

11. The method of claim 1, wherein the second state and the third state of the power amplifier satisfy a metric associated with an output power of the power amplifier.

12. A method according to claim 11, wherein the metric includes at least one of the following: a change in the output power relative to the output power during the first state, a first difference between the output power during the second state and a target output power of the power amplifier, and a second difference between the output power during the third state and the target output power.

13. The method of claim 11, wherein the second state and the third state of the power amplifier satisfy the metric associated with the output power of the power amplifier when the output power during the second state and the third state is within a power range from a target output power of the power amplifier.

14. The method according to claim 1, further comprising: In response to one or more criteria being satisfied, a second output signal of the power amplifier in the second state or the third state is acquired.

15. The method of claim 14, wherein the one or more criteria are satisfied when a timer expires or a characteristic associated with the power amplifier changes by reaching a threshold.

16. The method according to claim 1, further comprising: applying the predistortion to a second input signal in response to one or more criteria being satisfied; as well as The predistorted version of the second input signal is amplified using the power amplifier in the third state or in a fourth state in which the bias voltage is set to a fourth voltage.

17. The method of claim 16, wherein the one or more criteria are satisfied when a difference between a first output power associated with the first input signal and a second output power associated with the second input signal is within a threshold.

18. The method of claim 1, wherein applying the predistortion comprises: The predistortion is applied to the first input signal as digital predistortion.

19. A method for signal amplification, the method comprising: Acquire a first output signal of the power amplifier in a first state, in which a bias voltage is set to a first voltage determined based on a first tracking mode and is less than a second voltage; determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal; applying the predistortion to a first input signal of the power amplifier; as well as The predistorted version of the first input signal is amplified using the power amplifier in a second state in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

20. The method of claim 19, wherein determining the predistortion comprises: While determining the predistortion, the version of the first input signal is amplified using the power amplifier in the third state in which the bias voltage is set to the second voltage.

21. A device for signal amplification, the device comprising: Power amplifier; a power supply coupled to the power amplifier; a memory including executable instructions; and a controller coupled to the memory, the power amplifier, and the power supply, wherein the controller is configured to execute the executable instructions and cause the apparatus to: amplifying a version of a first input signal using the power amplifier in a first state in which a bias voltage of the power amplifier is set to a first voltage by the power supply based on a first tracking mode, acquiring a first output signal of the power amplifier in a second state, in which the bias voltage is set to a second voltage by the power supply, wherein the second voltage is less than the first voltage, determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal, applying the predistortion to the first input signal, and The predistorted version of the first input signal is amplified using the power amplifier in a third state in which the bias voltage is set to a third voltage by the power supply based on a second tracking mode, wherein the third voltage is less than the first voltage.

22. The apparatus of claim 21, wherein a compression point associated with the power amplifier in the second state and the third state satisfies a threshold.

23. The apparatus of claim 21, wherein to apply the predistortion to the first input signal, the controller is further configured to execute the executable instructions and cause the apparatus to apply the predistortion to the first signal after a single iteration of the acquiring and the determining.

24. The apparatus of claim 21, wherein: In order to obtain the first output signal, the controller is further configured to execute the executable instructions and cause the device to obtain the first output signal of the power amplifier in the second state, in which the bias voltage is only set to the second voltage; as well as To amplify the version of the predistorted first input signal, the controller is further configured to execute the executable instructions and cause the device to amplify the version of the predistorted first input signal using the power amplifier in the third state, in which the bias voltage is set only to the third voltage.

25. The apparatus of claim 21, wherein at least one of the first tracking mode or the second tracking mode comprises an average power tracking mode.

26. An apparatus according to claim 21, wherein to amplify the version of the first input signal, the controller is also configured to execute the executable instructions and cause the apparatus to amplify the version of the first input signal based at least in part on a lookup table associated with the output power of the power amplifier.

27. The apparatus of claim 21, wherein to determine the predistortion, the controller is further configured to execute the executable instructions and cause the apparatus to amplify the version of the first input signal using the power amplifier in the first state while determining the predistortion.

28. The apparatus of claim 21, wherein the second state and the third state of the power amplifier satisfy a metric associated with an output power of the power amplifier.

29. The apparatus of claim 21, wherein the controller is further configured to execute the executable instructions and cause the apparatus to obtain a second output signal of the power amplifier in the second state or the third state in response to one or more criteria being met.

30. A device for signal amplification, the device comprising: Power amplifier; a power supply coupled to the power amplifier; a memory including executable instructions; and a controller coupled to the memory, the power amplifier, and the power supply, wherein the controller is configured to execute the executable instructions and cause the apparatus to: acquiring a first output signal of the power amplifier in a first state, in which the bias voltage is set to a first voltage determined based on the first tracking mode and is less than the second voltage, determining a predistortion associated with the power amplifier based at least in part on the obtained first output signal, applying the predistortion to a first input signal of the power amplifier, and The predistorted version of the first input signal is amplified using the power amplifier in a second state in which the bias voltage is set to a third voltage based on a second tracking mode, wherein the third voltage is less than the first voltage.

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