Method for manufacturing wiring structure
By forming trenches and seed layers on the substrate and performing metal plating treatment thereon, the problem of difficult to manufacture fine wiring with high precision in the prior art is solved, and high precision wiring structure manufacturing is realized, suitable for semiconductors Wiring connection between components and packages.
Patent Information
- Application Number
- CN202380034681.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-05-01
- Publication Date
- 2025-01-03
AI Technical Summary
It is difficult to manufacture a wiring structure with fine wiring with high precision in the prior art, especially in semiconductor devices with semiconductor elements. The prior methods such as the semi-addition method and the trench method have limitations in accuracy and efficiency.
By providing a resist layer on the substrate, a trench is formed, followed by a seed layer inside and outside the trench, and a metal plating layer is formed on the seed layer, unnecessary parts are removed to leave the plating layer in the trench , the resist layer is then removed to form a wiring layer, and optionally a barrier layer and an insulating layer are formed.
The wiring structure with fine wiring is realized with high precision, avoiding the reduction in wiring width caused by etching, and can be used in semiconductor components and packages. It is suitable for the matching of semiconductor packages such as 2.5D and 2.3D. Wire connection.
Smart Images
Figure CN119256631A_ABST
Abstract
Description
Technical Field The present invention relates to a method for manufacturing a wiring structure having a wiring layer. Background Art In a semiconductor device having a semiconductor element, a wiring structure including fine wiring such as a redistribution layer connected to the semiconductor element is sometimes provided. The wiring structure is sometimes formed by a semi-additive method, which includes the following steps: forming a resist layer having a pattern including an opening on a seed layer, forming an electrolytic plating layer on the seed layer in the opening; removing the resist layer; and removing unnecessary portions of the seed layer by etching (for example, Patent Document 1). As another method for forming a wiring layer, a trench method has also been proposed, in which an insulating layer constituting a wiring layer is formed by a photosensitive resin material, and an electrolytic plating layer is formed in the opening of the insulating layer patterned by exposure and development (for example, Patent Document 2). Previous technical literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2004-06773 Patent Document 2: Japanese Patent Application Publication No. 2018-85358 Summary of the invention Technical issues to be solved by the invention The present invention relates to a novel method capable of manufacturing a wiring structure having a wiring layer including fine wiring with high precision. Means for solving technical problems The present invention includes the following contents.
[0001] A method for manufacturing a wiring structure, comprising the following steps: Disposing a resist layer on one main surface of the substrate; The resist layer is patterned by exposure and development, thereby forming a groove having a bottom surface including the surface of the substrate and a wall surface including the surface of the resist layer; forming a seed layer, the seed layer comprising an in-groove seed portion continuously formed in the groove from a position on the bottom surface to a position on the wall surface, and an out-groove seed portion provided on a side of the resist layer opposite to the substrate and continuously formed with the in-groove seed portion; forming a metal plating layer on the seed layer, the metal plating layer comprising a filling plating portion filling the trench together with the seed portion in the trench and a portion disposed on the seed portion outside the trench; removing a portion of the metal plating layer and the seed portion outside the trench so that the resist layer is exposed and the filling plating portion remains; and The resist layer is removed from the main surface of the substrate so that wiring including the in-trench seed portion and the filled plated portion remains.
[0002] The method according to [1], wherein: The method further includes the steps of: forming a barrier layer, the barrier layer including a portion continuously formed from a position on the bottom surface to a position on the wall surface in the groove; forming the seed layer on the barrier layer, The resist layer is removed from the main surface of the substrate so that the barrier layer remains together with the wiring.
[0003] The method according to [1] or [2], wherein: The method further includes the step of forming an insulating layer surrounding the wiring on the main surface of the substrate, thereby forming a wiring layer including the wiring and the insulating layer.
[0004] The method according to [3], wherein: The method further includes the step of laminating one or more additional wiring layers including additional wiring and an additional insulating layer surrounding the additional wiring on a surface of the wiring layer on the opposite side to the substrate. Effects of the Invention A wiring structure having a wiring layer including fine wiring can be manufactured with high precision. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 This is a process diagram showing an example of a method for manufacturing a wiring structure. Figure 2 This is a process diagram showing an example of a method for manufacturing a wiring structure. Figure 3 This is a process diagram showing an example of a method for manufacturing a wiring structure. Figure 4 This is a process diagram showing an example of a method for manufacturing a wiring structure. Figure 5 This is an electron microscope photograph of the intermediate structure after the grooves and seed layer are formed. Figure 6 This is an electron microscope photograph of the intermediate structure after the metal plating is formed. Figure 7 This is an electron microscope photograph of the formed wiring. DETAILED DESCRIPTION The present invention is not limited to the following examples. Figure 1 , Figure 2 and Figure 3 This is a process diagram showing an example of a method for manufacturing a wiring structure having a wiring layer. Figure 1 to Figure 3The method shown includes the following steps: preparing a substrate 1; setting a resist layer 2 on a main surface 1S of the substrate 1; patterning the resist layer 2 by exposure and development, thereby forming a groove 3 exposing the substrate 1; forming a barrier layer 4 covering the substrate 1 and the resist layer 2; forming a seed layer 5 on the barrier layer 4; forming a metal plating layer 6 on the seed layer 5; removing a portion of the metal plating layer 6, the seed layer 5 and the barrier layer 4, thereby exposing the resist layer 2; and removing the resist layer 2 from the main surface 1S of the substrate 1 so that the wiring 11 including the seed layer 5 and the metal plating layer 6 remains. The substrate 1 may be a temporary support for forming a wiring structure, or may be a component including a circuit connected to wiring in the wiring structure. For example, the substrate 1 may be a component including a semiconductor element, and the wiring structure may be a redistribution layer connected to the semiconductor element. In this case, the method of the present invention can be used to manufacture, for example, a fan-out semiconductor package having a semiconductor element and a redistribution layer. Furthermore, the method of the present invention can also be used to manufacture a wiring structure that connects semiconductor elements to each other in so-called 2.5D, 2.3D, 2.1D, etc. semiconductor packages, i.e., an intermediate layer. The resist layer 2 can be formed of a resist material commonly used for wiring formation, etc. The resist layer 2 can be provided on the main surface 1S by laminating a dry film resist. Alternatively, the resist layer 2 can be formed by a method including applying a liquid resist on the main surface 1S and drying the coating. The resist material used to form the resist layer 2 is removed after forming the metal plating layer for wiring and is not used as a material for forming the insulating layer constituting the wiring layer. Therefore, there is no need to consider the performance as an insulating layer, and the resist material can be selected mainly based on the performance as a photosensitive material. like Figure 1 As shown in (b), the resist layer 2 is patterned by a common method including exposure and subsequent development, thereby forming a groove 3 in which the substrate 1 is exposed. The groove 3 has a bottom surface 3a including the surface (main surface 1S) of the substrate 1 and a wall surface 3b including the surface (side) of the resist layer 2, and extends along the in-plane direction of the main surface 1S of the substrate 1. The groove 3 includes a portion corresponding to the position where the wiring is formed. Multiple grooves 3 can also be independently arranged on the main surface 1S. The minimum width of the groove 3 can be, for example, greater than 0.5μm and less than 10μm. The minimum spacing between the grooves 3 can be, for example, greater than 0.5μm and less than 10μm. The depth of the groove 3 (or the thickness of the resist layer 2) can be, for example, greater than 1μm and less than 15μm. The minimum width of the groove 3 can be the minimum value of the width in a direction perpendicular to the length direction of the groove 3. like Figure 1As shown in (c), the barrier layer 4 includes a portion formed continuously from a position on the bottom surface 3a to a position on the wall surface 3b in the groove 3 and a portion provided on the surface of the resist layer 2 on the opposite side to the substrate 1. In the groove 3, the barrier layer 4 is formed with a groove or a recessed portion having a shape corresponding to the groove 3. The barrier layer 4 is a layer provided mainly to suppress migration from the wiring, and is between the formed wiring 11 and the substrate 1 and the resist layer 2. The barrier layer 4 may be, for example, a layer containing titanium. The thickness of the barrier layer 4 may be, for example, greater than 10 nm and less than 50 nm. The barrier layer 4 may be formed, for example, by a sputtering method. The barrier layer 4 may also not be provided. like Figure 2 As shown in (d), the seed layer 5 formed on the barrier layer 4 includes an in-groove seed portion 5A formed continuously from a position on the bottom surface 3a to a position on the wall surface 3b in the groove 3, and an out-groove seed portion 5B provided on the side of the resist layer 2 opposite to the substrate 1. The out-groove seed region 5B is formed continuously with the in-groove seed region 5A. The seed layer 5 is used to form a metal plating layer 6 by electrolytic plating. The seed layer 5 can be a layer containing a metal such as copper. The thickness of the seed layer can be, for example, greater than 50 nm and less than 500 nm. Since a seed layer is not provided between the substrate 1 and the resist layer 2, etching for removing unnecessary seed layers, etc. is not required after removing the resist layer 2. Therefore, a reduction in the width of the wiring 11 due to etching can be avoided. In addition, the portion of the barrier layer 4 covering the side of the wiring 11 can also be easily left. The seed layer 5 can be formed, for example, by sputtering. The seed layer 5 can also be formed by electroless plating. like Figure 2 As shown in (e), the metal plating 6 is formed on the seed layer 5 by electrolytic plating. The metal plating 6 includes a filling plating portion 6A that fills the groove 3 together with the in-groove seed portion 5A of the seed layer 5 and the barrier layer 4, and a portion arranged on the seed portion 5B outside the groove of the seed layer 5. The metal plating 6 is usually formed to cover the entire surface of the seed layer 5 on the opposite side of the substrate 1. The metal plating 6 can be a layer containing copper. The surface of the metal plating 6 on the opposite side of the substrate 1 can be flat or have projections and depressions. The thickness of the filling plating portion 6A in the metal plating 6 (the thickness in the thickness direction of the substrate 1) can be greater than 1 μm and less than 15 μm. The thickness of the portion of the metal plating 6 arranged on the seed portion 5B outside the groove can be greater than 0.1 μm and less than 5 μm. After forming the metal plating layer 6, as Figure 3As shown in (f), a portion of the metal plating layer 6, the seed portion 5B outside the groove in the seed layer 5, and a portion of the barrier layer 4 are removed to expose the resist layer 2, and the filling plating portion 6A remains. The metal plating layer 6, the seed layer 5, and the barrier layer 4 can be removed, for example, by etching or chemical mechanical polishing (CMP). As a result of the removal, a flat surface including the surface of the resist layer 2 and the surface of the remaining filling plating portion 6A can be formed. Then, if Figure 3 As shown in (g), the resist layer 2 is removed from the main surface 1S of the substrate 1 so that the wiring 11 including the seed portion 5A in the groove and the filled plating portion 6A remains. Usually, the barrier layer 4 including the portion covering the side surface thereof also remains together with the wiring 11. The resist layer 2 can be removed by dissolving in a stripping solution, for example. After removing the resist layer 2, as Figure 4 As shown in (h), an insulating layer 21 surrounding the wiring 11 can be formed on the main surface 1S of the substrate 1. Thus, a wiring layer 31 including the wiring 11 and the insulating layer 21 is formed. The insulating layer 21 can be an insulating resin layer. For example, the insulating layer 21 can contain polybenzoxazole, polyimide, or a combination thereof. A part or the entirety of the main surface 1S of the substrate 1 can be a surface of the same insulating layer as the insulating layer 21. like Figure 4 As shown in (i), on the surface of the wiring layer 31 on the opposite side to the substrate 1, an additional wiring layer 32 including an additional wiring 12 and an additional insulating layer 22 surrounding the additional wiring 12 can be further stacked. The additional wiring 12 can be formed by the same method as the wiring 11. In this case, the additional wiring 12 can also include a seed portion 5A in the groove of the seed layer 5 and a filled plating portion 6A of the metal plating layer 6. The additional insulating layer 22 can be the same layer as the insulating layer 21. By stacking more than one additional wiring layer in the same way as the method exemplified for the wiring layer 31, a wiring structure 50 including multiple wiring layers can be formed. The multilayer structure composed of multiple wiring layers can include through holes connecting the wiring layers to each other. Example Hereinafter, an example of forming a wiring layer by the method according to the present invention will be described. The present invention is not limited to the following example. A liquid resist is applied to the main surface of a substrate having a surface containing a polyimide resin, and the coating is dried to form a resist layer. The resist layer is patterned by exposure to ultraviolet rays and subsequent development, thereby forming a plurality of linear grooves extending on the main surface of the substrate. The groove has a bottom surface including the substrate surface and a wall surface including the resist layer surface. The maximum width of each groove and the interval between adjacent grooves are about 5 μm. A Cu film covering the bottom surface and the wall surface in the trench and the surface of the resist layer on the opposite side to the substrate is formed as a seed layer by sputtering. Figure 5 This is an electron microscope photograph of the intermediate structure after the grooves and seed layer are formed. Figure 5 The photo (b) includes a cross section perpendicular to the length direction of the groove. The formed seed layer has an inner groove seed portion formed continuously from the bottom surface to the wall surface in the groove, and an outer groove seed portion provided on the side of the resist layer opposite to the substrate and formed continuously with the inner groove seed portion. Next, a metal plating layer (copper plating layer) was formed on the seed layer by electrolytic copper plating. Figure 6 This is an electron microscope photograph of the intermediate structure including the metal plating layer. Figure 6 The photograph (b) includes a cross section perpendicular to the longitudinal direction of the trench. The metal plating layer includes a filling plating portion that fills the trench together with the in-trench seed portion and a portion provided on the out-trench seed portion. A portion of the metal plating layer and the seed portion outside the trench in the seed layer are removed by etching, forming a flat surface formed by the exposed resist layer and the remaining metal plating layer (filled plating portion). Then, the resist layer is removed by dissolving it in a stripping solution. Figure 7 This is an electron microscope photograph of the wiring layer including the metal plating layer (filling plating portion) remaining on the substrate. It was confirmed that wiring with a good shape was formed with high precision. The wiring was formed in the same steps as above except that the maximum width of each groove and the interval between adjacent grooves were changed to about 3μm or about 2μm. As a result, wiring with a good shape was formed with high precision in either case. Description of Reference Numerals 1-substrate, 2-resist layer, 3-groove, 3a-bottom surface, 3b-wall surface, 4-barrier layer, 5-seed layer, 5A-seed portion inside the groove, 5B-seed portion outside the groove, 6-metal plating, 6A-filling plating portion, 11, 12-wiring, 21, 22-insulating layer, 31, 32-wiring layer, 50-wiring structure.
Claims
1. A method for manufacturing a wiring structure, comprising the following steps: Disposing a resist layer on one main surface of the substrate; The resist layer is patterned by exposure and development, thereby forming a groove having a bottom surface including the surface of the substrate and a wall surface including the surface of the resist layer; forming a seed layer, the seed layer comprising an in-groove seed portion continuously formed in the groove from a position on the bottom surface to a position on the wall surface, and an out-groove seed portion provided on a side of the resist layer opposite to the substrate and continuously formed with the in-groove seed portion; forming a metal plating layer on the seed layer, the metal plating layer comprising a filling plating portion filling the trench together with the seed portion in the trench and a portion disposed on the seed portion outside the trench; removing a portion of the metal plating layer and the seed portion outside the trench so that the resist layer is exposed and the filling plating portion remains; and The resist layer is removed from the main surface of the substrate so that wiring including the in-trench seed portion and the filled plated portion remains.
2. The method according to claim 1, wherein: The method further includes the steps of: forming a barrier layer, the barrier layer including a portion continuously formed from a position on the bottom surface to a position on the wall surface in the groove; forming the seed layer on the barrier layer, The resist layer is removed from the main surface of the substrate so that the barrier layer remains together with the wiring.
3. The method according to claim 1, wherein: The method further includes the step of forming an insulating layer surrounding the wiring on the main surface of the substrate, thereby forming a wiring layer including the wiring and the insulating layer.
4. The method according to claim 3, wherein: The method further includes the step of laminating one or more additional wiring layers including additional wiring and an additional insulating layer surrounding the additional wiring on a surface of the wiring layer on the opposite side to the substrate.