Wafer testing system and method

By integrating signal switches in the probe card of the wafer test system, the rapid switching of static and dynamic test modes is achieved, and the problems of low wafer testing efficiency and signal attenuation in the prior art are solved, thereby improving the testing efficiency and accuracy.

CN119269856AActive Publication Date: 2025-01-07MT MICROSYST

Patent Information

Application Number
CN202411783721.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-06
Publication Date
2025-01-07
Estimated Expiration
2044-12-06

AI Technical Summary

Technical Problem

At this stage, wafer testing efficiency is low, dynamic testing and static testing need to be carried out separately, switching between probes affects efficiency, and dynamic detection signals are inaccurate attenuation distortion due to long test links.

Method used

Design a wafer testing system, integrate signal switches in the probe card, and connect static or dynamic detection circuits through the target mode test command switching to realize mode selection of static and dynamic testing, reducing probe switching and improving efficiency.

Benefits of technology

It realizes rapid switching of static and dynamic test modes without replacing the probe, improves wafer testing efficiency, reduces attenuation loss of weak signals, and improves the accuracy of test data.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN119269856A_ABST
    Figure CN119269856A_ABST
Patent Text Reader

Abstract

The invention provides a wafer testing system and method, and belongs to the field of semiconductor testing. The wafer test system comprises a control host, a probe card and a test device, the probe card comprises a signal switch; the control host is used for generating a target mode test instruction and sending the target mode test instruction to the probe card; and the probe card is used for enabling the signal switch to select a corresponding target mode based on the target mode test instruction so as to acquire a test signal corresponding to the to-be-tested wafer device, and sending the test signal to the test device so as to obtain test data of the to-be-tested wafer device. Devices required for dynamic detection and static detection of wafer devices are integrated on the probe card, and mode selection is carried out through a signal switch. When a dynamic test and a static test need to be switched, the probe does not need to be switched, and only the signal switch needs to be switched on and off, so that the wafer test efficiency is improved.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a wafer testing system and method. Background Art

[0002] With the development of science and technology, micro devices manufactured by Micro-Electro-Mechanical System (MEMS) technology are increasingly widely used in aviation, aerospace and industrial fields due to their advantages in service life, reliability, cost, volume and weight. With the advancement of MEMS processing technology, micromachining technology is widely used in the manufacture of sensors and actuators.

[0003] Wafer testing is an important process in the production of MEMS devices. It is used to test the performance of MEMS structures, eliminate unqualified chips at the wafer level, and reduce the cost of later packaging and testing. At present, the wafer test vectors of MEMS devices mainly include two categories: static testing and dynamic testing. Static testing mainly includes capacitance, resistance, voltage, current, etc., and the test instruments include capacitance meters, resistance meters, voltmeters, switch matrices, etc.; dynamic testing mainly includes: natural frequency, quality factor, orthogonal coupling, etc., and the test devices are signal conversion circuits and data processing modules.

[0004] Since the detection signal of dynamic test is very small, dynamic test cannot pass the test point through the test cable, switch matrix and then to the signal conversion circuit like static test. Too long test link will cause the dynamic detection signal to attenuate and distort, and the test will be inaccurate. Therefore, dynamic test generally designs the detection circuit on the test probe card to reduce line attenuation loss.

[0005] However, the probe cards used for dynamic testing and static testing are different. Static test probe cards do not require detection circuits, while dynamic test probe cards do. Dynamic testing and static testing can only be performed separately. When performing tests, it is necessary to switch between different probes, which greatly affects the test efficiency. Summary of the invention

[0006] The embodiments of the present invention provide a wafer testing system and method to solve the problem of low wafer testing efficiency at present.

[0007] In a first aspect, an embodiment of the present invention provides a wafer testing system, the system comprising: Control host, probe card and test device; the probe card includes a signal switch; A control host, used for generating a target mode test instruction and sending the target mode test instruction to the probe card; The probe card is used to make the signal switch select the corresponding target mode based on the target mode test instruction to collect the test signal corresponding to the wafer device to be tested, and send the test signal to the test device to obtain the test data of the wafer device to be tested.

[0008] In a possible implementation, the probe card further includes a static test terminal and a dynamic test detection circuit; The target mode test instruction is a static mode test instruction or a dynamic mode test instruction; If the target mode test instruction is a static mode test instruction, the signal switch is switched to connect to the static test terminal; If the target mode test instruction is a dynamic mode test instruction, the signal switch is switched to connect to the dynamic test detection circuit.

[0009] In a possible implementation, the wafer testing system further includes a switch matrix; The switch matrix is ​​used to receive the target mode test instruction, adjust itself to the corresponding test mode based on the target mode test instruction, and send the target mode test instruction to the probe card.

[0010] In a possible implementation, if the target mode test instruction is a static mode test instruction, the target mode test instruction also includes a target test quantity detection instruction; The switch matrix is ​​also used to adjust itself and the corresponding test device to a conductive state based on the target test quantity detection instruction, so as to send the test signal corresponding to the wafer device to be tested to the corresponding test device to obtain the target test quantity of the wafer device to be tested.

[0011] In a possible implementation, the test device includes an acquisition card; The acquisition card is used to receive the target mode test instruction and send the target mode test instruction to the switch matrix; The acquisition card is also used to receive the test data output by the dynamic test detection circuit when the target mode test instruction is a dynamic mode test instruction.

[0012] In a possible implementation, the probe card includes at least one group of dynamic test detection circuits; If the number of dynamic test detection circuits is greater than or equal to two groups, each group of dynamic test detection circuits is connected in parallel.

[0013] In a possible implementation, the wafer testing system further includes a static signal cable and a dynamic signal cable; The static signal cable and the dynamic signal cable are arranged between the switch matrix and the probe card; The static signal cable is used to transmit various signals under the static mode test command; The dynamic signal cable is used to transmit various signals under the dynamic mode test command.

[0014] In a possible implementation, the wafer testing system further includes a probe, and the probe is used to connect the wafer device to be tested and the signal switch.

[0015] In a possible implementation, the wafer testing system further includes a probe station; Probe station, used to place the wafer devices to be tested.

[0016] In a second aspect, an embodiment of the present invention provides a wafer testing method, comprising: Get target mode test instructions; Selecting a corresponding target mode based on the target mode test instruction; In the selected corresponding target mode, the test signal corresponding to the wafer device to be tested is collected, and the test signal is sent to the testing device to obtain the test data of the wafer device to be tested.

[0017] The embodiment of the present invention provides a wafer testing system and method, which solves the problem of low wafer testing efficiency at the current stage by setting a signal switch on the probe card. Specifically, the embodiment of the present invention integrates the devices required for dynamic detection and static detection of wafer devices into the probe card, and selects the mode through a signal switch. When static detection is required, the control host sends a corresponding instruction. After the probe receives the instruction, the signal switch is controlled to select the static detection mode to obtain the relevant test data of the wafer device to be tested under static detection. Conversely, the same is true when dynamic detection is required. It can be seen that when the embodiment of the present invention needs to switch between dynamic testing and static testing, there is no need to switch the probe, and the efficiency of wafer testing can be improved by opening and closing the signal switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 is a schematic structural diagram of a wafer testing system provided by an embodiment of the present invention; Figure 2 is a structural schematic diagram of a wafer testing system provided by another embodiment of the present invention; Figure 3 is a flowchart of an implementation of a wafer testing method provided by an embodiment of the present invention; DETAILED DESCRIPTION In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clear, specific embodiments will be described below in conjunction with the accompanying drawings.

[0021] Figure 1 Schematic diagram of the structure of the wafer testing system provided by the embodiment of the present invention. Figure 1 As shown, the system may include: The control host 1 , the probe card 2 and the test device 3 ; the probe card 2 includes a signal switch 21 .

[0022] The control host 1 is used to generate a target mode test instruction and send the target mode test instruction to the probe card 2.

[0023] The probe card 2 is used to make the signal switch 21 select the corresponding target mode based on the target mode test instruction to collect the test signal corresponding to the wafer device to be tested, and send the test signal to the test device 3 to obtain the test data of the wafer device to be tested.

[0024] In this embodiment, the probe card 2 may include a plurality of signal switches 21, and the number of the signal switches 21 may be determined based on the number of wafer devices to be tested during each detection. The signal switch 21 may be a single-pole double-throw switch, wherein the fixed end 21a of the signal switch 21 is used to connect to the wafer device to be tested, and the moving ends 21b and 21c are connected to the static test end and the dynamic test end, respectively.

[0025] When wafer device testing is required, the control host 1 generates and issues a target mode test instruction, which is transmitted to the probe card 2 after passing through the test device 3. The probe card 2 determines whether a dynamic test or a static test is required according to the target mode test instruction, so that the signal switch 21 connects the active terminal 21b or 21c to select the corresponding target mode.

[0026] After the signal switch 21 selects and turns on the corresponding target mode, the test signal of the wafer device to be tested is input from the fixed end 21a of the signal switch 21, flows through the selected target end, and then flows to the test device 3. Various detection instruments are provided in the test device 3, which can select the corresponding detection instrument for detection according to the target mode test instruction to obtain the test data of the wafer device to be tested, and send the test data to the control host 1. When the control host 1 determines that the test data required in the current target mode test instruction has been fully tested, a new target mode test instruction is generated according to the test needs, and the above instructions are repeated until all the items of the wafer device to be tested are tested.

[0027] In this embodiment, the system provided by this embodiment integrates the test devices required for the two modes of static testing and dynamic testing into the probe card 2, and switches according to the test needs through the moving end of the probe card 2, without the need to replace the probe, which can improve the test efficiency. In addition, since the fixed end 21a of the signal switch 21 is directly connected to the wafer device to be tested through the probe, the fixed end 21a is close to the probe, which can minimize the impact of the cable and switch on the weak dynamic signal. The signal converted by the detection circuit is larger and less affected by the subsequent cable.

[0028] Figure 2 FIG. 1 is a schematic diagram of the structure of a wafer testing system provided by another embodiment of the present invention. Figure 2 As shown, the system may also include the following structures: Optionally, the probe card 2 further includes a static test terminal 22 and a dynamic test detection circuit 23 .

[0029] The target mode test instruction is a static mode test instruction or a dynamic mode test instruction.

[0030] If the target mode test instruction is a static mode test instruction, the signal switch 21 is switched to connect to the static test terminal 22 .

[0031] If the target mode test instruction is a dynamic mode test instruction, the signal switch 21 is switched to connect to the dynamic test detection circuit 23 .

[0032] In this embodiment, for the sake of brief introduction, only the fixed end of one of the signal switches 21 is described in the figure, but those skilled in the art should understand that in actual use, the fixed end of each signal switch 21 in the probe card 2 needs to be connected to the static test end 22 and the dynamic test detection circuit 23. Of course, in actual application, the moving end 21b of each signal switch 21 can also be connected to the dynamic test detection circuit 23, and the moving end 21c can also be connected to the static test end 22.

[0033] In this embodiment, the wafer device to be tested is generally a MEMS gyroscope or a MEMS accelerometer; the dynamic parameters of the MEMS gyroscope include frequency, quality factor, and orthogonal coupling; the dynamic parameters of the MEMS accelerometer are mainly -3DB bandwidth or +3dB bandwidth. Since the working principles of the MEMS gyroscope and the MEMS accelerometer are different, the required dynamic test detection circuit 23 is also different, so the form of the dynamic test detection circuit 23 is determined by the form of the wafer device to be tested.

[0034] When dynamic detection of the wafer device to be tested is required, the control host 1 generates a dynamic mode test instruction, and transmits the instruction to the probe card 2 after passing through the test device 3, so as to control the dynamic ends of all signal switches 21 to switch to 21c, so as to connect the dynamic test detection circuit 23, so that the test signal input from the fixed end 21a of all signal switches 21 to the wafer device to be tested flows through the dynamic test detection circuit 23, and the test data is obtained, and the test data is sent to the control host 1 through the test device 3.

[0035] When it is necessary to perform static detection on the wafer device to be tested, the control host 1 generates a static mode test instruction, and transmits the instruction to the probe card 2 after passing through the test device 3, so as to control the active ends of all signal switches 21 to switch to 21b to connect the static test end 22, so that the test signal input from the fixed end 21a of all signal switches 21 to the wafer device to be tested flows through the static test end 22 and is input into the test device 3. In the test device 3, the test is performed according to the test items required in the static mode test instruction to obtain test data, and the test data is sent to the control host 1.

[0036] Optionally, the dynamic test detection circuit 23 included in the probe card 2 is at least one group.

[0037] If the number of the dynamic test detection circuits 23 is greater than or equal to two groups, each group of dynamic test detection circuits 23 is connected in parallel.

[0038] In this embodiment, when the wafer device to be tested is a multi-axis device, for example, when the wafer device to be tested is a three-axis MEMS gyroscope, it is necessary to test the dynamic parameters of the four axes of drive, detection X, detection Y and detection Z during detection. In this way, there are four types of dynamic test probe cards, and each wafer test needs to switch between the four probe cards. In order to solve this technical problem, the embodiment of the present invention can increase the number of dynamic test detection circuits 23, and expand each group of dynamic test detection circuits 23 to the probe card 2 after being connected in parallel in hardware. In this way, in specific applications, for example, for the test of a three-axis gyroscope, four gyroscope detection circuit modules can be designed on the moving end 21c of the signal switch 21; for static testing, that is, three-axis table addition test, three table addition detection circuit modules can be designed. Similarly, four detection circuit modules and three table addition modules can be designed on the IMU measurement unit MEMS probe card.

[0039] Of course, whether each test channel can be tested in parallel depends on the actual situation. For example, the drive and three detections of the three-axis gyroscope share a mass block, and each channel can only be tested sequentially. With a three-axis plus meter, the three channels do not interfere with each other and can be tested in parallel.

[0040] Optionally, the wafer testing system further includes a switch matrix 4 .

[0041] The switch matrix 4 is used to receive the target mode test instruction, adjust itself to the corresponding test mode based on the target mode test instruction, and send the target mode test instruction to the probe card 2 at the same time.

[0042] In this embodiment, after the control host 1 issues a target mode test instruction, the target mode test instruction is transmitted to the switch matrix 4 through the test device 3 to instruct the switch matrix 4 to adjust itself to a designated test channel according to the target mode test instruction.

[0043] Exemplarily, when the target mode test instruction is a static mode test instruction, the switch matrix 4 turns on the static test channel. When the test signal of the wafer device to be tested is input from the fixed end 21a of all the signal switches 21 and flows through the static test end 22, the test signal flows to the test device 3 through the turned-on static test channel for static detection.

[0044] Exemplarily, when the target mode test instruction is a dynamic mode test instruction, the switch matrix 4 turns on the dynamic test channel. When the test signal of the wafer device to be tested is input by 21a of all signal switches 21 and flows through the dynamic test detection circuit 23, the test data is obtained, and the test data flows to the control host 1 through the turned-on dynamic test channel.

[0045] It can be seen that the embodiment of the present invention reconfigures the signal switch 21 and the switch matrix 4 in the wafer testing system, and selects static testing and dynamic testing through two-stage switches, which can maximize the efficiency of wafer testing.

[0046] Optionally, if the target mode test instruction is a static mode test instruction, the target mode test instruction also includes a target test quantity detection instruction.

[0047] The switch matrix 4 is also used to adjust itself and the corresponding test device 3 to a conductive state based on the target test quantity detection instruction, so as to send the test signal corresponding to the wafer device to be tested to the corresponding test device 3 to obtain the target test quantity of the wafer device to be tested.

[0048] In this embodiment, the test device 3 may include various detection instruments required for static mode detection, such as a voltmeter, an ammeter, and a resistance meter, etc. When the target mode test instruction is a static mode test instruction, the static mode test instruction also includes a target detection item, such as voltage detection.

[0049] For example, if the static mode test instruction includes voltage detection, then after receiving the static mode test instruction, the switch matrix 4 adjusts the detection channel between itself and the voltmeter to the conduction mode. In this case, the test signal corresponding to the wafer device to be tested can flow to the voltmeter in the test device 3 based on the conducted detection channel to perform voltage detection and obtain a voltage test value.

[0050] Optionally, the testing device 3 may further include a collection card 31 .

[0051] The acquisition card 31 is used to receive the target mode test instruction and send the target mode test instruction to the switch matrix 4.

[0052] The acquisition card 31 is also used to receive the test data output by the dynamic test detection circuit when the target mode test instruction is a dynamic mode test instruction.

[0053] In this embodiment, when the control host 1 issues a target mode test instruction, the target mode test instruction can be transmitted to the acquisition card 31 in the test device 3. The acquisition card 31 controls the switch matrix 4 to turn on the corresponding test channel according to the target mode test instruction. At the same time, the acquisition card 31 controls the probe card 2 according to the target mode test instruction, so that the selection end 21b or 21c of the signal switch 21 in the probe card 2 is turned on, thereby realizing the corresponding control.

[0054] In addition, in this embodiment, when the target mode test instruction is a dynamic mode test instruction, since the dynamic test data required by the wafer device to be tested has been obtained through the dynamic test detection circuit 23, the dynamic test detection circuit 23 can be directly sent to the acquisition card 31 through the switch matrix 4. After receiving the dynamic test data, the acquisition card 31 stores and sends the dynamic test data to the control host 1.

[0055] Optionally, the wafer testing system also includes static signal cables and dynamic signal cables.

[0056] The static signal cables and the dynamic signal cables are arranged between the switch matrix 4 and the probe card 2 .

[0057] The static signal cable is used to transmit various signals under the static mode test command.

[0058] The dynamic signal cable is used to transmit various signals under the dynamic mode test command.

[0059] In this embodiment, the wafer test system is also provided with a static signal cable and a dynamic signal cable, which adopts a coaxial cable with strong anti-interference ability. These two cables are arranged between the switch matrix 4 and the probe card 2. When the target mode test instruction is a static mode test instruction, the related instructions and the data signal transmitted back by the probe card 2 are transmitted through the static signal cable.

[0060] When the target mode test instruction is a dynamic mode test instruction, the related instruction and the data signal transmitted back by the probe card 2 are transmitted through the dynamic signal cable.

[0061] Optionally, the wafer testing system further includes a probe, which is used to connect the wafer device to be tested and the signal switch 2 .

[0062] Optionally, the wafer testing system further includes a probe station 5 .

[0063] The probe station 5 is used to place the wafer device to be tested.

[0064] In this embodiment, the wafer testing system may further include a probe station 5, which is used to place the wafer device to be tested. The probe station 5 is a wafer carrier, which moves in a certain step length and may be a manual probe station, a semi-automatic probe station, or a fully automatic probe station.

[0065] In this embodiment, the probe material is generally rhenium-tungsten alloy or beryllium-copper alloy, and the probe material and size depend on the material and size of the chip pad to be tested. When the wafer device to be tested is a MEMS device, it is generally placed on the probe station 5 in the form of a wafer, and the wafer size is 4 inches, 6 inches, 8 inches or 12 inches.

[0066] When the wafer device to be tested is placed in the corresponding position and the test can be started, the control host 1 sends a control signal to control the probe station 5 to rise and fall according to the control signal, so that each probe can accurately connect with each wafer device to be tested. After the test items required in the current target mode test instruction are completed, the probe station 5 feeds back a test completion signal to the control host 1, and the control host 1 displays the corresponding feedback signal to facilitate the tester to determine whether to perform other tests on the current test wafer device on the probe station 5, or to control the probe station 5 to replace a new wafer device to be tested and re-test it.

[0067] It can be seen that the embodiment of the present invention provides a wafer testing system, which integrates the devices required for dynamic detection and static detection of wafer devices into a probe card, and selects a mode through a signal switch. When static detection is required, the control host sends a corresponding instruction. After the probe receives the instruction, the control signal switch selects the static detection mode to obtain relevant test data of the wafer device to be tested under static detection. Conversely, the same is true when dynamic detection is required. It can be seen that when the embodiment of the present invention needs to switch between dynamic testing and static testing, there is no need to switch the probe, and the efficiency of wafer testing can be improved by opening and closing the signal switch.

[0068] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0069] Figure 3 : is a flowchart of the implementation of the wafer testing method provided by the embodiment of the present invention. For the parts that are not described in detail in this embodiment, reference can be made to the other related embodiments mentioned above. Accordingly, the wafer testing method may include: Step 110: Obtain target mode test instructions.

[0070] Step 120: Select a corresponding target mode based on the target mode test instruction.

[0071] Step 130: Under the selected corresponding target mode, a test signal corresponding to the wafer device to be tested is collected, and the test signal is sent to a testing device to obtain test data of the wafer device to be tested.

[0072] In this embodiment, the target mode test instruction can be a dynamic mode test instruction or a static mode test instruction. When the target mode test instruction is a dynamic mode test instruction, the dynamic mode is selected, the test signal corresponding to the wafer device to be tested is collected, and the collected test signal is input into the dynamic test circuit to obtain the dynamic test data of the wafer device to be tested.

[0073] When the target mode test instruction is a static mode test instruction, the static mode test instruction also includes a target test item. The test mode is adjusted to the static mode, a test signal corresponding to the wafer device to be tested is collected, and the collected test signal is input into the target test instrument of the test device to obtain the static test data of the wafer device to be tested.

[0074] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0075] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0076] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A wafer testing system, characterized in that: include: Control host, probe card and test device; the probe card includes a signal switch; The control host is used to generate a target mode test instruction and send the target mode test instruction to the probe card; The probe card is used to make the signal switch select the corresponding target mode based on the target mode test instruction to collect the test signal corresponding to the wafer device to be tested, and send the test signal to the test device to obtain the test data of the wafer device to be tested.

2. The wafer testing system according to claim 1, characterized in that: The probe card also includes a static test terminal and a dynamic test detection circuit; The target mode test instruction is a static mode test instruction or a dynamic mode test instruction; If the target mode test instruction is a static mode test instruction, switching the signal switch to connect to the static test terminal; If the target mode test instruction is a dynamic mode test instruction, the signal switch is switched to connect to the dynamic test detection circuit.

3. The wafer testing system according to claim 2, characterized in that: The wafer testing system also includes a switch matrix; The switch matrix is ​​used to receive the target mode test instruction, adjust itself to a corresponding test mode based on the target mode test instruction, and send the target mode test instruction to the probe card.

4. The wafer testing system according to claim 3, characterized in that: If the target mode test instruction is a static mode test instruction, the target mode test instruction also includes a target test quantity detection instruction; The switch matrix is ​​also used to adjust itself and the corresponding test device to a conductive state based on the target test quantity detection instruction, so as to send the test signal corresponding to the wafer device to be tested to the corresponding test device to obtain the target test quantity of the wafer device to be tested.

5. The wafer testing system according to claim 3, characterized in that: The test device includes an acquisition card; The acquisition card is used to receive the target mode test instruction and send the target mode test instruction to the switch matrix; The acquisition card is further used to receive the test data output by the dynamic test detection circuit when the target mode test instruction is a dynamic mode test instruction.

6. The wafer testing system according to claim 2, characterized in that: The probe card includes at least one group of dynamic test detection circuits; If the number of the dynamic test detection circuits is greater than or equal to two groups, each group of dynamic test detection circuits is connected in parallel in the probe card.

7. The wafer testing system according to claim 2, characterized in that: The wafer testing system also includes a static signal cable and a dynamic signal cable; The static signal cable and the dynamic signal cable are arranged between the switch matrix and the probe card; The static signal cable is used to transmit various signals under the static mode test instruction; The dynamic signal cable is used to transmit various signals under the dynamic mode test instruction.

8. The wafer testing system according to claim 1, characterized in that: The wafer testing system further comprises a probe, and the probe is used to connect the wafer device to be tested and a signal switch.

9. The wafer testing system according to claim 1, characterized in that: The wafer testing system also includes a probe station; The probe station is used to place the wafer device to be tested.

10. A wafer testing method, characterized in that: include: Get target mode test instructions; Selecting a corresponding target mode based on the target mode test instruction; In the selected corresponding target mode, the test signal corresponding to the wafer device to be tested is collected, and the test signal is sent to the testing device to obtain the test data of the wafer device to be tested.

Citation Information

Patent Citations

  • Method for measuring voltage transmittance under influence of direct-current bias voltage and equipment

    CN102542959A

  • System and method for measuring output voltage of internal power source of chip

    CN102818923A

  • Chip interface test probe card and test method

    CN112782561A

  • Probe card of probe station

    CN113640556A

  • WAT test system and method and readable storage medium

    CN118707159A

Cited By

  • Probe card board, system and method for batch testing of wafer-level inertial devices

    CN120741904A

  • Power semiconductor wafer electrical parameter test system and test method

    CN121955669A

  • A power semiconductor wafer electrical parameter testing system and testing method

    CN121955669B