Fault location detection in tapped distribution lines

Abstract

The embodiment of the invention relates to fault location detection in a tapped distribution line. A method of detecting a location of a fault in a distribution line having a first terminal and a second terminal and a line segment disposed between the first terminal and the second terminal is provided. The method includes identifying synchronous voltage and current phasors at the first and second terminals before and during the fault, calculating equivalent sequence components for the voltage phasors and the current phasors, locating a virtual load point on the line segment, and calculating a voltage at the virtual load point. The method further includes calculating a compensated load current at the first terminal and / or the second terminal based on one or more of the current phasors before and / or after the fault, and calculate a distance from the virtual load point to the fault based on the voltage at the virtual load point, the compensated load current, and the one or more equivalent sequence components to detect a location of the fault.

Description

Technical Field

[0001] The field of the present disclosure relates to electrical grids, and in particular to detecting faults in distribution lines of an electrical grid. Background Art

[0002] Rapid and accurate location of line faults is essential for modern power distribution systems because it improves system reliability and helps reduce downtime by correctly dispatching maintenance personnel to the fault location and clearing the source of the fault as quickly as possible. Different fault location methods have been used in the past, but each method has varying degrees of complexity and disadvantages. Therefore, it is desirable to improve fault location in power distribution systems. Summary of the invention

[0003] In one aspect, a fault detector for detecting the location of a fault in a tap distribution line is provided, the tap distribution line having a first terminal and a second terminal and a line segment arranged between the first terminal and the second terminal. The fault detector includes at least one processor configured to identify synchronous voltage phasors and current phasors at the first terminal and the second terminal before and during the fault, calculate equivalent sequence components for the voltage phasors and the current phasors, locate a virtual tap load point on the line segment, and calculate the voltage at the virtual tap load point based on one or more of the current phasors before the fault. The at least one processor is also configured to calculate a compensated load current at the first terminal and / or the second terminal based on one or more of the current phasors before and / or after the fault, and calculate a distance from the virtual tap load point to the fault based on the voltage, the compensated load current and one or more equivalent sequence components at the virtual tap load point to detect the location of the fault.

[0004] On the other hand, a method for detecting the location of a fault in a tapped distribution line is provided, the distribution line having a first terminal and a second terminal and a line segment arranged between the first terminal and the second terminal. The method includes identifying synchronous voltage phasors and current phasors at the first terminal and the second terminal before and during the fault, calculating equivalent sequence components for the voltage phasors and the current phasors, locating a virtual tap load point on the line segment, and calculating the voltage at the virtual tap load point based on one or more of the current phasors before the fault. The method also includes calculating a compensated load current at the first terminal and / or the second terminal based on one or more of the current phasors before and / or after the fault, and calculating a distance from the virtual tap load point to the fault based on the voltage at the virtual tap load point, the compensated load current, and one or more equivalent sequence components to detect the location of the fault. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] These and other features, aspects and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings, wherein like characters refer to like parts throughout.

[0006] Figure 1 A fault detector for detecting a fault location in a power distribution line in an exemplary embodiment is depicted.

[0007] Figure 2 A load profile of a power distribution line in an exemplary embodiment is depicted.

[0008] Figure 3 Depicting an exemplary embodiment Figure 2 Equivalent load diagram of the distribution line.

[0009] Figure 4 A first failure scenario of a power distribution line in an exemplary embodiment is depicted.

[0010] Figure 5 A second failure scenario for the power distribution line in the exemplary embodiment is depicted.

[0011] Figure 6 A block diagram of a fault detector in an exemplary embodiment is depicted.

[0012] Figure 7 A flow chart is depicted of a method of detecting a fault location in a tapped distribution line in an exemplary embodiment.

[0013] Figure 8 An electrical distribution network is depicted in an exemplary embodiment.

[0014] Unless otherwise specified, the drawings provided herein are intended to illustrate features of the embodiments of the present disclosure. These features are believed to be applicable to various systems including one or more embodiments of the present disclosure. As such, the drawings are not intended to include all conventional features known to those of ordinary skill in the art and required to practice the embodiments disclosed herein. DETAILED DESCRIPTION

[0015] In the following specification and claims, reference will be made to various terms which shall be defined to have the following meanings.

[0016] The singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise.

[0017] “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

[0018] Throughout the specification and claims, approximating language may be applied to modify any quantitative representation that may allow variation without causing a change in the basic function to which it is associated. Therefore, a value modified by one or more terms (such as "about", "approximately", and "substantially") is not limited to the precise value specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Here and throughout the specification and claims, range limitations may be combined and / or interchanged, and unless the context or language indicates otherwise, these ranges are defined and include all subranges contained therein.

[0019] As used herein, the terms "processor" and "computer" and related terms such as "processing device", "computing device" and "controller" are not limited to those integrated circuits known in the art as computers, but broadly refer to microcontrollers, microcomputers, analog computers, programmable logic controllers (PLCs), application specific integrated circuits (ASICs) and other programmable circuits, and these terms are used interchangeably herein. In the embodiments described herein, "memory" may include, but is not limited to, computer-readable media such as random access memory (RAM), computer-readable non-volatile media such as flash memory. Alternatively, floppy disks, compact disk-read only memory (CD-ROM), magneto-optical disks (MODs) and / or digital versatile disks (DVDs) may also be used. In addition, in the embodiments described herein, additional input channels may be, but are not limited to, computer peripherals associated with an operator interface, such as a touch screen, a mouse, and a keyboard. Alternatively, other computer peripherals may also be used, such as, but not limited to, a scanner. In addition, in example embodiments, additional output channels may include, but are not limited to, an operator interface monitor or a head-up display. Some embodiments involve the use of one or more electronic or computing devices. Such devices typically include a processor, a processing device, or a controller, such as a general-purpose central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, a reduced instruction set computer (RISC) processor, an ASIC, a programmable logic controller (PLC), a field programmable gate array (FPGA), a digital signal processing (DSP) device, and / or any other circuit or processing device capable of performing the functions described herein. The methods described herein may be encoded as executable instructions, which are embodied in a computer-readable medium, including but not limited to a storage device and / or a memory device. When a processing device executes such instructions, the processing device is caused to perform at least a portion of the methods described herein. The above examples are not intended to limit the definition and / or meaning of the terms processor and processing device in any way.

[0020] As briefly discussed above, different fault location techniques have been used previously to locate faults in electrical networks, including single-ended and double-ended impedance based methods.

[0021] Impedance-based methods are more commonly used in distribution systems due to their low cost and high accuracy. Impedance-based fault location techniques use basic phasor measurements of voltage and current at the ends of the distribution line and the parameters of the distribution line. However, the single-ended impedance method is subject to multiple estimation error sources and is not applicable to distribution systems with distributed generation or meshed distribution topologies.

[0022] The embodiments described herein provide a multi-terminal impedance system and a method in which synchronized measurements from two or more ends of a distribution line are identified. The main advantages of multi-terminal impedance-based methods are their robustness to fault resistance, zero-sequence impedance uncertainty, and system grounding, which are the main sources of inaccuracy in locating faults. The embodiments described herein are tailored for modern distribution systems with distributed generation resources and are applicable to radial and mesh / ring networks. The systems and methods described herein utilize knowledge of synchronized voltages and currents at two or more ends of a distribution line and the positive sequence impedance of the distribution line. In some embodiments, these measurements can be obtained from relays (or any other measuring device) at the terminals of the distribution line via time-stamped value capture that can be accurate to a few microseconds. The systems and methods described herein take into account the presence of tapped loads on the distribution line and the presence of distributed generation at the ends of the distribution line in order to accurately locate faults on the feeder.

[0023] Figure 1 A fault detector 102 for detecting a fault location in a distribution line 104 in an exemplary embodiment is depicted. In this embodiment, the distribution line 104 includes a first terminal 106, a second terminal 108, and a line segment 110 disposed between the first terminal 106 and the second terminal 108. In this embodiment, the first terminal 106 and the second terminal 108 are separated by a distance (L) 112, and a fault (F) 114 is located at a distance (D) 116 from the first terminal 106 and a distance (LD) 118 from the second terminal 108 in this embodiment. In this embodiment, the distribution line 104 includes relays 120, 122.

[0024] In this embodiment, the fault detector 102 measures, collects and / or communicates with the relays 120, 122 to identify the voltage phasor and the current phasor at the first terminal 106 and the second terminal 108. In some embodiments, the fault detector 102 directly measures the voltage phasor and / or the current phasor at the first terminal 106 and the second terminal 108. In other embodiments, the relays 120, 122 measure the voltage phasor and / or the current phasor at the terminals 106, 108, and the fault detector 102 communicates with the relays 120, 122 to identify the voltage phasor and the current phasor measured at the terminals 106, 108. In other embodiments, one or more voltage and current measurement systems and / or detection systems are implemented that measure and provide the relays 120, 122 and / or the fault detector 102 with the voltage phasor and the current phasor information at the terminals 106, 108. In this embodiment, the voltage phasor measured at the first terminal 106 includes V abc1 124, the voltage phasor measured at the second terminal 108 includes V abc2 126, the current phasor measured at the first terminal 106 includes I abc1 128, and the current phasor measured at the second terminal 108 includes I abc2 130. V abc1 124. V abc2 126.I abc1 128 and I abc2 130 may be time stamped and captured before and during the fault 114 to identify the synchronous voltage and current phasors at the terminals 106, 108. Typically, V abc =[V a V b V c ], where V a 、V b and V c is the measured phase voltage phasor. In other words, V abc is a matrix including all measured phase voltage phasors. Similarly, I abc =[I a I b I c ], where I a ,I b and I c is the measured phase current phasor. In other words, I abc is a matrix including all measured phase current phasors. This also applies to the V abc and I abc Variants (e.g., V abc1 、V abc2 ,I abc1 ,I abc2 ,Iabc1(comp) wait).

[0025] In some embodiments, line segment 110 includes one or more tapped loads ( Figure 1 Furthermore, the distribution line 104 may include power generation at one or more terminals 106 , 108 (eg, power generation at one or more terminals 106 , 108 ).

[0026] During operation, the fault detector 102 identifies synchronous voltage phasor and current phasor information at the terminals 106, 108 before and during the fault 114. For example, the fault detector 102 identifies V at the first terminal 106 before and during the fault 114. abc1 124、I abc1 128, and identifies the V at the second terminal 108 abc2 126 and I abc2 130. Then, the fault detector 102 calculates V abc1 124、I abc1 128. V abc2 126 and I abc2 130 equivalent sequence components, where the equivalent sequence components include V 0+-1 ,I 0+-1 、V 0+-2 ,I 0+-2 . (0, +, -) represent V abc1 124、I abc1 128. V abc2 126 and I abc2 130 zero-sequence, positive-sequence and negative-sequence components.

[0027] Then, the fault detector 102 determines whether the fault 114 is a symmetrical fault or an asymmetrical fault. For example, the fault detector 102 determines whether the fault 114 is a symmetrical fault or an asymmetrical fault based on the equivalent sequence component V 0+-1 ,I 0+-1 、V 0+-2 ,I 0+-2 To determine whether the fault is a symmetrical fault or an asymmetrical fault. A symmetrical fault may occur when all phases are affected so that the system remains balanced. For example, a three-phase fault is a symmetrical fault. Other types of faults (such as line-to-ground, line-to-line, and / or two-line-to-ground faults) include asymmetrical faults. Asymmetrical faults may also be referred to as asymmetrical or asymmetric faults.

[0028] Fault detector 102 can determine whether fault 114 is a symmetrical fault or an asymmetrical fault in a number of different ways. In one embodiment, fault detector compares positive sequence voltage V + and negative sequence voltage V -To determine whether the fault 114 is a symmetrical fault or an asymmetrical fault. For example, the fault detector 102 can detect the positive sequence voltage V at the first terminal 106 and / or the second terminal 108. + The corresponding and / or opposite negative sequence voltage V - is compared, and if V + >>V - , then the fault 114 is determined to be a symmetrical fault. For example, if V + V - Approximately one hundred times greater, then fault detector 102 may determine that fault 114 is a symmetrical fault.

[0029] If the fault detector 102 determines that the fault 114 is a symmetrical fault, the fault detector 102 may use the positive sequence component V +1 ,I +1 、V +2 ,I +2 Subsequent calculations are performed to locate fault 114 along line segment 110, where V +1 The positive sequence voltage at the first terminal 106, I +1 Including the positive sequence current at the first terminal 106, V +2 includes the positive sequence voltage at the second terminal 108, and I +2 The positive sequence current at the second terminal 108 is included.

[0030] Similarly, if the fault detector 102 determines that the fault 114 is an asymmetric fault, the fault detector 102 may use the negative sequence component V -1 ,I -1 、V -2 ,I -2 Various calculations are performed to locate fault 114 along line segment 110, where V -1 The negative sequence voltage at the first terminal 106, I -1 Including the negative sequence current at the first terminal 106, V -2 includes the negative sequence voltage at the second terminal 108, and I -2 A negative sequence current at the second terminal 108 is included.

[0031] While continuing to analyze to locate fault 114 , fault detector 102 calculates, identifies, and / or locates a virtual tapping point of distribution line 104 . Figure 2 A load profile 202 of distribution line 104 is depicted in an exemplary embodiment. Figure 2 In FIG. 1 , a virtual tap load point 204 divides a line segment 110 at a virtual load point on a distribution line 104 based on one or more tap loads 206. Figure 2Eight tap loads 206 are illustrated in FIG. 1 , but in other embodiments, the distribution circuit 104 may include more or fewer tap loads 206 .

[0032] The location of the virtual tap load point 204 along the line segment 110 is distributed based on the load along the line segment 110, and the virtual tap load point 204 moves left and right along the line segment 110 based on the weighted value of the load associated with the tap load 206. In this embodiment, the tap loads 206-1, 206-2, 206-3, 206-4 are depicted as 200 kilowatt (kw) loads, and the tap loads 206-5, 206-6, 206-7, 206-N are depicted as 50 kilowatt loads. However, in other embodiments, the tap loads 206 can have other load values.

[0033] In some embodiments, the location of the virtual tap load points 204 is calculated by the fault detector 102. For example, the fault detector 102 measures or identifies the load at each tapped load 206 and calculates the location of the virtual tap load points 204 based on the weights of the tapped loads 206 along the line segment 110. In other embodiments, a load flow program is used to identify the location of the virtual tap load points 204 and provide this information to the fault detector 102.

[0034] In this embodiment, the load distribution diagram 202 depicts a first equivalent power source 208 at the first terminal 106 and a second equivalent power source 210 at the second terminal 108, wherein the virtual tap load point 204 is set at a distance (L ) from the first terminal 106 and the first equivalent power source 208. V )218, and the distance (L R )220 places.

[0035] Figure 3 An equivalent load diagram 302 of the distribution line 104 in an exemplary embodiment is depicted. In this embodiment, the virtual tap load point 204 includes a first terminal 106 located at a distance (L V )218 and the distance (L R ) 220 1 MW dummy load 304. Distance (L V )218 and distance (L R ) 220 is distributed based on the weighting of the tap loads 206 along the distribution line 104 (see Figure 2 ), and the virtual load 304 is the sum of the tapped loads 206. However, in other embodiments, the location of the virtual tapped load point 204 relative to the terminals 106, 108 and the value of the virtual load 304 may be different depending on the distribution and load associated with the tapped loads 206.

[0036] Figure 4 A first fault scenario of the distribution line 104 in an exemplary embodiment is depicted. In this embodiment, the fault 114 is located between the virtual tap load point 204 and the second terminal 108. Specifically, the fault 114 is located at a distance (D 1 )402 and the distance (L R -D 1 ). In this scenario, the distance (L V )218 and the impedance of the line segment 110, and calculate the voltage (V abc,tap ) 406, and the fault detector 102 also calculates its equivalent symmetric component using the following equation:

[0037] V abc，tap =V abc1 -L V *Z abc *I abc1(pre-fault) (Equation 1),

[0038] Where V abc1 The voltage phasor V at the first terminal 106 during the fault 114 is included abc1 124,L v The distance (L V )218, Z abc The impedance of the line segment 110 included in the abc domain, and I abc1(pre-fault) The current phasor I at the first terminal 106 before the fault 114 is included abc1 128. Usually, Z abc =[Z a Z b Z c ], where Z a , Z b and Z c is the positive sequence impedance of each phase a, b and c of line segment 110. In other words, Z abc is a matrix comprising the positive sequence impedances of all phases of line section 110.

[0039] To calculate the compensating current (I abc1(comp) ), the fault detector uses the following equation:

[0040] I abc1(comp) =I abc1(fault) -(I abc1(pre-fault) +Iabc2(pre-fault) ) (Equation 2),

[0041] Among them I abc1(fault) The current phase I during the fault 114 is included abc1 128,I abc1(pre-fault) The current phase I before the fault 114 is included abc1 128, and I abc2(pre-fault) The current phase I before the fault 114 is included abc2 130.

[0042] In response to calculation I abc1(comp) , the fault detector 102 calculates I abc1(comp) The equivalent sequence component, that is, I 0+-1(comp) I 01(comp) isI abc1(comp) The zero sequence component, I +1(comp) isI abc1(comp) The positive sequence component, and I -1(comp) isI abc1(comp) The negative sequence component of .

[0043] At this point in the analysis of locating fault 114, fault detector 102 may perform different calculations depending on whether fault 114 is a symmetric fault or an asymmetric fault. If fault 114 is a symmetric fault, fault detector 102 may use the positive sequence component to calculate distance (D) using the following equation: 1 )402:

[0044] D 1 =V +，tap -V +2 +L R *Z+*I +2(fault) ) / (Z + *(I +1(comp) +I +2(fault ))), (Equation 3),

[0045] Where V +，tap Including V during fault 114 abc,tap 406 positive sequence voltage, V +2 The voltage phasor V at the second terminal 108 during the fault 114 is included abc2 The positive sequence of 126, L R The distance (L R )220,Z + includes the positive sequence impedance of line section 110, and I +2(fault) The current phase I at the second terminal 108 during the fault 114 is included abc2 130 in positive sequence.

[0046] However, if the fault 114 is an asymmetric fault, the fault detector 102 may use the negative sequence component to calculate the distance (D1) 402 using the following equation:

[0047] D 1 =(V -，tap -V -2 +L R *Z + *I -2(fault) ) / (Z + *I -1(comp) +I -2(fault) )), (Equation 4),

[0048] Where V -,tap Including V during fault 114 abc,tap Negative sequence voltage of 406, V -2 The voltage phasor V at the second terminal 108 during the fault 114 is included abc2 126 negative sequence, L R The distance (L R )220,Z + The positive sequence impedance of the line section 110, I -1(comp) Including I abc1(comp) The negative sequence component, I -2(fault) The current phase I at the second terminal 108 during the fault 114 is included abc2 130 negative sequence.

[0049] In response to calculating the distance (D 1 ) 402, the fault detector 102 is based on the distance (D 1 )402, distance (L V )218, distance (L R ) 220 and the distance (L) 112 positively identify the location of the fault 114 along the line segment 110.

[0050] Figure 5 A second fault scenario of the distribution line 104 in the exemplary embodiment is depicted. In this embodiment, the fault 114 is located between the virtual tap load point 204 and the first terminal 106. Specifically, the fault 114 is located at a distance (D 2 )502 and the distance (L V -D 2 )504. In the second scenario, the distance (L V) 218 ​​and the impedance of line segment 110, the voltage (V abc,tap )406:

[0051] V abctap =V abc2 -L R *Z abc *I abc2(pre-fault) (Equation 5),

[0052] Where V abc2 The voltage phasor V at the second terminal 108 during the fault 114 is included abc2 126,L R The distance (L R )220,Z abc The impedance of the line segment 110 included in the abc domain, and I abc2(pre-fault) The current phasor I at the second terminal 108 before the fault 114 is included abc2 130.

[0053] To calculate the compensation current (I abc2(comp) ), the compensation current compensates for the pre-fault load condition along the line segment 110, and the fault detector 102 uses the following equation:

[0054] I abc2(comp) =I abc2(fault) -(I abc1(pre-fault) +I abc2(pre-fault) ) (Equation 6),

[0055] Among them I abc2(fault) The current phase I at the second terminal 108 during the fault 114 is included abc2 130,I abc1(pre-fault) The current phasor I at the first terminal 106 before the fault 114 is included abc 1 128, and I abc2(pre-fault) The current phasor I at the second terminal 108 before the fault 114 is included abc2 130.

[0056] In response to calculation I abc2(comp) , the fault detector 102 calculates I abc2(comp) The equivalent sequence component, that is, I 0+-2(comp) I 02(comp) isI abc2(comp) The zero sequence component, I +2(comp) isI abc2(comp) The positive sequence component, and I -2(comp) isI abc2(comp)The negative sequence component of .

[0057] At this point in the analysis, the fault detector 102 may perform different calculations depending on whether the fault 114 is a symmetric fault or an asymmetric fault. If the fault 114 is a symmetric fault, the fault detector 102 may use the positive sequence component to calculate the distance (D) using the following equation 2 )402:

[0058] D 2 =(V +，tap- V +1 +L V *Z + *I +1(fauot) / (Z + *(I +1(fauot) +I +2(comp) )), (Equation 7),

[0059] Where V +，tap Including V during fault 114 abc,tap 406 positive sequence voltage, V +1 The voltage phasor V at the first terminal 106 during the fault 114 is included abc1 The positive sequence of 124, L V The distance (L v )218, Z + The positive sequence impedance of the line section 110, I +1(fault) The current phase I at the first terminal 106 during the fault 114 is included abc1 128 in positive order, and I +2(comp) isI abc2(comp) The positive sequence component of .

[0060] However, if the fault 114 is an asymmetric fault, the fault detector 102 may use the negative sequence component to calculate the distance (D 2 )502:

[0061] D 2 =(V -，tap -V -1 +L V *Z + *I -1(fault) ) / (Z + *(I -1(fault) +I -2(comp) )), (Equation 8),

[0062] Where V -,tap Including V during fault 114 abc,tap Negative sequence voltage of 406, V -1The voltage phasor V at the first terminal 106 during the fault 114 is included abc1 124 negative sequence, L V The distance (L v )218, Z + Includes the positive sequence impedance of the line section, I -1(fault) The current phase I at the first terminal 106 during the fault 114 is included abc1 128 negative sequence, and I -2(comp) Including I abc2(comp) The negative sequence component of .

[0063] In response to calculating the distance (D 2 ) 502, the fault detector 102 is based on the distance (D 2 )502, distance (L V )218, distance (L R ) 220 and the distance (L) 112 positively identify the location of the fault 114 along the line segment 110.

[0064] In some embodiments, the fault detector 102 uses one or more criteria to determine whether to use the distance (D 1 )402 and / or distance (D 2 ) 502 to find the location of the fault 114. For example, if the distance (D 1 )402>zero, then the fault detector 102 can determine that the fault 114 is located at a distance (L V )218+Distance(D 1 )402 (see Figure 4 ). If the distance (D 2 )502>zero, then the fault detector 102 can determine that the fault 114 is located at a distance (L V )218-Distance(D 2 )502 (see Figure 5 ).

[0065] Figure 6A block diagram of the fault detector 102 in an exemplary embodiment is depicted. In this embodiment, the fault detector 102 includes at least one processor 602, at least one communication interface 604, at least one memory 606, and one or more sensors 608. The memory 606 may store, for example, programming instructions that, when executed by the processor 602, direct the fault detector 102 to perform any of the functions previously described herein for the fault detector 102. Some examples of the communication interface 604 include a serial interface, a parallel interface, a Wi-Fi interface, a cellular network interface, and the like.

[0066] In some embodiments, when the relays 120, 122 measure V at the first terminal 106 abc1 124 and I abc1 128 and measuring V at the second terminal 108 abc2 126 and I abc2 130, the fault detector 102 can be communicatively coupled to the relays 120, 122 via the communication interface 604. In other embodiments, the fault detector 102 can be communicatively coupled to one or more measurement systems (not shown) via the communication interface 604, and the one or more measurement systems measure V at the first terminal 106. abc1 124 and I abc1 128, and also measure V at the second terminal 108 abc2 126 and I abc2 130.

[0067] In some embodiments, the fault detector 102 uses the sensor 608 to measure V at the first terminal 106. abc1 124 and I abc1 128, and measuring V at the second terminal 108 abc2 126 and I abc2 130. However, in other embodiments, the fault detector 102 may utilize a combination of sensors 608 to obtain the V at the first terminal 106. abc1 124 and I abc1 128 and obtain V at the second terminal 108 abc2 126 and I abc2 130, and / or may communicate with relays 120, 122 and / or an external measurement system via communication interface 604 to obtain V at first terminal 106. abc1 124 and I abc1 128 and obtain V at the second terminal 108 abc2 126 and I abc2 130.

[0068] Figure 7A flow chart of a method 700 for detecting the location of a fault in a tapped distribution line in an exemplary embodiment is depicted. The distribution line has a first terminal and a second terminal and a line segment disposed between the first terminal and the second terminal. The method 700 will be related to the fault detector 102 and Figure 1-Figure 6 700 is discussed, although the method 700 may be performed by other systems not shown.

[0069] In this embodiment, the method 700 includes identifying 702 synchronous voltage phasors and current phasors at the first terminal and the second terminal before and during a fault. In one example, the processor 602 measures V at the first terminal 106 using the sensor 608. abc1 124 and I abc1 128 and measure V at the second terminal 108 abc2 126 and I abc2 130 (see Figure 1 and Figure 6 In another example, the processor 602 obtains the V at the first terminal 106 from, for example, the relays 120, 122 and / or an external measurement system using the communication interface 604. abc1 124 and I abc1 128 and measure V at the second terminal 108 abc2 126 and I abc2 130.

[0070] Method 700 also includes calculating 704 equivalent sequence components for the voltage phasor and the current phasor. For example, processor 602 calculates V before and during a fault. abc1 124、I abc1 128. V abc2 126 and I abc2 The equivalent sequence components of 130 are (0,+,-).

[0071] The method 700 also includes locating 706 a virtual tap point on the line segment. For example, the processor 602 locates the virtual tap load point 204 (see Figure 2-Figure 5 For example, processor 602 may use information about tapped load 206 to calculate virtual tapped load point 204 (see Figure 2 In another example, the processor 602 communicates with an external system (eg, via the communication interface 604 ) to identify information about the virtual tap load point 204 and / or the tapped load 206 .

[0072] The method 700 also includes calculating 708 a voltage at the virtual tap load point based on one or more of the current phasors before the fault. For example, the processor 602 calculates the V of the virtual tap load point 204 using Equation 1 and / or Equation 5. abc,tap .

[0073] The method 700 further includes calculating 710 a compensating load current at the first terminal and / or the second terminal based on one or more of the current phasors before and / or after the fault. For example, the processor 602 calculates the compensating load current using Equation 2 and / or Equation 6.

[0074] Method 700 also includes determining 712 whether the fault is a symmetrical fault or an asymmetrical fault based on the equivalent sequence component. For example, processor 602 determines whether fault 114 is a symmetrical fault or an asymmetrical fault by, for example, comparing positive sequence voltage and negative sequence voltage at terminal 106 and / or terminal 108 .

[0075] If the fault is symmetrical, the method 700 further includes calculating 714 a distance from the virtual tap load point to the fault using the positive sequence component. For example, the processor 602 calculates the distance using Equation 3 and / or Equation 7.

[0076] However, if the fault is asymmetric, then the method 700 further includes calculating 716 the distance from the virtual tap load point to the fault using the negative sequence component. For example, the processor 602 calculates the distance using Equation 4 and / or Equation 8.

[0077] Figure 8 A distribution network 800 in an exemplary embodiment is depicted. In this embodiment, the distribution network 800 includes a plurality of busbars 801-834 powered by a power source 836, and the distribution network 800 has interconnection points at busbars 803, busbars 806, busbars 807, and busbars 810. Although locating faults in the distribution network 800 may be difficult using prior art techniques, fault location in the distribution network 800 is improved using the embodiments described herein by subdividing the distribution network 800 into segments of point-to-point protection zones. In one embodiment, a central controller and / or relay (such as an SSC600 or REX640 from ABB) may be used to obtain information from two of the busbars 801-834 at both ends of the protection zone. Although it may be challenging to assess faults in the distribution network 800 using only data on busbars 801 and busbars 812, a more accurate fault location detection scheme is described below for each zone.

[0078] Area 1: bus 801 to bus 806, SMVRECEIVE1: bus 801, SMVRECEIVE2: bus 806.

[0079] Area 2: bus 807 to bus 812, SMVRECEIVE3: bus 807, SMVRECEIVE4: bus 812.

[0080] Region 3: bus 813 to bus 816, SMVRECEIVE5: bus 813, SMVRECEIVE6: bus 816.

[0081] Area 4: bus 817 to bus 827, SMVRECEIVE7: bus 813, SMVRECEIVE8: bus 827.

[0082] Area 5: bus 831 to bus 834, SMVRECEIVE9: bus 831, SMVRECEIVE10: bus 834.

[0083] By utilizing the advanced group settings, the sample measurement value ID (SMV-ID) of each bus 801-834 can be identified, and the busbars 801-834 of the distribution network 800 can be divided into smaller zones. In this format, up to five zones can be formed, each with two unique SMV-IDs, and segmented line lengths for each zone. A central controller such as the SCC600 can automatically identify the fault zone when triggered and assign the correct SMV streams to the three-phase voltage and current inputs of this function block. If the controller does not have the ability to identify the fault segment, then in another embodiment, the previously described fault location calculation can be iteratively applied, once per zone, in order to identify the fault segments with D 1 or D 2 If the fault is outside the segment being analyzed, inherent in these calculations is D 1 or D 2 The overshoot of , makes the detection fault limited to the area currently being evaluated. Since only the active fault area is isolated and participates in the calculation, this technology minimizes demand interruption and enhances the reliability of the distribution network 800 during the fault.

[0084] These types of calculations are also suitable for doubly-fed distribution systems where two of the busbars 801-834 at either end of the protection zone are supplying power. Measurements between any two of the busbars 801-834 with only loads will result in more accurate calculations within the protection zone compared to single-ended algorithms. When a source is SMV-tagged, protection functions can be applied to divide the distribution network 800 into point-to-point zones, with only active fault zones participating in the calculations.

[0085] The embodiments described herein provide a robust fault location mechanism that utilizes synchronized voltage and current phasor information at the end of a distribution line and virtual tap load point information to quickly and reliably locate faults.

[0086] Example technical effects of the embodiments described herein include at least one of the following: (a) the fault location mechanism described herein is applicable to different types of faults without knowing the zero-sequence impedance of the distribution line and other uncertain parameters; (b) the fault location mechanism described herein is applicable to distribution systems with tapped loads without knowing the physical location of the tapped loads; (c) the fault location mechanism described herein is applicable to radial, mesh and ring networks and different grounding configurations; and (d) the fault location mechanism described herein utilizes synchronization technology that is increasingly common in distribution systems, where the time-stamped voltage and current phasors are accurate to a few microseconds.

[0087] Although specific features of various embodiments of the present disclosure may be shown in some drawings and not in other drawings, this is for convenience only. According to the principles of the present disclosure, any feature in the drawings may be combined with any feature in any other drawings for reference and / or protection.

[0088] This written description uses examples to disclose embodiments, including the best mode, and also to enable those skilled in the art to practice the embodiments, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to fall within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements that do not differ substantially from the literal language of the claims.

Claims

1. A fault detector for detecting the location of a fault in a tapped distribution line, the tapped distribution line having a first terminal, a second terminal and a line section arranged between the first terminal and the second terminal, the fault detector comprising: at least one processor, the at least one processor being configured to: identifying synchronized voltage phasors and current phasors at the first terminal and the second terminal before and during the fault; calculating equivalent sequence components for the voltage phasor and the current phasor; a virtual tap load point located on the line segment; calculating a voltage at the virtual tapped load point based on one or more of the current phasors prior to the fault; calculating a compensating load current at the first terminal and / or the second terminal based on one or more of the current phasors before the fault and / or after the fault; as well as The distance from the virtual tap load point to the fault is calculated based on the voltage at the virtual tap load point, the compensated load current, and one or more equivalent sequence components of the equivalent sequence components to detect the location of the fault.

2. The fault detector according to claim 1, wherein: The at least one processor is further configured to: determining whether the fault comprises a symmetrical fault or an asymmetrical fault based on the equivalent sequence component; In response to determining that the fault includes the symmetric fault, calculating the distance using a positive sequence component in the equivalent sequence component; as well as In response to determining that the fault includes the asymmetric fault, the distance is calculated using a negative sequence component of the equivalent sequence components.

3. The fault detector according to claim 2, wherein: The fault is located between the virtual tap load point and the second terminal at a distance D1 from the virtual tap load point, The voltage at the virtual tap load point includes V abc，tap , V abc，tap =V abc1 -L v *Z abc *I abc1(pre-fault) ,as well as V abc1 comprising the voltage phasor identified at the first terminal during the fault, L v The distance between the first terminal and the virtual tap load point, Z abc The impedance of the line segment included in the abc domain, and I abc1(pre-fault) The current phasor identified at the first terminal prior to the fault is included.

4. The fault detector according to claim 3, wherein: The compensation load current includes I abc1(comp) , I abc1(comp) =I abc1(fault) -(I abc1(pre-fault) +I abc2(pre-fault) ),as well as I abc1(fault) comprising the current phasor identified at the first terminal during the fault, I abc1(pre-fault) includes the current phasor identified at the first terminal before the fault, and I abc2(pre-fault) The current phasor identified at the second terminal prior to the fault is included.

5. The fault detector according to claim 4, wherein: The fault includes the symmetric fault, D1=(V +，tap -V +2 +L R *Z + *I +2(fault) ) / (Z + *(I +1(comp) +I +2(fault) )),as well as V +,tap Included in the fault period V abc,tap Positive sequence voltage, V +2 comprising a positive sequence voltage of said voltage phasor identified at said second terminal during said fault, L R The distance between the second terminal and the virtual tap load point, Z + includes the positive sequence impedance of the line section, I +2(fault) comprises a positive sequence current of the current phasor identified at the second terminal during the fault, and I +1(comp) Including I abc1(comp) The equivalent positive sequence current.

6. The fault detector according to claim 4, wherein: The fault includes the asymmetric fault, and D1=(V -，tap -V -2 +L R *Z + *I -2(fault) ) / (Z + *(I -1(comp) +I -2(fault) ),as well as V -,tap Included in the fault period V abc,tap Negative sequence voltage, V -2 comprising a negative sequence voltage of said voltage phasor identified at said second terminal during said fault, L R The distance between the second terminal and the virtual tap load point, Z + includes the positive sequence impedance of the line section, I -2(fault) comprises a negative sequence current of the current phasor identified at the second terminal during the fault, and I -1(comp) Including I abc1(comp) The equivalent negative sequence current.

7. The fault detector according to claim 2, wherein: The fault is located between the virtual tap load point and the first terminal at a distance D2 from the virtual tap load point, The voltage at the virtual tap load point includes V abc,tap , V abc，tap =V abc2 -L r *Z abc *I abc2(pre-fault) ,as well as V abc2 comprises the voltage phasor identified at the second terminal during the fault, Lr comprises the distance between the second terminal and the virtual tap load point, Z abc The impedance of the line segment included in the abc domain, and I abc2(pre-fault) The current phasor identified at the second terminal prior to the fault is included.

8. The fault detector according to claim 7, wherein: The compensation load current includes I abc2(comp) , I abc2(comp) =I abc2(fault) -(I abc1(pre-fault) +I abc2(pre-fault) ),as well as I abc2(fault) comprising the current phasor identified at the second terminal during the fault, I abc1(pre-fault) includes the current phasor identified at the first terminal before the fault, and I abc2(pre-fault) The current phasor identified at the second terminal prior to the fault is included.

9. The fault detector according to claim 8, wherein: The fault includes the symmetrical fault, and D2=(V +，tap -V +1 +L v *Z + *I +1(fault) ) / (Z + *(I +1(fault) +I +2(comp) ),as well as V +,tap Included in the fault period V abc,tap Positive sequence voltage, V +1(fault) comprising a positive sequence voltage of said voltage phasor identified at said first terminal during said fault, L v The distance between the first terminal and the virtual tap load point, Z + includes the positive sequence impedance of the line section, I +1(fault) comprises a positive sequence current of the current phasor identified at the first terminal during the fault, and I +2(comp) Including I abc2(comp) The equivalent positive sequence current.

10. The fault detector according to claim 8, wherein: The fault includes the asymmetric fault, D2=(V -，tap -V -1 +L v *Z + *I -1(fault) ) / (Z + *(I -1(fault) +I -2(comp) ),as well as V -,tap Included in the fault period V abc,tap Negative sequence voltage, V -1(fault) comprising a negative sequence voltage, L, of said voltage phasor identified at said first terminal during said fault v The distance between the first terminal and the virtual tap load point, Z + includes the positive sequence impedance of the line section, I -1(fault) comprises a negative sequence current of the current phasor identified at the first terminal during the fault, and I -2(comp) Including I abc2(comp) The equivalent negative sequence current.

11. A method of detecting a location of a fault in a tapped distribution line, the tapped distribution line having a first terminal, a second terminal, and a line segment disposed between the first terminal and the second terminal, the method comprising: identifying synchronized voltage phasors and current phasors at the first terminal and the second terminal before and during the fault; calculating equivalent sequence components for the voltage phasor and the current phasor; a virtual tap load point located on the line segment; calculating a voltage at the virtual tapped load point based on one or more of the current phasors prior to the fault; calculating a compensating load current at the first terminal and / or the second terminal based on one or more of the current phasors before the fault and / or after the fault; as well as The distance from the virtual tap load point to the fault is calculated based on the voltage at the virtual tap load point, the compensated load current, and one or more equivalent sequence components of the equivalent sequence components to detect the location of the fault.

12. The method according to claim 11, further comprising: determining whether the fault comprises a symmetrical fault or an asymmetrical fault based on the equivalent sequence component; In response to determining that the fault includes the symmetric fault, calculating the distance using a positive sequence component in the equivalent sequence component; as well as In response to determining that the fault includes the asymmetric fault, the distance is calculated using a negative sequence component of the equivalent sequence components.

13. The method according to claim 12, wherein: The fault is located between the virtual tap load point and the second terminal at a distance D1 from the virtual tap load point, The voltage at the virtual tap load point includes V abc，tap , V abc，tap =V abc1 -L v *Z abc *I abc1(pre-fault) , V abc1 comprising the voltage phasor identified at the first terminal during the fault, L v The distance between the first terminal and the virtual tap load point, Z abc The impedance of the line segment included in the abc domain, and I abc1(pre-fault) comprising said current phasor identified at said first terminal prior to said fault, The compensation load current includes I abc1(comp) , I abc1(comp) =I abc1(fault) -(I abc1(pre-fault) +I abc2(pre-fault) ),as well as I abc1(fault) comprising the current phasor identified at the first terminal during the fault, I abc1(pre-fault) includes the current phasor identified at the first terminal before the fault, and I abc2(pre-fault) The current phasor identified at the second terminal prior to the fault is included.

14. The method according to claim 13, wherein: The fault includes the symmetric fault, D1=(V +，tap -V +2 +L R *Z + *I +2(fault) ) / (Z + *(I +1(comp) +I +2(fault) )), as well as V +,tap Included in the fault period V abc,tap Positive sequence voltage, V +2 comprising a positive sequence voltage of said voltage phasor identified at said second terminal during said fault, L R The distance between the second terminal and the virtual tap load point, Z + includes the positive sequence impedance of the line section, I +2(fault) comprises a positive sequence current of the current phasor identified at the second terminal during the fault, and I +1(comp) Including I abc1(comp) The equivalent positive sequence current.

15. The method of claim 13, wherein: The fault includes the asymmetric fault, and D1=(V -，tap -V -2 +L R *Z + *I -2(fault) ) / (Z + *(I -1(comp) +I -2(fault) ),as well as V -,tap Included in the fault period V abc,tap Negative sequence voltage, V -2 comprising a negative sequence voltage of said voltage phasor identified at said second terminal during said fault, L R The distance between the second terminal and the virtual tap load point, Z + includes the positive sequence impedance of the line section, I -2(fault) comprises a negative sequence current of the current phasor identified at the second terminal during the fault, and I -1(comp) Including I abc1(comp) The equivalent negative sequence current.

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