General test sampling circuit for high-speed serial IO interface receiving end

Abstract

The invention provides a general test sampling circuit for a high-speed serial IO interface receiving end. Comprising a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator and an RX test bias circuit for providing reference voltage and bias voltage for the two RX test sampling circuits and the two comparators, the general test sampling circuit can test and sample each of two differential signal paths of a receiving end of a high-speed serial IO interface, and judges whether short circuit and open circuit exist in a PCB, a pressure welding point and IO according to received signals. The universal test sampling circuit provided by the invention is suitable for a differential receiving end in a high-speed data transmission rate serial interface (above 10G Baud rate), can respectively work in a direct current mode and an alternating current mode through a mode selection signal, and can sample a direct current signal and an alternating current signal.

Description

Technical Field

[0001] The invention belongs to the technical field of interface test sampling and relates to a universal test sampling circuit for a high-speed serial IO interface receiving end. Background Art

[0002] Figure 1 A PCB circuit board containing multiple chips is shown. With the rapid development of VLSI manufacturing technology, today's electronic system boards contain many high-density devices, and the spacing between devices is getting smaller and smaller. Traditional probe-based contact testing methods cannot be performed, so many devices now contain boundary scan test circuits to perform manufacturing tests, detect and diagnose faults such as disconnected solder joints, short circuits and missing devices.

[0003] As an emerging advanced information transmission I / O technology, high-speed serial IO interface uses various termination resistors and capacitors in the signal transmission path to avoid signal integrity problems such as reflection caused by high-speed signals. This will make the transmission wire no longer be simply regarded as a small resistance model, but form a new type of transmission line network model. The problem is that the traditional boundary scan test circuit cannot cope with the AC signal. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art and provide a universal test sampling circuit for a high-speed serial IO interface receiving end, which can perform test sampling on each of the two differential signal paths of the high-speed serial IO interface receiving end.

[0005] The technical solution of the present invention is:

[0006] The present invention discloses a universal test sampling circuit for a high-speed serial IO interface receiving end, comprising a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator and an RX test bias circuit for providing a reference voltage and a bias voltage for the two test sampling circuits and the two comparators: wherein,

[0007] The input end of the first low-pass filter is connected to the RXP of the high-speed serial IO interface receiving end, and the output end is connected to the first data input end rx of the first RX test sampling circuit, so as to filter the peak noise on the RXP signal line;

[0008] The input end of the second low-pass filter is connected to the RXN of the high-speed serial IO interface receiving end, and the output end is connected to the first data input end rx of the second RX test sampling circuit, so as to filter the peak noise on the RXN signal line;

[0009] The second data input terminal feedback of the first RX test sampling circuit is connected to the second output terminal feedback of the first comparator, the first data output terminal outp of the first RX test sampling circuit is connected to the inp input terminal of the first comparator, and the second data output terminal outn of the first RX test sampling circuit is connected to the inn input terminal of the first comparator; the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit;

[0010] The second data input terminal feedback of the second RX test sampling circuit is connected to the second output terminal feedback of the second comparator, the first data output terminal outp of the second RX test sampling circuit is connected to the inp input terminal of the second comparator, and the second data output terminal outn of the second RX test sampling circuit is connected to the inn input terminal of the second comparator; the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit;

[0011] The first control signal input terminal mode and the second control signal input terminal test_init of the first RX test sampling circuit and the second RX test sampling circuit are both connected to the mode selection signal mode and the test initialization signal test_init generated by the external digital control logic;

[0012] The first comparator, as a high-gain operational amplifier, is used to compare the magnitudes of the first data input terminal inp and the second data input terminal inn, which are marked as positive and negative poles respectively, and generate an output signal with a large swing. The bias voltage input terminal nbias of the first comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit. The first data output terminal OUTP of the first comparator is sent to the subsequent digital logic as the output value after comparison for analysis and processing;

[0013] The second comparator has the same internal structure as the first comparator circuit; the bias voltage input terminal nbias of the second comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit; the first data output terminal OUTN of the second comparator is sent to the subsequent digital logic for analysis and processing as the compared output value.

[0014] Furthermore, in the above sampling circuit,

[0015] The internal circuit structure of the second RX test sampling circuit is consistent with that of the first RX test sampling circuit;

[0016] The internal circuit structure of the first comparator is consistent with that of the second comparator.

[0017] Furthermore, in the above sampling circuit,

[0018] The RX test bias circuit is turned on or off under the control of a test enable signal test_en generated by an external digital control logic, receives a stable current source iref_test provided by an external power supply bias circuit, generates four stable voltage biases Vrm, Vdc, Vrp and Vbias and provides them to the first RX test sampling circuit and the second RX test sampling circuit and the first comparator and the second comparator.

[0019] Furthermore, in the above sampling circuit, under the control of the mode selection signal mode, it can work in two test modes: when mode=1, it works in AC mode and samples AC signals; when mode=0, it works in DC mode and samples DC signals.

[0020] Further, in the above sampling circuit, the first RX test sampling circuit includes: a first capacitor C1, a P-type transistor M1, a second capacitor C2, a first resistor R1, an N-type transistor M2, a P-type transistor M3, an inverter I1, a P-type transistor M4, a P-type transistor M5, a P-type transistor M6, a second resistor R2, an N-type transistor M7, an N-type transistor M8 and an N-type transistor M9; wherein,

[0021] The first data input terminal rx is connected to one end of the first capacitor C1 and is also connected to the gate of the P-type transistor M1; the drain of the transistor M1 is connected to the ground level VS, the source of the transistor M1 is connected to the other end of the first capacitor C1, and is also connected to the input of the second capacitor C2 and the input of the first resistor R1; the output of the first resistor R1 is connected to the stable current source iref_test provided by the external power bias circuit, and this connection point is denoted as Vif; the output of the second capacitor C2 is connected to the first data output terminal outp; the drain of the transistor M2 and the source of the transistor M3 are connected to the connection point Vif; the source of the transistor M2 and the drain of the transistor M3 are connected to the first data output terminal outp; the first control signal input terminal mode is connected to the input of the inverter I1, and the output signal of the inverter I1 is denoted as mode_N; the gate of the transistor M3 is connected to the first control signal input terminal mode, and the gate of the transistor M2 is connected to the inverter The output terminal mode_N of the inverter I1 is connected to the output terminal mode_N of the inverter I1; the gate of the transistor M4 is connected to the gate of the transistor M5 and the gate of the transistor M6, and is connected to the output terminal mode_N of the inverter I1; the source terminal of the transistor M4 is connected to the input terminal of the second resistor R2, and the connection point is recorded as vnod2, the drain terminal of the transistor M4 is connected to the source terminal of the transistor M5, the drain terminal of the transistor M5 is connected to the source terminal of the transistor M6, and the drain terminal of the transistor M6 is connected to the second bias voltage input terminal Vdc; the gate of the transistor M7 is connected to the gate of the transistor M8 and the gate of the transistor M9, and is connected to the first control signal input terminal mode, and the drain terminal of the transistor M7 is connected to the connection point vnod2; the source terminal of the transistor M7 is connected to the drain terminal of the transistor M8, the source terminal of the transistor M8 is connected to the drain terminal of the transistor M9, the source terminal of the transistor M9 is connected to the second bias voltage input terminal Vdc, and the output terminal of the second resistor R2 is connected to the first data output terminal outp;

[0022] Furthermore, in the above sampling circuit, the first RX test sampling circuit further includes a high-level effective latch LAT1, a second inverter I2, a P-type transistor M10 and a P-type transistor M11; wherein the latch LAT1 includes a first data input terminal D, a first clock input terminal CP, a first high-level setting terminal CD and a first data output terminal Q; the first data input terminal D of the latch LAT1 is connected to the second data input terminal feedback of the first RX test sampling circuit, the first clock input terminal CP of the latch LAT1 is connected to the first control signal input terminal mode, and the first The high level set terminal CD is connected to the second control signal input terminal test_init, the first data output terminal Q of the latch LAT1 is connected to the input terminal of the second inverter I2, and this connection point is recorded as sel. The output terminal of the second inverter I2 is connected to the gate of the P-type transistor M10, and the connection point is recorded as sel_N; the source terminal of the transistor M10 is connected to the first bias voltage input terminal Vrm, the source terminal of the transistor M11 is connected to the first bias voltage input terminal Vrp, the gate of the transistor M11 is connected to the connection point sel, and the drain terminal of the transistor M10 and the drain terminal of the transistor M11 are connected to the second data output terminal outn.

[0023] Further, in the above sampling circuit, the first comparator includes an N-type transistor M101, an N-type transistor M102, an N-type transistor M103, an N-type transistor M104, a P-type transistor M105, a P-type transistor M106, a P-type transistor M107, an inverter INV1, an inverter INV2, and an inverter INV3; wherein the first data input terminal inp is connected to the gate of the N-type transistor M104 as the positive input of the comparator, and the second data input terminal inn is connected to the gate of the N-type transistor M103 as the negative input of the comparator; the source terminal of the transistor M103 and the source terminal of M104 are connected to the drain terminal of the N-type transistor M101; the gate of the transistor M101 is connected to the bias voltage input terminal nbias, and the source terminal of the transistor M101 is connected to the ground VS; the The source terminal and the source terminal of transistor M106 are connected to the power supply VP, the drain terminal and the gate terminal of transistor M105 are connected to the drain terminal of transistor M103 and the gate terminal of transistor M106; the drain terminal of transistor M106 is connected to the drain terminal of transistor M104 and the gate terminal of P-type transistor M107; the source terminal of transistor M107 is connected to the power supply VP, the drain terminal of transistor M107 is connected to the drain terminal of transistor M102 and the input terminal of inverter INV1; the gate terminal of transistor M102 is connected to the bias voltage input terminal nbias, the source terminal of transistor M102 is connected to the ground VS, the output terminal of inverter INV1 is connected to the input terminals of inverter INV2 and inverter INV3, the output terminal of inverter INV2 is connected to the first data output terminal out, and the output terminal of inverter INV3 is connected to the second data output terminal feedback.

[0024] Further, in the above sampling circuit, the RX test bias circuit includes a P-type transistor M204, a resistor R203, a resistor R202, a P-type transistor M201, an N-type transistor M202, an N-type transistor M203 and a resistor R201; wherein the gate and drain of the transistor M204 are connected to the ground VS, the source of the transistor M204 is connected to the output of the resistor R203 as a first bias voltage output terminal Vrm; the input of the resistor R203 is connected to the output of the resistor R202 as a second bias voltage output terminal Vdc, and the input of the resistor R202 receives a stable current source iref_test provided by an external power supply bias circuit , the potential generated here serves as the third bias voltage output terminal Vrp; the source terminal of the transistor M201 is connected to the power supply VP, and the gate of the transistor M201 is connected to the test enable signal test_en generated by the external digital control logic; the drain terminal of the transistor M201 is connected to the input terminal of the resistor R201, and the output terminal of the resistor R201 is connected to the drain terminal and the gate of the transistor M202, serving as the fourth bias voltage output terminal Vbias; the source terminal of the transistor M202 is connected to the ground VS; the gate of the transistor M203 is connected to the test enable signal test_en generated by the external digital control logic, the source terminal of the transistor M203 is connected to the ground VS, and the drain terminal of the transistor M203 is connected to the fourth bias voltage output terminal Vbias.

[0025] Further, in the above-mentioned sampling circuit, when the first high-level set terminal CD of the high-level valid latch LAT1 is at a low potential and the first clock input terminal CP is at a high potential, the output of the first data output terminal Q is consistent with the first data input terminal D, when the first high-level set terminal CD is at a low potential and the first clock input terminal CP is at a low potential, the output of the first data output terminal Q maintains the previous valid value, and when the first high-level set terminal CD is high, the first data output terminal Q is at a high potential.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] (1) The present invention provides a universal test sampling circuit for a high-speed serial IO interface receiving end, which is applied to the high-speed serial IO interface to test and sample the signal at the high-speed serial IO interface receiving end. The sampling value is transmitted to the boundary scan logic in the chip. After logic analysis, various conduction defects that may be introduced during the PCB circuit board manufacturing, chip electrical assembly and packaging processes can be detected and diagnosed;

[0028] (2) The universal test sampling circuit of the present invention can improve the effectiveness of the differential input terminal test by adding a test sampling and comparator circuit to perform independent test sampling on each of the two differential signal paths of the high-speed serial IO interface receiving end, thereby avoiding some of its unique manufacturing defects from being concealed;

[0029] (3) The universal test sampling circuit of the present invention can sample the effective transition edge of the AC signal through the high-frequency signal characteristics of the capacitor in the RX test sampling circuit, thereby solving the problem that the traditional boundary scan test circuit cannot test the AC signal in the high-speed serial IO;

[0030] (4) The universal test sampling circuit of the present invention can simultaneously meet the two working modes of DC test and AC test by introducing a sampling mode selection signal, and has wide applicability. When both DC test and AC test are performed, the test throughput rate is improved;

[0031] (5) The universal test sampling circuit of the present invention adopts a feedback mechanism in the AC test mode, and selects the reference voltage of the comparator to be higher or lower according to the sampling logic value currently output by the comparator, which ingeniously simplifies the design of the comparator;

[0032] (6) The present invention can test and sample each of the two differential signal paths at the receiving end of the high-speed serial IO interface, and can work in the DC mode and the AC mode respectively through the mode selection signal, and can sample both the DC signal and the AC signal, analyze the sampled received signal, and diagnose the conduction condition of the PCB circuit board, the pad and the IO;

[0033] (7) The present invention provides a universal test sampling circuit for a high-speed serial IO interface, which can work in a DC mode and an AC mode respectively according to different input control signal settings. The circuit can sample both DC signals and AC signals, solving the problem that the traditional boundary scan test circuit cannot test AC signals in the high-speed serial IO interface. In addition, the circuit performs test sampling on each of the two differential signal paths at the receiving end of the high-speed serial IO interface respectively. This can easily, accurately and completely solve the problem of detecting and diagnosing various conduction defects that may be introduced into the chips of the high-speed serial IO interface that use differential and AC forms for signal transmission during the PCB circuit board manufacturing, chip electrical assembly and packaging processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a simple schematic diagram of a PCB circuit board containing multiple chips;

[0035] Figure 2 A structural diagram of a universal test sampling circuit for a high-speed serial IO interface receiving end of the present invention;

[0036] Figure 3 Schematic diagram of the RX test sampling circuit of the present invention; (a) is a schematic diagram of the received data sampling path, and (b) is a schematic diagram of the received data sampling reference voltage selection path;

[0037] Figure 4 is a schematic diagram of a comparator in the present invention;

[0038] Figure 5 This is a schematic diagram of the RX test bias circuit of the present invention;

[0039] Figure 6 It is a simulation waveform diagram of the present invention in the AC working mode;

[0040] Figure 7 This is a simulation waveform diagram of the present invention under the DC working mode. DETAILED DESCRIPTION

[0041] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0042] The technical solution of the present invention is: a universal test sampling circuit for a high-speed serial IO interface receiving end, comprising a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit that provides reference voltage and bias voltage for the two test sampling circuits and the two comparators. The first low-pass filter is the most common RC low-pass filter, composed of a resistor and a capacitor, and is mainly used to filter the spike noise on the RXP signal line; the second low-pass filter, whose internal composition is the same as that of the first low-pass filter, is mainly used to filter the spike noise on the RXN signal line;

[0043] The first data input terminal rx of the first RX test sampling circuit receives the input signal after the spike noise is filtered by the first low-pass filter, and completes the sampling of the input DC or AC signal according to the different first control signal input terminals mode, and the sampling result is reflected as the second data output terminal outp, which is further sent to the positive input terminal inp of the first comparator. The second data input terminal feedback of the first RX test sampling circuit is connected to the second data output terminal feedback of the first comparator, and is selected from its first bias voltage input terminal Vrm and the third bias voltage input terminal Vrp according to the current comparator output result, and is transmitted to the second data output terminal outn through a P-type transistor for lossless transmission of high level, and is further sent to the negative input terminal inn of the first comparator. The first comparator compares and amplifies the small swing signals of the two input terminals, and the output OUTP signal swings between the power supply and the ground, completing the process of sampling the AC signal at the RXP terminal and converting it into a digital logic signal;

[0044] The second RX test sampling circuit and the second comparator have the same working principle as the above second RX test sampling circuit and the second comparator, and complete the process of sampling the AC signal at the RXN terminal and converting it into a digital logic signal.

[0045] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0046] A universal test sampling circuit for a high-speed serial IO interface receiving end, such as Figure 2 As shown, it includes a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit that provides reference voltage and bias voltage for the two test sampling circuits and the two comparators.

[0047] A first low-pass filter comprises an input end and an output end, wherein the input end is connected to the RXP of the high-speed serial IO interface receiving end, and the output end is connected to the first data input end rx of the first RX test sampling circuit, and plays a role in filtering the spike noise on the RXP signal line;

[0048] A second low-pass filter comprises an input end and an output end, wherein the input end is connected to the RXN of the high-speed serial IO interface receiving end, and the output end is connected to the first data input end rx of the second RX test sampling circuit, and plays a role in filtering the spike noise on the RXN signal line;

[0049] The first RX test sampling circuit includes a first data input terminal rx, a second data input terminal feedback, a first data output terminal outp, a second data output terminal outn, a first control signal input terminal mode, a second control signal input terminal test_init, and a first bias voltage input terminal Vrm, a second bias voltage input terminal Vdc, and a third bias voltage input terminal Vrp. The circuit can work in a DC mode and an AC mode respectively according to different input control signal settings, and can sample both DC signals and AC signals.

[0050] The second RX test sampling circuit has the same internal structure as the first RX test sampling circuit, and also includes a first data input terminal rx, a second data input terminal feedback, a first data output terminal outp, a first data output terminal outn, a first control signal input terminal mode, a second control signal input terminal test_init, a first bias voltage input terminal Vrm, a second bias voltage input terminal Vdc, and a third bias voltage input terminal Vrp;

[0051] The first comparator includes a first data input terminal inp, a second data input terminal inn, a first data output terminal out, a second data output terminal feedback, and a bias voltage input terminal nbias, and is used as a high-gain operational amplifier to compare the first data input terminal inp and the second data input terminal inn, which are marked as positive and negative poles respectively, and generate an output signal with a large swing, wherein the first data input terminal inp is connected to the first data output terminal outp of the first RX test sampling circuit, the second data input terminal inn is connected to the second data output terminal outn of the first RX test sampling circuit, the bias voltage input terminal nbias is connected to the fourth bias voltage output terminal of the RX test bias circuit, and the connection is marked as Vbias, the first data output terminal out is sent to the subsequent digital logic as the output value after comparison for analysis and processing, and the second data output terminal feedback is connected to the feedback terminal of the first RX test sampling circuit, and the connection is marked as feed_p;

[0052] The second comparator has the same internal structure as the first comparator circuit, and also includes a first data input terminal inp, a second data input terminal inn, a first data output terminal out, a second data output terminal feedback, and a bias voltage input terminal nbias. It is also used as a high-gain operational amplifier, and is used to compare the first data input terminal inp and the second data input terminal inn, which are marked as positive and negative poles respectively, and generate an output signal with a large swing. Its first data input terminal inp is connected to the first data output terminal outp of the second RX test sampling circuit, its second data input terminal inn is connected to the second data output terminal outn of the second RX test sampling circuit, and the bias voltage input terminal nbias is connected to the fourth bias voltage output terminal of the RX test bias circuit, and the connection is marked as Vbias. Its first data output terminal out is sent to the subsequent digital logic as the output value after comparison for analysis and processing, and the second data output terminal feedback is connected to the feedback terminal of the second RX test sampling circuit, and the connection is marked as feed_n.

[0053] The RX test bias circuit includes a control signal input terminal, a bias current input terminal, a first bias voltage output terminal, a second bias voltage output terminal, a third bias voltage output terminal and a fourth bias voltage output terminal, is turned on or off under the control of a test enable signal test_en generated by an external digital control logic, receives a stable current source iref_test provided by an external power supply bias circuit, generates four stable voltage biases Vrm, Vdc, Vrp and Vbias and provides them to the first RX test sampling circuit and the second RX test sampling circuit and the first comparator and the second comparator mentioned above;

[0054] Wherein, the first data input terminal rx of the first RX test sampling circuit is connected to the output terminal of the first low-pass filter, the second data input terminal feedback is connected to the second output terminal feedback of the first comparator, the first data output terminal outp of the first RX test sampling circuit is connected to the inp input terminal of the first comparator, the second data output terminal outn of the first RX test sampling circuit is connected to the inn input terminal of the first comparator, the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage input terminal of the RX test bias circuit, and the connecting lines are marked as Vrm, Vdc, and Vrp respectively;

[0055] wherein the first data input terminal rx of the second RX test sampling circuit is connected to the output terminal of the second low-pass filter, the second data input terminal feedback is connected to the second output terminal feedback of the second comparator, the first data output terminal outp of the second RX test sampling circuit is connected to the inp input terminal of the second comparator, the second data output terminal outn of the second RX test sampling circuit is connected to the inn input terminal of the second comparator, the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit, and the connecting lines are marked as Vrm, Vdc, and Vrp, respectively;

[0056] The first control signal input terminal mode and the second control signal input terminal test_init of the first RX test sampling circuit and the second RX test sampling circuit are both connected to the mode selection signal mode and the test initialization signal test_init generated by the external digital control logic;

[0057] The above-mentioned universal test sampling circuit, the first low-pass filter and the second low-pass filter, are generally in the form of connecting a resistor in series between the input and output ends of the low-pass filter, and connecting a capacitor between the output end of the low-pass filter and the ground, or between the output end and the power supply, or between the output end and the power supply and the ground, which can be specifically determined by the designer according to the use process and the layout area;

[0058] The first RX test sampling circuit and the second RX test sampling circuit have the same internal circuit structure. Figure 3As shown, the first data input terminal rx is connected to one end of the first capacitor C1 and the first gate of the P-type transistor M1. The transistor M1 includes a first source terminal, a first drain terminal, and a first gate. The first drain terminal of the transistor M1 is connected to the ground level VS. The first source terminal of the transistor M1 is connected to the other end of the first capacitor C1 and is connected to one end of the second capacitor C2 and one end of the first resistor R1. This connection point is recorded as vnod1. The other end of the first resistor R1 is connected to the stable current source iref_test provided by the external power bias circuit. This connection point is recorded as Vif. The other end of the second capacitor C2 is connected to the first data output terminal outp. The N-type transistor M2 includes a first The first source terminal, the first drain terminal, and the first gate terminal of the P-type transistor M3 include a first source terminal, a first drain terminal, and a first gate terminal. The first drain terminal of the transistor M2 and the first source terminal of the transistor M3 are connected to the above-mentioned connection point Vif. The first source terminal of the transistor M2 and the first drain terminal of the transistor M3 are connected to the first data output terminal outp. The first control signal input terminal mode is connected to the input terminal of the inverter I1. The output terminal signal of the inverter I1 is recorded as mode_N. The first gate terminal of the transistor M3 is connected to the first control signal input terminal mode. The first gate terminal of the transistor M2 is connected to the output terminal mode_N of the inverter I1. The P-type transistor M4 includes a first source terminal, a first drain terminal, and a first gate terminal. The P-type transistor The transistor M5 includes a first source terminal, a first drain terminal, and a first gate terminal. The P-type transistor M6 includes a first source terminal, a first drain terminal, and a first gate terminal. The first gate terminal of the transistor M4 is connected to the first gate terminal of the transistor M5 and the first gate terminal of the transistor M6, and is connected to the output terminal mode_N of the inverter I1. The first source terminal of the transistor M4 is connected to one end of the second resistor R2, and the connection point is recorded as vnod2. The first drain terminal of the transistor M4 is connected to the first source terminal of the transistor M5, and the first drain terminal of the transistor M5 is connected to the first source terminal of the transistor M6. The first drain terminal of the transistor M6 is connected to the second bias voltage input terminal Vdc. The N-type transistor M7 includes a first source terminal, a first drain terminal, and a first gate terminal. The N-type transistor M8 includes a first source terminal, a first drain terminal, and a first gate terminal, the N-type transistor M9 includes a first source terminal, a first drain terminal, and a first gate terminal, the first gate terminal of the transistor M7 is connected to the first gate terminal of the transistor M8 and the first gate terminal of the transistor M9, and is connected to the first control signal input terminal mode, the first drain terminal of the transistor M7 is connected to one end of the second resistor R2 (i.e., point vnod2), the first source terminal of the transistor M7 is connected to the first drain terminal of the transistor M8, the first source terminal of the transistor M8 is connected to the first drain terminal of the transistor M9, the first source terminal of the transistor M9 is connected to the second bias voltage input terminal Vdc, and the other end of the second resistor R2 is connected to the first data output terminal outp; Figure 3 shown.

[0059] The RX test sampling circuit also includes a high-level valid latch LAT1, the latch LAT1 includes a first data input terminal D, a first clock input terminal CP, a first high-level setting terminal CD and a first data output terminal Q, the first data input terminal D of the latch LAT1 is connected to the second data input terminal feedback, the first clock input terminal CP of the latch LAT1 is connected to the first control signal input terminal mode, the first high-level setting terminal CD of the latch LAT1 is connected to the second control signal input terminal test_init, the first data output terminal Q of the latch LAT1 is connected to the input terminal of the second inverter I2 The output terminal of the second inverter I2 is connected to the first gate of the P-type transistor M10, which is recorded as sel_N. The P-type transistor M10 includes a first source terminal, a first drain terminal, and a first gate terminal. The P-type transistor M11 includes a first source terminal, a first drain terminal, and a first gate terminal. The first source terminal of the transistor M10 is connected to the first bias voltage input terminal Vrm, the first source terminal of the transistor M11 is connected to the first bias voltage input terminal Vrp, the first gate of the transistor M11 is connected to the sel signal, and the first drain terminal of the transistor M10 and the first drain terminal of the transistor M11 are connected to the second data output terminal outn;

[0060] The first comparator and the second comparator (with the same internal circuit structure) are as follows: Figure 4As shown, its first data input terminal inp is connected to the first gate of N-type transistor M104 as the positive input of the comparator, and N-type transistor M104 includes a first source terminal, a first drain terminal, and a first gate. Its second data input terminal inn is connected to the first gate of N-type transistor M103 as the negative input of the comparator, and N-type transistor M103 includes a first source terminal, a first drain terminal, and a first gate. The first source terminal of transistor M103 and the first source terminal of M104 are connected to the first drain terminal of N-type transistor M101. N-type transistor M101 includes a first source terminal, a first drain terminal, and a first gate. The first gate of transistor M101 is connected to the bias voltage input terminal nbias. The first source terminal of transistor M101 is connected to ground VS. P-type transistor M105 includes a first source terminal, a first drain terminal, and a first gate. P-type transistor M106 includes a first source terminal, a first drain terminal, and a first gate. The first source terminal of transistor M105 and the first source terminal of transistor M106 are connected to power supply VP. The first drain terminal and the first gate of the transistor M105 are connected to the first drain terminal of the transistor M103 and the first gate of the transistor M106. The first drain terminal of the transistor M106 is connected to the first drain terminal of the transistor M104 and the first gate of the P-type transistor M107. The P-type transistor M107 includes a first source terminal, a first drain terminal, and a first gate. The first source terminal of the transistor M107 is connected to the power supply VP. The first drain terminal of the transistor M107 is connected to the first drain terminal of the transistor M102 and the input terminal of the inverter INV1. The N-type transistor M102 includes a first source terminal, a first drain terminal, and a first gate. The first gate of the transistor M102 is connected to the bias voltage input terminal nbias. The first source terminal of the transistor M101 is connected to the ground VS. The output terminal of the inverter INV1 is connected to the input terminals of the inverter INV2 and the inverter INV3. The output terminal of the inverter INV2 is connected to the first data output terminal out. The output terminal of the inverter INV3 is connected to the second data output terminal feedback.

[0061] RX test bias circuit, such as Figure 5As shown, it includes a P-type transistor M204, the transistor M204 includes a first source terminal, a first drain terminal, and a first gate terminal, the first gate terminal and the first drain terminal of the transistor M204 are connected to the ground VS, the first source terminal of the transistor M204 is connected to one end of the resistor R203, as the first bias voltage output terminal Vrm, the other end of the resistor R203 is connected to one end of the resistor R202, as the second bias voltage output terminal Vdc, the other end of the resistor R202 receives the stable current source iref_test provided by the external power supply bias circuit, and the potential generated here is used as the third bias voltage output terminal Vrp, the RX test bias circuit also includes a P-type transistor M201, an N-type transistor M202, an N-type transistor M203 and a resistor R201, the transistor M201 includes a first source terminal, a first drain terminal, first gate, transistor M202 includes a first source terminal, a first drain terminal, and a first gate, transistor M203 includes a first source terminal, a first drain terminal, and a first gate, the first source terminal of transistor M201 is connected to the power supply VP, the first gate of M201 is connected to the test enable signal test_en generated by the external digital control logic, the first drain terminal of transistor M201 is connected to one end of resistor R201, and the other end of resistor R201 is connected to the first drain terminal and the first gate of transistor M202 as the fourth bias voltage output terminal Vbias, the first source terminal of transistor M202 is connected to the ground VS, the first gate of transistor M203 is connected to the test enable signal test_en generated by the external digital control logic, the first source terminal of transistor M203 is connected to the ground VS, and the first drain terminal of transistor M203 is connected to the fourth bias voltage output terminal Vbias.

[0062] The working mode of the universal test sampling circuit designed in the present invention for the high-speed serial IO interface receiving end is as follows:

[0063] After the chip is powered on, the power bias circuit of the high-speed serial IO interface will provide a stable current source iref_test for the universal test sampling circuit at its receiving end. After the current is injected into the RX test bias circuit, it is converted into three bias voltages, Vrp, Vdc and Vrm, through the fixed series resistors R202 and R203 in the bias circuit. Vdc is generally set to half of the power supply voltage, Vrm is generally set to Vdc-Vth (the threshold voltage of an N-type transistor), and Vrp is generally set to Vdc+Vth; when the test enable signal test_en is input at a low level, the P-type transistor M201 in the RX test bias circuit is turned on, and current passes through the resistor R201. The generated bias voltage Vbias provides a bias voltage for the first comparator and the second comparator.

[0064] When the mode selection signal mode generated by the external digital control logic is at a high level, the first RX test sampling circuit and the second RX test sampling circuit both operate in the AC test mode. Figure 3 As shown, transistors M2 and M3 are both turned off, and transistors M4, M5, M6, M7, M8, and M9 are all turned on. At this time, the rx terminal of the RX test sampling circuit receives an AC signal. When the AC signal changes from low to high, transistor M1 is turned off, and the potential at vnod1 is pulled high by resistor R1. The high-frequency component in the rising edge of rx is coupled to the first data output terminal outp through capacitors C1 and C2, and the first data output terminal outp is connected to the first data output terminal outp. Figure 6 It can be seen from the simulation waveform that the output signal of outp generates a part of the peak at the rising edge; when the mode signal is high, the high-level effective latch LAT1 in the RX test sampling circuit, because its clock CP terminal is connected to the mode signal, which is high at this time, and the data terminal D is connected to the feedback signal of the comparator, so the output of the latch LAT1 is the comparison value of the comparator. When the current output of the comparator is high, Figure 3 The P-type transistor M10 in the circuit is turned on, and Vrm is transmitted to the negative input terminal of the comparator and compared with the sampling signal of the positive input. When the current output of the comparator is low, Figure 3 The P-type transistor M11 in the circuit is turned on, and Vrp is transmitted to the negative input terminal of the comparator to be compared with the sampling signal of the positive input. This form of using the comparator output as the feedback voltage to determine the different potentials of the reference voltage connected to the negative input terminal of the comparator can simplify the design of the comparator and cope with the stable value of the input signal after the rising edge peak signal.

[0065] When the mode selection signal mode generated by the external digital control logic is at a low level, the first RX test sampling circuit and the second RX test sampling circuit both operate in a DC test mode. Figure 3 As shown, transistors M2 and M3 are both turned on, and transistors M4, M5, M6, M7, M8, and M9 are all turned off. The working state at this time is relatively simple. The first data output terminal outp of the RX test sampling circuit is equivalent to directly "copying" the signal received by the rx terminal; when the mode signal is at a low level, the output of the high-level effective latch LAT1 in the RX test sampling circuit is determined by the second control signal input terminal test_init. The latch LAT1 is in a set state at this time, and its output terminal Q is at a high potential. The P-type transistor M10 is turned on, and Vrm is transmitted to the second data output terminal outn of the RX test sampling circuit; the comparator compares the positive and negative inputs to generate the final sampling output signal, such as Figure 7 shown.

[0066] Through the universal test sampling circuit for the receiving end of the high-speed serial IO interface in the present invention, a universal test sampling circuit is provided which can work in a DC mode and an AC mode respectively according to different input control signal settings. It can sample both DC signals and AC signals, solving the problem that the traditional boundary scan test circuit cannot test the AC signal in the high-speed serial IO interface, and test sampling is performed on each of the two differential signal paths at the receiving end of the high-speed serial IO interface respectively, so that the chip of the high-speed serial IO interface which adopts differential and AC forms for signal transmission can be easily, accurately and perfectly solved to detect and diagnose various conduction defects that may be introduced in the PCB circuit board production, chip electrical assembly and packaging processes.

[0067] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0068] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A universal test sampling circuit for a high-speed serial IO interface receiving end, characterized in that: The invention comprises a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator and an RX test bias circuit for providing a reference voltage and a bias voltage for the two test sampling circuits and the two comparators: wherein, The input end of the first low-pass filter is connected to the RXP of the high-speed serial IO interface receiving end, and the output end is connected to the first data input end rx of the first RX test sampling circuit, so as to filter the peak noise on the RXP signal line; The input end of the second low-pass filter is connected to the RXN of the high-speed serial IO interface receiving end, and the output end is connected to the first data input end rx of the second RX test sampling circuit, so as to filter the peak noise on the RXN signal line; The second data input terminal feedback of the first RX test sampling circuit is connected to the second output terminal feedback of the first comparator, the first data output terminal outp of the first RX test sampling circuit is connected to the inp input terminal of the first comparator, and the second data output terminal outn of the first RX test sampling circuit is connected to the inn input terminal of the first comparator; the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit; The second data input terminal feedback of the second RX test sampling circuit is connected to the second output terminal feedback of the second comparator, the first data output terminal outp of the second RX test sampling circuit is connected to the inp input terminal of the second comparator, and the second data output terminal outn of the second RX test sampling circuit is connected to the inn input terminal of the second comparator; the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit; The first control signal input terminal mode and the second control signal input terminal test_init of the first RX test sampling circuit and the second RX test sampling circuit are both connected to the mode selection signal mode and the test initialization signal test_init generated by the external digital control logic; The first comparator, as a high-gain operational amplifier, is used to compare the magnitudes of the first data input terminal inp and the second data input terminal inn, which are marked as positive and negative poles respectively, and generate an output signal with a large swing. The bias voltage input terminal nbias of the first comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit. The first data output terminal OUTP of the first comparator is sent to the subsequent digital logic as the output value after comparison for analysis and processing; The second comparator has the same internal structure as the first comparator circuit; the bias voltage input terminal nbias of the second comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit; the first data output terminal OUTN of the second comparator is sent to the subsequent digital logic for analysis and processing as the compared output value.

2. A universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 1, characterized in that: The internal circuit structure of the second RX test sampling circuit is consistent with that of the first RX test sampling circuit; The internal circuit structure of the first comparator is consistent with that of the second comparator.

3. The universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 1, characterized in that: The RX test bias circuit is turned on or off under the control of a test enable signal test_en generated by an external digital control logic, receives a stable current source iref_test provided by an external power supply bias circuit, generates four stable voltage biases Vrm, Vdc, Vrp and Vbias and provides them to the first RX test sampling circuit and the second RX test sampling circuit and the first comparator and the second comparator.

4. The universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 1, characterized in that: Under the control of the mode selection signal mode, it can work in two test modes. When mode=1, it works in AC mode and samples AC signals. When mode=0, it works in DC mode and samples DC signals.

5. The universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 1, characterized in that: The first RX test sampling circuit includes: a first capacitor C1, a P-type transistor M1, a second capacitor C2, a first resistor R1, an N-type transistor M2, a P-type transistor M3, an inverter I1, a P-type transistor M4, a P-type transistor M5, a P-type transistor M6, a second resistor R2, an N-type transistor M7, an N-type transistor M8 and an N-type transistor M9; wherein, The first data input terminal rx is connected to one end of the first capacitor C1 and is also connected to the gate of the P-type transistor M1; the drain of the transistor M1 is connected to the ground level VS, the source of the transistor M1 is connected to the other end of the first capacitor C1, and is also connected to the input of the second capacitor C2 and the input of the first resistor R1; the output of the first resistor R1 is connected to the stable current source iref_test provided by the external power bias circuit, and this connection point is denoted as Vif; the output of the second capacitor C2 is connected to the first data output terminal outp; the drain of the transistor M2 and the source of the transistor M3 are connected to the connection point Vif; the source of the transistor M2 and the drain of the transistor M3 are connected to the first data output terminal outp; the first control signal input terminal mode is connected to the input of the inverter I1, and the output signal of the inverter I1 is denoted as mode_N; the gate of the transistor M3 is connected to the first control signal input terminal mode, and the gate of the transistor M2 is connected to the inverter The output terminal mode_N of the inverter I1 is connected to the output terminal mode_N of the inverter I1; the gate of the transistor M4 is connected to the gate of the transistor M5 and the gate of the transistor M6, and is connected to the output terminal mode_N of the inverter I1; the source terminal of the transistor M4 is connected to the input terminal of the second resistor R2, and the connection point is recorded as vnod2, the drain terminal of the transistor M4 is connected to the source terminal of the transistor M5, the drain terminal of the transistor M5 is connected to the source terminal of the transistor M6, and the drain terminal of the transistor M6 is connected to the second bias voltage input terminal Vdc; the gate of the transistor M7 is connected to the gate of the transistor M8 and the gate of the transistor M9, and is connected to the first control signal input terminal mode, and the drain terminal of the transistor M7 is connected to the connection point vnod2; the source terminal of the transistor M7 is connected to the drain terminal of the transistor M8, the source terminal of the transistor M8 is connected to the drain terminal of the transistor M9, the source terminal of the transistor M9 is connected to the second bias voltage input terminal Vdc, and the output terminal of the second resistor R2 is connected to the first data output terminal outp.

6. The universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 1, characterized in that: The first RX test sampling circuit also includes a high-level effective latch LAT1, a second inverter I2, a P-type transistor M10 and a P-type transistor M11; wherein the latch LAT1 includes a first data input terminal D, a first clock input terminal CP, a first high-level setting terminal CD and a first data output terminal Q; the first data input terminal D of the latch LAT1 is connected to the second data input terminal feedback of the first RX test sampling circuit, the first clock input terminal CP of the latch LAT1 is connected to the first control signal input terminal mode, and the first high-level setting terminal CD of the latch LAT1 is connected to the first control signal input terminal mode. D is connected to the second control signal input terminal test_init, the first data output terminal Q of the latch LAT1 is connected to the input terminal of the second inverter I2, and this connection point is recorded as sel. The output terminal of the second inverter I2 is connected to the gate of the P-type transistor M10, and the connection point is recorded as sel_N; the source terminal of the transistor M10 is connected to the first bias voltage input terminal Vrm, the source terminal of the transistor M11 is connected to the first bias voltage input terminal Vrp, the gate of the transistor M11 is connected to the connection point sel, and the drain terminal of the transistor M10 and the drain terminal of the transistor M11 are connected to the second data output terminal outn.

7. The universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 1, characterized in that: The first comparator comprises an N-type transistor M101, an N-type transistor M102, an N-type transistor M103, an N-type transistor M104, a P-type transistor M105, a P-type transistor M106, a P-type transistor M107, an inverter INV1, an inverter INV2, and an inverter INV3; wherein the first data input terminal inp is connected to the gate of the N-type transistor M104 as the positive input of the comparator, and the second data input terminal inn is connected to the gate of the N-type transistor M103 as the negative input of the comparator; the source terminal of the transistor M103 and the source terminal of M104 are connected to the drain terminal of the N-type transistor M101; the gate of the transistor M101 is connected to the bias voltage input terminal nbias, and the source terminal of the transistor M101 is connected to the ground VS; the source terminal of the transistor M105 and the transistor M The source terminal of transistor M106 is connected to the power supply VP, the drain terminal and the gate terminal of transistor M105 are connected to the drain terminal of transistor M103 and the gate terminal of transistor M106; the drain terminal of transistor M106 is connected to the drain terminal of transistor M104 and the gate terminal of P-type transistor M107; the source terminal of transistor M107 is connected to the power supply VP, the drain terminal of transistor M107 is connected to the drain terminal of transistor M102 and the input terminal of inverter INV1; the gate terminal of transistor M102 is connected to the bias voltage input terminal nbias, the source terminal of transistor M102 is connected to the ground VS, the output terminal of inverter INV1 is connected to the input terminals of inverter INV2 and inverter INV3, the output terminal of inverter INV2 is connected to the first data output terminal out, and the output terminal of inverter INV3 is connected to the second data output terminal feedback.

8. The universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 1, characterized in that: The RX test bias circuit includes a P-type transistor M204, a resistor R203, a resistor R202, a P-type transistor M201, an N-type transistor M202, an N-type transistor M203 and a resistor R201; wherein the gate and drain of the transistor M204 are connected to the ground VS, the source of the transistor M204 is connected to the output of the resistor R203 as a first bias voltage output terminal Vrm; the input of the resistor R203 is connected to the output of the resistor R202 as a second bias voltage output terminal Vdc, the input of the resistor R202 receives a stable current source iref_test provided by an external power supply bias circuit, and the current generated here is The gate of transistor M203 is connected to the test enable signal test_en generated by the external digital control logic, the source terminal of transistor M203 is connected to the ground VS, and the drain terminal of transistor M203 is connected to the fourth bias voltage output terminal Vbias.

9. The universal test sampling circuit for a high-speed serial IO interface receiving end according to claim 6, characterized in that: When the first high-level set terminal CD of the high-level effective latch LAT1 is at a low potential and the first clock input terminal CP is at a high potential, the output of the first data output terminal Q is consistent with the first data input terminal D; when the first high-level set terminal CD is at a low potential and the first clock input terminal CP is at a low potential, the output of the first data output terminal Q maintains the previous valid value; when the first high-level set terminal CD is high, the first data output terminal Q is at a high potential.

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