Low-power-consumption single-fixed-type fault testing device and method and electronic design automation product

Abstract

The invention relates to a low-power-consumption single-fixed fault testing device and method and an electronic design automation product, and the device comprises a multi-stage linear feedback shift register which is configured to realize primitive polynomials of different stages, and outputs a test vector according to the structure of a scanning forest and a target fault type; the phase shifter is used for carrying out phase shift processing on the test vectors, the phase shifter comprises multiple stages of outputs, and each stage of output is used for outputting the test vectors of different phases to drive the multiplexer connected with the phase shifter; the scan flip-flop is from combinational logic of the tested circuit; the response compressor is used for compressing the circuit response signal output by the scanning forest to obtain a compressed circuit response signal; and the feature analyzer is used for performing comparative analysis according to the compressed circuit response signal and an expected circuit response signal to obtain a fault test result of the tested circuit. The low-power-consumption single-fixed type fault testing device provided by the embodiment of the invention has relatively high testing efficiency and relatively high flexibility.

Description

Technical Field

[0001] The present disclosure relates to the field of testing technology, and in particular to a low-power single fixed-fault testing device and method, and an electronic design automation product. Background Art

[0002] Because of the chips with large-scale logic devices, the designed integrated circuits can be integrated and solidified into these chips, so as to realize the designed integrated circuits with high density and smaller volume. Before mass production, the chips with solidified integrated circuits must test the circuit characteristics, such as testing whether the circuit logic and timing of the chip are correct, to detect whether the chip can achieve the integrated circuit functions required by the design. Self-test technology can conveniently test integrated circuit chips. Self-test technology refers to the integrated circuit designers adding some additional test circuits to the integrated circuit chips and using the test circuits to self-test the designed integrated circuits. However, the current self-test schemes have problems with low efficiency and flexibility. Summary of the invention

[0003] According to one aspect of the present disclosure, a low-power single stuck-at fault test device is provided, the device comprising a multi-stage linear feedback shift register, a phase shifter, a plurality of multiplexers, a scan forest, a response compressor and a feature analyzer, wherein:

[0004] The multi-stage linear feedback shift register is configured to implement primitive polynomials of different orders, and the multi-stage linear feedback shift register is used to output a test vector, and the test vector is related to the structure of the scan forest and the target fault type;

[0005] Each input end of the phase shifter is connected to a plurality of output nodes of the multi-stage linear feedback shift register, the phase shifter is used to perform phase shift processing on the test vector, the phase shifter includes a multi-stage output, each stage of output is used to output a test vector of a different phase to drive a connected multiplexer;

[0006] The scan forest includes a plurality of scan tree sets, each scan tree set includes a plurality of scan trees, each scan tree includes a plurality of scan chains, each scan chain includes a plurality of cascaded scan triggers, and the scan triggers are from the combinational logic of the circuit under test;

[0007] The response compressor is connected to the scanning forest and is used to compress the circuit response signal output by the scanning forest to obtain a compressed circuit response signal;

[0008] The characteristic analyzer is connected to the response compressor and is used to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain the fault test result of the tested circuit.

[0009] In one possible implementation, the multi-stage linear feedback shift register includes a plurality of cascaded D flip-flops, and the multi-stage linear feedback shift register is configured as a primitive polynomial of a target number of stages by setting a multiplexer between the D flip-flops at one or more specific positions and the D flip-flops adjacent to the D flip-flops at the specific positions, and controlling the multiplexer.

[0010] In a possible implementation, the multi-stage linear feedback shift register includes a first input multiplexer, n cascaded D flip-flops, an additional register group, n two-input AND gates and n XOR gates, each two-input AND gate, each D flip-flop and each XOR gate correspondingly,

[0011] A series control multiplexer is arranged between the mth D flip-flop and the m+1th D flip-flop to realize an n-level primitive polynomial or an nm-level primitive polynomial, an input end of the series control multiplexer is connected to an output end of the mth D flip-flop and an input end of a two-input AND gate corresponding to the mth D flip-flop, and an output end of the series control multiplexer is connected to an input end of the m+1th D flip-flop, wherein n>m and both are positive integers;

[0012] In other D flip-flops except the m-th D flip-flop, the output end of the k-th D flip-flop is connected to one input end of the k-th two-input AND gate and the input end of the k+1-th D flip-flop, the other input end of the k-th two-input AND gate is connected to the k-th register in the additional register group, the output end of the k-th two-input AND gate is connected to one input end of the k-th XOR gate, the other input end of the k-th XOR gate is connected to the output end of the k+1-th XOR gate, the output end of the 1st XOR gate is connected to the first input end of the first input multiplexer, and the second input end of the first input multiplexer is used to input a preset seed sequence, wherein k≤n is an integer, and the other input end of the n-th XOR gate is connected to the output end of the n-th D flip-flop;

[0013] The control end of the first input multiplexer and the control end of the stage control multiplexer are used to receive control signals to configure the stages of the primitive polynomial of the multi-stage linear feedback shift register.

[0014] In one possible implementation, when the value of the kth register in the additional register group is 1, the kth two-input AND gate output is the output value of the kth D flip-flop; or, when the value of the kth register in the additional register group is 0, the kth two-input AND gate output is 0.

[0015] In a possible implementation manner, if the control end of the first input multiplexer and the control end of the stage control multiplexer receive a control signal s and a control signal s' respectively, then,

[0016] When ss'=00, the multi-stage linear feedback shift register is configured as a linear shift register; or

[0017] When ss'=11, the multi-stage linear feedback shift register is configured as a primitive polynomial of nm level, the m-th stage D flip-flop is used as a shift register, and a test vector can be shifted into the connected phase shifter; or

[0018] When ss'=10, the multi-stage linear feedback shift register is configured with an n-stage primitive polynomial.

[0019] In a possible implementation, if the multi-stage linear feedback shift register can implement primitive polynomials of n-stage, i1-stage, i2-stage, ..., il-stage, ..., ic-stage, where n>i1>i2>...>il>...>ic, and i1, i2, il, ic are all positive integers,

[0020] When the multi-stage linear feedback shift register is configured with an n-stage primitive polynomial, the control signal of the first input multiplexer 101 is 1, and the control signals of the stage control multiplexers of stage i1, stage i2, ..., stage il, ..., stage ic are set to 0;

[0021] When the multi-stage linear feedback shift register is configured with an il-stage primitive polynomial, the control signals of the first input multiplexer and the il-stage stage control multiplexer are set to 1, and the control signals of the i1, i2, ..., il-1-stage stage control multiplexers are set to 0;

[0022] When the multi-stage linear feedback shift register is configured with the primitive polynomial of stage ic, the control signals of the first input multiplexer and the stage control multiplexer of stage ic are set to 1, and the control signals of the stage control multiplexers of stages i1, i2, ..., ic-1 are set to 0.

[0023] In a possible implementation manner, the control signal is provided by a control signal register.

[0024] In a possible implementation manner, the multi-stage linear feedback shift register is further connected to a plurality of additional vector input AND gates, and two input ends of each additional vector input AND gate are used to receive additional vector bits and external input data.

[0025] According to one aspect of the present disclosure, an electronic design automation product is provided, wherein the electronic design automation product comprises the low-power consumption single stuck-at fault test device.

[0026] According to one aspect of the present disclosure, a low-power single stuck-at fault testing method is provided, the method comprising:

[0027] Using a multi-stage linear feedback shift register to implement primitive polynomials of different orders, the multi-stage linear feedback shift register is used to output a test vector according to the structure of a scan forest and a target fault type, wherein the scan forest includes a plurality of scan tree sets, each scan tree set includes a plurality of scan trees, each scan tree includes a plurality of scan chains, each scan chain includes a plurality of cascaded scan triggers, and the scan triggers come from the combinational logic of the circuit under test;

[0028] Performing phase shift processing on the test vector by using a phase shifter, wherein the phase shifter includes multiple output stages, and each output stage is used to output a test vector with a different phase to drive a connected multiplexer;

[0029] Using a response compressor to compress the circuit response signal output by the scanning forest to obtain a compressed circuit response signal;

[0030] A characteristic analyzer is used to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain a fault test result of the circuit under test.

[0031] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0032] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0033] The multi-stage linear feedback shift register of the embodiment of the present disclosure can realize primitive polynomials of different levels as needed to flexibly output test vectors according to the structure of the scan forest and the target fault type. The phase shifter outputs test vectors of different phases after phase shifting the test vector to drive the connected multiplexer, so that the response compressor compresses the circuit response signal output by the scan forest to obtain a compressed circuit response signal, and uses a feature analyzer to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain the fault test result of the circuit under test, thereby achieving efficient testing of the circuit under test. It can be seen that the low-power single fixed-type fault testing device of the embodiment of the present disclosure has higher testing efficiency and higher flexibility.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0036] Figure 1 A schematic diagram of a low power single stuck-at fault testing device according to an embodiment of the present disclosure is shown.

[0037] Figure 2 A schematic diagram of a multi-stage linear feedback shift register according to an embodiment of the present disclosure is shown.

[0038] Figure 3 A schematic diagram of a low power single stuck-at fault testing device according to an embodiment of the present disclosure is shown.

[0039] Figure 4 A schematic diagram of a low power single stuck-at fault testing device according to an embodiment of the present disclosure is shown.

[0040] Figure 5 Shows Figure 1 The low power single stuck-at fault test device structure shown is a schematic diagram of the construction of a group of scan trees and corresponding response compressors.

[0041] Figure 6 The figure is a schematic diagram of the overall working process of the low power single fixed fault testing device according to the embodiment of the present disclosure.

[0042] Figure 7 A flow chart of a low-power single stuck-at fault testing method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0044] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0047] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0048] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0049] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0050] See also Figure 1, Figure 1 A schematic diagram of a low power single stuck-at fault testing device according to an embodiment of the present disclosure is shown.

[0051] like Figure 1 As shown, the device includes a multi-stage linear feedback shift register 10 (Multi Series LinearFeedback Shift Register, MS-LFSR), a phase shifter 20 (Phase Shifter, PS), a plurality of multiplexers 30 (MUX), a scanning forest 40, a response compressor 50 and a feature analyzer 60, wherein,

[0052] The multi-stage linear feedback shift register 10 is configured to implement primitive polynomials of different orders, and the multi-stage linear feedback shift register 10 is used to output a test vector, and the test vector is related to the structure of the scan forest 40 and the target fault type;

[0053] Each input end of the phase shifter 20 is connected to a plurality of output nodes of the multi-stage linear feedback shift register 10. The phase shifter 20 is used to perform phase shift processing on the test vector. The phase shifter 20 includes a multi-stage output, and each stage of output is used to output a test vector of a different phase to drive a connected multiplexer 30.

[0054] The scan forest 40 includes a plurality of scan tree sets, each scan tree set includes a plurality of scan trees 410, each scan tree 410 includes a plurality of scan chains 420, each scan chain 420 includes a plurality of cascaded scan triggers, and the scan triggers are from the combinational logic of the circuit under test 70;

[0055] The response compressor 50 is connected to the scanning forest 40 and is used to compress the circuit response signal output by the scanning forest 40 to obtain a compressed circuit response signal;

[0056] The feature analyzer 60 is connected to the response compressor 50 , and is used to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain the fault test result of the circuit under test 70 .

[0057] The multi-stage linear feedback shift register 10 of the embodiment of the present disclosure can realize primitive polynomials of different levels as needed, so as to flexibly output test vectors according to the structure of the scan forest 40 and the target fault type. The phase shifter 20 outputs test vectors of different phases after phase shifting the test vector to drive the connected multiplexer 30, so that the response compressor 50 compresses the circuit response signal output by the scan forest 40 to obtain a compressed circuit response signal, and uses the feature analyzer 60 to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain the fault test result of the circuit under test 70, thereby realizing efficient testing of the circuit under test 70. It can be seen that the low-power single fixed-type fault test device of the embodiment of the present disclosure has higher testing efficiency and higher flexibility.

[0058] The disclosed embodiment does not limit the specific implementation of the multi-stage linear feedback shift register 10, the phase shifter 20, the multiple multiplexers 30, the scanning forest 40, the response compressor 50 and the feature analyzer 60. Those skilled in the art can set them according to actual conditions and needs. For example, they can all be implemented using software-defined technology. In the specific implementation, they can be implemented through logic processing components such as FPGA and CPLD.

[0059] It should be understood that the number of registers in a linear feedback shift register LFSR is usually called the number of stages of the linear feedback shift register LFSR. The maximum period of an n-stage LFSR is 2 n -1, period is 2 n The sequence generated by the LFSR of -1 can be called an m-sequence, and the characteristic polynomial corresponding to the m-sequence LFSR feedback function is called a primitive polynomial. The embodiment of the present disclosure does not limit the specific number of stages (the size of n) of the multi-stage linear feedback shift register 10, and those skilled in the art can set it according to actual conditions and needs.

[0060] Exemplarily, the registers in the linear feedback shift register LFSR can be implemented by D flip-flops. In one possible implementation, the multi-stage linear feedback shift register 10 of the embodiment of the present disclosure may include multiple cascaded D flip-flops. The embodiment of the present disclosure configures the multi-stage linear feedback shift register 10 as a primitive polynomial of a target level by setting a multiplexer between the D flip-flops at one or more specific positions and the D flip-flops adjacent to the D flip-flops at the specific positions, and controlling the multiplexer.

[0061] For example, assuming that the multi-stage linear feedback shift register 10 can realize a primitive polynomial of a maximum of n levels, the embodiment of the present disclosure can realize a primitive polynomial of any target level less than n by setting a multiplexer between a D flip-flop at one or more specific positions and a D flip-flop adjacent to the D flip-flop at the specific position, and controlling the multiplexer. For example, if an nm-level primitive polynomial is to be realized, a multiplexer is set between the m-th D flip-flop and the m+1-th D flip-flop, where n>m and both are positive integers.

[0062] See also Figure 2 , Figure 2 A schematic diagram of a multi-stage linear feedback shift register according to an embodiment of the present disclosure is shown.

[0063] In a possible implementation, Figure 2 As shown, the multi-stage linear feedback shift register 10 may include a first input multiplexer 101, n cascaded D flip-flops 100, an additional register group (including n registers 104), n two-input AND gates 103 and n XOR gates 105, each two-input AND gate 103, each D flip-flop 100 and each XOR gate 105 correspondingly,

[0064] In the mth D flip-flop 100 (eg Figure 2 S im-1 ) and the m+1th D flip-flop 100 (e.g. Figure 2 S im ) to realize n-level primitive polynomials or nm-level primitive polynomials, one input end of the level control multiplexer 102 is connected to the output end of the m-th D flip-flop 100 and the two-input AND gate 103 (for example, Figure 2 d in n-m ), the output end of the stage control multiplexer 102 is connected to the input end of the m+1th D flip-flop 100, wherein n>m and both are positive integers;

[0065] In the other D flip-flops except the m-th D flip-flop, the output terminal of the k-th D flip-flop 100 is connected to an input terminal of the k-th two-input AND gate 103 and an input terminal of the k+1-th D flip-flop 100.

[0066] The other input terminal of the k-th two-input AND gate 103 is connected to the k-th register 104 in the additional register group, the output terminal of the k-th two-input AND gate 103 is connected to one input terminal of the k-th XOR gate 105, and the other input terminal of the k-th XOR gate 105 is connected to the output terminal of the k+1-th XOR gate 105.

[0067] The first XOR gate 105 (eg Figure 2 d in n-1 ) is connected to the first input terminal of the first input multiplexer 101, and the second input terminal of the first input multiplexer 101 is used to input a preset seed sequence, wherein k≤n is an integer, and the nth XOR gate 105 (e.g. Figure 2 The other input end of d1) is connected to the output end of the nth D flip-flop.

[0068] The control end of the first input multiplexer 101 and the control end of the stage control multiplexer 102 are used to receive a control signal (ss′) to configure the stage of the primitive polynomial of the multi-stage linear feedback shift register 10 .

[0069] As required, the output end of any D flip-flop can be used as an output node of the multi-stage linear feedback shift register and connected to the phase shifter.

[0070] For example, if we want to implement nm-level primitive polynomials, Figure 2 As shown, the D flip-flop Si m-1 (mth D flip-flop 100) and D flip-flop Si m A series control multiplexer 102 is set between (the m+1th D flip-flop 100) to realize an n-level primitive polynomial or an nm-level primitive polynomial, one input end of the series control multiplexer 102 is connected to the output end of the m-th D flip-flop 100 and one input end of the two-input AND gate 103ANDm-1 corresponding to the m-th D flip-flop 100, and the output end of the series control multiplexer 102 is connected to the input end of the m+1th D flip-flop 100, wherein n>m and both are positive integers.

[0071] Exemplarily, each register 104 in the additional register group can store the tap coefficient of the multi-stage linear feedback shift register 10, and the tap coefficient is used to determine the bit participating in the XOR operation in the multi-stage linear feedback shift register 10 (i.e., the value of the D flip-flop output). Exemplarily, in a possible implementation, when the value of the kth register 104 in the additional register group is 1, the output of the kth two-input AND gate 103 is the output value of the kth D flip-flop 100 (participating in the XOR operation); or, when the value of the kth register 104 in the additional register group is 0, the output of the kth two-input AND gate 103 is 0 (not participating in the XOR operation).

[0072] Exemplarily, the seed sequence mainly plays an initialization role. The specific value of the preset seed sequence received by the second input end of the first input multiplexer 101 is not limited in the embodiment of the present disclosure, and those skilled in the art can set it according to actual conditions and needs.

[0073] It should be understood that, for a multi-stage linear feedback shift register 10 provided with different numbers of stage control multiplexers 102, the control signal is set in an adaptive manner according to the target number of stages to be set. Therefore, those skilled in the art can implement the setting of the control signal according to actual conditions and needs. The embodiments of the present disclosure are not limited to this and are exemplarily introduced below.

[0074] In a possible implementation manner, if the control end of the first input multiplexer 101 and the control end of the stage control multiplexer 102 receive a control signal s and a control signal s′ respectively, then,

[0075] When ss'=00, the multi-stage linear feedback shift register 10 is configured as a linear shift register. In this case, the pre-configured preset seed sequence can be shifted into the multi-stage linear feedback shift register 10; or

[0076] When ss'=11, the multi-stage linear feedback shift register 10 is configured as a primitive polynomial of nm level, the m-th stage D flip-flop 100 is used as a shift register, and a test vector can be shifted into the connected phase shifter 20. In this case, the multi-stage linear feedback shift register 10 activates the linear feedback shift register f(x)=c of nm level. n-m ·x n-m +c n-2 ·x n-m-1 +…+c1·x+1, the highest m-level D-flip-flop is used as a shift register and can simultaneously shift the required test vector into all the connected phase shifters 20 (PS), where c1,…,c n-2 、c n-m represents the tap coefficients stored in each register 104 in the additional register group, x, ..., x n-m-1 、x n-m represents the value in each D flip-flop 100; or

[0077] When ss'=10, the multi-stage linear feedback shift register 10 is configured with an n-stage primitive polynomial. In this case, according to the c stored in each register 104 in the additional register group, n-1 , c n-2 , ..., c1, c0 activate the multi-stage linear feedback shift register 10 to the corresponding primitive polynomial f(x) = x n +c n-1 ·x n-1 +c n-2 ·x n-2 +…+c1·x+1, where c1,…,c n-2 、c n-1represents the tap coefficients stored in each register 104 in the additional register group, x, ..., x n-1 、x n represents the value in each D flip-flop 100 .

[0078] Exemplarily, the phase shifter 20 can be constructed according to the multi-stage linear feedback shift register 10 with the highest number of stages (such as n stages). The change of the number of stages of the multi-stage linear feedback shift register 10 will not cause the change of the phase shifter 20. As mentioned above, a multi-stage linear feedback shift register 10 with a low number of stages can be implemented by setting the highest corresponding position of the additional register to 0. In this case, the m bits corresponding to the highest number of stages are used as shift registers. For example, for an additional register with a total of n bits, after the highest nm positions are set to 0, the lower m bits are used as shift registers.

[0079] In a possible implementation, if the multi-stage linear feedback shift register 10 can implement primitive polynomials of n-stage, i1-stage, i2-stage, ..., il-stage, ..., ic-stage, where n>i1>i2>...>il>...>ic, and i1, i2, il, ic are all positive integers,

[0080] Taking the multi-stage linear feedback shift register 10 to realize the i1-level primitive polynomial as an example, refer to Figure 2 , a stage control multiplexer 102 can be set between the i1th and i1+1th D flip-flops, and the control signal is set to 1. At this time, the output ends of the nth to i+1th D flip-flops serve as the output ends of the shift register, and the same applies to other cases. That is, the stage control multiplexer 102 can be inserted between the required D flip-flops, and its operation can be controlled by the control signal to realize primitive polynomials of different stages.

[0081] Exemplarily, when the multi-stage linear feedback shift register 10 is configured with an n-stage primitive polynomial, the control signal of the first input multiplexer 101 is 1, and the control signals of the level control multiplexers 102 of the i1-level, i2-level, ..., il-level, ..., ic-level are set to 0 (at this time, the level control multiplexers 102 of the i1-level, i2-level, ..., il-level, ..., ic-level are used for shifting signals); at this time, the output ends of the 1-n D flip-flops are all used as output nodes. Exemplarily, when the multi-stage linear feedback shift register 10 is configured with an i1-level primitive polynomial, the control signals of the first input multiplexer 101 and the i1-level level control multiplexers 102 are set to 1, and the control signals of the remaining level control multiplexers 102 are set to 0, that is, i1, i2, ..., il-1, i2-level, ..., ic-level. l+1 ,…,i cThe control signal of the stage number control multiplexer 102 is set to 0. At this time, the stage number control multiplexer 102 of the i1, i2, ..., il-1 levels is used to shift the signal; at this time, the output ends of the 1st to il-th D flip-flops are all used as output nodes.

[0082] Exemplarily, when the multi-stage linear feedback shift register 10 is configured with an ic-stage primitive polynomial, the control signals of the first input multiplexer 101 and the ic-stage stage control multiplexer 102 are set to 1, and the control signals of the remaining stage control multiplexers 102 are set to 0, that is, the control signals of the i1, i2, ..., ic-1 stage stage control multiplexers 102 are set to 0. At this time, the i1, i2, ..., ic-1 stage stage control multiplexers 102 are used for shifting signals. In this case, the output terminals of the 1st to ic-th D flip-flops are all used as output nodes.

[0083] For example, Figure 2 As shown, inserting MUX into the shift chain inside the multi-stage linear feedback shift register 10 indicates that the multi-stage linear feedback shift register 10 can support the linear feedback shift register implemented by the primitive polynomial of this stage. Each MUX inserted in the multi-stage linear feedback shift register 10 uses an independent control signal; multiple MUXs can reduce the additional pin overhead by adding an additional shift register.

[0084] The disclosed embodiment can determine the number of stages of the multi-stage linear feedback shift register 10 as needed and generate a corresponding control signal. In a possible implementation, the control signal is provided by a control signal register, and the control signal register can be implemented by software-defined technology. For example, a control signal generated in advance can be stored in the control signal register. When testing the circuit under test 70, the control signal in the control signal register can be used to control the stage control multiplexer 102 and the first input multiplexer 101 to configure the multi-stage linear feedback shift register 10 to a target number of stages.

[0085] Each output node of the multi-stage linear feedback shift register is used as an output to an input of the phase shifter. The phase shifter shifts the bit data output by the output node to form a vector, and can form the required phase shift by shifting as needed to obtain test vectors with different phases.

[0086] The disclosed embodiment does not limit the specific correlation between the test vector and the structure of the scan forest 40 and the target fault type. Those skilled in the art can set it according to actual conditions and needs. For example, after selecting the target fault type and determining the structure of the scan forest 40, relevant technologies (such as the test vector generation component in the EDA software) can be used to realize the adaptive generation of test vectors.

[0087] See also Figure 3 , Figure 3 A schematic diagram of a low power single stuck-at fault testing device according to an embodiment of the present disclosure is shown.

[0088] In a possible implementation, Figure 3 As shown, the multi-stage linear feedback shift register 10 is also connected to a plurality of additional vector input AND gates, and two input ends of each additional vector input AND gate are used to receive additional vector bits and external input data.

[0089] The embodiment of the present disclosure sets two input ends of the additional vector input AND gate for receiving the additional vector bit and external input data, and can use external pins to input external input data to adaptively change the primitive polynomial of the multi-stage linear feedback shift register 10, so that the multi-stage linear feedback shift register 10 outputs a suitable test vector. The output end of the additional vector input AND gate can be connected to the input end of a specific D flip-flop in the multi-stage linear feedback shift register. Of course, the embodiment of the present disclosure does not limit the number of additional pins, the number of additional vector input AND gates, external data, and the specific setting of the additional vector bit, and those skilled in the art can set it according to actual conditions and needs.

[0090] The embodiments of the present disclosure do not limit the specific method of establishing the scan forest, the scan tree set, the number of scan trees in the scan tree set, and the specific number of scan chains for each scan tree type. Those skilled in the art can set them according to actual conditions and needs.

[0091] The embodiment of the present disclosure does not limit the specific implementation method of the response compressor compressing the circuit response signal output by the scan forest to obtain the compressed circuit response signal. Those skilled in the art can set it according to actual conditions and needs. For example, the response compressor can be implemented by an XOR network. The response compressor can receive the circuit response signals output by each scan chain and then perform compression processing through the XOR network.

[0092] The specific implementation method of the embodiment of the present disclosure that the feature analyzer compares and analyzes the compressed circuit response signal and the expected circuit response signal to obtain the fault test result of the tested circuit is not limited. Those skilled in the art can set it according to actual conditions and needs. For example, if the circuit response signal is consistent with the expected circuit response signal, it can be said that the tested circuit is normal, otherwise it is abnormal. The expected circuit response signal can be obtained according to the test vector and the structure of the scan forest, and its specific determination method is not limited in the embodiment of the present disclosure.

[0093] The following is an exemplary introduction to possible implementations of a low-power single stuck-at fault testing device.

[0094] For example, Figure 1 and Figure 3 As shown, in the low-power single fixed fault test device, the phase shifter 20 is directly connected to the output of the multi-stage linear feedback shift register 10, and the output of each phase shifter 20 is connected to a multiplexer, each multiplexer drives a scan tree set, and each output of each of the multiplexers drives a scan tree 410, and each scan tree 410 includes multiple scan chains 420.

[0095] The scan tree set is divided, and all outputs with the same label driven by different multiplexers are allocated to the same scan tree 410 subset, wherein all scan chains 420 in the same scan tree 410 subset are driven by the same clock signal. According to the single stuck-at fault test method, the activated scan tree 410 subset is put into test.

[0096] For example, Figure 3 As shown, a two-input AND gate is added to the external pin of the multi-stage linear feedback shift register 10, and the input end of the two-input AND gate is controlled by an additional vector bit to realize whether the external input pin is used in the test compression process, which is completely different from the traditional test compression tool Tessent, where the external input pin is fixed. The external pin of the embodiment of the present disclosure can be implemented by software definition technology.

[0097] For example, Figure 1 and Figure 3 As shown, the output of the software-defined multi-stage linear feedback shift register 10 is connected to a phase shifter (PS) 20. Each stage of the phase shifter 20 drives a multiplexer 30 (demultiplexer, referred to as DMUX), and each of the multiplexers 30 is used to drive k scan trees 410, each of which includes multiple scan chains 420.

[0098] For example, using Figure 1 , Figure 3 The multi-stage linear feedback shift register 10 shown implements test compression, and all scan trees 410 driven by the same output of all dmuxes are placed in the same scan tree set, wherein all scan chains 420 in the same scan tree set are driven by the same clock signal; a preset seed sequence of the multi-stage linear feedback shift register 10 and an injected additional variable are connected according to a selected primitive polynomial to encode all determined test bits; a control vector is shifted into the multi-stage linear feedback shift register 10 to configure the multi-stage linear feedback shift register 10 into a desired primitive polynomial; and a test signal is placed into the activated scan tree set through the multi-stage linear feedback shift register 10 and the phase shifter 20 according to a single stuck-at fault test.

[0099] Exemplarily, the disclosed embodiment can encode all determined test vectors according to the pre-stored primitive polynomial and the injected additional variables, and process them in order from low to high degrees of the primitive polynomial to determine whether the encoding is correct. The specific operations are as follows:

[0100] If the multi-stage linear feedback shift register 10 without the additional variables cannot encode the determined test code, check whether the primitive polynomial can encode the determined test vector when increasing the external pin (external scan-in pin) from low to high; repeat the above operation until all pre-stored primitive polynomials are tried; if the test still cannot be encoded, abandon the test and regenerate the test by reducing the number of faults selected by the sub-target fault set simplified by dynamic test or changing the target fault.

[0101] The testing method, encoding the determined test vector, comprises:

[0102] All scan trees 410 are divided into multiple scan tree sets, each DMUX drives multiple scan trees 410, and each scan tree 410 subset is driven by a same clock signal; according to the primitive polynomial selected by the multi-stage linear feedback shift register 10, a preset seed sequence is shifted into the selected multi-stage linear feedback shift register 10; each scan tree 410 group is activated sequentially, and only one scan tree 410 subset of the variable input by the external input pin is activated during the scan placement, and the entire test application process is controlled by the gating logic.

[0103] A linear equation is constructed for each data bit of the test code by using each bit of the multi-stage linear feedback shift register 10 and each bit of data shifted in by the external pin as variables; usually, when s+e≥d b When the linear equation system is determined, the values ​​of the seed and external input variables can satisfy all linear equations, where s, e, and d b They are respectively the number of stages of the multi-stage linear feedback shift register 10, the number of data bits of the external input, and the determination number of the test code; when enough external input variables are added, the external pin can input a constant of all 0s.

[0104] The preset seed sequence is shifted into the multi-stage linear feedback shift register 10. When the coding seed is placed in the first subset of the activated scan tree 410, the additional variable is injected into the multi-stage linear feedback shift register 10. When processing the second subset of the scan tree 410, the value of the multi-stage linear feedback shift register 10 is calculated by the feedback function constructed by placing the external data bit and the primitive polynomial of the multi-stage linear feedback shift register 10 on the basis of the original seed. The above operation is repeated until all the required sufficient external variables are input, after which the external variable is changed to a constant 0, and the equations for determining the positions of all subsequent tests are obtained on this basis.

[0105] For example, Figure 1 , Figure 3 Each of the scan trees 410 includes multiple scan chains 420, which are assumed to be (f 1，1 , f 1，2 , …, f 1，d ), (f 2，1 , f 2，2 , …, f 2，d ),…,(f w，1 , f w，2 , …, f w，d ), the condition scanning unit group (f 1，1 , f 2，1 , …, f w，1 ) In a single-frame combinatorial circuit, there is no identical combinatorial successor, (f 1，2 , f 2，2 , …, f w，2 ) does not contain the same combinational successor in a single frame, ..., scan trigger group (f 1，d , f 2，d , …, f w，d ) does not contain the same combinational successor in the combinational circuit of a single frame. It is not within the technical scope of the embodiments of the present disclosure to quickly implement the scan tree 410 construction with low memory consumption.

[0106] See also Figure 4 , Figure 4 A schematic diagram of a low power single stuck-at fault testing device according to an embodiment of the present disclosure is shown.

[0107] For example, Figure 4 As shown, the response compressor 50 includes a plurality of XOR networks, and the plurality of XOR networks output compressed response signals respectively through a multiplexer MUX, wherein the scan outputs corresponding to the scan tree 410 driven by the same clock signal are connected to the same XOR sub-network, and each XOR sub-network contains a plurality of scan outputs; and the scan chains 420 (f 1，1 , f 1，2 , …, f1，d ), (f 2，1 , f 2，2 , …, f 2，d ),…,(f w，1 , f w，2 , …, f w，d ) meets the following conditions: Scanning unit group (f 1，1 , f 2，1 , …, f w，1 ) In a single frame, the combinational circuit does not contain the same combinational predecessor, (f 1，2 , f 2，2 , …, f w，2 ) does not contain the same combinational predecessor in the combinational circuit of a single frame, ..., the scan trigger group in the combinational circuit of a single frame (f 1，d , f 2，d , …, f w，d ) do not contain the same combined predecessor. If any node c in the two scan chains 1，1 and c 2，1 , c 1，2 and c 2，2 , …, c 1，l and c 2，l The two scan chains 420 may be connected to the same XOR gate 105 because they have no common predecessors in a single frame combinatorial logic circuit.

[0108] For example, Figure 4 As shown, the response compressor 50 has k sub-XOR networks (the same as the number of clock signals in the gated logic), and all scan trees 410 driven by each clock signal construct an XOR sub-network. If the output numbers of each XOR sub-network are O1, O2, ..., O k The response compressor 50 of the embodiment of the present disclosure comprises: max =max(O1, O2, ..., O k ) outputs, the first output of each XOR sub-network is connected to the input of the multiplexer MUX1, the second output of each XOR sub-network is connected to the input of the multiplexer MUX2, and the last output is connected to the multiplexer MUX k (The later multiplexers may not have k inputs);

[0109] Exemplarily, the multiplexers (up to k) in the response compressor 50 have the same control signal as the multiplexer DMUX used at the test stimulus compression structure end, that is, when the test stimulus signal is placed into the subset of the scan tree 410 activated by the clock signal, the response compressor 50 output is open to the corresponding response compressor 50 subnetwork.

[0110] Figure 5 Shows Figure 1 The low power single stuck-at fault test device structure shown is a schematic diagram of the construction of a group of scan trees and corresponding response compressors.

[0111] The present disclosure also provides a low power consumption scan test algorithm, including:

[0112] (1) Scan forest 40, response compressor 50 is constructed, multi-stage linear feedback shift register 10 is inserted and the corresponding test set T is generated, and low power test insertion is performed;

[0113] (2) When the test set T is not empty, the test t in T is moved into the front-end fast cache of the feature analyzer 60, and the seed of t is moved into the decompressor; the repeater of the feature analyzer 60 is used to perform the operations (3) to (6):

[0114] (3) 00…01 is placed into the additional register of the gating logic, the first group of scan trees 410 is activated, and the test response corresponding to the first group of scan trees 410 is selected to be connected to the scan output terminal, and the additional register of the multi-stage linear feedback shift register 10 is placed into the additional control vector set to the corresponding primitive polynomial structure;

[0115] (4) moving the test data into the first set of activated scan trees 410 and moving the response of the previous test back to the feature analyzer 60;

[0116] (5) Shift the additional shift register left by one position; shift the test data into the currently activated scan tree 410 and shift out the response of the previous test; repeat (5) until all k groups of scan trees 410 receive the test signal; (6) set all scan triggers to the functional state and receive the test response.

[0117] The test vector generation unit uses an independent test code generator, including dynamic and static test reduction technology, to generate tests for all faults; for the generated test set, the additional vectors required for encoding the primitive polynomials required for all tests are obtained, and the control vector for controlling the multi-stage linear feedback shift register 10 is generated; it is used to encode all the determined test vectors in the reconfigurable linear feedback shift register multi-stage linear feedback shift register 10 according to the primitive polynomial and the injected additional variables, and generate the required seeds and external input variable assignments.

[0118] An embodiment of the present disclosure also provides a low-power vector compression device, wherein the test device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the test method when executing the computer program.

[0119] It can be seen from the above technical scheme that a low-power vector compression test method and related equipment described in the embodiment of the present disclosure; the test method includes: establishing a scan forest 40; setting all scan chains 420 controlled by the same multiplexer 30 in the same scan tree set; placing a test signal into the activated scan tree set; encoding all the determination vectors in the multi-stage linear feedback shift register 10 according to the primitive polynomial and the injected additional variables, and generating the value of the seed and the additional variables; compressing the test vector; testing according to the compressed test vector, and calculating the test response result. The embodiment of the present disclosure can effectively combine low-power single fixed fault test and determination BIST, and has low hardware overhead, does not bring additional delay overhead, has a simple structure, is convenient for widespread use in the industry, is easy to embed in existing EDA tools, can support pseudo-random testing and determination self-test, and can also be used independently for determination test compression.

[0120] For example, Figure 1 , Figure 3 As shown, the phase shifter 20 (PS) of the embodiment of the present disclosure drives multiple scan inputs, each scan input drives multiple scan trees 410, and each scan tree 410 is composed of multiple scan chains 420. Different from the multiple scan chain 420 architecture used in previous methods, the phase shifter 20 drives the multiplexer 30 at each stage, and each multiplexer 30 drives multiple scan trees 410.

[0121] Compared with a multi-scan chain 420 architecture in which each stage of the PS drives a scan chain 420, the disclosed embodiment can also significantly reduce the size of the phase shifter 20. According to the technology of the disclosed embodiment, each stage of the phase shifter 20 (PS) drives a multiplexer 30DMUX (demultiplexer) instead of a scan chain 420.

[0122] The disclosed embodiment uses a single fixed fault test method. During the test placement of the current scan tree 410 subset, the PPI corresponding to the scan triggers in all other scan trees 410 is fixed to a constant value. The low power test test placement process is as follows: the first group of scan trees 410 is activated, and the other scan chains 420 are solidified (test signals cannot be placed). The scan tree 410 set to the scan chain 420 placement state places the test signal and the additional variable value into the scan chain 420 through the multi-stage linear feedback shift register 10; the solidified scan chain 420 is set to scan all the corresponding scan units to a fixed value. When a group of scan trees 410 receives the test signal, the second group of scan trees 410 is activated, and the remaining scan trees 410 are all solidified, and the above operation steps are continued and the same additional variables are placed in the multi-stage linear feedback shift register 10. This process continues until all scan trees 410 receive the test signal. All scan triggers are set to the capture cycle, and the test response is stored in the scan unit. Repeat the above operation until all tests are processed.

[0123] The low-power test compression technology proposed in the embodiment of the present disclosure can effectively compress the test stimulus data and significantly reduce the test power consumption. The test compression adopts the scan forest 40 and a test compression technology based on the multi-stage linear feedback shift register 10. The above-mentioned low-power test compression structure can be added to each core. The scan input does not require additional pins, and the control signal can be shared.

[0124] The fan-out coefficient of the DMUX used has an impact on the test compression rate. The larger the coefficient, the higher the test compression efficiency. For deterministic BIST, this parameter can be set very large, such as 16 or 32, which helps compress deterministic test data. The gating logic used injects the same set of additional variables into each group of scan trees 410, and all scan tree 410 subsets use the same seed. Increasing this parameter can reduce the mobile power consumption of the test process.

[0125] The embodiment of the present disclosure encodes all the determined test vectors by selecting an appropriate primitive polynomial and an injected additional variable. This method can encode all the determined test vectors. Due to the use of the scan tree 410 structure and the gating technology of the embodiment of the present disclosure, the size of the multi-stage linear feedback shift register 10 can be controlled to be very small, thereby controlling the number of bits of each test seed to be very low. After the primitive polynomial of the multi-stage linear feedback shift register 10 is selected, the control vector of the multi-stage linear feedback shift register 10 can be determined.

[0126] The test compression technique used in the disclosed embodiment injects additional variables. By adopting a new scheme to select the size of the multi-stage linear feedback shift register 10 and the number of additional variables, the amount of data for determining the test vector is minimized. Generally, when a well-designed phase shifter 20 is used, a very small LFSR constructed from primitive polynomials is sufficient to encode all the determined test vectors.

[0127] The original polynomial generation tool used in the disclosed embodiment can process the polynomials of a 128-bit word length computer. According to experimental results, only a very small (no more than 30 bits) multi-stage linear feedback shift register 10 is needed to encode the determined test vectors of all circuits, because the disclosed embodiment adds some additional variables in the multi-stage linear feedback shift register 10 through external pins.

[0128] The disclosed embodiment proposes a new algorithm to select a primitive polynomial with the minimum degree, which can encode all the determined test vectors. The number of determined bits of all determined test vectors is usually different. When some additional variables are injected into the multi-stage linear feedback shift register 10, the method of the disclosed embodiment selects a primitive polynomial with a lower degree to encode all test pairs.

[0129] The disclosed embodiment selects a primitive polynomial with a degree not less than 20. The first consideration is a multi-stage linear feedback shift register 10 without additional variables. If such a multi-stage linear feedback shift register 10 cannot encode the determined vector, then check whether other primitive polynomials with the same degree can encode all determined test vectors; if all multi-stage linear feedback shift registers 10 connected by the primitive polynomials cannot encode the test vector, then consider adding an additional variable to the multi-stage linear feedback shift register 10 connected by each primitive polynomial. It is determined whether there is an unencoded determined test vector in the current multi-stage linear feedback shift register 10.

[0130] If there are still uncoded determination test vectors in the current multi-stage linear feedback shift register 10, then continue to add additional variables to the multi-stage linear feedback shift register 10, and then return to re-determine whether there are uncoded determination test vectors in the current multi-stage linear feedback shift register 10, until the number of additional variables in the multi-stage linear feedback shift register 10 reaches the preset upper limit. The above strategy is adopted until the degree of the primitive polynomial and the number of additional variables are determined. After the primitive polynomial is determined, the data amount of the determination test vector is reduced by using an effective encoding scheme. The encoding seed is first shifted into the multi-stage linear feedback shift register 10. Then the determination test vector is shifted into all scan trees 410 activated by the gate control logic. Each scan input signal drives a group of scan trees 410, but at the same time, only one scan tree 410 driven by each multiplexer 30 is activated. When the seed is placed in the activated scan tree 410 subset, the additional variable is also shifted into the multi-stage linear feedback shift register 10.

[0131] When the activated scan tree 410 subset receives the test data, the scan trees 410 of the first group are solidified. The second group of scan trees 410 is activated, and the scan trees 410 of the other groups are set to the solidified state. When the same additional variables are shifted in, the above scan shift operation is repeated. The repetitive process will continue until all scan trees 410 receive the test data.

[0132] When the test data is placed into the original input, all scan triggers are activated to enter the capture cycle. The method of the embodiment of the present disclosure cannot reduce the power consumption of the capture cycle, but can only reduce the shift power consumption.

[0133] To achieve test response compression, the outputs of all scan chains 420 driven by the same clock signal are connected to the same XOR network. The outputs of all scan chains 420 are connected to the XOR network, and the output of the XOR network is connected to the signature analyzer 60.

[0134] Let L, i, v, S represent the size of the multi-stage linear feedback shift register 10, the clock cycle required to add the external input variable, the number of additional variables and the size of the test code determination bit. Assume that the size of the determination bit at the kth layer is bk, and the additional variable time after the jth cycle is Vj. The necessary conditions that need to be met are L+i﹒v≥S and

[0135] The sum of the size of the multi-stage linear feedback shift register 10 and the total number of additional variables in the multi-stage linear feedback shift register 10 must be greater than the number of bits of the determined vector. Therefore, the condition L+i﹒v≥S must be satisfied. In any clock cycle, the sum of the size of the multi-stage linear feedback shift register 10 and the number of additional variables must be greater than the number of bits of the flip-flop of the transferred test data. In addition, in order to ensure that the linear equation system has a solution, it must be satisfied conditions.

[0136] When the number of multiplexers 30 (DMUX) increases, the test time does not increase. The reason is that when the number of multiplexers 30 increases, the depth of the scan tree 410 will also decrease. However, when the number of multiplexers 30 increases, the amount of test data can be better compressed, which is also confirmed by the experimental results given later.

[0137] The increase in the number of multiplexers 30 of the disclosed embodiment can better compress the test data for the following reasons: (1) When the scan tree 410 is divided into more subsets, it is easier to find the solution of the linear equation system. Before inserting enough additional variables, the number of linear equation systems will be smaller. Therefore, the additional variables injected into the LFSR can be smaller. (2) If the number of additional variables injected into the LFSR remains unchanged, the depth of the scan tree 410 is reduced and the total number of additional variables can be smaller. In this article, the total number of additional variables T is T≤v﹒d, where v and d are the number of additional variables and the depth of the scan tree 410.

[0138] From the above description, it can be seen that the embodiments of the present disclosure provide a test method for low-power test vector compression, which can effectively combine low-power deterministic BIST, and has low hardware overhead, does not bring additional delay overhead, has a simple structure, is convenient for widespread use in the industry, and is easy to embed in existing EDA tools. It can support pseudo-random testing and deterministic self-testing, and can also be used independently to determine test compression.

[0139] See also Figure 6 , Figure 6 The figure is a schematic diagram of the overall working process of the low power single fixed fault testing device according to the embodiment of the present disclosure.

[0140] like Figure 6As shown, first insert the scanning structure, decompression / response compressor 50, and multi-stage linear feedback shift register 10 into the circuit, then generate the test of the selected target and secondary target faults to generate the test set of the circuit, select a primitive polynomial to encode the generated test set, and perform the encoding test. If the encoding can be completed, the fault test is performed using the encoding test set until all faults are processed and the static compression test on the encoding test set is performed, and the compressed test data is returned. If the current primitive polynomial cannot complete the encoding, other primitive polynomials are tried. If all primitive polynomials cannot be encoded, the current work is terminated and the target fault is regenerated. Determine the control vector of the multi-stage linear feedback shift register 10 and its corresponding additional register control vector. All tests are placed in the circuit in a low-power manner.

[0141] The encoding of the current determined test vector according to the primitive polynomial and the injected external additional variables includes: if the software-defined linear feedback shift register multi-stage linear feedback shift register 10 without the additional variables cannot encode all the determined test vectors, then checking whether other primitive polynomials of the same degree can encode all the determined test vectors; if all the multi-stage linear feedback shift registers 10 connected to the primitive polynomials of the degree cannot encode all the test vectors, then considering adding an external to the multi-stage linear feedback shift register 10 connected to each primitive polynomial.

[0142] If the multi-stage linear feedback shift register 10 cannot encode the determined test vector, then continue to add external pins to the multi-stage linear feedback shift register 10, and then return to re-determine whether the current multi-stage linear feedback shift register 10 can encode the determined test vector, until the number of additional variables in the multi-stage linear feedback shift register 10 reaches the preset upper limit. If the determined test vector still cannot be encoded, a similar strategy is used to try the next primitive polynomial. Repeat the above operation until all primitive polynomials are tried and still cannot be encoded, then abandon the test and put the fault detected by the test back into the undetected fault table. Reselect the target fault and sub-target fault set and repeat the above operation until all faults are processed.

[0143] The low power scan test process may include: dividing all scan chains 420 into multiple subsets, wherein only one subset of scan trees 410 is activated during scan placement, and controlling the entire test placement process through gating logic; shifting the encoding seed into the multi-stage linear feedback shift register 10, and when the encoding seed is placed into the first subset of the activated scan tree 410, injecting additional variables into the multi-stage linear feedback shift register 10.

[0144] When the same additional variable is placed into the multi-stage linear feedback shift register 10, the result in the multi-stage linear feedback shift register 10 is placed into the second activated scan tree 410, and the above process is repeated until all scan trees 410 receive the test vector.

[0145] Exemplarily, the control vector for implementing the multi-stage linear feedback shift register 10 is mainly determined based on the primitive polynomial. For example, the control vector can be placed in an additional register of the multi-stage linear feedback shift register 10 so that the multi-stage linear feedback shift register 10 implements the selected primitive polynomial.

[0146] For example, Figure 2 As shown, the reconfigurable linear feedback shift register multi-stage linear feedback shift register 10 can be simplified into an AND implementation form. Each stage of the multi-stage linear feedback shift register 10 corresponds to a two-input AND gate, one input is connected to the corresponding bit of the additional register, and the other is connected to the output of the corresponding D flip-flop 100 of the multi-stage linear feedback shift register 10. When the corresponding bit of the additional register is 1, the D flip-flop 100 of the corresponding multi-stage linear feedback shift register 10 is connected to the XOR tree; when the control input of the multiplexer is set to 0, the output of the 2-input AND gate is set to 0, and the output of the D flip-flop 100 of the corresponding multi-stage linear feedback shift register 10 is not connected to the XOR tree. The output of the XOR tree is connected to the data input of the D flip-flop 100 of the lowest stage of the multi-stage linear feedback shift register 10. Figure 3 The lowest position of the additional register is 1, indicating that the multi-stage linear feedback shift register 10 is set as the linear feedback shift register with the highest number of stages.

[0147] The multi-stage linear feedback shift register 10 can also be applied to other pseudo-random test code generators. The multi-stage linear feedback shift register 10 proposed in the embodiment of the present disclosure can also support LOC jump delay fault low power consumption test compression; this can be achieved by simply changing the scan forest 40 structure and the test response compression structure.

[0148] Figure 2 As shown, the lowest m positions of the additional register of the multi-stage linear feedback shift register 10 are set to 0, and the multi-stage linear feedback shift register 10 is set to an nm-bit LFSR, and the lowest m bits are used as a linear feedback shift register. At this time, the structure of the phase shifter 20PS remains unchanged, and is only related to all bits of the highest level, so the PS structure remains unchanged.

[0149]

[0150] Table 1: Comparison of experimental results

[0151] Table 1 shows the comparison between the test compression technology of the disclosed embodiment and the commercial tool EDT. The disclosed embodiment uses the external number ext. and the internal scan number SI, ext. / SI is the expected test compression multiple, CTD is the compressed test data capacity (number of bits), FC: fault coverage (%), CPU (s) refers to the ATPG running time (seconds), vec: the number of test codes, CR (times): the test compression multiple. The data shows that the disclosed embodiment technology obtains a test compression of up to about 17,900 times for the circuit1 circuit (the circuit contains about 1.1 million triggers and 11 million gates), and the data capacity is only about 14M bits.

[0152] According to one aspect of the present disclosure, an electronic design automation (EDA) product is provided, wherein the electronic design automation product includes the low-power consumption single stuck-at fault test device.

[0153] See also Figure 7 , Figure 7 A flow chart of a low-power single stuck-at fault testing method according to an embodiment of the present disclosure is shown.

[0154] like Figure 7 As shown, the method includes:

[0155] Step S11, using a multi-stage linear feedback shift register 10 to implement primitive polynomials of different orders, the multi-stage linear feedback shift register 10 is used to output a test vector according to the structure of the scan forest 40 and the target fault type, wherein the scan forest 40 includes a plurality of scan tree sets, each scan tree set includes a plurality of scan trees 410, each scan tree 410 includes a plurality of scan chains 420, each scan chain 420 includes a plurality of cascaded scan triggers, and the scan triggers come from the combinational logic of the circuit under test 70;

[0156] Step S12, performing phase shift processing on the test vector by using the phase shifter 20, wherein the phase shifter 20 includes a multi-level output, and each level of output is used to output a test vector with a different phase to drive a connected multiplexer 30;

[0157] Step S13, using the response compressor 50 to compress the circuit response signal output by the scanning forest 40 to obtain a compressed circuit response signal;

[0158] Step S14 , using the characteristic analyzer 60 to compare and analyze the compressed circuit response signal and the expected circuit response signal, to obtain a fault test result of the circuit under test 70 .

[0159] The multi-stage linear feedback shift register 10 of the embodiment of the present disclosure can realize primitive polynomials of different levels as needed, so as to flexibly output test vectors according to the structure of the scan forest 40 and the target fault type. The phase shifter 20 outputs test vectors of different phases after phase shifting the test vector to drive the connected multiplexer 30, so that the response compressor 50 compresses the circuit response signal output by the scan forest 40 to obtain a compressed circuit response signal, and uses the feature analyzer 60 to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain the fault test result of the circuit under test 70, thereby realizing efficient testing of the circuit under test 70. It can be seen that the low-power single fixed-type fault test device of the embodiment of the present disclosure has higher testing efficiency and higher flexibility.

[0160] In a possible implementation, the multi-stage linear feedback shift register 10 includes a plurality of cascaded D flip-flops 100, and the multi-stage linear feedback shift register 10 is configured as a primitive polynomial of a target level by setting a multiplexer 30 between the D flip-flops 100 at one or more specific positions and the D flip-flops 100 adjacent to the D flip-flops 100 at the specific positions, and controlling the multiplexer 30.

[0161] In a possible implementation, the multi-stage linear feedback shift register 10 includes a first input multiplexer 10130, n cascaded D flip-flops 100, an additional register group, n two-input AND gates 103 and n XOR gates 105, each two-input AND gate 103, each D flip-flop 100 and each XOR gate 105 correspondingly,

[0162] A series control multiplexer 10230 is provided between the mth D flip-flop 100 and the m+1th D flip-flop 100 to realize an n-level primitive polynomial or an nm-level primitive polynomial, an input end of the series control multiplexer 10230 is connected to an output end of the mth D flip-flop 100 and an input end of a two-input AND gate 103 corresponding to the mth D flip-flop 100, and an output end of the series control multiplexer 10230 is connected to an input end of the m+1th D flip-flop 100, wherein n>m and both are positive integers;

[0163] The output end of the kth D flip-flop 100 is connected to one input end of the kth two-input AND gate 103 and the input end of the k+1th D flip-flop 100, the other input end of the kth two-input AND gate 103 is connected to the kth register in the additional register group, the output end of the kth two-input AND gate 103 is connected to one input end of the kth XOR gate 105, the other input end of the kth XOR gate 105 is connected to the output end of the k+1th XOR gate 105, the output end of the 1st XOR gate 105 is connected to the first input end of the first input multiplexer 10130, and the second input end of the first input multiplexer 10130 is used to input a preset seed sequence, wherein k≤n is an integer,

[0164] The control end of the first input multiplexer 10130 and the control end of the stage control multiplexer 10230 are used to receive control signals to configure the stages of the primitive polynomial of the multi-stage linear feedback shift register 10 .

[0165] In one possible implementation, when the value of the kth register in the additional register group is 1, the output of the kth two-input AND gate 103 is the output value of the kth D flip-flop 100; or, when the value of the kth register in the additional register group is 0, the output of the kth two-input AND gate 103 is 0.

[0166] In a possible implementation manner, if the control end of the first input multiplexer 10130 and the control end of the stage control multiplexer 10230 receive a control signal s and a control signal s′ respectively, then,

[0167] When ss'=00, the multi-stage linear feedback shift register 10 is configured as a linear shift register; or

[0168] When ss'=11, the multi-stage linear feedback shift register 10 is configured as a primitive polynomial of nm level, the m-th stage D flip-flop 100 is used as a shift register, and a test vector can be shifted into the connected phase shifter 20; or

[0169] When ss'=10, the multi-stage linear feedback shift register 10 is configured with an n-stage primitive polynomial.

[0170] In a possible implementation, if the multi-stage linear feedback shift register 10 can implement primitive polynomials of n-stage, i1-stage, i2-stage, ..., il-stage, ..., ic-stage, where n>i1>i2>...>il>...>ic, and i1, i2, il, ic are all positive integers,

[0171] When the multi-stage linear feedback shift register 10 is configured with an n-stage primitive polynomial, the control signal of the stage control multiplexer 10230 of stage i1, stage i2, ..., stage il, ..., stage ic is set to 0;

[0172] When the multi-stage linear feedback shift register 10 is configured with an il-stage primitive polynomial, the control signal of the first input multiplexer 10130 is set to 1, and the control signal of the stage control multiplexer 10230 of the i1, i2, ..., il-1 stages is set to 0;

[0173] When the multi-stage linear feedback shift register 10 is configured with a primitive polynomial of stage ic, the control signal of the first input multiplexer 10130 is set to 1, and the control signal of the stage control multiplexer 10230 of stages i1, i2, ..., il-1 is set to 0.

[0174] In a possible implementation manner, the control signal is provided by a control signal register.

[0175] In a possible implementation manner, the multi-stage linear feedback shift register 10 is further connected to a plurality of additional vector input AND gates, and two input terminals of each additional vector input AND gate are used to receive additional vector bits and external input data.

[0176] It should be understood that the low-power single stuck-at fault test method corresponds to the aforementioned low-power single stuck-at fault test device. For its detailed introduction, please refer to the previous description of the device, which will not be repeated here.

[0177] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A low power single stuck fault test device, characterized in that: The device includes a multi-stage linear feedback shift register, a phase shifter, a plurality of multiplexers, a scanning forest, a response compressor and a feature analyzer, wherein: The multi-stage linear feedback shift register is configured to implement primitive polynomials of different orders, and the multi-stage linear feedback shift register is used to output a test vector, and the test vector is related to the structure of the scan forest and the target fault type; Each input end of the phase shifter is connected to a plurality of output nodes of the multi-stage linear feedback shift register, the phase shifter is used to perform phase shift processing on the test vector, the phase shifter includes a multi-stage output, each stage of output is used to output a test vector of a different phase to drive a connected multiplexer; The scan forest includes a plurality of scan tree sets, each scan tree set includes a plurality of scan trees, each scan tree includes a plurality of scan chains, each scan chain includes a plurality of cascaded scan triggers, and the scan triggers are from the combinational logic of the circuit under test; The response compressor is connected to the scanning forest and is used to compress the circuit response signal output by the scanning forest to obtain a compressed circuit response signal; The characteristic analyzer is connected to the response compressor and is used to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain the fault test result of the tested circuit.

2. The device according to claim 1, characterized in that The multi-stage linear feedback shift register includes a plurality of cascaded D flip-flops. By setting a multiplexer between the D flip-flops at one or more specific positions and the D flip-flops adjacent to the D flip-flops at the specific positions, and controlling the multiplexer, the multi-stage linear feedback shift register is configured as a primitive polynomial of a target number of stages.

3. The device according to claim 1, characterized in that The multi-stage linear feedback shift register includes a first input multiplexer, n cascaded D flip-flops, an additional register group, n two-input AND gates and n XOR gates, each two-input AND gate, each D flip-flop and each XOR gate correspondingly, A series control multiplexer is arranged between the mth D flip-flop and the m+1th D flip-flop to realize an n-level primitive polynomial or an nm-level primitive polynomial, an input end of the series control multiplexer is connected to an output end of the mth D flip-flop and an input end of a two-input AND gate corresponding to the mth D flip-flop, and an output end of the series control multiplexer is connected to an input end of the m+1th D flip-flop, wherein n>m and both are positive integers; In the other D flip-flops except the m-th D flip-flop, the output terminal of the k-th D flip-flop is connected to one input terminal of the k-th two-input AND gate and the input terminal of the k+1-th D flip-flop. The other input end of the kth two-input AND gate is connected to the kth register in the additional register group, the output end of the kth two-input AND gate is connected to one input end of the kth XOR gate, the other input end of the kth XOR gate is connected to the output end of the k+1th XOR gate, the output end of the 1st XOR gate is connected to the first input end of the first input multiplexer, and the second input end of the first input multiplexer is used to input a preset seed sequence, wherein k≤n is an integer, and the other input end of the nth XOR gate is connected to the output end of the nth D flip-flop; The control end of the first input multiplexer and the control end of the stage control multiplexer are used to receive control signals to configure the stages of the primitive polynomial of the multi-stage linear feedback shift register.

4. The device according to claim 3, characterized in that When the value of the kth register in the additional register group is 1, the kth two-input AND gate output is the output value of the kth D flip-flop; or, when the value of the kth register in the additional register group is 0, the kth two-input AND gate output is 0.

5. The device according to claim 3, characterized in that If the control end of the first input multiplexer and the control end of the stage control multiplexer receive a control signal s and a control signal s' respectively, then, When ss'=00, the multi-stage linear feedback shift register is configured as a linear shift register; or When ss'=11, the multi-stage linear feedback shift register is configured as a primitive polynomial of nm level, the m-th stage D flip-flop is used as a shift register, and a test vector can be shifted into the connected phase shifter; or When ss'=10, the multi-stage linear feedback shift register is configured with an n-stage primitive polynomial.

6. The device according to claim 3, characterized in that If the multi-stage linear feedback shift register can realize the primitive polynomials of n-stage, i1-stage, i2-stage, ..., il-stage, ..., ic-stage, where n>i1>i2>...>il>...>ic, and i1, i2, il, ic are all positive integers, When the multi-stage linear feedback shift register is configured with an n-stage primitive polynomial, the control signal of the first input multiplexer 101 is 1, and the control signals of the stage control multiplexers of stage i1, stage i2, ..., stage il, ..., stage ic are set to 0; When the multi-stage linear feedback shift register is configured with an il-stage primitive polynomial, the control signals of the first input multiplexer and the il-stage stage control multiplexer are set to 1, and the control signals of the i1, i2, ..., il-1-stage stage control multiplexers are set to 0; When the multi-stage linear feedback shift register is configured with the primitive polynomial of stage ic, the control signals of the first input multiplexer and the stage control multiplexer of stage ic are set to 1, and the control signals of the stage control multiplexers of stages i1, i2, ..., ic-1 are set to 0.

7. The device according to claim 3, characterized in that The control signal is provided by a control signal register.

8. The device according to claim 1, characterized in that The multi-stage linear feedback shift register is also connected to a plurality of additional vector input AND gates, and two input ends of each additional vector input AND gate are used to receive additional vector bits and external input data.

9. An electronic design automation product, characterized in that: The electronic design automation product comprises the low power consumption single stuck-at fault testing device as claimed in any one of claims 1 to 8.

10. A low power single stuck fault testing method, characterized in that: The method comprises: Using a multi-stage linear feedback shift register to implement primitive polynomials of different orders, the multi-stage linear feedback shift register is used to output a test vector according to the structure of a scan forest and a target fault type, wherein the scan forest includes a plurality of scan tree sets, each scan tree set includes a plurality of scan trees, each scan tree includes a plurality of scan chains, each scan chain includes a plurality of cascaded scan triggers, and the scan triggers come from the combinational logic of the circuit under test; Performing phase shift processing on the test vector by using a phase shifter, wherein the phase shifter includes multiple output stages, and each output stage is used to output a test vector with a different phase to drive a connected multiplexer; Using a response compressor to compress the circuit response signal output by the scanning forest to obtain a compressed circuit response signal; A characteristic analyzer is used to compare and analyze the compressed circuit response signal and the expected circuit response signal to obtain a fault test result of the circuit under test.

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