Circuit detection method and device in chip test

Abstract

The invention discloses a circuit detection method and device in chip testing, and belongs to the technical field of chip testing. The method comprises the following steps: respectively distributing corresponding target voltage amplitudes for a plurality of digital input / output (DIO) channels between test equipment and a test circuit board; when the actual voltage value of each DIO channel in the plurality of DIO channels is within a preset range, displaying a prompt that the channel connection is correct on a test interface, and starting a subsequent test program; or when the actual voltage value of at least one DIO channel in the multiple DIO channels is not within the preset range, a prompt of channel connection errors is displayed on the test interface, and starting of the follow-up test program is interrupted. According to the method, after the target voltage amplitude is distributed, the actual voltage value in each channel is detected to judge the line connection state, the test is interrupted in time when the connection fails, test errors caused by line connection errors are effectively prevented, and the chip test efficiency and reliability are improved.

Description

Technical Field

[0001] The present application belongs to the field of chip testing technology, and in particular, relates to a circuit detection method and device in chip testing. Background Art

[0002] In order to improve chip testing efficiency, multi-slot chip testing methods have been widely used.

[0003] In the current multi-station test process, a large number of DIO (digital input / output) lines need to be connected between the tester and the test board. Due to the large number of lines, connection errors are prone to occur during manual wiring, which may cause test failure and affect the accuracy of chip test results.

[0004] Therefore, how to design a method to verify the correctness of line connection in chip testing has become a problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the present application is to provide a circuit detection method and device in chip testing, which can meet the need of detecting the circuit connection status in chip testing.

[0006] In a first aspect, an embodiment of the present application provides a circuit detection method in a chip test, the method comprising:

[0007] Corresponding target voltage amplitudes are respectively allocated to a plurality of digital input and output DIO channels between the test equipment and the test circuit board, and the plurality of DIO channels are used to transmit chip test signals;

[0008] When the actual voltage value of each DIO channel among the multiple DIO channels is within the preset range, a prompt that the channel connection is correct is displayed on the test interface, and the subsequent test program is started; or,

[0009] When the actual voltage value of at least one DIO channel among the multiple DIO channels is out of the preset range, a prompt indicating a channel connection error is displayed on the test interface, and the subsequent test program is interrupted.

[0010] In a possible implementation of the first aspect, when an actual voltage value of at least one DIO channel among the multiple DIO channels is not within a preset range, a prompt of a channel connection error is displayed on a test interface, and a subsequent test program is interrupted and started, which may include the following steps:

[0011] A prompt window containing the DIO channel number with connection error pops up on the test interface. The prompt window is used to guide the operator to check the DIO channel number and repair it.

[0012] In a possible implementation manner of the first aspect, when actual voltage values ​​of the plurality of DIO channels are not within a preset range, the method further includes the following steps:

[0013] In response to the operator clicking the confirmation button in the current prompt window, the next prompt window pops up to display the DIO channel number contained in the next prompt window. One prompt window contains one DIO channel number.

[0014] In a possible implementation manner of the first aspect, the method further includes the following steps:

[0015] In response to the operator clicking the confirmation button in the last prompt window, displaying the first control on the test interface;

[0016] In response to an operator clicking the first control, re-detecting a connection status of each DIO channel;

[0017] When it is detected that the actual voltage value of each DIO channel is within the preset range, a prompt indicating that the line connection is correct is displayed on the test interface, and the subsequent test program is started.

[0018] In a possible implementation of the first aspect, corresponding target voltage amplitudes are respectively allocated to a plurality of digital input and output DIO channels between a test device and a test circuit board, including:

[0019] According to the target voltage amplitude of each DIO channel, the voltage amplitude applied to each DIO channel is adjusted to the target voltage amplitude corresponding to the DIO channel by controlling the opening and closing state of the relay on the test circuit board.

[0020] In a possible implementation of the first aspect, a plurality of relays are provided on the test circuit board, each relay corresponds to a preset power supply, each relay corresponds to a DIO channel, and according to a target voltage amplitude of each DIO channel, the voltage amplitude applied to each DIO channel is adjusted to the target voltage amplitude corresponding to the DIO channel by controlling the opening and closing state of the relay on the test circuit board, and the method includes:

[0021] When the multiple relays are closed one by one in a preset sequence, each DIO channel is connected to the preset power supply corresponding to the DIO channel one by one in sequence.

[0022] In a possible implementation manner of the first aspect, multiple preset power sources are generated by the FOVI100 module.

[0023] In a second aspect, an embodiment of the present application provides a circuit detection device in a chip test, the device comprising:

[0024] A voltage distribution module, used to respectively distribute corresponding target voltage amplitudes to a plurality of digital input and output DIO channels between the test device and the test circuit board, each digital input and output DIO channel being used to transmit a test signal;

[0025] The first detection module is used to display a prompt that the channel connection is correct on the test interface when the actual voltage value of each DIO channel among the multiple DIO channels is within a preset range, and start a subsequent test program;

[0026] The second detection module is used to display a prompt of channel connection error on the test interface and interrupt the start of subsequent test procedures when the actual voltage value of at least one DIO channel among the multiple DIO channels is not within a preset range.

[0027] In a third aspect, an embodiment of the present application provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the computer device implements any one of the implementation methods of the first and second aspects described above.

[0028] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a computer device, it implements any implementation method of the first aspect and the second aspect mentioned above.

[0029] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a computer device, the computer device executes any one of the implementation methods described in the first aspect above.

[0030] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0031] This solution assigns a target voltage amplitude to each DIO channel, monitors its actual voltage value, and determines whether the line is correctly connected based on the actual voltage value: when the actual voltage value is within the preset reasonable range, it can be determined that the line connection is correct; otherwise, it indicates that there may be problems such as wrong connection, disconnection or short circuit, which can interrupt subsequent tests in time and guide personnel to repair. Through this pre-verification solution, the system can identify and prompt any possible line connection errors, avoid test errors caused by wrong or unconnected lines, and thus improve the accuracy and reliability of the overall test. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of an application scenario of a circuit detection method in a chip test provided in an embodiment of the present application;

[0033] Figure 2A schematic diagram of a flow chart of a circuit detection method in a chip test provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a test interface provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of a flow chart of a circuit detection method in a chip test provided by another embodiment of the present application;

[0036] Figure 5 A schematic diagram of a flow chart of a circuit detection method in a chip test provided by another embodiment of the present application;

[0037] Figure 6 A structural device diagram of a circuit test in a chip test provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of the structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] Figure 1 A schematic diagram of an application scenario of a circuit detection method in a chip test provided in an embodiment of the present application is shown.

[0041] like Figure 1 As shown, the scenario includes a test machine A, a test circuit board B, and chips to be tested 1-n. Among them, the test circuit board B is used to carry and connect the chips to be tested, and the test machine A is used to perform automated testing on the chips to be tested on the test circuit board B. The test machine A and the test circuit board B are connected via a cable. In the test setting, the test machine A sends a test signal to the test circuit board B via the cable, receives a response and analyzes it, and evaluates whether the performance and function of the chip to be tested on the test circuit board B meet the expected requirements.

[0042] Exemplarily, the cable between the test machine A and the test circuit board B is a DIO (digital input / output) line. The DIO line is used to connect the DIO module of the test machine A and the chip to be tested, and is responsible for the transmission of digital signals.

[0043] In the actual multi-station test process, multiple DIO lines need to be connected between the tester A and the test circuit board B. However, manual wiring is prone to errors, resulting in incorrect line connection. Such errors may cause the failure of related test items, resulting in errors in the chip test results, affecting the accuracy of the test results.

[0044] In view of the above problems, the present application scheme detects the connection status of the test line before formally executing the test procedure to ensure that the line is correctly connected.

[0045] Figure 2 A schematic flow chart of a circuit detection method in a chip test provided in an embodiment of the present application is shown.

[0046] like Figure 2 As shown, the method may include the following steps.

[0047] S210 , respectively allocating corresponding target voltage amplitudes to a plurality of DIO channels between the test device and the test circuit board.

[0048] by Figure 1 For example, test machine A is an example of a test device, and test circuit board B is an example of a test circuit board. There are usually multiple DIO channels between the test device and the test circuit board, and the multiple DIO channels are used to transmit chip test signals.

[0049] It should be understood that the voltage amplitude refers to the amplitude of the signal waveform, that is, the maximum voltage value of the waveform.

[0050] It should also be understood that each DIO channel corresponds to a target voltage amplitude, and the target voltage amplitude of each DIO channel is pre-set according to test requirements.

[0051] Optionally, different power supplies or signal paths are used to provide voltage for each DIO channel, and relays on the test circuit board are used to control switching of different power supplies or signal paths to allocate corresponding target voltage amplitudes to each DIO channel.

[0052] That is, the relay is connected to a plurality of preset power supplies, and by controlling the closing of the relay, the plurality of preset power supplies are used to provide the required target voltage amplitudes for the corresponding DIO channels respectively.

[0053] Based on the above description, in one implementation, step S210 may include the following steps:

[0054] S211, before the test starts, according to the test requirements, determine the target voltage amplitude required for each DIO channel. The target voltage amplitude required for each DIO channel is pre-set in the system.

[0055] S212, connect the relay to the corresponding power supply or signal path, and ensure that the relay can connect the specific power supply or signal path to the corresponding DIO channel by closing.

[0056] It should be noted that steps S211 and S212 are preparations before testing.

[0057] S213. During the test, according to the target voltage amplitude of each DIO channel, the voltage amplitude applied to each DIO channel is adjusted to the target voltage amplitude corresponding to the DIO channel through the opening and closing state of the relay. This step can be automatically completed by the control system of the test equipment to ensure that each DIO channel receives the correct voltage amplitude at the appropriate time point.

[0058] Optionally, a plurality of relays may be provided on the test circuit board, each relay corresponding to a preset power supply, and each relay corresponding to a DIO channel.

[0059] In the process of voltage distribution, when a plurality of relays are closed one by one in a preset sequence, each DIO channel is connected to a preset power source corresponding to the DIO channel one by one in sequence.

[0060] For example, there are three DIO channels, whose preset target voltage amplitudes are 5V, 3.3V and 2V, and are pre-configured with 5V, 3.3V and 2V power supplies. In the voltage distribution process, first control the closure of relay 1 to connect a 5V power supply to DIO channel 1, then control the closure of relay 2 to connect a 3.3V power supply to DIO channel 2, and finally control the closure of relay 3 to connect a 2V power supply to DIO channel 3.

[0061] As can be seen from the above, through step S210, the control system can automatically and accurately allocate the required voltage amplitude to each DIO channel, reducing the complexity of manual operation and the possibility of manual intervention, reducing the risk of human error, and ensuring the accuracy and reliability of the DIO channel signal.

[0062] S220. When the actual voltage value of each DIO channel among the multiple DIO channels is within the preset range, a prompt indicating that the channel connection is correct is displayed on the test interface, and a subsequent test procedure is started.

[0063] It should be understood that the preset range refers to a preset range of allowable errors, which is usually defined by circuit design requirements or test standards to ensure the reliability and consistency of signal transmission.

[0064] It should also be understood that the preset range may be a percentage of the target voltage amplitude (eg, ±5% of the target voltage amplitude) or a specific value (eg, ±0.2), and the present application does not limit this.

[0065] Check the actual voltage value of each DIO channel one by one to see if it is within the allowable range. After confirming that all channels are connected correctly, the prompt message "Channel connection correct" is displayed on the test interface to inform the operator that all channels are in good condition. After the prompt message is displayed, the system automatically enters the next stage of the test procedure. This ensures that the test is carried out under the premise of correct channel connection and avoids unnecessary test failures.

[0066] S230: When the actual voltage value of at least one DIO channel among the multiple DIO channels is not within the preset range, a prompt indicating a channel connection error is displayed on the test interface, and the subsequent test program is interrupted and started.

[0067] This step is used to handle the situation where the DIO channel connection is abnormal.

[0068] The actual voltage value of each DIO channel is monitored one by one. Once the actual voltage value of a channel is found to be out of the preset range, the channel is immediately marked as abnormal, and a prompt message pops up on the test interface to remind the operator to check and repair the connection problem of the channel. In order to prevent incorrect test data from affecting the test results or damaging the equipment, the system will interrupt the execution of subsequent test programs and wait for the operator to fix the error and retest.

[0069] As can be seen from the above, the method of this application uses the principle of voltage consistency to verify the line connection status: assign a target voltage amplitude to each channel, monitor its actual voltage value, and judge whether the line is correctly connected based on the actual voltage value. When the actual voltage value is within a reasonable range, it means that the line connection is correct; otherwise, it means that there may be problems such as wrong connection, disconnection or short circuit, and subsequent tests are interrupted in time to guide personnel to repair. This solution effectively prevents test errors caused by line connection errors through automated control and standardized verification, and significantly improves the efficiency and reliability of chip testing.

[0070] Figure 3 A schematic diagram of a test interface of a circuit detection method in a chip test provided in an embodiment of the present application is shown.

[0071] Step S230 may include: popping up a prompt window containing the DIO channel number of the connection error on the test interface.

[0072] by Figure 3 For example, during the test, when it is detected that the actual voltage value of at least one DIO channel does not meet the preset range, a prompt window will pop up on the test interface. The window contains the specific DIO channel number (for example Figure 3 DIO channel 2 in the , indicating that a connection error has occurred.

[0073] The prompt window is used to guide the operator to identify the DIO channel with problems and perform necessary inspections and repairs.

[0074] This method significantly improves the efficiency and accuracy of the testing process through automated error prompts and clear repair guidance.

[0075] In one embodiment, when the actual voltage values ​​of the plurality of (at least two) DIO channels do not meet the preset range, step S230 may further include the following steps:

[0076] In response to the operator clicking the confirmation button in the current prompt window, the next prompt window pops up, and the DIO channel number contained in the next prompt window is displayed until the last prompt window pops up.

[0077] It should be understood that a prompt window contains a DIO channel number. That is, a prompt window will only display one DIO channel number. When multiple DIO channels are connected incorrectly, clicking the confirmation button in the prompt pop-up window will prompt the next incorrectly connected channel, and the incorrectly connected channels appear in order during the pop-up window confirmation process.

[0078] In this method, the next prompt window pops up automatically after clicking the confirmation button, ensuring that the operator can handle the errors one by one in the order in which they occurred, systematically repair each error, and avoid omissions.

[0079] Figure 4 A schematic flow chart of a circuit detection method in a chip test provided in an embodiment of the present application is shown.

[0080] like Figure 4 As shown, the method may include the following steps.

[0081] S410: In response to the operator completing the click operation on the confirmation buttons in all prompt windows, displaying a first control in the test interface.

[0082] S420: In response to the operator's click operation on the first control, re-detect the connection status of the plurality of DIO channels.

[0083] The operator's click on the first control indicates that all connection errors have been fixed and the next step of testing is ready. In other words, clicking the first control will trigger the next test phase.

[0084] S430: When it is detected that the actual voltage values ​​of the current multiple DIO channels are all within the preset range, a prompt indicating that the line connection is correct is displayed on the test interface, and the subsequent test program is started.

[0085] This method demonstrates the re-inspection process after the error repair is completed. By automatically displaying controls and re-inspecting, the need for manual intervention is reduced, and the automation and efficiency of the test process are improved.

[0086] The following are listed Figure 5 An example is shown to illustrate the solution of the present application.

[0087] In this example, the method of the present application is performed using an STS8200 test machine. It can be understood that the STS8200 test machine is an example of a test device.

[0088] The STS8200 tester includes FOVI100 module, DIO module and CBIT128 module. Among them, FOVI100 and FPVI modules are used to realize pressure measurement and pressure measurement of chips. The accuracy and range of the two modules are different. Select the appropriate module for testing according to the product test content and characteristics; DIO digital channel module is used to generate digital mode waveforms, high-speed digital transmission, etc.; CBIT128 module provides relay control signals.

[0089] The test equipment and the test circuit board are connected via 8 DIO channels.

[0090] This embodiment includes the following steps:

[0091] S510. Pre-set different waveform voltage amplitudes for the eight DIO channels, and at the same time, allocate different FOVI resources (FOVI resources may include different voltage sources, current sources or signal sources, which are key elements for testing DIO channels) to the eight DIO channels by closing the relay control on the test board, and use the FOVI100 module's function of measuring current and voltage to test the voltage value at each DIO channel.

[0092] S520, preset a specific voltage test card value range for each channel according to the set waveform voltage amplitude, and determine whether the voltage test value of each DIO channel is within the preset voltage range.

[0093] For each DIO channel, the program presets a voltage "card value range" based on the previously set waveform voltage amplitude. This range represents the interval that the voltage value of each channel should fall into under normal circumstances. For example, if the waveform voltage amplitude of a DIO channel is set to 3V, the card value range may be set to 2.9V to 3.1V.

[0094] S530, when the voltage test value is not within the card value range, it means that the DIO line is connected incorrectly or not connected. At this time, a pop-up window "DIOX connect fail" will appear on the test interface of the test machine host, and X represents the specific DIO channel. When multiple channels connect fail, you need to click the confirmation button in the pop-up window to prompt which other channels have connect failed. If you do not confirm the pop-up window, you cannot test the test item as usual. At this time, you need to check the connection circuit of the corresponding DIO channel. After reconnecting, point testing will continue to detect the connection of the DIO line until all channels are connected correctly.

[0095] S540. When the voltage test value is within the card value range, it indicates that the DIO line on the test machine has been correctly connected to the corresponding SMA socket on the test machine board, and connected to the FOVI resource channel on the common end of the relay via the SMA socket. The DIO input signal passes through this circuit and the execution of the DIO foolproof program test statement, and outputs the voltage test value, forming a correct test connection circuit, and the test can be carried out normally.

[0096] The above example uses the method of the present application to effectively test and verify whether the voltage output of each DIO channel is within the set range, ensuring the reliability and accuracy of the test process.

[0097] The above mainly introduces a circuit detection method in a chip test of an embodiment of the present application in conjunction with the accompanying drawings. At the same time, it should be understood that although the various steps in the flowcharts involved in the embodiments described above are displayed in sequence, these steps are not necessarily performed in sequence in the order shown in the figure. Unless clearly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the embodiments described above may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a part of the steps or stages in other steps. The following is an introduction to a device of an embodiment of the present application in conjunction with the accompanying drawings. For the sake of brevity, when introducing the device below, it will be appropriately omitted, and the relevant content can refer to the relevant description in the method above, and will not be repeated.

[0098] Corresponding to the method described in the above embodiment, Figure 6 A structural block diagram of a circuit detection device 600 in a chip test provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0099] Reference Figure 6, the apparatus 600 may include:

[0100] The voltage distribution module 601 is used to distribute corresponding target voltage amplitudes to multiple digital input and output DIO channels between the test equipment and the test circuit board.

[0101] Each digital input and output DIO channel is used to transmit a test signal.

[0102] The first detection module 602 is used to display a prompt indicating that the channel connection is correct on the test interface when the actual voltage value of each DIO channel among the multiple DIO channels is within a preset range, and start a subsequent test program.

[0103] The second detection module 603 is used to display a prompt of channel connection error on the test interface and interrupt the start of subsequent test procedures when the actual voltage value of at least one DIO channel among the multiple DIO channels is not within a preset range.

[0104] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0105] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0106] Figure 7 This is a schematic diagram of the structure of a computer device provided in one embodiment of the present application. Figure 7 As shown, the computer device 1000 includes: at least one processor 1003 ( Figure 7 Only one is shown in the figure), a memory 1001, and a computer program 1002 stored in the memory 1001 and executable on the processor 1003. When the processor 1003 executes the computer program 1002, the above Figure 2Steps S210 to S230 in the method embodiment; or, the processor 1003 implements the above when executing the computer program 1002 Figure 6 Functions of modules 601 to 603 in the device embodiment.

[0107] The processor 1003 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0108] In some embodiments, the memory 1001 may be an internal storage unit of the computer device 1000, such as a hard disk or memory of the computer device 1000. In other embodiments, the memory 1001 may also be an external storage device of the computer device 1000, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the computer device 1000. Further, the memory 1001 may also include both an internal storage unit of the computer device 1000 and an external storage device. The memory 1001 is used to store an operating system, an application program, a boot loader (Boot Loader), data and other programs, such as the program code of the computer program, etc. The memory 1001 may also be used to temporarily store data that has been output or is to be output.

[0109] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by an electronic device, the steps in the above-mentioned method embodiments can be implemented.

[0110] The computer-readable medium may include at least: any entity or device capable of carrying computer program codes to a camera / electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk, or an optical disk. In some jurisdictions, according to legislation and patent practice, a computer-readable medium cannot be an electric carrier signal or a telecommunication signal.

[0111] The present application embodiment provides a computer program product, which includes a computer program, and when the computer program is executed by an electronic device, the steps in the above-mentioned various method embodiments can be implemented. The computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0114] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0115] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0116] In the above description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0117] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0118] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0119] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0120] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0121] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0122] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A circuit detection method in chip testing, characterized in that: include: respectively allocating corresponding target voltage amplitudes to a plurality of digital input and output DIO channels between a test device and a test circuit board, wherein the plurality of DIO channels are used to transmit chip test signals; When the actual voltage value of each DIO channel among the multiple DIO channels is within the preset range, a prompt that the channel connection is correct is displayed on the test interface, and a subsequent test procedure is started; or, When the actual voltage value of at least one DIO channel among the multiple DIO channels is not within the preset range, a prompt of a channel connection error is displayed on the test interface, and the subsequent test program is interrupted.

2. The method according to claim 1, characterized in that: When the actual voltage value of at least one DIO channel among the plurality of DIO channels is not within the preset range, a prompt of a channel connection error is displayed on the test interface, and a subsequent test procedure is interrupted and started, including: A prompt window containing the DIO channel number with a connection error pops up on the test interface, and the prompt window is used to guide the operator to check the DIO channel number and repair it.

3. The method according to claim 2, characterized in that When the actual voltage values ​​of the plurality of DIO channels are not within the preset range, the method further includes: In response to the operator clicking the confirmation button in the current prompt window, the next prompt window pops up to display the DIO channel number contained in the next prompt window. One prompt window contains one DIO channel number.

4. The method according to claim 3, characterized in that The method further comprises: In response to the operator clicking the confirmation button in the last prompt window, displaying the first control on the test interface; In response to an operator clicking operation on the first control, re-detecting the connection status of the plurality of DIO channels; When it is detected that the actual voltage values ​​of the current plurality of DIO channels are all within the preset range, a prompt indicating that the line connection is correct is displayed on the test interface, and the subsequent test program is started.

5. The method according to any one of claims 1 to 4, characterized in that The method allocates corresponding target voltage amplitudes to multiple digital input and output DIO channels between the test equipment and the test circuit board respectively, including: According to the target voltage amplitude of each DIO channel, the voltage amplitude applied to each DIO channel is adjusted to the target voltage amplitude corresponding to the DIO channel by controlling the opening and closing state of the relay on the test circuit board.

6. The method according to any one of claims 1 to 4, characterized in that The test circuit board is provided with a plurality of the relays, each relay corresponds to a preset power supply, and each relay corresponds to a DIO channel. According to the target voltage amplitude of each DIO channel, by controlling the opening and closing state of the relays on the test circuit board, the voltage amplitude applied to each DIO channel is adjusted to the target voltage amplitude corresponding to the DIO channel, including: When the plurality of relays are closed one by one in a preset sequence, each DIO channel is connected to a preset power source corresponding to the DIO channel one by one in sequence.

7. The method according to claim 5, characterized in that The preset power supply is generated by the FOVI100 module.

8. A circuit detection device in chip testing, characterized in that: include: A voltage distribution module, used to respectively distribute corresponding target voltage amplitudes to a plurality of digital input and output DIO channels between the test device and the test circuit board, wherein each digital input and output DIO channel is used to transmit a test signal; A first detection module, configured to display a prompt that the channel connection is correct on a test interface and start a subsequent test procedure when the actual voltage value of each DIO channel among the plurality of DIO channels is within a preset range; The second detection module is used to display a prompt of channel connection error on the test interface and interrupt the start of a subsequent test program when the actual voltage value of at least one DIO channel among the multiple DIO channels is not within the preset range.

9. A computer device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the computer device implements the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a computer device, the method according to any one of claims 1 to 7 is implemented.

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