Trimming voltage source circuit and memory

Abstract

The invention provides a trimmable voltage source circuit which comprises a first current generating circuit used for providing a first current with a positive temperature coefficient; the second current generating circuit is used for providing a second current with a negative temperature coefficient; the current trimming circuit is connected with the first current generating circuit and the second current generating circuit and is used for performing mirror image amplification on the first current and the second current according to a set proportional relation and accumulating the first current and the second current into trimming current with an adjustable temperature coefficient; and the resistance trimming circuit is connected with the output end of the current trimming circuit and is used for converting the trimming current into an output voltage with an adjustable voltage value.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to an adjustable voltage source circuit and a memory using the adjustable voltage source circuit. Background Art

[0002] With the continuous development of integrated circuit process technology, the size of memory cells is shrinking, which makes the area of ​​memory shrink and the capacity expand. Due to the offset of threshold voltage, the reliability of memory chip is easily affected by temperature, resulting in the attenuation of memory cycle erase and write durability. Therefore, in order to reduce the influence of temperature on threshold voltage offset, it is necessary to design a voltage source with adjustable temperature coefficient to meet different temperature changes. Summary of the invention

[0003] In view of this, the present invention provides an adjustable voltage source circuit and a memory, which can adjust the temperature coefficient.

[0004] In a first aspect, the present invention provides an adjustable voltage source circuit, comprising:

[0005] A first current generating circuit, used for providing a first current with a positive temperature coefficient;

[0006] A second current generating circuit, used for providing a second current having a negative temperature coefficient;

[0007] A current trimming circuit, connected to the first current generating circuit and the second current generating circuit, for mirror-amplifying the first current and the second current according to a set proportional relationship and accumulating them into a trimming current with an adjustable temperature coefficient;

[0008] The resistance adjustment circuit is connected to the output end of the current adjustment circuit and is used for converting the adjustment current into an output voltage with an adjustable voltage value.

[0009] Optionally, the current trimming circuit adopts a current mirror structure, including: a first current mirror unit and a second current mirror unit,

[0010] The first current mirror unit comprises N (N≥2) branches, each branch is connected to the first current generating circuit, and is used to mirror-amplify the first current according to different proportional relationships, and each branch has a configurable on / off state;

[0011] The second current mirror unit includes N branches, each branch is connected to the second current generating circuit and is used to mirror-amplify the second current according to different proportional relationships, and each branch has a configurable on / off state.

[0012] Optionally, one of the branches of the first current mirror unit is configured to be always in a conducting state;

[0013] One of the branches of the second current mirror unit is configured to be always in a conducting state;

[0014] The on / off states of the remaining N-1 branches of the first current mirror unit are opposite to the on / off states of the remaining N-1 branches of the second current mirror unit.

[0015] Optionally, each branch of the first current mirror unit includes a PMOS tube and a branch switch.

[0016] The source end of the PMOS tube of each branch of the first current mirror unit is connected to the power supply end,

[0017] A first bias voltage is input to the gate end of the PMOS tube of each branch of the first current mirror unit, and the first bias voltage is provided by the first current generating circuit;

[0018] The drain end of the PMOS tube of each branch of the first current mirror unit is connected to the input end of the branch switch correspondingly, the control end of the branch switch of each branch of the first current mirror unit receives a respective control signal, and the output ends of the branch switches of each branch of the first current mirror unit are connected to each other as the output end of the first current mirror unit;

[0019] Each branch of the second current mirror unit includes a PMOS tube and a branch switch.

[0020] The source end of the PMOS tube of each branch of the second current mirror unit is connected to the power supply end,

[0021] A second bias voltage is input to the gate end of the PMOS tube of each branch of the second current mirror unit, and the second bias voltage is provided by the second current generating circuit;

[0022] The drain end of the PMOS tube of each branch of the second current mirror unit is connected to the input end of the branch switch correspondingly, the control end of the branch switch of each branch of the second current mirror unit receives a respective control signal, and the output ends of the branch switches of each branch of the second current mirror unit are connected to each other as the output end of the second current mirror unit;

[0023] The output end of the first current mirror unit is connected to the output end of the second current mirror unit to serve as the output end of the current trimming circuit.

[0024] Optionally, it further includes: a first control signal generating circuit, used for providing control signals of branch switches in each branch of the first current mirror unit and control signals of branch switches in each branch of the second current mirror unit.

[0025] Optionally, the resistance adjustment circuit includes:

[0026] A second resistor;

[0027] a plurality of adjusting resistors having resistance values ​​in proportional relationship, wherein the second resistor and the plurality of adjusting resistors are connected in series to form a series structure, one end of the series structure is connected to the output end of the current trimming circuit and serves as the output end of the adjustable voltage source circuit, and the other end of the series structure is grounded;

[0028] A plurality of NMOS tubes are connected in parallel corresponding to the plurality of regulating resistors, a drain end and a source end of each NMOS tube are respectively connected to two ends of the corresponding regulating resistor, and a gate end of each NMOS tube receives a respective control signal.

[0029] Optionally, it also includes: a second control signal generating circuit, used for providing a gate control signal of each NMOS tube of the resistance trimming circuit.

[0030] Optionally, the first current generating circuit includes:

[0031] A bandgap reference current source, used for outputting a bandgap reference current with a positive temperature coefficient;

[0032] The bandgap reference current preprocessing unit is used to receive the bandgap reference current and amplify the bandgap reference current.

[0033] Optionally, the bandgap reference current preprocessing unit adopts a current mirror structure, including:

[0034] A first PMOS tube, wherein a source terminal of the first PMOS tube is connected to a power supply terminal, a drain terminal of the first PMOS tube is connected to a gate terminal thereof, and the drain terminal of the first PMOS tube receives the bandgap reference current;

[0035] a second PMOS tube, wherein a source end of the second PMOS tube is connected to a power supply end, and a gate end of the second PMOS tube is connected to a gate end of the first PMOS tube;

[0036] a first NMOS tube, wherein a drain terminal of the first NMOS tube is connected to a drain terminal of the second PMOS tube, a gate terminal of the first NMOS tube is connected to its own drain terminal, and a source terminal of the first NMOS tube is grounded;

[0037] The gate end of the first PMOS tube is also connected to the gate ends of the PMOS tubes of each branch of the first current mirror unit to provide the first bias voltage, and the size of the PMOS tubes of each branch of the first current mirror unit is proportional to the first PMOS tube.

[0038] Optionally, the second current generating circuit includes:

[0039] a third PMOS tube, wherein a source end of the third PMOS tube is connected to the power supply end, and a gate end of the third PMOS tube inputs a third bias voltage;

[0040] A PNP transistor, the emitter of the PNP transistor is connected to the drain of the third PMOS transistor, and the base and collector of the PNP transistor are grounded;

[0041] An operational amplifier, wherein a negative input terminal of the operational amplifier is connected to the emitter of the PNP transistor;

[0042] a fourth PMOS tube, wherein a source end of the fourth PMOS tube is connected to the power supply end, a gate end of the fourth PMOS tube is connected to the output end of the operational amplifier, and a drain end of the fourth PMOS tube is connected to the positive input end of the operational amplifier;

[0043] A first resistor, one end of the first resistor is connected to the drain end of the fourth PMOS tube, and the other end of the first resistor is grounded;

[0044] The gate end of the fourth PMOS tube is also connected to the gate ends of the PMOS tubes of each branch of the second current mirror unit to provide the second bias voltage, and the size of the PMOS tubes of each branch of the second current mirror unit is proportional to the fourth PMOS tube.

[0045] In a second aspect, the present invention provides a memory, comprising the above-mentioned adjustable voltage source circuit.

[0046] The present invention provides an adjustable voltage source circuit, which uses a current adjustment circuit to adjust a first current with a positive temperature coefficient and a second current with a negative temperature coefficient to generate a voltage source with a positive or negative temperature coefficient, wherein the slope of the voltage source is radial and intersects at a temperature point, and the size of the temperature point is adjustable. In addition, the output end resistance is adjusted by a resistance adjustment circuit to adjust the voltage value of the voltage source. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A structural block diagram of an adjustable voltage source circuit according to an embodiment of the present invention;

[0048] Figure 2 is a schematic diagram of the circuit structure of a first current generating circuit according to an embodiment of the present invention;

[0049] Figure 3 is a schematic diagram of the circuit structure of a second current generating circuit according to an embodiment of the present invention;

[0050] Figure 4A schematic diagram of the circuit structure of a current trimming circuit and a resistance trimming circuit according to an embodiment of the present invention;

[0051] Figure 5 FIG. 4 is a schematic diagram of a control signal generating circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0054] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0055] An embodiment of the present invention provides an adjustable voltage source circuit, such as Figure 1 As shown, the voltage source circuit includes a first current generating circuit 10, a second current generating circuit 20, a current trimming circuit 30 and a resistance trimming circuit 40, wherein:

[0056] The first current generating circuit 10 is used to provide a first current with a positive temperature coefficient;

[0057] The second current generating circuit 20 is used to provide a second current having a negative temperature coefficient;

[0058] The current trimming circuit 30 is connected to the first current generating circuit 10 and the second current generating circuit 20, and is used to mirror-amplify the first current and the second current according to a set proportional relationship and accumulate them into a trimming current with an adjustable temperature coefficient;

[0059] The resistance trimming circuit 40 is connected to the output end of the current trimming circuit 30 and is used for converting the trimming current into an output voltage with an adjustable voltage value.

[0060] Further, as an implementation mode, the first current generating circuit 10 includes:

[0061] A bandgap reference current source, used for outputting a bandgap reference current with a positive temperature coefficient;

[0062] The bandgap reference current preprocessing unit is used to receive the bandgap reference current and amplify the bandgap reference current.

[0063] The amplified bandgap reference current is used as the first current finally output by the first current generating circuit 10 .

[0064] Figure 2 A circuit structure of the first current generating circuit 10 is shown. Figure 2 As shown, the bandgap reference current source outputs a bandgap reference current with a positive temperature coefficient, which is denoted as IPTAT. In this embodiment, its expression is:

[0065]

[0066] In formula 1, △V BE is the difference between the base-emitter voltages of the two transistors Q0 and Q1 in the bandgap reference current source circuit, △V BE It has the characteristic of positive temperature coefficient. The number ratio of the two transistors is 1:n. R0 is the resistor connected to the emitter of Q1. V T is the thermal voltage, which is related to temperature and its formula is V T =kT / q, where k is the Boltzmann constant, q is the charge of the electron, and T is the temperature.

[0067] like Figure 2 As shown, the bandgap reference current preprocessing unit adopts a current mirror structure, including: a first PMOS transistor PM3, a second PMOS transistor PM4, and a first NMOS transistor NM2, wherein:

[0068] The source terminal of PM3 is connected to the power supply terminal VDD, the drain terminal of PM3 is connected to its own gate terminal, and the drain terminal of PM3 receives the bandgap reference current IPTAT;

[0069] The source terminal of PM4 is connected to the power supply terminal VDD, the gate terminal of PM4 is connected to the gate terminal of PM3, and the gate terminal voltage of PM4 is recorded as VB1;

[0070] The drain terminal of NM2 is connected to the drain terminal of PM4, the gate terminal of NM2 is connected to its own drain terminal, and the source terminal of NM2 is grounded to VSS.

[0071] The size of PM4 is proportional to that of PM3.

[0072] Further, as an implementation method, Figure 3 As shown, the second current generating circuit 20 includes: a third PMOS transistor PM5, a PNP transistor Q2, an operational amplifier SA, a fourth PMOS transistor PM6, and a first resistor R1, wherein:

[0073] The source terminal of PM5 is connected to the power supply terminal VDD, and the gate terminal of PM5 inputs the third bias voltage VB3, where VB3 can be provided by an external circuit, or can also be obtained from a bandgap reference current source. For example, Figure 2 In the embodiment, the voltage at the OP output terminal of the bandgap reference current source structure can be used as VB3;

[0074] The emitter of Q2 is connected to the drain of the third PMOS tube PM5, and the base and collector of Q2 are grounded;

[0075] The negative input terminal of the operational amplifier SA is connected to the emitter of the PNP transistor Q2;

[0076] The source terminal of PM6 is connected to the power supply terminal VDD, the gate terminal of the fourth PMOS transistor PM6 is connected to the output terminal of the operational amplifier SA, the gate terminal voltage of PM6 is recorded as VB2, and the drain terminal of PM6 is connected to the positive input terminal of the operational amplifier SA;

[0077] One end of the first resistor R1 is connected to the drain end of the fourth PMOS transistor PM6 , and the other end of the first resistor R1 is grounded.

[0078] In the second current generating circuit 20 of the present embodiment, the base-emitter voltage V BE The characteristic of having a negative temperature coefficient is that a second current having a negative temperature coefficient is generated on the resistor R1 through the operational amplifier SA and PM6, which is recorded as ICTAT.

[0079] Its expression is

[0080]

[0081] Further, as an implementation method, Figure 4 As shown, the current trimming circuit 30 adopts a current mirror structure, including: a first current mirror unit 301 and a second current mirror unit 302, wherein:

[0082] The first current mirror unit 301 includes N branches, where N=5, which are respectively used to mirror and amplify the first current IPTAT according to different proportional relationships. Each branch includes a PMOS tube and a branch switch. The PMOS tube is marked as PM7-PM11. The branch switch uses a PMOS tube, which is marked as PM17-PM21. The gate terminal of PM17 is grounded to VSS, PM17 is always turned on, and the gate terminals of PM18-PM21 are connected to control signals S0-S3. Among them,

[0083] The sizes of the PMOS transistors PM7 to PM11 of each branch of the first current mirror unit 301 are proportional to the first PMOS transistor PM3.

[0084] The source terminals of the PMOS transistors PM7-PM11 of each branch of the first current mirror unit 301 are connected to the power supply terminal VDD.

[0085] The gate terminals of the PMOS transistors PM7-PM11 of each branch of the first current mirror unit 301 are connected to the gate terminal of the first PMOS transistor PM3, and the bias voltage VB1 is input.

[0086] The drain ends of the PMOS transistors PM7-PM11 of each branch of the first current mirror unit 301 are connected to the source ends of the branch switches PM17-PM21 correspondingly.

[0087] The gate terminals of the branch switches PM17-PM21 of each branch of the first current mirror unit 301 receive respective control signals.

[0088] The drain ends of the branch switches PM17 to PM21 of each branch of the first current mirror unit 301 are connected to each other as the output end of the first current mirror unit 301;

[0089] The second current mirror unit 302 includes N branches, which is the same as the number of branches of the first current mirror unit 301, where N=5, and is used to mirror and amplify the second current ICTAT according to different proportional relationships. Each branch includes a PMOS tube and a branch switch. The PMOS tube is denoted as PM12 to PM16. The branch switch uses a PMOS tube, denoted as PM22 to PM26. The gate terminal of PM22 is grounded to VSS, PM22 is always turned on, and the gate terminals of PM23 to PM26 are connected to control signals S0N to S3N. Among them,

[0090] The sizes of the PMOS transistors PM12 to PM16 of each branch of the second current mirror unit 302 and the fourth PMOS transistor PM6 are proportional.

[0091] The source terminals of the PMOS transistors PM12 to PM16 of each branch of the second current mirror unit 302 are connected to the power supply terminal VDD.

[0092] The gate terminals of the PMOS transistors PM12 to PM16 of each branch of the second current mirror unit 302 are connected to the gate terminal of the fourth PMOS transistor PM6 and input the bias voltage VB2;

[0093] The drain ends of the PMOS transistors PM12-PM16 of each branch of the second current mirror unit 302 are connected to the source ends of the branch switches PM22-PM26 correspondingly.

[0094] The gate terminals of the branch switches PM22-PM26 of each branch of the second current mirror unit 302 receive respective control signals.

[0095] The drain terminals of the branch switches PM22 to PM26 of each branch of the second current mirror unit 302 are connected to each other as the output terminal of the second current mirror unit 302;

[0096] The output end of the first current mirror unit 301 is connected to the output end of the second current mirror unit 302 to serve as the output end of the current trimming circuit 30 .

[0097] The first current IPTAT with a positive temperature coefficient flows through PMOS tubes PM7 to PM11, and the second current ICTAT with a negative temperature coefficient flows through PMOS tubes PM12 to PM16. The two currents are added at the output end in a certain proportional relationship to form a trimming current Itotal with a positive or negative temperature coefficient. The expression is:

[0098] ltotal=a*IPTAT+b*lCTAT (Formula 3)

[0099] Further, the branch switch of one of the branches of the first current mirror unit 301 is configured to be always in the on state;

[0100] The branch switch of one branch of the second current mirror unit 302 is configured to be always in the on state;

[0101] The control signals of the branch switches of the remaining N-1 branches of the first current mirror unit 301 and the control signals of the branch switches of the remaining N-1 branches of the second current mirror unit 302 are opposite signals.

[0102] In this embodiment, Figure 4 As shown, branch switches PM17 and PM22 are always turned on, and control signals S0-S3 of branch switches PM18-PM21 and control signals S0N-S3N of branch switches PM23-PM26 are opposite signals. The digital signal ITRIM<3:0> can be used to select whether to turn on / off branch switches PM18-PM21, PM23-PM26 to adjust the current Itotal.

[0103] Furthermore, the voltage source circuit of this embodiment further includes: a first control signal generating circuit, configured to provide control signals for branch switches in each branch of the first current mirror unit and control signals for branch switches in each branch of the second current mirror unit.

[0104] Further, as an implementation method, refer to Figure 4 , the resistance adjustment circuit 40 comprises:

[0105] A second resistor R2;

[0106] A plurality of adjusting resistors having proportional resistance values, wherein four adjusting resistors R3 to R6 are shown here, wherein the resistance values ​​of the resistor R3 are proportional to the resistance values ​​of the resistors R4, R5, and R6, and the second resistor R2 is connected in series with R3 to R6 to form a series structure, one end of the series structure is connected to the output end of the current trimming circuit to receive the current Itotal and serve as the output end of the trimmable voltage source circuit to output the voltage Vout, and the other end of the series structure is grounded;

[0107] A plurality of NMOS transistors NM3 to NM6 are connected in parallel corresponding to the regulating resistors R3 to R6, the drain and source of each NMOS transistor are respectively connected to the two ends of the corresponding regulating resistor, and the gate of each NMOS transistor receives a respective control signal.

[0108] The resistance after the resistance trimming circuit 40 is trimmed is recorded as Rtrim. The digital signal RTRIM<3:0> can be used to control the on / off of the MOS transistors NM3 - NM6 , so as to trim the resistance Rtrim.

[0109] The trimmed current Itotal generates an output voltage after passing through the trimming resistor Rtrim, and its expression is:

[0110]

[0111] (Formula 4) Taking partial derivatives of both sides with respect to T, we get

[0112]

[0113] From (Equation 5), it can be seen that the trimmed current has a temperature coefficient that can be positive or negative, and because the resistor is also trimmed, the voltage source has a temperature coefficient and both the temperature coefficient and the voltage value can be trimmed. In addition, the slope of the voltage source after current trimming is radial and intersects at a temperature point, and the size of this temperature point can be changed by modifying the proportional relationship between Rtrim and R1.

[0114] Furthermore, the voltage source circuit of this embodiment further includes: a second control signal generating circuit, which is used to provide a gate control signal for each NMOS tube of the resistance trimming circuit.

[0115] Figure 5The control signals of the branch switches of each branch of the first current mirror unit 301, the control signals of the branch switches of each branch of the second current mirror unit 302, and the gate terminal control signals of each NMOS tube of the resistance trimming circuit are shown.

[0116] An adjustable voltage source circuit provided by an embodiment of the present invention generates a voltage source with a positive or negative temperature coefficient by adjusting a first current with a positive temperature coefficient and a second current with a negative temperature coefficient. The voltage source slope is radial and intersects at a temperature point, and the temperature point is adjustable. In addition, the output resistance is adjusted by a resistance adjustment circuit to adjust the voltage value of the voltage source.

[0117] On the other hand, an embodiment of the present invention further provides a memory, wherein the memory includes the above-mentioned adjustable voltage source circuit.

[0118] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An adjustable voltage source circuit, characterized in that: include: A first current generating circuit, used for providing a first current with a positive temperature coefficient; A second current generating circuit, used for providing a second current having a negative temperature coefficient; A current trimming circuit, connected to the first current generating circuit and the second current generating circuit, for mirror-amplifying the first current and the second current according to a set proportional relationship and accumulating them into a trimming current with an adjustable temperature coefficient; The resistance adjustment circuit is connected to the output end of the current adjustment circuit and is used for converting the adjustment current into an output voltage with an adjustable voltage value.

2. The adjustable voltage source circuit according to claim 1, characterized in that: The current trimming circuit adopts a current mirror structure, including: a first current mirror unit and a second current mirror unit, The first current mirror unit comprises N (N≥2) branches, each branch is connected to the first current generating circuit, and is used to mirror-amplify the first current according to different proportional relationships, and each branch has a configurable on / off state; The second current mirror unit includes N branches, each branch is connected to the second current generating circuit and is used to mirror-amplify the second current according to different proportional relationships, and each branch has a configurable on / off state.

3. The adjustable voltage source circuit according to claim 2, characterized in that: One of the branches of the first current mirror unit is configured to be always in a conducting state; One of the branches of the second current mirror unit is configured to be always in a conducting state; The on / off states of the remaining N-1 branches of the first current mirror unit are opposite to the on / off states of the remaining N-1 branches of the second current mirror unit.

4. The adjustable voltage source circuit according to claim 2, characterized in that: Each branch of the first current mirror unit includes a PMOS tube and a branch switch. The source end of the PMOS tube of each branch of the first current mirror unit is connected to the power supply end, A first bias voltage is input to the gate end of the PMOS tube of each branch of the first current mirror unit, and the first bias voltage is provided by the first current generating circuit; The drain end of the PMOS tube of each branch of the first current mirror unit is connected to the input end of the branch switch correspondingly, the control end of the branch switch of each branch of the first current mirror unit receives a respective control signal, and the output ends of the branch switches of each branch of the first current mirror unit are connected to each other as the output end of the first current mirror unit; Each branch of the second current mirror unit includes a PMOS tube and a branch switch. The source end of the PMOS tube of each branch of the second current mirror unit is connected to the power supply end, A second bias voltage is input to the gate end of the PMOS tube of each branch of the second current mirror unit, and the second bias voltage is provided by the second current generating circuit; The drain end of the PMOS tube of each branch of the second current mirror unit is connected to the input end of the branch switch correspondingly, the control end of the branch switch of each branch of the second current mirror unit receives a respective control signal, and the output ends of the branch switches of each branch of the second current mirror unit are connected to each other as the output end of the second current mirror unit; The output end of the first current mirror unit is connected to the output end of the second current mirror unit to serve as the output end of the current trimming circuit.

5. The adjustable voltage source circuit according to claim 4, characterized in that: Also includes: The first control signal generating circuit is used to provide control signals for the branch switches in each branch of the first current mirror unit and control signals for the branch switches in each branch of the second current mirror unit.

6. The adjustable voltage source circuit according to claim 1, characterized in that: The resistance adjustment circuit comprises: A second resistor; a plurality of adjusting resistors having resistance values ​​in proportional relationship, wherein the second resistor and the plurality of adjusting resistors are connected in series to form a series structure, one end of the series structure is connected to the output end of the current trimming circuit and serves as the output end of the adjustable voltage source circuit, and the other end of the series structure is grounded; A plurality of NMOS tubes are connected in parallel corresponding to the plurality of regulating resistors, a drain end and a source end of each NMOS tube are respectively connected to two ends of the corresponding regulating resistor, and a gate end of each NMOS tube receives a respective control signal.

7. The adjustable voltage source circuit according to claim 6, characterized in that: Also includes: The second control signal generating circuit is used to provide gate terminal control signals of each NMOS tube in the resistance trimming circuit.

8. The adjustable voltage source circuit according to claim 4, characterized in that: The first current generating circuit comprises: A bandgap reference current source, used for outputting a bandgap reference current with a positive temperature coefficient; The bandgap reference current preprocessing unit is used to receive the bandgap reference current and amplify the bandgap reference current.

9. The adjustable voltage source circuit according to claim 8, characterized in that: The bandgap reference current preprocessing unit adopts a current mirror structure, including: A first PMOS tube, wherein a source terminal of the first PMOS tube is connected to a power supply terminal, a drain terminal of the first PMOS tube is connected to a gate terminal thereof, and the drain terminal of the first PMOS tube receives the bandgap reference current; a second PMOS tube, wherein a source end of the second PMOS tube is connected to a power supply end, and a gate end of the second PMOS tube is connected to a gate end of the first PMOS tube; a first NMOS tube, wherein a drain terminal of the first NMOS tube is connected to a drain terminal of the second PMOS tube, a gate terminal of the first NMOS tube is connected to its own drain terminal, and a source terminal of the first NMOS tube is grounded; The gate end of the first PMOS tube is also connected to the gate ends of the PMOS tubes of each branch of the first current mirror unit to provide the first bias voltage, and the size of the PMOS tubes of each branch of the first current mirror unit is proportional to the first PMOS tube.

10. The adjustable voltage source circuit according to claim 4, characterized in that: The second current generating circuit comprises: a third PMOS tube, wherein a source end of the third PMOS tube is connected to the power supply end, and a gate end of the third PMOS tube inputs a third bias voltage; A PNP transistor, the emitter of the PNP transistor is connected to the drain of the third PMOS transistor, and the base and collector of the PNP transistor are grounded; An operational amplifier, wherein a negative input terminal of the operational amplifier is connected to the emitter of the PNP transistor; a fourth PMOS tube, wherein a source end of the fourth PMOS tube is connected to the power supply end, a gate end of the fourth PMOS tube is connected to the output end of the operational amplifier, and a drain end of the fourth PMOS tube is connected to the positive input end of the operational amplifier; A first resistor, one end of the first resistor is connected to the drain end of the fourth PMOS tube, and the other end of the first resistor is grounded; The gate end of the fourth PMOS tube is also connected to the gate ends of the PMOS tubes of each branch of the second current mirror unit to provide the second bias voltage, and the size of the PMOS tubes of each branch of the second current mirror unit is proportional to the fourth PMOS tube.

11. A memory, characterized in that: The memory comprises an adjustable voltage source circuit as claimed in any one of claims 1 to 10.

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