Low latency memory compatible with multi-thread scenarios
By introducing cache control, cache completion and write back logic modules into the memory, data state management is optimized, and memory delay and power consumption problems in multi-threaded scenarios are solved, thereby realizing low latency and efficient data reading and writing.
Patent Information
- Application Number
- CN202411094150.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-01-07
AI Technical Summary
Existing memory has low read and write efficiency in multi-threaded scenarios, resulting in increased latency and increased power consumption, and is incompatible with multi-threaded scenarios.
A low-latency memory compatible with multi-threaded scenarios is designed, including storage modules, cache control modules, cache modules, cache completion logic modules and cache writeback logic modules. By maintaining the data status and storage age of each address bit, it is optimized. Data read and write operations to reduce delay and power consumption.
It realizes low-latency data reading and writing in multi-threaded scenarios, shortens the read and write cycle, improves data reading and writing efficiency, and reduces storage access power consumption.
Smart Images
Figure CN119271122A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of storage technology, and in particular to a low-latency memory compatible with multi-threading scenarios. Background Art
[0002] The storage structure is a very important component of the chip. In the decades since Moore's Law was developed, the speed of the memory has been far lower than the computing speed of the CPU. The von Neumann architecture requires frequent data exchange, which brings bandwidth, latency and power consumption problems, making the memory a bottleneck that limits computing power.
[0003] At present, with the development of artificial intelligence and deep learning, the application of Single Instruction Multiple Data (SIMD) processors is becoming more and more widespread, and partial reading and writing will further reduce the efficiency of memory access. For example, 16 threads are calculated in parallel, and only part of the calculation results are valid. At this time, only part of the results are expected to be updated to the memory. The general steps are as follows: 1) Read out the address data to be written; 2) Splice the valid data to be written with the original data; 3) Write back to the memory. In this way, the efficiency of memory writing becomes lower, resulting in greater read and write delays for subsequent instructions, more severe memory access conflicts, and greater power consumption for storage access. In addition, this solution is not compatible with multi-threaded scenarios. Summary of the invention
[0004] The present invention provides a low-latency memory compatible with multi-threaded scenarios, so as to achieve multi-threaded compatible data reading and writing and reduce data reading and writing delay and storage access power consumption.
[0005] The present invention provides a low-latency memory compatible with multi-threaded scenarios, comprising: A storage module, used for storing historical data; A cache control module, for responding to a target instruction, selecting a target address bit, caching an access address carried in the target instruction to the target address bit, and maintaining the data state and data storage age of each thread in each address bit; responding to a read instruction, determining an access address to be read; A cache module, configured to respond to the target instruction and cache the data of each target thread carried in the target instruction to the target address bit; and respond to the read instruction and read data from the address bit corresponding to the access address to be read; a cache completion logic module, which is respectively connected to the storage module and the cache module in communication, and is used to complete the address bits to be completed in the cache module based on the historical data when the storage module is idle; A cache write-back logic module is respectively connected to the storage module and the cache module for writing the data of the address bits to be written back to the storage module according to the corresponding access address at the idle time of the storage module when the capacity of the cache module exceeds a preset value.
[0006] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the data states include: invalid, data calculating, valid and consistent, and valid and inconsistent; wherein, the invalid is used to represent that the thread in the address bit has no valid data; the data calculating is used to represent that the data to be written by the thread in the address bit in the future is in the calculation pipeline; the valid and consistent is used to represent that the data of the thread in the address bit is consistent with the corresponding data in the storage module; the valid and inconsistent is used to represent that the data of the thread in the address bit is inconsistent with any data in the storage module.
[0007] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the cache control module is specifically used for: For each address bit, if the data state of each thread in the address bit is valid and consistent or invalid, the address bit is used as a candidate address bit; If there are multiple candidate address bits, then select the best candidate address bit from the multiple candidate address bits as the target address bit; When each target thread of the target address bit writes new data, the data status of each target thread in the target address bit is updated to be valid and inconsistent.
[0008] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the optimal candidate address bit is the candidate address bit with the oldest data storage age or the candidate address bit whose data has been read.
[0009] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the cache completion logic module is specifically used for: For each address bit, if the data status of some threads in the address bit is invalid, the address bit is used as the address bit to be completed for data completion; The cache control module is specifically used for: For each of the address bits to be completed, when the data at the address bits to be completed are completed, the data status of each thread of the address bits to be completed is updated to be valid and consistent.
[0010] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the cache control module is specifically used for: When the data of the address bit to be written back is written back to the storage module, the data status of each thread of the address bit to be written back is updated to be valid and consistent.
[0011] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the address bits to be written back are address bits with the oldest data storage age or address bits whose data has been read.
[0012] A low-latency memory compatible with multi-threaded scenarios provided according to the present invention further includes: a forward transmission logic module; the forward transmission logic module is specifically used to: If the read data of the current instruction is the calculation result of the calculation instruction before the current instruction, determining whether the data state of the thread corresponding to the calculation instruction is in data calculation; If the data state of the thread corresponding to the computing instruction is in data computing, prohibiting the current instruction from being issued; If the calculation cycle of the calculation instruction is reached, the calculation result is output to the memory access write port; When the calculation result is being written to the memory access write port, the current instruction is allowed to be issued and the read data is output.
[0013] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the cache control module is specifically used for: When the calculation result of the target instruction is being calculated in the pipeline, the data status of each target thread of the target address bit is updated to data calculation in progress.
[0014] According to a low-latency memory compatible with multi-threaded scenarios provided by the present invention, the storage module is also used for: If there is a thread whose data status is invalid in the address bit corresponding to the access address to be read, data is read from the access address to be read.
[0015] The low-latency memory compatible with multi-threaded scenarios provided by the present invention includes: a storage module, a cache control module, a cache module, a cache completion logic module and a cache write-back logic module. Among them, the storage module is used to store historical data and can realize large-capacity storage; the cache control module is used to respond to target instructions, select target address bits, cache the access address carried in the target instructions to the target address bits, and maintain the data status and data storage age of each thread in each address bit, which can realize thread-by-thread maintenance and is compatible with multi-threaded scenarios; respond to read instructions to determine the access address to be read; the cache module is used to respond to target instructions, cache the data of each target thread carried in the target instruction to the target address bit, and can cache the newly written data into the cache module first; respond to read instructions, read data from the address bit corresponding to the access address to be read, and can quickly read the required data from the cache module, shortening the read and write cycle from three clock cycles to A clock cycle, thereby reducing data read and write delay; a cache completion logic module, which is respectively connected to the storage module and the cache module for communication, and is used to complete the address bits to be completed in the cache module based on historical data at the idle time of the storage module, so that most of the data can be read from the completed cache module, which can improve data read and write efficiency and reduce data read and write delay; a cache write-back logic module, which is respectively connected to the storage module and the cache module for communication, and is used to write the data of the address bits to be written back to the storage module according to the corresponding access address at the idle time of the storage module when the capacity of the cache module exceeds the preset value, because most of the data can be read from the cache module, and the write frequency of the storage module is reduced, access conflicts and storage access power consumption can be reduced. Therefore, the present invention can be compatible with multi-threaded data reading and writing, and reduce data reading and writing delay and storage access power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0017] Figure 1 It is a schematic diagram of the storage structure of a low-latency memory compatible with multi-threaded scenarios provided by an embodiment of the present invention.
[0018] Figure 2 It is a schematic diagram of data state changes provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0020] Combine the following Figure 1-Figure 2 The present invention is described as a low-latency memory compatible with multi-threaded scenarios.
[0021] Please refer to Figure 1 , Figure 1 Schematic diagram of the storage structure of a low-latency memory compatible with multi-threaded scenarios provided by an embodiment of the present invention. Figure 1 As shown, the low-latency memory compatible with multi-threaded scenarios includes: a storage module 1, a cache control module 2, a cache module 3, a cache completion logic module 4 and a cache write-back logic module 5.
[0022] The following is a detailed description of each module of the low-latency memory compatible with multi-threaded scenarios.
[0023] Storage module 1 is used to store historical data.
[0024] Specifically, the storage module 1 may be a static random access memory (SRAM), which can realize large-capacity storage. The present embodiment is not limited thereto, and may also be other large-capacity memories.
[0025] The cache control module 2 is used to respond to the target instruction, select the target address bit, cache the access address carried in the target instruction to the target address bit, and maintain the data status and data storage age of each thread in each address bit (entry); respond to the read instruction and determine the access address to be read.
[0026] Specifically, the cache control module 2 may be a cache controller. The target instruction may be a write instruction, a calculation instruction, a processing instruction, etc. The target address bit may be the optimal address bit selected from the cache module 3. The target instruction carries the access address a. The cache control module 2 responds to the target instruction, selects the optimal address bit from the cache module 3 as the target address bit, and caches the access address a to the target address bit.
[0027] The cache control module 2 can also maintain the data status and data storage age of each thread in each address bit, can implement thread-by-thread maintenance, and is compatible with multi-thread scenarios.
[0028] The read instruction carries the access address to be read, and the cache control module 2 responds to the read instruction to obtain the access address to be read.
[0029] The cache module 3 is used to respond to the target instruction and cache the data of each target thread carried in the target instruction to the target address bit; respond to the read instruction and read the data from the address bit corresponding to the access address to be read.
[0030] Specifically, the cache module can be a cache element with a small depth. The cache module 3 responds to the target instruction, caches the data of each target thread carried in the target instruction to the target address bit, and can cache the newly written data into the cache module first.
[0031] The cache module 3 responds to the read instruction and reads data from the address bit corresponding to the access address to be read, so that the required data can be quickly read from the cache module 3, shortening the read and write cycle from three clock cycles to one clock cycle, thereby reducing data read and write delays.
[0032] The cache completion logic module 4 is respectively connected to the storage module 1 and the cache module 3 for completing the address bits to be completed in the cache module 3 based on the historical data when the storage module 1 is idle.
[0033] Specifically, the cache completion logic module 4 can be composed of logic gate circuits such as comparators, selectors, and NAND gate circuits. The cache completion logic module 4 can obtain the data to be completed from the historical data of the storage module 1 when the storage module 1 is idle, and complete the address bits to be completed in the cache module 3, so that most of the data can be read from the completed cache module 3, which can improve the data reading and writing efficiency and reduce the data reading and writing delay.
[0034] The cache write-back logic module 5 is respectively connected to the storage module 1 and the cache module 3 for writing the data of the address bits to be written back to the storage module 1 according to the corresponding access address at the idle time of the storage module 1 when the capacity of the cache module 3 exceeds a preset value.
[0035] Specifically, the cache write-back logic module 5 can be composed of logic gate circuits such as comparators, selectors, and NAND gate circuits. As the data of multiple target instructions are cached in the cache module 3, the capacity of the cache module 3 may exceed the preset value. When the capacity of the cache module 3 exceeds the preset value, the cache write-back logic module 5 can write the data of the address bit to be written back to the storage module 1 according to the corresponding access address at the idle time of the storage module 1. Since most of the data can be read from the cache module 3 and the write frequency of the storage module 1 is reduced (for example: if the write target of multiple consecutive cycles is the same access address, it will only be written to the storage module 1 once), access conflicts and storage access power consumption can be reduced.
[0036] The low-latency memory compatible with multi-threaded scenarios provided by the embodiment of the present invention includes: a storage module, a cache control module, a cache module, a cache completion logic module and a cache write-back logic module. Among them, the storage module is used to store historical data and can realize large-capacity storage; the cache control module is used to respond to the target instruction, select the target address bit, cache the access address carried in the target instruction to the target address bit, and maintain the data status and data storage age of each thread in each address bit, which can realize thread-by-thread maintenance and is compatible with multi-threaded scenarios; respond to the read instruction to determine the access address to be read; the cache module is used to respond to the target instruction, cache the data of each target thread carried in the target instruction to the target address bit, and can cache the newly written data to the cache module first; respond to the read instruction, read the data from the address bit corresponding to the access address to be read, and can quickly read the required data from the cache module, shortening the read and write cycle from three clock cycles to A clock cycle is realized, thereby reducing the data reading and writing delay; a cache completion logic module is respectively connected to the storage module and the cache module for communicating and completing the address bits to be completed in the cache module based on historical data at the idle time of the storage module, so that most of the data can be read from the completed cache module, which can improve the data reading and writing efficiency and reduce the data reading and writing delay; a cache write-back logic module is respectively connected to the storage module and the cache module for communicating and completing the address bits to be written back to the storage module according to the corresponding access address at the idle time of the storage module when the capacity of the cache module exceeds the preset value. Since most of the data can be read from the cache module and the writing frequency of the storage module is reduced, access conflicts and storage access power consumption can be reduced. Therefore, the embodiment of the present invention can be compatible with multi-threaded data reading and writing, and reduce data reading and writing delays and storage access power consumption.
[0037] Alternatively, if Figure 2 As shown, the data status includes: invalid, data calculation (on the way), valid and consistent (valid_cons) and valid and inconsistent (valid_incons). Invalid is used to indicate that the thread in the address bit has no valid data; data calculation is used to indicate that the data to be written by the thread in the address bit in the future is in the calculation pipeline; valid and consistent is used to indicate that the data of the thread in the address bit is consistent with the corresponding data in storage module 1; valid and inconsistent is used to indicate that the data of the thread in the address bit is inconsistent with any data in storage module 1. ins-issue indicates instruction issuance.
[0038] In one embodiment, the cache control module 2 is specifically used to: For each address bit, if the data status of each thread in the address bit is valid and consistent or invalid, then the address bit is used as a candidate address bit; If there are multiple candidate address bits, then select the best candidate address bit from the multiple candidate address bits as the target address bit; When each target thread of the target address bit writes new data, the data status of each target thread in the target address bit is updated to be valid and inconsistent.
[0039] Specifically, for each address bit, if the data state of each thread in the address bit is any one of valid and consistent and invalid data states, it means that the data of each thread in the address bit already exists in the storage module or there is no valid data, and new data can be written, and the address bit is used as a candidate address bit. If there are multiple candidate address bits, then the best candidate address bit is selected from the multiple candidate address bits as the target address bit. When each target thread of the target address bit writes new data, the data state of each target thread in the target address bit is updated to valid and inconsistent, that is, the data of each target thread in the target address bit is newly written data and has not yet been written back to storage module 1.
[0040] Optionally, the best candidate address bit is a candidate address bit with the oldest data storage age or a candidate address bit from which data has been read.
[0041] In this embodiment, the cache control module can filter out candidate address bits whose data status of each thread is valid and consistent or invalid from multiple address bits, select the best candidate address bit from the multiple candidate address bits as the target address bit, and maintain the data status of each target thread in the target address bit when new data is written to the target address bit, that is, update the data status of each target thread in the target address bit to valid and inconsistent, which can be compatible with multi-threaded writing scenarios.
[0042] In one embodiment, the cache completion logic module 4 is specifically used for: For each address bit, if the data status of some threads in the address bit is invalid, the address bit is used as the address bit to be completed for data completion; The cache control module 2 is specifically used for: For each address bit to be completed, when the address bit to be completed completes data, the data status of each thread of the address bit to be completed is updated to be valid and consistent.
[0043] Specifically, the cache completion logic module 4 can use the address bits with invalid data status of some threads as the address bits to be completed for data completion. That is, there are threads with invalid data status in the address bits to be completed, but not all of them are threads with invalid data status. When the cache control module 2 completes the data of the address bits to be completed, it can update the data status of each thread of the address bits to be completed to be valid and consistent.
[0044] In this embodiment, the cache completion logic module can use the address bits of some threads with invalid data status as the address bits to be completed for data completion, and the cache control module can maintain the data status of each thread of the address bits to be completed during data completion, that is, update the data status of each thread of the address bits to be completed to be valid and consistent. In this way, most of the data can be read from the cache module after completion, which can improve data reading and writing efficiency and reduce data reading and writing delay.
[0045] In one embodiment, the cache control module 2 is specifically used to: When the data of the address bits to be written back are written back to the storage module, the data status of each thread of the address bits to be written back is updated to be valid and consistent.
[0046] Optionally, the address bit to be written back is the address bit with the oldest data storage age or the address bit from which data has been read.
[0047] Exemplarily, when the data of the address bit with the oldest data storage age is written back to the storage module 1, the cache control module 2 can update the data status of each thread of the address bit with the oldest data storage age to be valid and consistent, and the data status of each thread of the address bit at the time of writing back can be maintained. Since the data of the address bit with the oldest data storage age is written back to the storage module 1, the data can be written back to the storage module 1 as late as possible, so that even in a multi-threaded scenario, most data accesses can hit the data stored in the cache module 3, thereby reducing access latency.
[0048] In one embodiment, the low-latency memory compatible with multi-threaded scenarios further includes: a forward transmission logic module 6; the forward transmission logic module 6 is specifically used for: If the read data of the current instruction is the calculation result of the calculation instruction before the current instruction, then determine whether the data state of the thread corresponding to the calculation instruction is in data calculation; If the data state of the thread corresponding to the calculation instruction is in data calculation, the current instruction is prohibited from being issued; If the calculation cycle of the calculation instruction is reached, the calculation result is output to the memory access write port; When the calculation result is being written to the memory access write port, the current instruction is allowed to be issued and the read data is output.
[0049] Exemplarily, two instructions are issued continuously, and the read data of the current instruction is the calculation result of the previous calculation instruction. The forward transmission logic module 6 can determine whether the data state of the thread corresponding to the previous calculation instruction is in data calculation when the read data of the current instruction is the calculation result of the previous calculation instruction, that is, determine whether the data result of the previous calculation instruction is in the calculation pipeline. If the data result of the previous calculation instruction is in the calculation pipeline, it means that the data result of the previous calculation instruction has not been calculated yet, and the current instruction is prohibited from being issued. Assuming that the calculation cycle of the previous calculation instruction is three clock cycles, when three clock cycles are reached, the calculation result of the previous calculation instruction is output to the access memory write port. When the calculation result of the previous calculation instruction is being written in the access memory write port, the current instruction is allowed to be issued, without waiting for the calculation result of the previous calculation instruction to be written, and the read data is directly output. In this way, the increase in delay caused by waiting for data to be written and then read out can be avoided, thereby further reducing the data reading and writing delay.
[0050] In this embodiment, the forward transmission logic module can avoid the increase in delay caused by waiting for data to be written and then read out, thereby further reducing the data reading and writing delay.
[0051] In one embodiment, the cache control module 2 is specifically used to: When the calculation result of the target instruction is being calculated in the pipeline, the data status of each target thread of the target address bit is updated to data calculation in progress.
[0052] Specifically, assuming that the target instruction may require multiple clock cycles to calculate the result, the cache control module 2 can maintain the data status of each target thread at the target address bit when the calculation result of the target instruction is in the calculation pipeline, that is, update the data status of each target thread at the target address bit to data calculation.
[0053] In one embodiment, the storage module 1 is further used for: If there is a thread whose data status is invalid in the address bit corresponding to the access address to be read, data is read from the access address to be read.
[0054] Specifically, the cache module 3 responds to the read instruction, obtains the access address to be read in the read instruction, and determines whether there is a thread with an invalid data state in the address bit corresponding to the access address to be read, that is, determines whether there is valid data in the thread of the address bit. When the storage module 1 has a thread with an invalid data state in the address bit corresponding to the access address to be read, it means that there is no valid data in the thread of the address bit, and the data cannot be read from the thread, so it is necessary to read the data from the access address to be read of the storage module 1. In this way, it can be ensured that the required data can be read.
[0055] In order to more clearly understand the present invention, the working principle of the low-latency memory compatible with multi-threaded scenarios is described below with reference to a specific embodiment.
[0056] (1) A calculation instruction is issued, and the calculation result of the calculation instruction is expected to be stored in sram[a]. This calculation instruction may require multiple clock cycles to calculate the result. The cache control module 2 responds to the calculation instruction. For each address bit, if the data state of each thread in the address bit is any one of the data states of valid and consistent and invalid, the address bit is used as a candidate address bit; if there are multiple candidate address bits, the candidate address bit with the oldest data storage age or the candidate address bit that has been read is selected from the multiple candidate address bits as the target address bit; the access address a carried in the target instruction is cached to the target address bit. Since the calculation result of the calculation instruction is being calculated in the pipeline, the data state of each target thread of the target address bit is updated to data calculation.
[0057] (2) When the calculation cycle of the calculation instruction is reached, that is, the result of the calculation instruction is calculated, when the cache control module 2 writes the calculation result of the calculation instruction to each target thread in the target address bit, the data status of each target thread in the target address bit is updated to be valid and inconsistent.
[0058] (3) When the storage module 1 is idle, the cache completion logic module 4 obtains the data to be completed from the historical data of the storage module 1. The address bits of some threads with invalid data status can be used as the address bits to be completed for data completion, so that most of the data can be read from the completed cache module 3, which can improve the data reading and writing efficiency and reduce the data reading and writing delay. When the cache control module 2 completes the data of the address bits to be completed, it updates the data status of each thread of the address bits to be completed to be valid and consistent.
[0059] (4) Another current instruction is issued. The current instruction needs to access sram[a]. The cache module 3 determines whether sram[a] exists. If sram[a] exists in the cache module 3, and the data status of the thread corresponding to sram[a] is valid and consistent or valid and inconsistent, the calculation result of the previous calculation instruction is read from the cache module 3. If the data status of the thread corresponding to sram[a] is in data calculation, the forward transmission logic module 6 prohibits the current instruction from being issued. When the calculation cycle of the previous calculation instruction is reached, the calculation result of the previous calculation instruction is output to the memory access write port. When the calculation result is being written to the memory access write port, the current instruction is allowed to be issued without waiting for the calculation result of the previous calculation instruction to be written. The calculation result of the previous calculation instruction is directly output. If the data status of the thread corresponding to sram[a] is invalid, data is read from sram[a] of the storage module 1. Due to the existence of a data completion mechanism, this situation is very low frequency.
[0060] (5) Subsequently, many instructions are continuously issued, causing the capacity of the cache module 3 to exceed the preset value, or the number of available address bits of the cache module 3 to be less than the preset number. The cache write-back logic module 5 writes the data of the address bit with the oldest data storage age back to the storage module. When the data of the address bit with the oldest data storage age is written back to the storage module 1, the cache control module 2 can update the data status of each thread of the address bit with the oldest data storage age to be valid and consistent, and can maintain the data status of each thread of the address bit at the time of write-back. Since the data of the address bit with the oldest data storage age is written back to the storage module 1, the data can be written back to the storage module 1 as late as possible, so that even in a multi-threaded scenario, most data accesses can hit the data stored in the cache module 3, thereby reducing access latency.
[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A low-latency memory compatible with multi-threaded scenarios, characterized in that: include: A storage module, used for storing historical data; A cache control module, for responding to a target instruction, selecting a target address bit, caching an access address carried in the target instruction to the target address bit, and maintaining the data state and data storage age of each thread in each address bit; responding to a read instruction, determining an access address to be read; A cache module, configured to respond to the target instruction and cache the data of each target thread carried in the target instruction to the target address bit; and respond to the read instruction and read data from the address bit corresponding to the access address to be read; a cache completion logic module, which is respectively connected to the storage module and the cache module in communication, and is used to complete the address bits to be completed in the cache module based on the historical data when the storage module is idle; A cache write-back logic module is respectively connected to the storage module and the cache module for writing the data of the address bits to be written back to the storage module according to the corresponding access address at the idle time of the storage module when the capacity of the cache module exceeds a preset value.
2. The low-latency memory compatible with multi-threaded scenarios according to claim 1, characterized in that: The data status includes: invalid, data calculating, valid and consistent, and valid and inconsistent; wherein, invalid is used to represent that the thread in the address position has no valid data; data calculating is used to represent that the data to be written by the thread in the address position in the future is in the calculation pipeline; valid and consistent is used to represent that the data of the thread in the address position is consistent with the corresponding data in the storage module; valid and inconsistent is used to represent that the data of the thread in the address position is inconsistent with any data in the storage module.
3. The low-latency memory compatible with multi-threaded scenarios according to claim 2, characterized in that: The cache control module is specifically used for: For each address bit, if the data state of each thread in the address bit is valid and consistent or invalid, the address bit is used as a candidate address bit; If there are multiple candidate address bits, then select the best candidate address bit from the multiple candidate address bits as the target address bit; When each target thread of the target address bit writes new data, the data status of each target thread in the target address bit is updated to be valid and inconsistent.
4. The low-latency memory compatible with multi-threaded scenarios according to claim 3, characterized in that: The optimal candidate address bit is the candidate address bit with the largest data storage age or the candidate address bit from which data has been read.
5. The low-latency memory compatible with multi-threaded scenarios according to claim 2, characterized in that: The cache completion logic module is specifically used for: For each address bit, if the data status of some threads in the address bit is invalid, the address bit is used as the address bit to be completed for data completion; The cache control module is specifically used for: For each of the address bits to be completed, when the data at the address bits to be completed are completed, the data status of each thread of the address bits to be completed is updated to be valid and consistent.
6. The low-latency memory compatible with multi-threaded scenarios according to claim 2, characterized in that: The cache control module is specifically used for: When the data of the address bit to be written back is written back to the storage module, the data status of each thread of the address bit to be written back is updated to be valid and consistent.
7. The low-latency memory compatible with multi-threaded scenarios according to claim 6, characterized in that: The address bit to be written back is the address bit with the oldest data storage age or the address bit whose data has been read.
8. The low-latency memory compatible with multi-threaded scenarios according to claim 2, characterized in that: Also includes: Forward transmission logic module; the forward transmission logic module is specifically used for: If the read data of the current instruction is the calculation result of the calculation instruction before the current instruction, determining whether the data state of the thread corresponding to the calculation instruction is in data calculation; If the data state of the thread corresponding to the computing instruction is in data computing, prohibiting the current instruction from being issued; If the calculation cycle of the calculation instruction is reached, the calculation result is output to the memory access write port; When the calculation result is being written into the memory access write port, the current instruction is allowed to be issued and the read data is output.
9. The low-latency memory compatible with multi-threaded scenarios according to claim 2, characterized in that: The cache control module is specifically used for: When the calculation result of the target instruction is being calculated in the pipeline, the data status of each target thread of the target address bit is updated to data being calculated.
10. The low-latency memory compatible with multi-threaded scenarios according to claim 2, characterized in that: The storage module is also used for: If there is a thread whose data status is invalid in the address bit corresponding to the access address to be read, data is read from the access address to be read.