CPU memory access optimization control method and system applied to SoC system

Abstract

The present invention relates to the field of intelligent control technology, and discloses a CPU memory access optimization control method and system applied to a SoC system, including: when the CPU triggers a first memory access command, a memory access pass-through module performs a format conversion operation on the first memory access command according to a protocol supported by the memory to obtain a second memory access command and provides it to a comprehensive arbitration module, the comprehensive arbitration module arbitrates the second memory access command and sends the second memory access command to the memory according to the arbitration result, so that the memory responds to the second memory access command. It can be seen that the present invention optimizes the memory access path of the CPU in the memory access architecture, and directly participates in the last step of arbitration before sending it to the memory after performing protocol conversion on the memory access command triggered by the CPU through the memory access pass-through module, and no longer participates in packaging and arbitration operations between other hosts, which can effectively reduce the memory access delay of the CPU in the SoC system to further improve the performance of the CPU.

Description

Technical Field

[0001] The present invention relates to the field of intelligent control technology, and in particular to a CPU memory access optimization control method and system applied to a SoC system. Background Art

[0002] As the core control of SoC (System on Chip), the performance of CPU affects the data processing capability of SoC system, and the factors affecting CPU performance mainly include: core architecture, frequency, number of cores, cache size, CPU memory access delay, etc. Among them, CPU memory access delay can be understood as the waiting time required for CPU to access memory. In practical applications, once the product integrated with SoC system is determined, the aforementioned four factors of "core architecture, frequency, number of cores, cache size" are basically determined, so these four factors can be considered to be determined by the product itself, while "memory access delay" is different. It directly reflects the architectural design capability of SoC system. Different architectures are limited by factors such as physical feasibility, bus architecture, memory access path, memory management method, etc., which ultimately lead to large differences in memory access delay. Therefore, it is crucial to shorten memory access delay and reduce the impact of memory access delay on CPU performance.

[0003] In order to shorten the memory access delay, the optimization schemes adopted in the prior art mainly involve: cache optimization scheme, which stores commonly used data in the cache, and the CPU can read data directly from the cache without accessing the memory every time; multi-core parallel optimization scheme, which integrates multiple CPU cores into one chip, and then collaboratively processes data tasks by sharing memory and bus. However, in addition to the optimization of internal cache and the number of cores, in the architectural design of SoC, bus delay is also a bottleneck that cannot be ignored. Reducing the bus delay of the SoC system is also a method to improve CPU performance. The bus delay optimization schemes commonly used in the prior art mainly involve: optimizing the bus structure, reducing the level and distribution of the bus, reducing the complexity of the bus, thereby reducing the bus delay; optimizing the data transmission protocol, reducing the waiting time and processing time during the data transmission process, thereby reducing the bus delay; using parallel processing technology to perform multiple data transmission operations at the same time, thereby reducing the bus delay. In practical applications, the above-mentioned technical solutions can be used alone or in combination to reduce the CPU memory access delay by reducing the bus delay.

[0004] In complex SoC systems, NoC (Network on Chip) architecture is usually adopted (such as Figure 1The advantage of the bus is distributed arbitration, which can effectively solve the common winding problems in the chip layout and routing process and accelerate timing convergence. However, practice has found that the CPU, as a master device on the NoC architecture, has the same processing flow as other master devices when accessing memory: protocol parsing -> packaging -> arbitration -> unpacking. Although the CPU can be set to the highest priority during arbitration within the NoC, the delay caused by the processing flow related to memory access is unavoidable, and thus the CPU memory access delay cannot be effectively reduced.

[0005] It can be seen that how to effectively reduce the memory access delay of the CPU in the SoC system to further improve the performance of the CPU is a technical problem that needs to be solved urgently. Summary of the invention

[0006] The present invention provides a CPU memory access optimization control method and system applied to a SoC system, which can effectively reduce the memory access delay of the CPU in the SoC system to further improve the performance of the CPU.

[0007] In order to solve the above technical problems, the first aspect of the present invention discloses a CPU memory access optimization control method applied to a SoC system, wherein the SoC system at least includes a pre-built memory access architecture, wherein the memory access architecture at least includes a comprehensive arbitration module and a memory access pass-through module corresponding to the CPU, and wherein the memory access architecture is at least used to implement the data memory access operation of the CPU facing the target memory, and the method includes:

[0008] When the CPU triggers a first memory access command, the memory access pass-through module performs a format conversion operation on the first memory access command according to a first protocol supported by the target memory to obtain a second memory access command supported by the first protocol, and provides the second memory access command to the comprehensive arbitration module, wherein an operation type of the second memory access command is the same as that of the first memory access command;

[0009] After receiving the second memory access command, the comprehensive arbitration module arbitrates the second memory access command, obtains a first arbitration result corresponding to the second memory access command, and sends the second memory access command to the target memory according to the first arbitration result to trigger the target memory to respond to the second memory access command.

[0010] As an optional implementation, in the first aspect of the present invention, when the operation type of the second memory access command is a read operation type, the target memory responding to the second memory access command includes: the target memory reading the first target data required by the CPU from the data storage space and providing the first target data to the integrated arbitration module;

[0011] And, the method further comprises:

[0012] After receiving the first target data, the comprehensive arbitration module provides the first target data to the memory access direct module;

[0013] The memory access pass-through module performs a format conversion operation on the first target data according to a second protocol supported by the CPU, obtains second target data supported by the second protocol, and provides the second target data to the CPU.

[0014] As an optional implementation, in the first aspect of the present invention, the memory access architecture further includes a memory access control module corresponding to a non-CPU type host, and the memory access architecture is further used to implement a data memory access operation of at least one non-CPU type host toward the target memory;

[0015] The method further comprises:

[0016] For any of the non-CPU type hosts, when the host triggers a third memory access command, the memory access control module corresponding to the host sequentially performs a protocol parsing operation, a packaging operation, a host arbitration operation, and an unpacking operation on the third memory access command triggered by the host, obtains a fourth memory access command corresponding to the host, and provides the fourth memory access command corresponding to the host to the comprehensive arbitration module;

[0017] And, a first cache space corresponding to the CPU is provided at a connection interface between the memory access pass-through module and the comprehensive arbitration module, and / or a second cache space corresponding to all the hosts is provided at a connection interface between the memory access control module and the comprehensive arbitration module; wherein the method further comprises:

[0018] When the comprehensive arbitration module receives any memory access command provided by the memory access direct module and / or the memory access control module, the any memory access command is stored in the corresponding cache space.

[0019] As an optional implementation manner, in the first aspect of the present invention, after receiving the second memory access command, the comprehensive arbitration module arbitrates the second memory access command to obtain a first arbitration result corresponding to the second memory access command, including:

[0020] After receiving the second memory access command, if the second memory access command currently needs to participate in arbitration and there are other memory access commands to be arbitrated in the first cache space and / or the second cache space, the comprehensive arbitration module performs a comprehensive arbitration operation on the second memory access command and at least one of the memory access commands to be arbitrated to obtain a first arbitration result of the second memory access command and a second arbitration result of each of the memory access commands to be arbitrated;

[0021] The sending the second memory access command to the target memory according to the first arbitration result to trigger the target memory to respond to the second memory access command includes:

[0022] If the first arbitration result of the second memory access command indicates that the response condition of the second memory access command is currently met, the comprehensive arbitration module sends the second memory access command to the target memory to trigger the target memory to respond to the second memory access command.

[0023] As an optional implementation, in the first aspect of the present invention, the memory access control module includes an IA module corresponding to each of the hosts, an RA module corresponding to all of the IA modules, and a TA module connected to the RA module;

[0024] Wherein, for any of the IA modules, the IA module is used to perform protocol parsing and packaging operations on the third memory access command triggered by the host corresponding to the IA module, obtain the memory access command packaging result corresponding to the host, and provide the memory access command packaging result corresponding to the host to the RA module;

[0025] The RA module is used to receive the memory access command packaging results respectively sent by at least one of the IA modules, and arbitrate all the received memory access command packaging results to obtain the host arbitration result corresponding to each memory access command packaging result, and provide each memory access command packaging result and its corresponding host arbitration result to the TA module; wherein each memory access command packaging result includes a fourth memory access command corresponding to the corresponding host;

[0026] The TA module is used to complete the unpacking process according to the host arbitration result corresponding to each memory access command packaging result, and send the fourth memory access command corresponding to the corresponding host to the comprehensive arbitration module.

[0027] As an optional implementation, in the first aspect of the present invention, the memory access architecture further includes a bandwidth control module, and the method further includes:

[0028] The bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one of the hosts.

[0029] As an optional implementation, in the first aspect of the present invention, the bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one of the hosts, including:

[0030] If the current first data memory access demand of the CPU indicates that the CPU has a write data demand, the bandwidth control module obtains the amount of data to be written corresponding to the write data demand; wherein the amount of data to be written corresponding to the write data demand is determined based on the current write pointer status in the target memory;

[0031] The bandwidth control module compares the amount of data to be written with a predetermined write operation OT threshold to obtain a comparison result, and adjusts the data writing capability of the CPU according to the comparison result;

[0032] and / or,

[0033] If the CPU's current first data memory access demand indicates that the CPU has a data read demand, the bandwidth control module obtains the current first cache status of the first cache space and the current second cache status of the second cache space, and adjusts the CPU's data read capability according to the first cache status and the second cache status.

[0034] As an optional implementation, in the first aspect of the present invention, the bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one of the hosts, including:

[0035] The bandwidth control module selects a matching comprehensive arbitration strategy according to the current first data memory access demand of the CPU and / or the current second data memory access demand of at least one of the hosts, and provides the comprehensive arbitration strategy to the comprehensive arbitration module; wherein the comprehensive arbitration strategy includes a read-write separation arbitration strategy or a read-write merger arbitration strategy, and the comprehensive arbitration strategy is used as a basis for the comprehensive arbitration module to perform the comprehensive arbitration operation.

[0036] As an optional implementation, in the first aspect of the present invention, the bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one of the hosts, including:

[0037] For at least one of the current second data memory access requirements of the host, the bandwidth control module senses the urgency of the current second data memory access requirement of the host, and if the urgency of the current second data memory access requirement of the host is greater than or equal to a predetermined urgency threshold, then, according to the current operation type corresponding to the current second data memory access requirement of the host, controls the memory access command corresponding to the current second data memory access requirement of the host to enter the high priority channel corresponding to the current operation type;

[0038] and / or,

[0039] For at least one of the hosts' current second data memory access requirements, the bandwidth control module identifies the host identifier corresponding to the memory access command that requires the memory access control module to arbitrate, and determines based on a preset host identifier whether the host corresponding to the host identifier is a target host with adjustable memory access priority; if so, configures the memory access priority of the target host based on the memory access delay allowed by the target host.

[0040] The second aspect of the present invention discloses a CPU memory access optimization control system applied to a SoC system, wherein the SoC system at least includes a pre-built memory access architecture, wherein the memory access architecture at least includes a comprehensive arbitration module and a memory access pass-through module corresponding to the CPU, and wherein the memory access architecture is at least used to implement data memory access operations of the CPU oriented to a target memory;

[0041] The system is used to execute part or all of the steps in the CPU memory access optimization control method applied to the SoC system disclosed in the first aspect of the present invention.

[0042] The third aspect of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute part or all of the steps in the CPU memory access optimization control method applied to the SoC system disclosed in the first aspect of the present invention.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] In the present invention, firstly, the memory access architecture in the SoC system is optimized, and the optimized memory access architecture at least includes a comprehensive arbitration module and a memory access pass-through module corresponding to the CPU, and the memory access architecture is at least used to implement the data memory access operation of the CPU to the target memory. Specifically, when the CPU triggers a first memory access command, the memory access pass-through module in the memory access architecture performs a format conversion operation on the first memory access command according to a first protocol supported by the target memory (such as DDR) to obtain a second memory access command supported by the first protocol, and provides the second memory access command to the comprehensive arbitration module, wherein the operation type of the second memory access command is the same as the operation type of the first memory access command; after receiving the second memory access command, the comprehensive arbitration module arbitrates the second memory access command to obtain a first arbitration result corresponding to the second memory access command, and sends the second memory access command to the target memory according to the first arbitration result, so as to trigger the target memory to respond to the second memory access command, such as writing the target data to be written into the target memory, or reading the target data to be read from the target memory and feeding it back to the CPU. It can be seen that the present invention optimizes the memory access path of the CPU in the memory access architecture. When the CPU triggers a memory access command, the memory access command triggered by the CPU is directly converted into a protocol through the CPU's memory access pass-through module and then provided to the comprehensive arbitration module. The module directly participates in the last arbitration operation before sending it to the memory, and no longer participates in packaging and arbitration operations with other hosts. This can effectively reduce the memory access delay of the CPU in the SoC system to further improve the performance of the CPU. In addition, the CPU will not issue a full-protocol memory access command. Through the protocol conversion operation of the memory access pass-through module, the read and write delays increased by the CPU in the traditional memory access architecture due to the CPU's need to participate in some functions in the bus are reduced, and the design complexity of the memory access pass-through module corresponding to the CPU can also be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 It is a schematic diagram of a traditional memory access architecture disclosed in the prior art;

[0047] Figure 2 It is a schematic diagram of a memory access architecture applied in a SoC system disclosed in an embodiment of the present invention;

[0048] Figure 3 It is a flow chart of a CPU memory access optimization control method applied to a SoC system disclosed in an embodiment of the present invention;

[0049] Figure 4 It is a flow chart of another CPU memory access optimization control method applied to a SoC system disclosed in an embodiment of the present invention;

[0050] Figure 5 It is a schematic diagram of the application of the bandwidth control strategy based on the memory access architecture disclosed in the embodiment of the present invention;

[0051] Figure 6 It is a structural schematic diagram of another CPU memory access optimization control system applied to a SoC system disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or end including a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or ends.

[0054] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0055] The present invention discloses a CPU memory access optimization control method and system applied to a SoC system, wherein the memory access path of the CPU is optimized in a memory access architecture, and after the CPU triggers a memory access command, the memory access command triggered by the CPU is directly converted to a protocol through the memory access direct module of the CPU and provided to a comprehensive arbitration module, and directly participates in the last arbitration operation before being sent to the memory, and no longer participates in packaging and arbitration operations between other hosts, so that the memory access delay of the CPU in the SoC system can be effectively reduced to further improve the performance of the CPU; in addition, the CPU will not issue a full-protocol memory access command, and through the protocol conversion operation of the memory access direct module, while reducing the read and write delays increased by the CPU needing to participate in some functions in the bus in the traditional memory access architecture, the design complexity of the memory access direct module corresponding to the CPU can also be reduced. The following are detailed descriptions.

[0056] In order to better understand the CPU memory access optimization control method applied to the SoC system according to the present invention, the memory access architecture applied to the SoC system according to the present invention is first described. Figure 2 .like Figure 2 As shown, the memory access architecture applied to the SoC system according to the present invention may include at least a comprehensive arbitration module and a memory access pass-through module corresponding to the CPU, and Figure 2 The memory access architecture shown is at least used to implement the data access operation (including read data operation and / or write data operation) of the CPU to the target memory (such as DDR), that is: when the CPU has a memory access requirement, the memory access direct module and the comprehensive arbitration module corresponding to the CPU implement the memory access control of the CPU to the target memory. Furthermore, the memory access architecture applied to the SoC system can also include a memory access control module corresponding to a non-CPU type host, that is: Figure 2 The memory access architecture shown is also used to implement data access operations of at least one non-CPU type host to the target memory, that is: when the non-CPU type host has a memory access requirement, the memory access control module and the integrated arbitration module implement the host's memory access control of the target memory.

[0057] Furthermore, if Figure 2 As shown, the memory access control module corresponding to the non-CPU type host can further include an IA (Initiator Agent) module corresponding to each host, an RA (Router of Arbiter) module corresponding to all IA modules, and a TA (Target Agent) module connected to the RA module. Among them, the IA module, the RA module and the TA module are used to implement the protocol parsing operation, packaging operation, host arbitration operation and unpacking operation of the memory access control module.

[0058] Furthermore, Figure 2The memory access architecture shown can also be integrated with a bandwidth dynamic control function. For ease of understanding, the bandwidth dynamic control function is specifically implemented through a virtualized bandwidth control module in the following embodiments. The bandwidth dynamic control function integrated in the memory access architecture is not only conducive to reducing the situation where the memory access needs of other hosts are not responded to in a timely manner due to the CPU's memory access operations occupying more bandwidth, but also can achieve reasonable utilization of bandwidth resources.

[0059] Furthermore, Figure 2 The memory access architecture shown may also include a cache module located between the comprehensive arbitration module and the target memory, which is used to cache memory access commands after comprehensive arbitration. Furthermore, it may also cache data to be written corresponding to write commands and data read corresponding to read commands.

[0060] It should be noted that Figure 2 Only two hosts (Master0-Master1) are shown for example. The number of hosts may be at least two, and the present invention does not limit the number of hosts.

[0061] Embodiment 1

[0062] See also Figure 3 , Figure 3 1 is a flow chart of a CPU memory access optimization control method applied to a SoC system disclosed in an embodiment of the present invention. Figure 3 The method shown is applied to a SoC system, and the SoC system may include Figure 2 The memory access architecture shown in the figure is based on Figure 3 The described method is at least used to implement the data access operation of the CPU to the target memory, which is not limited in the embodiment of the present invention. Figure 3 As shown, the CPU memory access optimization control method applied to the SoC system may include the following operations:

[0063] 101. When the CPU triggers a first memory access command, the memory access pass-through module performs a format conversion operation on the first memory access command according to a first protocol supported by the target memory to obtain a second memory access command supported by the first protocol, and provides the second memory access command to the comprehensive arbitration module.

[0064] In the embodiment of the present invention, the operation type of the second memory access command is the same as the operation type of the first memory access command, wherein the first memory access command may be a read command or a write command.

[0065] In the embodiment of the present invention, it should be particularly noted that: if the format of the first memory access command issued by the CPU is a format supported by the target memory, there is no need to perform the protocol conversion operation involved in step 101. Optionally, the memory access pass-through module can be an AXI2HIF module, which is used to convert the AXI standard interface protocol supported by the CPU into a standard interface protocol supported by the target memory, such as converting it into the HIF standard interface protocol supported by the double data rate synchronous dynamic random access memory DDR. The CPU will not issue a full-protocol memory access command, so the CPU only needs to issue memory access instructions of INCR1, INCR2, INCR4, WRAP2, and WRAP4, thereby reducing the design complexity of the memory access pass-through module.

[0066] 102. After receiving the second memory access command, the comprehensive arbitration module arbitrates the second memory access command to obtain a first arbitration result corresponding to the second memory access command.

[0067] Among them, the comprehensive arbitration module arbitrates the second memory access command and obtains the first arbitration result corresponding to the second memory access command, which can specifically indicate the response order or response priority of the second memory access command. It should be noted that if the current memory access architecture only receives the above-mentioned first memory access command and there are no other memory access commands to be arbitrated, the arbitration operation involved in step 102 may not be performed.

[0068] 103. The comprehensive arbitration module sends a second memory access command to the target memory according to the first arbitration result, so as to trigger the target memory to respond to the second memory access command.

[0069] In an embodiment of the present invention, after obtaining the first arbitration result corresponding to the second memory access command, the comprehensive arbitration module can determine whether it is necessary to give priority to responding to the second memory access command according to the first arbitration result corresponding to the second memory access command. If so, the second memory access command is sent to the target memory. If not, the second memory access command is cached and participates in the next comprehensive arbitration. Further optionally, if the first arbitration result indicates that it is not necessary to give priority to responding to the second memory access command, when caching the second memory access command to participate in the next comprehensive arbitration, the historical comprehensive arbitration times of the second memory access command can also be cached, so as to provide a comprehensive arbitration reference basis for the comprehensive arbitration module when the subsequent second memory access command continues to participate in arbitration.

[0070] Optional, based on Figure 2When the described memory access architecture realizes the memory access control of the CPU, in the direct access mode provided by the memory access direct access module, the write operation channel and the read operation channel are independent, which is conducive to reducing the occurrence of more CPU read operation delays due to responding to the CPU write operation, and is conducive to improving the response efficiency of the CPU read operation. Further, when the memory access direct access module receives the first memory access command triggered by the CPU, it can first determine the operation type corresponding to the first memory access command, so as to perform subsequent memory access control operations through the matching channel.

[0071] It can be seen that the embodiment of the present invention optimizes the memory access path of the CPU in the memory access architecture. When the CPU triggers a memory access command, the memory access command triggered by the CPU is directly converted into a protocol through the CPU's memory access pass-through module and then provided to the comprehensive arbitration module. The module directly participates in the last arbitration operation before sending it to the memory, and no longer participates in the packaging within the NoC and the arbitration operation between other hosts. This saves the consumption of the CPU's memory access commands within the bus, and can effectively reduce the memory access delay of the CPU in the SoC system to further improve the performance of the CPU. In addition, the CPU will not issue a full-protocol memory access command. Through the protocol conversion operation of the memory access pass-through module, while reducing the read and write delays increased by the CPU in the traditional memory access architecture due to the CPU's need to participate in some functions in the bus, the design complexity of the memory access pass-through module corresponding to the CPU can also be reduced.

[0072] In an optional embodiment, when the operation type of the second memory access command is a read operation type, the target memory responding to the second memory access command may include: the target memory reads the first target data required by the CPU from the data storage space corresponding to the target memory and provides the first target data to the comprehensive arbitration module. In this optional embodiment, the method may also include the following operations:

[0073] After receiving the first target data, the comprehensive arbitration module provides the first target data to the memory access direct module;

[0074] The memory access pass-through module performs a format conversion operation on the first target data according to a second protocol supported by the CPU, obtains second target data supported by the second protocol, and provides the second target data to the CPU.

[0075] In this optional embodiment, if the operation type corresponding to the first memory access command triggered by the CPU is a read operation type, the memory access architecture returns the data that the CPU needs to read according to the process of issuing the memory access command, that is, taking the CPU read operation as an example, the CPU read command is issued to the AXI2HIF module, and after completing the conversion of the CPU AXI standard interface protocol to the HIF standard interface protocol supported by DDR, it directly conducts comprehensive arbitration with the HIF interface of the TA module in the hif_arb module, and sends the read command to the DDR according to the arbitration result, waiting for the DDR to return the read data, and the data is returned to the CPU after the protocol conversion is completed by the AXI2HIF module. Compared with the CPU passing through the bus, the command issuance process reduces command packaging, unpacking, arbitration transmission, and a layer of cross-clock domain, effectively reducing the bus delay of the CPU read operation.

[0076] In another optional embodiment, in combination Figure 2 As shown, the memory access architecture in the SoC system may further include a memory access control module corresponding to a non-CPU type host. In this case, the memory access architecture is also used to implement data memory access operations of at least one non-CPU type host to the target memory. In this optional embodiment, the method may also include:

[0077] For any non-CPU type host, when the host triggers the third memory access command, the memory access control module corresponding to the host performs protocol parsing operation, packing operation, host arbitration operation and unpacking operation on the third memory access command triggered by the host in sequence, obtains the fourth memory access command corresponding to the host, and provides the fourth memory access command corresponding to the host to the comprehensive arbitration module.

[0078] In this optional embodiment, further optionally, a first cache space corresponding to the CPU is provided at the connection interface between the memory access pass-through module and the comprehensive arbitration module, and / or a second cache space corresponding to all hosts is provided at the connection interface between the memory access control module and the comprehensive arbitration module. Further, the first cache space corresponding to the CPU may include a first sub-cache space corresponding to a read command triggered by the CPU and a second sub-cache space corresponding to a write command triggered by the CPU. It can be seen that by setting cache space for different memory access objects and different operation types, it is not only beneficial to expand the comprehensive arbitration mechanism, but also beneficial to ensure the reliability of the comprehensive arbitration module in executing the comprehensive arbitration operation, and reduce the occurrence of abnormalities in the comprehensive arbitration due to the influx of multiple memory access instructions in a short period of time.

[0079] In this optional embodiment, further optionally, the method may also include:

[0080] When the comprehensive arbitration module receives any memory access command provided by the memory access direct module and / or the memory access control module, the any memory access command is stored in the corresponding cache space.

[0081] For example, if the memory access command is a write command triggered by the CPU, the comprehensive arbitration module caches it to the second sub-cache space; if the memory access command is a read command triggered by the CPU, the comprehensive arbitration module caches it to the first sub-cache space.

[0082] It can be seen that this optional embodiment, by setting cache space for different memory access objects and different operation types, is not only conducive to expanding the comprehensive arbitration mechanism, but also conducive to ensuring the reliability of the comprehensive arbitration module in executing the comprehensive arbitration operation, and reducing the occurrence of abnormalities in the comprehensive arbitration caused by the influx of multiple memory access instructions in a short period of time.

[0083] In yet another optional embodiment, after receiving the second memory access command, the comprehensive arbitration module arbitrates the second memory access command to obtain a first arbitration result corresponding to the second memory access command, which may include:

[0084] After receiving the second memory access command, if the second memory access command currently needs to participate in arbitration and there are other memory access commands to be arbitrated in the first cache space and / or the second cache space, the comprehensive arbitration module performs a comprehensive arbitration operation on the second memory access command and at least one memory access command to be arbitrated to obtain a first arbitration result of the second memory access command and a second arbitration result of each memory access command to be arbitrated.

[0085] In this optional embodiment, if the second memory access command currently needs to participate in arbitration and there are other memory access commands to be arbitrated in the first cache space and / or the second cache space, when the comprehensive arbitration module performs a comprehensive arbitration operation, it is preferred to perform a comprehensive arbitration operation on the second memory access command and one of the memory access commands to be arbitrated. This is beneficial to improving the arbitration efficiency of the comprehensive arbitration module, and further beneficial to improving the response efficiency of the SoC system to memory access operations.

[0086] In this optional embodiment, further optionally, the comprehensive arbitration module sends the second memory access command to the target memory according to the first arbitration result to trigger the target memory to respond to the second memory access command, which may include:

[0087] If the first arbitration result of the second memory access command indicates that the response condition of the second memory access command is currently met, the comprehensive arbitration module sends the second memory access command to the target memory to trigger the target memory to respond to the second memory access command.

[0088] It can be seen that this optional embodiment can improve the response reliability and response accuracy of the memory access command.

[0089] In yet another optional embodiment, in combination Figure 2As shown, the memory access control module includes an IA module corresponding to each host, an RA module corresponding to all IA modules, and a TA module connected to the RA module. For any IA module, the IA module is used to perform protocol parsing and packaging operations on the third memory access command triggered by the host corresponding to the IA module, obtain the memory access command packaging result corresponding to the host, and provide the memory access command packaging result corresponding to the host to the RA module;

[0090] The RA module is used to receive the memory access command packaging results respectively sent by at least one IA module, and arbitrate all the received memory access command packaging results to obtain the host arbitration result corresponding to each memory access command packaging result, and provide each memory access command packaging result and its corresponding host arbitration result to the TA module; wherein each memory access command packaging result includes a fourth memory access command corresponding to the corresponding host;

[0091] The TA module is used to complete the unpacking process according to the host arbitration result corresponding to each memory access command packaging result, and send the fourth memory access command corresponding to the corresponding host to the comprehensive arbitration module.

[0092] It can be seen that this optional embodiment can implement memory access control of non-CPU type hosts based on the IA module, the RA modules corresponding to all IA modules, and the RA modules, further expanding the memory access control function of the memory access architecture, which is conducive to expanding the application scenarios of the memory access architecture.

[0093] In yet another optional embodiment, in combination with Figure 2 It can be seen from the description that the memory access architecture in the SoC system may further include a bandwidth control module. The method may further include:

[0094] The bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access demand of the CPU and / or the current second data memory access demand of at least one host.

[0095] It should be noted that the bandwidth control module is not a specific hardware module. Figure 2 A functional module virtualized for the bandwidth control function of the corresponding memory access architecture can be applied to the CPU memory access path and / or the host memory access path, and can also be applied to the comprehensive arbitration module, which is not limited in the embodiment of the present invention.

[0096] It can be seen that this optional embodiment can not only realize direct control of CPU memory access to reduce CPU memory access latency, but also further consider the problem of bandwidth balance, realize dynamic regulation of CPU memory access capability, and reduce the occurrence of real-time device shortages in some special scenarios or special needs. For example: in scenarios where the CPU has high bandwidth and other hosts are not sensitive to bandwidth, more bandwidth can be allocated to the CPU; and for scenarios where real-time devices are working, it is necessary to regulate the CPU's memory access capability to a certain extent to reduce the situation where other hosts with response efficiency requirements are not responded to in time due to the CPU occupying more bandwidth.

[0097] In this optional embodiment, as an optional implementation, the bandwidth control module may obtain a matching target bandwidth control strategy and execute the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one host, which may include:

[0098] If the current first data access demand of the CPU indicates that the CPU has a write data demand, the bandwidth control module obtains the amount of data to be written corresponding to the write data demand; optionally, the amount of data to be written corresponding to the write data demand is determined based on the current write pointer status in the target memory;

[0099] The bandwidth control module compares the amount of data to be written with a predetermined write operation OT (Outstanding) threshold, obtains a comparison result, and adjusts the CPU's write data capability according to the comparison result.

[0100] It can be seen that in this optional embodiment, the low latency brought by the direct memory access architecture corresponding to the CPU will make the CPU's write operation have a higher bandwidth occupancy rate. By monitoring the write pointer sent by the CPU to the target memory, it is determined whether the data corresponding to the write operation triggered by the CPU is actually written to the target memory, thereby ensuring that the write operation OT threshold on the memory access path from the CPU to the target memory is effective, that is: according to the write pointer corresponding to the write data in the target memory, the actual number of incomplete operations of the CPU's current write operation is obtained, and the actual incomplete number is compared with the write operation OT threshold, and then a back pressure signal is generated according to the comparison result to act on the CPU's write data path, thereby realizing dynamic regulation of the CPU's write data capability.

[0101] In this optional embodiment, as another optional implementation, the bandwidth control module may obtain a matching target bandwidth control strategy and execute the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one host, which may include:

[0102] If the CPU's current first data memory access demand indicates that the CPU has a data read demand, the bandwidth control module obtains the current first cache status of the first cache space and the current second cache status of the second cache space, and adjusts the CPU's data read capability according to the first cache status and the second cache status.

[0103] It can be seen that in this optional embodiment, when the CPU triggers a read operation, the memory access pass-through architecture corresponding to the CPU ensures that the CPU has a separate RoB (Re-order Buffer), and the CPU's ability to seize bandwidth is higher than other real-time hosts on the NoC. Therefore, in addition to monitoring the FIFO situation in the RoB corresponding to the CPU, it is necessary to further monitor the FIFO situation in the RoB corresponding to other hosts, so as to combine the two to achieve dynamic regulation of the CPU's ability to read data. For example: if the FIFO situation in the RoB corresponding to other hosts indicates that the FIFO waterline has reached the highest threshold, the read operation OT threshold corresponding to the CPU is adjusted to the lowest to ensure that real-time commands and data inside the NoC are sent first; if the FIFO situation in the RoB corresponding to other hosts indicates that the FIFO waterline has reached the lowest threshold, the read operation OT threshold corresponding to the CPU is adjusted to the highest. In this way, by dynamically adjusting the CPU's ability to read data, the impact of the CPU's bandwidth seizure on the real-time hosts inside the NoC can be reduced.

[0104] In this optional embodiment, as another optional implementation, the bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one host, which may include:

[0105] The bandwidth control module selects a matching comprehensive arbitration strategy according to the current first data memory access demand of the CPU and / or the current second data memory access demand of at least one host, and provides the comprehensive arbitration strategy to the comprehensive arbitration module; wherein the comprehensive arbitration strategy includes a read-write separation arbitration strategy or a read-write merger arbitration strategy, and the comprehensive arbitration strategy is used as the basis for the comprehensive arbitration module to perform the comprehensive arbitration operation.

[0106] It can be seen that this optional embodiment can also provide a variety of comprehensive arbitration mechanisms, realizing flexible selection of comprehensive arbitration mechanisms, and enabling both read-write combined arbitration and read-write separated arbitration.

[0107] In this optional embodiment, as another optional implementation, the bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one host, including:

[0108] For at least one host's current second data memory access demand, the bandwidth control module senses the urgency of the host's current second data memory access demand. If the urgency of the host's current second data memory access demand is greater than or equal to a predetermined urgency threshold, then according to the current operation type corresponding to the host's current second data memory access demand, the memory access command corresponding to the host's current second data memory access demand is controlled to enter a high priority channel corresponding to the current operation type.

[0109] It can be seen that this optional embodiment can also monitor the FIFO data volume inside the real-time host based on the host's emergency memory access strategy. When the FIFO data volume inside the host triggers the preset waterline, the memory access command of the real-time host will enter the high priority read (HPR, High Priotiry Reads) channel, so as to improve the response priority of the real-time host on the target memory side. At the same time, the memory access control module will record the memory access commands entering the high priority read (HPR, High Priotiry Reads) channel. When the amount of memory access commands entering the high priority read (HPR, High Priotiry Reads) channel reaches a pre-configured threshold, the memory access command of the real-time host will be switched to the low priority read (LPR, Low Priotiry Reads) channel.

[0110] In this optional embodiment, as another optional implementation, the bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one host, including:

[0111] For the current second data memory access demand of at least one host, the bandwidth control module identifies the host identifier corresponding to the memory access command that needs to be arbitrated by the memory access control module, and determines whether the host corresponding to the host identifier is a target host with adjustable memory access priority based on the preset host identifier. If so, the memory access priority of the target host is configured according to the memory access delay allowed by the target host.

[0112] It can be seen that in this optional embodiment, a register for identifying the host ID can be added inside the NoC, and the register can be used to enable the host's command to enter the variable priority read (VPR) channel. The register can also be used to configure the memory access delay allowed or accepted by the host memory access command entering the variable priority read channel, so as to provide a reliable reference for adjusting the priority of the host memory access command.

[0113] It should be specially noted that: this optional embodiment discloses five optional bandwidth control strategies. In practical applications, one of the strategies can be selected for execution according to the actual situation. Taking the target memory as DDR as an example, strategy 1 is to control the CPU's write data capability, strategy 2 is to control the CPU's read data capability, strategy 3 is to select a suitable comprehensive arbitration mechanism, strategy 4 is to set the priority of the host memory access command according to the degree of urgency, and strategy 5 is to dynamically adjust the host memory access priority according to the host identifier. The CPU memory access optimization control method applied to the SoC system can realize both the CPU's memory access pass-through control and the host's memory access control, and can also match and execute the corresponding bandwidth control strategy. Figure 4 Further, combined with Figure 2 The memory access architecture shown in the figure can be applied to the above five strategies. Figure 5 As shown, Figure 5 Schematic diagram of the application of the bandwidth control strategy based on the memory access architecture disclosed in the embodiment of the present invention. Figure 4-5 It can be seen that for the CPU, the CPU sends a memory access command to the memory access direct path, and then the memory access direct path determines the operation type of the memory access command, and applies different bandwidth control strategies according to different operation types. If it is a write operation, the write operation capability will be limited according to strategy 1, and the write operation that has been issued will be converted into a HIF write operation; if it is a read operation, the read operation will be limited according to strategy 2, and the read operation that has been issued will be converted into a HIF read operation; for other Masters, when sending a memory access command, first determine whether to enter the urgency mode according to strategy 4, and then the bus IA module performs protocol parsing and packaging on the transmitted memory access command, and the RA module arbitrates the transmission packet. The TA module will perform unpacking and complete the host priority control according to strategy 5. Furthermore, the memory access commands sent by the CPU and other hosts will be arbitrated before entering the DDR. This part can use strategy 3 to select the comprehensive arbitration mechanism.

[0114] Embodiment 2

[0115] The embodiment of the present invention discloses a CPU memory access optimization control system applied to a SoC system, and the SoC system at least comprises Figure 2 The corresponding memory access architecture is described. The system in the embodiment of the present invention is used to execute part or all of the steps in any of the CPU memory access optimization control methods applied to SoC systems described in the first embodiment of the present invention.

[0116] Embodiment 3

[0117] See also Figure 6 , Figure 61 is a schematic diagram of another CPU memory access optimization control system applied to a SoC system disclosed in an embodiment of the present invention. Figure 6 The system shown is used to implement memory access control for the CPU, and further, can also implement memory access control for the host. Figure 6 As shown, the system may include:

[0118] A memory 201 storing executable program codes;

[0119] a processor 202 coupled to the memory 201;

[0120] The processor 202 calls the executable program code stored in the memory 201 to execute the steps of any one of the CPU memory access optimization control methods applied to the SoC system described in the first embodiment of the present invention.

[0121] Embodiment 4

[0122] An embodiment of the present invention discloses a computer storage medium, which stores computer instructions. When the computer instructions are called, they are used to execute the steps of any CPU memory access optimization control method applied to a SoC system described in any one of the first embodiments of the present invention.

[0123] The device embodiments described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, and may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative work.

[0124] Through the specific description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on such an understanding, the above technical solution can be essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0125] Finally, it should be noted that the CPU memory access optimization control method and system applied to the SoC system disclosed in the embodiment of the present invention only discloses the preferred embodiment of the present invention, which is only used to illustrate the technical solution of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A CPU memory access optimization control method applied to a SoC system, characterized in that: The SoC system at least includes a pre-built memory access architecture, the memory access architecture at least includes a comprehensive arbitration module, a memory access pass-through module corresponding to the CPU, and a memory access control module corresponding to a non-CPU type host, the memory access architecture is at least used to implement the data memory access operation of the CPU facing the target memory and implement the data memory access operation of at least one non-CPU type host facing the target memory, and the method includes: When the CPU triggers a first memory access command, the memory access pass-through module performs a format conversion operation on the first memory access command according to a first protocol supported by the target memory to obtain a second memory access command supported by the first protocol, and provides the second memory access command to the comprehensive arbitration module, wherein an operation type of the second memory access command is the same as that of the first memory access command; After receiving the second memory access command, the comprehensive arbitration module arbitrates the second memory access command to obtain a first arbitration result corresponding to the second memory access command, and sends the second memory access command to the target memory according to the first arbitration result to trigger the target memory to respond to the second memory access command; And, the method further includes: for any of the non-CPU type hosts, when the host triggers a third memory access command, the memory access control module corresponding to the host sequentially performs a protocol parsing operation, a packaging operation, a host arbitration operation, and an unpacking operation on the third memory access command triggered by the host, obtains a fourth memory access command corresponding to the host, and provides the fourth memory access command corresponding to the host to the comprehensive arbitration module; The connection interface between the memory access direct access module and the comprehensive arbitration module is provided with a first cache space corresponding to the CPU, and / or the connection interface between the memory access control module and the comprehensive arbitration module is provided with a second cache space corresponding to all the hosts; wherein the method further comprises: When the comprehensive arbitration module receives any memory access command provided by the memory access direct module and / or the memory access control module, the any memory access command is stored in the corresponding cache space.

2. The CPU memory access optimization control method applied to a SoC system according to claim 1, characterized in that: When the operation type of the second memory access command is a read operation type, the target memory responds to the second memory access command by: the target memory reads the first target data required by the CPU from the data storage space and provides the first target data to the comprehensive arbitration module; And, the method further comprises: After receiving the first target data, the comprehensive arbitration module provides the first target data to the memory access direct module; The memory access pass-through module performs a format conversion operation on the first target data according to a second protocol supported by the CPU, obtains second target data supported by the second protocol, and provides the second target data to the CPU.

3. The CPU memory access optimization control method applied to a SoC system according to claim 1, characterized in that: After receiving the second memory access command, the comprehensive arbitration module arbitrates the second memory access command to obtain a first arbitration result corresponding to the second memory access command, including: After receiving the second memory access command, if the second memory access command currently needs to participate in arbitration and there are other memory access commands to be arbitrated in the first cache space and / or the second cache space, the comprehensive arbitration module performs a comprehensive arbitration operation on the second memory access command and at least one of the memory access commands to be arbitrated to obtain a first arbitration result of the second memory access command and a second arbitration result of each of the memory access commands to be arbitrated; The integrated arbitration module sends the second memory access command to the target memory according to the first arbitration result to trigger the target memory to respond to the second memory access command, including: If the first arbitration result of the second memory access command indicates that the response condition of the second memory access command is currently met, the comprehensive arbitration module sends the second memory access command to the target memory to trigger the target memory to respond to the second memory access command.

4. The CPU memory access optimization control method applied to a SoC system according to claim 3, characterized in that: The memory access control module includes an IA module corresponding to each of the hosts, an RA module corresponding to all of the IA modules, and a TA module connected to the RA module; Wherein, for any of the IA modules, the IA module is used to perform protocol parsing and packaging operations on the third memory access command triggered by the host corresponding to the IA module, obtain the memory access command packaging result corresponding to the host, and provide the memory access command packaging result corresponding to the host to the RA module; The RA module is used to receive the memory access command packaging results respectively sent by at least one of the IA modules, and arbitrate all the received memory access command packaging results to obtain the host arbitration result corresponding to each memory access command packaging result, and provide each memory access command packaging result and its corresponding host arbitration result to the TA module; wherein each memory access command packaging result includes a fourth memory access command corresponding to the corresponding host; The TA module is used to complete the unpacking process according to the host arbitration result corresponding to each memory access command packaging result, and send the fourth memory access command corresponding to the corresponding host to the comprehensive arbitration module.

5. The CPU memory access optimization control method applied to a SoC system according to claim 3 or 4, characterized in that: The memory access architecture further includes a bandwidth control module, and the method further includes: The bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data memory access requirement of the CPU and / or the current second data memory access requirement of at least one of the hosts.

6. The CPU memory access optimization control method applied to a SoC system according to claim 5, characterized in that: The bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data access memory requirement of the CPU and / or the current second data access memory requirement of at least one of the hosts, including: If the current first data memory access demand of the CPU indicates that the CPU has a write data demand, the bandwidth control module obtains the amount of data to be written corresponding to the write data demand; wherein the amount of data to be written corresponding to the write data demand is determined based on the current write pointer status in the target memory; The bandwidth control module compares the amount of data to be written with a predetermined write operation OT threshold to obtain a comparison result, and adjusts the data writing capability of the CPU according to the comparison result; and / or, If the CPU's current first data memory access demand indicates that the CPU has a data read demand, the bandwidth control module obtains the current first cache status of the first cache space and the current second cache status of the second cache space, and adjusts the CPU's data read capability according to the first cache status and the second cache status.

7. The CPU memory access optimization control method applied to a SoC system according to claim 5, characterized in that: The bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data access memory requirement of the CPU and / or the current second data access memory requirement of at least one of the hosts, including: The bandwidth control module selects a matching comprehensive arbitration strategy according to the current first data memory access demand of the CPU and / or the current second data memory access demand of at least one of the hosts, and provides the comprehensive arbitration strategy to the comprehensive arbitration module; wherein the comprehensive arbitration strategy includes a read-write separation arbitration strategy or a read-write merger arbitration strategy, and the comprehensive arbitration strategy is used as a basis for the comprehensive arbitration module to perform the comprehensive arbitration operation.

8. The CPU memory access optimization control method applied to a SoC system according to claim 5, characterized in that: The bandwidth control module obtains a matching target bandwidth control strategy and executes the target bandwidth control strategy according to the current first data access memory requirement of the CPU and / or the current second data access memory requirement of at least one of the hosts, including: For at least one of the current second data memory access requirements of the host, the bandwidth control module senses the urgency of the current second data memory access requirement of the host, and if the urgency of the current second data memory access requirement of the host is greater than or equal to a predetermined urgency threshold, then, according to the current operation type corresponding to the current second data memory access requirement of the host, controls the memory access command corresponding to the current second data memory access requirement of the host to enter the high priority channel corresponding to the current operation type; and / or, For at least one of the hosts' current second data memory access requirements, the bandwidth control module identifies the host identifier corresponding to the memory access command that requires the memory access control module to arbitrate, and determines based on a preset host identifier whether the host corresponding to the host identifier is a target host with adjustable memory access priority; if so, configures the memory access priority of the target host based on the memory access delay allowed by the target host.

9. A CPU memory access optimization control system applied to a SoC system, characterized in that: The SoC system at least includes a pre-built memory access architecture, the memory access architecture at least includes a comprehensive arbitration module, a memory access pass-through module corresponding to the CPU, and a memory access control module corresponding to a non-CPU type host, and the memory access architecture is at least used to implement the data memory access operation of the CPU facing the target memory and implement the data memory access operation of at least one non-CPU type host facing the target memory; The system is used to execute the steps in the CPU memory access optimization control method applied to a SoC system as described in any one of claims 1 to 8.

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