Interface function block and design method thereof

Abstract

An interface function block includes: a first data I / O circuit and a second data I / O circuit sequentially arranged along a first axis; a strobe signal I / O circuit disposed on a left side of the first axis from the first data I / O circuit; a clock generator circuit disposed on a right side of the first axis from the second data I / O circuit; a first type of routing unit and a second type of routing unit sequentially arranged at a first axis coordinate of the strobe signal I / O circuit along a second axis perpendicular to the first axis; a third type routing unit and a fourth type routing unit sequentially arranged at the first axis coordinates of the first data I / O circuit along the second axis, and another third type routing unit and another fourth type routing unit sequentially arranged at the first axis coordinates of the second data I / O circuit along the second axis, wherein a clock generated by the clock generator circuit is transmitted toward the first and second data I / O circuits and the strobe signal I / O circuit in a left direction of the first axis.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0087985 filed in the Korean Intellectual Property Office on July 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to interface functional blocks and design methods thereof, and more particularly, to a high-speed serializer / deserializer (SERDES) interface and design methods thereof. Background Art

[0004] Recently, with the increase in the data transmission speed of semiconductor devices, the amount of data transmitted per unit time has increased rapidly. Specifically, in cellular communication products, the data transmission speed between the radio frequency (RF) transceiver and the modem (baseband) is on the order of 10Gbps (gigabits per second). Because the RF transceiver and the modem are mounted on a printed circuit board (PCB) with limited area in cellular products, the use of parallel interfaces that increase the amount of data transmission by physically increasing the number of transmission lines has reached a limit. In order to overcome this limit, serial interfaces that increase the amount of data transmission while maintaining the number of transmission lines using serializer / deserializer (SERDES) technology are being applied to products. The SERDES transmitter can serialize the data transmitted in parallel on the data link and transmit the data through the transmission line by using a double data rate (DDR) protocol. The SERDES receiver receives the data transmitted serially by the transmitter according to the DDR protocol, deserializes the received data, and transmits the deserialized data on the link.

[0005] Different products with high-speed interfaces may have different corresponding requirements for data transfer speed (i.e., bandwidth). Traditionally, it is necessary to design interface function blocks individually according to the data bandwidth required for each product. The need for individual design programs makes it difficult to shorten the time used to develop products. Summary of the invention

[0006] Embodiments of the inventive concept provide an optimal interface function block supporting various data bandwidths by using a routing unit in which routing lines are patterned in advance, and a design method of the optimal interface function block.

[0007] According to one aspect of the inventive concept, there is provided an interface functional block, including: a first data input / output (I / O) circuit and a second data I / O circuit, sequentially arranged along a first axis; a strobe signal I / O circuit, arranged on the left side of the first axis from the first data I / O circuit; a clock generator circuit, arranged on the right side of the first axis from the second data I / O circuit; a first type routing unit and a second type routing unit, sequentially arranged at the first axis coordinate of the strobe signal I / O circuit along a second axis perpendicular to the first axis; a third type routing unit and a fourth type routing unit, sequentially arranged at the first axis coordinate of the first data I / O circuit along the second axis, another third type routing unit and another fourth type routing unit, sequentially arranged at the first axis coordinate of the second data I / O circuit along the second axis, wherein a clock generated by the clock generator circuit is transmitted in the left direction of the first axis toward the first data I / O circuit and the second data I / O circuit and the strobe signal I / O circuit.

[0008] According to another aspect of the inventive concept, there is provided an interface functional block, comprising: a first data input / output (I / O) circuit and a second data I / O circuit, arranged sequentially along a first axis; a strobe signal I / O circuit, arranged on the right side of the first axis from the second data I / O circuit; a clock generator circuit, arranged on the left side of the first axis from the first data I / O circuit; a first type routing unit and a second type routing unit, arranged sequentially at the first axis coordinate of the strobe signal I / O circuit along a second axis perpendicular to the first axis; a third type routing unit and a fourth type routing unit, arranged sequentially at the first axis coordinate of the first data I / O circuit along the second axis, another third type routing unit and another fourth type routing unit, arranged sequentially at the first axis coordinate of the second data I / O circuit along the second axis, wherein a clock generated by the clock generator circuit is transmitted in the right direction of the first axis toward the first data I / O circuit and the second data I / O circuit and the strobe signal I / O circuit.

[0009] According to another aspect of the inventive concept, a design method for an interface functional block is provided, the design method comprising: generating, based on a classification result of signal lines between a data input / output (I / O) circuit, a strobe signal I / O circuit, and a clock generator circuit, a routing unit for a data I / O circuit based on an arrangement position of the data I / O circuit and the strobe signal I / O circuit, and a routing unit for the strobe signal I / O circuit based on an arrangement position of the strobe signal I / O circuit and the clock generator circuit; generating a combined data I / O circuit in which the data I / O circuit is combined with the routing unit for the data I / O circuit, and a combined strobe signal I / O circuit in which the strobe signal I / O circuit is combined with the routing unit for the strobe signal I / O circuit; placing two or more combined data I / O circuits and two or more combined strobe signal I / O circuits along a first axis; and placing a clock generator circuit along the first axis so that a clock generated by the clock generator circuit is transmitted toward the combined data I / O circuit and the combined strobe signal I / O circuit in a left direction or a right direction of the first axis. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description considered in conjunction with the accompanying drawings, in which:

[0011] Figure 1 Modules constituting an interface functional block according to an embodiment are shown;

[0012] Figure 2 It is shown Figure 1 A block diagram of an example configuration of a data input / output (I / O) module is shown;

[0013] Figure 3 It is shown Figure 1 A block diagram of an example configuration of a strobe signal I / O module is shown;

[0014] Figure 4 It is shown Figure 1 A block diagram of an example configuration of a clock generator module is shown;

[0015] Figure 5 It is shown Figure 1 A diagram of an example configuration of a routing cell is shown;

[0016] Fig. 6A , Figure 6B , Figure 6C and Fig.6D shows corresponding examples of connections between a data I / O module and a routing unit according to an embodiment;

[0017] Fig. 7A and Figure 7BAn example of connection between a strobe signal I / O module and a routing unit according to an embodiment is shown;

[0018] Fig. 8A and Figure 8B An interface functional block including two data channels according to an embodiment is shown;

[0019] Fig.9A and Fig. 9B An interface functional block including four data channels according to an embodiment is shown;

[0020] Fig. 10A and Fig. 10B An interface functional block including eight data channels according to an embodiment is shown;

[0021] Fig.11 is a graph showing the delay of a signal relative to the number of data lanes of an interface function block according to an embodiment;

[0022] Fig.12 is a design flow chart of an interface function block according to an embodiment; and

[0023] Fig.13 is a block diagram of a semiconductor system including an interface functional block according to an embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 A circuit ("module") configuring an interface circuit block 100 (hereinafter referred to as an interface functional block 100) according to an embodiment is shown. The interface functional block 100 may include a data input / output (I / O) circuit 110 (hereinafter referred to as a DQ module), a selection signal I / O circuit 120 (hereinafter referred to as a DQS module), a clock generator circuit 130 (hereinafter referred to as a CLKGEN module), and a routing unit 140 including passive circuit elements. For example, in an example embodiment, the interface functional block 100 may be a functional block that transmits or receives data between a transmitter and a receiver based on a double data rate (DDR) standard by using a source synchronous clock. In other embodiments, the interface functional block 100 may represent an interface functional block that transmits or receives data serially in synchronization with a transmission reference clock. Although Figure 1 One DQ module 110 is shown in FIG. 1 , but the interface functional block 100 may include a plurality of DQ modules 110 .

[0026] Here, the module may correspond to a functional circuit that is pre-designed for a predetermined function and registered in a database of a computer. The DQ module 110 may be a circuit that performs a function of transmitting data to the outside and receiving data from an external source. The DQS module 120 may be a circuit that performs a function of transmitting a data strobe signal DQS to the outside and receiving a data strobe signal DQS from an external source. The CLKGEN module may be a circuit that performs a function of providing a clock for processing data transmitted or received by the DQ module and providing a clock for transmitting or receiving a DQS signal using the DQS module.

[0027] In addition, the routing unit may be a basic passive unit in which the metal wiring for transmitting the input signal to the output end is pre-patterned (the routing unit may not perform a predetermined logic function). Based on the input or transmission direction of the signal, the routing unit may include a buffer circuit and a metal wiring. In addition, the interface function block 100 may be an element included in the physical layer and may include a hardware circuit including one or more transmitters and receivers.

[0028] Designs for the modules 110, 120, and 130 and the routing unit 140, each constituting the interface functional block 100, may be included in a computer database including standard cells and library cells such as AND gates or OR gates. The number of DQ modules may be determined based on the data bandwidth desired by the interface functional block 100, and based on this, a plurality of DQ modules 110, DQS modules 120, and CLKGEN modules 130 may be arranged, and the routing unit 140 connects signals to each other therebetween, thereby constituting the interface functional block 100.

[0029] Figure 2 It shows that according to the embodiment Figure 1 The DQ module 110 and its I / O signals. Figure 3 It shows that according to the embodiment Figure 1 The DQS module 120 and its I / O signals. Figure 4 It shows that according to the embodiment Figure 1 The CLKGEN module 130 and its I / O signals.

[0030] First, refer to Figure 2, the DQ module 110 may include a transmitter 111, a receiver 113, and a test unit 115. The transmitter 111 may include: a multiplexer (M1) 111-1, which selects the output data Tx_data and the test data T_data respectively input in parallel on the data link; a serializer 111-3, which serializes the output of the multiplexer (M1) 111-1 using a first clock CLKL and a second clock CLKH; and a driver (Tx_D) 111-5, which transmits the serialized data. The serializer 111-3 may include a plurality of flip-flops. For example, the serializer 111-3 may include a flip-flop that sorts the 16-bit parallel data Tx_data transmitted by the multiplexer (M1) 111-1 into two 8-bit parallel data based on the first clock CLKL. In the transmission mode, the serializer 111-3 can serialize the sorted 8-bit parallel data at a double data rate (DDR) based on the rising and falling edges of the second clock CLKH, and can transmit the serialized data to the driver (Tx_D) 111-5. The frequency of the second clock CLKH can be a data transmission frequency, and can be four or more times higher than the frequency of the first clock CLKL. The driver 111-5 can output the data transmitted by the serializer 111-3 to an external receiver (not shown).

[0031] The receiver 113 may include an input buffer (B_In) 113-1 that receives input data Rx_data serially input from an external circuit (e.g., a logic / processing circuit) at a port 117; a multiplexer (M2) 113-2 that selects between the input data Rx_data and the test data T_data transmitted through the serializer 111-3 based on a mode; and a deserializer 113-5 that delays the data output from the multiplexer (M2) 113-2 by a certain delay value, samples the delayed input data with respect to the data strobe signal DQS transmitted from the DQS module 120 by using the second clock CLKH, deserializes the sampled input data by using the first clock CLKL, and outputs the deserialized input data to the data link. The deserializer 113-5 may set the delay value through a data training (DQ training) operation, and may receive a change reference signal UDL from the CLKGEN module 130, the change reference signal UDL determining the timing for changing the operation using the set delay value.

[0032] The test unit 115 may check whether each of the transmitter 111 and the receiver 113 included in the DQ module 110 normally performs a predetermined function. The test unit 115 may generate a random test pattern T_data in response to a mode setting Mode_set indicating a test mode operation, and may transmit the generated test pattern to the transmitter 111. The test pattern T_data transmitted to the multiplexer 111-1 of the transmitter 111 may be transmitted to the deserializer 113-5 via the serializer 111-3 and the multiplexer 113-3, and the test pattern passed through the deserializer 113-5 may be input to the test unit 115. In the test mode, the test unit 115 may compare the generated test pattern with the input test pattern to verify the expected operation of each of the transmitter 111 and the receiver 113.

[0033] The interface functional block 100 may include a plurality of DQ modules 110, and each DQ module 110 may receive output data Tx_data and a signal DQ_reg, the output data Tx_data may be a dedicated signal transmitted only to the corresponding DQ module, and the signal DQ_reg sets the driver Tx_D strength. The DQ module 110 may output input data R_data, which is a dedicated signal output only from the corresponding DQ module 110. The DQ module 110 may receive a mode selection signal Mode_set indicating a transmission / reception mode or a test mode.

[0034] refer to Figure 3 , the DQS module 120 may include a transmitter 121 and a receiver 123. As in the embodiment of the transmitter 111 of the DQ module 110, the transmitter 121 may include a serializer 121_3 and a driver (Tx_D) 121-5. The transmitter 121 may have the same configuration as that of the transmitter 111 of the DQ module 110, except that a fixed pattern (e.g., a pattern of repeating 0101) is received in order to generate a data strobe signal DQS as an output and a clock type. The receiver 123 may include an input buffer (B_in) 123-1 and a delay unit 123-3, the input buffer (B_in) 123-1 receiving a data strobe signal iDQS input from an external circuit (e.g., a logic or processing circuit) at a port 127, and the delay unit 123-3 delaying the received iDQS signal and outputting a delayed DQS signal. The delayed DQS signal may be transmitted to the receiver 113 of the DQ module 110. The receiver 123 may set a delay value through a training operation of controlling a delay of an input DQS signal, and may receive a change reference signal UDL which is a timing signal for changing an operation by using the set delay value from the CLKGEN module 130 as in the DQ module 110 .

[0035] When at least one of the multiple DQ modules within the interface functional block 100 is enabled, the DQS module 120 is enabled together and can therefore receive the operation enable signal Enable. The DQS module 120 can receive a setting signal DQS_reg for setting the driver strength as a dedicated signal. The DQS module 120 can receive a mode selection signal Mode_set indicating a transmission / reception mode or a test mode. In addition, the DQS module 120 can operate based on a differential signal scheme that transmits or receives a data strobe signal and an inverted data strobe signal together.

[0036] refer to Figure 4 , the CLKGEN module 130 may include frequency dividers 131 and 133 and a "change reference" signal generator 135. The CLKGEN module 130 may include a first frequency divider (DIV0) 131 and a second frequency divider (DIV1) 133, the first frequency divider (DIV0) 131 receiving a clock CLK PLL generated by a phase-locked loop or a delayed lock loop (DLL) and dividing it to generate a second clock CLKH, and the second frequency divider (DIV1) 133 dividing the second clock CLKH to generate a first clock CLKL. For example, the first frequency divider (DIV0) 131 may divide the frequency of the clock CLK_PLL by 2 to generate the second clock CLKH, and the second frequency divider (DIV1) 133 may divide the second clock CLKH by 8 to generate the first clock CLKL. Alternatively, the second divider (DIV1) 133 may directly divide the clock CLK_PLL to generate the first clock CLKL instead of dividing the second clock CLKH. In synchronization with the first clock CLKL, the change reference signal generator 135 may simultaneously reflect the setting value set in each of the DQ module 110 and the DQS module 120 to generate a change reference signal UDL input to enable operation, and may transmit the change reference signal UDL to the DQ module 110 and the DQS module 120. For example, the setting value may be a delay value set in each of the delay unit 123-3 of the deserializer 113-5 of the DQ module 110 and the receiver 121 of the DQS module 120.

[0037] The CLKGEN module 130 may receive a mode selection signal Mode_set indicating a transmission / reception mode or a test mode. When at least one of a plurality of DQ modules within the interface function block 100 is enabled, the CLKGEN module 130 is enabled together and thus may receive an operation enable signal Enable.

[0038] Reference again Figures 2 to 4, signals input to or output from the DQ module 110, the DQS module 120 and the CLKGEN module 130, which all constitute the interface function block 100, can be classified into dedicated signals Tx_data, Rx_data and DQ_reg of the DQ module 110, a dedicated signal DQS_reg of the DQS module 120, a mode selection signal Mode_set, an operation enable signal Enable, and a change reference signal DUL, the mode selection signal Mode_set is a first common signal C1 commonly input to all modules 110, 120 and 130, the operation enable signal Enable is a second common signal C2 commonly input to the DQS module 120 and the CLKGEN module 130, and the change reference signal UDL is a third common signal C3 transmitted from the CLKGEN module 130 to the DQ module 110 and the DQS module 120.

[0039] The data bandwidth required for each product can be determined, and therefore, the interface function block 100 may include two or more DQ modules 110, a DQS module 120 and a CLKGEN module 130, and may also include a routing unit 140 for connecting the dedicated signal, the first common signal C1, the second common signal C2 and the third common signal C3 to each other.

[0040] Figure 5 Various types of routing units for routing units according to an embodiment are shown. According to an embodiment, a plurality of routing units including routing lines arranged in different types may be defined, at least some of the defined plurality of routing units may be selected in association with the transmission of various signals between the DQ module 110, the DQS module 120, and the CLKGEN module 130, and may be arranged in the interface functional block 100. Figure 5 and discussed later FIG. 6A to FIG. 10B , routing unit 140 and modules 110, 120, and 130 are shown and described in the context of an XYZ Cartesian coordinate system (Z direction entering / leaving the paper), where the relative terms left and right represent the relative position (coordinate) or signal direction of the element along the X axis, and "up" and "down" represent the relative position or relative signal direction of the element along the Y axis. Metal lines located at different Z-direction coordinates can be connected by vias (VIAs).

[0041] refer to Figure 5 , a plurality of routing units having different types (or “routing patterns”) may be defined or classified based on the positions of the DQS module 120 and the CLKGEN module 130 relative to the DQS module 120 included in the interface functional block 100 and the signals transmitted to or received from the DQ module 110, the DQS module 120, and the CLKGEN module 130, and Figure 5, six routing units A to F are shown as an example. However, the embodiment is not limited thereto, and a different number of routing units may be defined based on various different types in which the interface function block 100 may be implemented, or a number other than Figure 5 Another routing pattern other than the routing pattern shown. For example, in the embodiment, data, data selection signal and clock are described, but in the case where various types of signals are transmitted to the interface functional block 100, routing lines can be further provided based on this. For example, in the embodiment, two clocks are described, but N clock signals can be defined in association with the transmission or reception of data, and the routing lines can be implemented in the routing units corresponding thereto.

[0042] In an embodiment, each routing unit may include routing lines formed in at least two metal routing layers ML1 and ML2, and routing lines of different metal routing layers ML1 and ML2 may be connected to each other through vias VIA. Each type of routing unit may include a buffer that determines a transmission direction of a signal transmitted to the routing line.

[0043] exist Figure 5 In the example, for ease of description, each routing line is shown as a single routing line, but based on the type of transmitted signals, a "routing line" can actually be configured as multiple routing lines. Figure 5 In FIG. 1 , an arrow shown on a routing line indicates a transmission direction of a signal transmitted to the routing line.

[0044] The routing units may include four types of routing units A to D for DQ module 110 (each an example of a “third type” or a “fourth type” routing unit) and two types of routing units E and F for DQS module 120 (each an example of a “first type routing unit” or a “second type routing unit”).

[0045] The routing unit E may receive a dedicated signal for the DQS module 120, a first common signal C1, and a second common signal C2. The routing units A and B may receive a dedicated signal for the DQ module 110, and may receive the first common signal C1 from the routing unit E. The routing unit F may receive a signal for the DQS module 120, the first common signal C1, the second common signal C2, and a third common signal C3 transmitted from the CLKGEN module 130 from the routing unit E, transmit the received signal to the DQS module 120, and transmit the second common signal C2 and the third common signal C3 to the routing unit C or the routing unit D.

[0046] Routing unit C and routing unit D may receive a dedicated signal for DQ module 110 and first common signal C1 from routing unit A or routing unit B, transfer the received signals to DQ module 110 , and receive third common signal C3 from routing unit F.

[0047] Each of the routing units A to F may include a routing line 51 extending along the Y axis for a dedicated signal and a routing line 52 extending along the Y axis for a first common signal C1. As a dedicated signal for the DQ module 110 or the DQS module 120, the transmission data Tx_data, the reception data R_data, and the module setting signals DQ_reg and DQS_reg may be transmitted to the routing line 51, so the arrows may be shown in two directions. Each of the routing units A, B, and E may also include a routing line 52' connected to the routing line 52 and extending along the X axis. Each of the routing units E and F may also include a routing line 53 extending along the Y axis for the second common signal C2. Each of the routing units F, C, and D may also include a routing line 53' connected to the routing line 53 for the second common signal C2 and extending along the X axis. Each of the routing units F, C, and D may also include a routing line 54 extending along the X axis for the third common signal C3 transmitted from the CLKGEN module 130.

[0048] In routing unit A and routing unit B, driving directions of buffers b1 and b2 may be different based on the transmission direction of the first common signal C1. Routing unit A may include a buffer that receives the first common signal C1 on the right side of the X-axis and drives the first common signal C1 to the left side of the X-axis. Routing unit B may include a buffer that receives the first common signal C1 on the left side of the X-axis and drives the first common signal C1 to the right side of the X-axis.

[0049] In the routing unit C and the routing unit D, the driving direction of the buffer may be different based on the transmission direction of the second common signal C2 or the third common signal C3. The routing unit C may include a buffer that receives the second common signal C2 on the left side of the X-axis and drives the second common signal C2 to the right side of the X-axis, and a buffer that receives the third common signal C3 on the right side of the X-axis and drives the third common signal C3 to the left side of the X-axis. The routing unit D may include a buffer that receives the second common signal C2 on the right side of the X-axis and drives the second common signal C2 to the left side of the X-axis, and a buffer that receives the third common signal C3 on the left side of the X-axis and drives the third common signal C3 to the right side of the X-axis.

[0050] Therefore, the transmission directions of the first common signal C1, the second common signal C2, and the third common signal C3 may be determined based on the positions at which the DQS module 120 and the CLKGEN module 130 are arranged relative to the DQ module 110. Figure 5 As shown, six types of routing units may be provided, and the interface function block 100 may be formed by combining the routing units based on the arrangement positions of the DQ module 110 , the DQS module 120 , and the CLKGEN module 130 .

[0051] FIG. 6A to FIG. 6D Each shows the DQ module with Figure 5 FIG. 1 is an example combination structure between routing units A to D for a DQ module. Fig. 7A and Figure 7B shows the DQS module with Figure 5 1 and 2. The coupling structure between routing units E and F for the DQS module. In these figures, arrows shown in the routing units indicate the directions of routing lines and signals transmitted to the routing lines.

[0052] First, refer to FIG. 6A to FIG. 6D , the combination of routing units A to D and DQ module 110 for DQ can include four cases, wherein DQ module 110 is coupled to a combination of routing units A and C, a combination of routing units A and D, a combination of routing units B and C, and a combination of routing units B and D. Fig. 6A A combined DQ module is shown, in which routing units C and A are sequentially arranged along the Y axis at the X axis coordinate of the DQ module 110 ("DQ0" at the lower part of the circuit structure, the routing units C and A are sequentially located above the DQ module 110 along the Y axis and occupy the corresponding X axis coordinate range of the DQ module 110), because when the DQS module 120 and the CLKGEN module 130 are both arranged on the right side of the X axis relative to the DQ module 110, the first common signal C1 and the third common signal C3 are transmitted from the right side of the X axis to the left side of the X axis. Figure 6B A combined DQ module is shown, in which routing units D and A are sequentially arranged along the Y-axis at the X-axis coordinate of the DQ module 110, because when the DQS module 120 is arranged on the right side of the X-axis relative to the DQ module 110 and the CLKGEN module 130 is arranged on the left side of the X-axis relative to the DQ module 110, the first common signal C1 is transmitted from the right side of the X-axis to the left side of the X-axis, and the third common signal C3 is transmitted from the left side of the X-axis to the right side of the X-axis. Figure 6CA combined DQ module is shown, in which routing units C and B are sequentially arranged along the Y axis at the X axis coordinate of the DQ module 110, because when the DQS module 120 is arranged on the left side of the X axis relative to the DQ module 110 and the CLKGEN module 130 is arranged on the right side of the X axis relative to the DQ module 110, the first common signal C1 and the second common signal C2 are transmitted from the left side of the X axis to the right side of the X axis, and the third common signal C3 is transmitted from the right side of the X axis to the left side of the X axis. Fig.6D A combined DQ module is shown, in which routing units D and B are sequentially arranged along the Y-axis at the X-axis coordinate of the DQ module 110, because when the DQS module 120 and the CLKGEN module 130 are both arranged on the left side of the X-axis relative to the DQ module 110, the first common signal C1 and the third common signal C3 are transmitted from the left side of the X-axis to the right side of the X-axis, and the second common signal C2 is transmitted from the right side of the X-axis to the left side of the X-axis.

[0053] Therefore, the transmission directions of the first common signal C1, the second common signal C2, and the third common signal C3 may be determined based on the positions of the DQS module 120 and the CLKGEN module 130 relative to the DQ module 110, and thus, as shown in FIG. FIG. 6A to FIG. 6D As shown, four types of combined DQ modules can be configured.

[0054] refer to Fig. 7A and Figure 7B , the combination of the routing units E and F for DQS and the DQS module 120 may include two cases. Fig. 7A A combined DQS module is shown in which routing units F and E are sequentially arranged along the Y axis from the DQS module 120 while the CLKGEN module 130 is arranged on the right side of the X axis from the DQS module 120 . Figure 7B 1 shows a combined DQS module, in which the routing units F and E are flipped when the CLKGEN module 130 is arranged on the left side of the X-axis relative to the DQS module 120, and the flipped routing units F and E are sequentially arranged along the Y-axis from the flipped DQS module 120. Therefore, the DQS module 120 can be implemented based on the position of the CLKGEN module 130 relative to the DQS module 120. Fig. 7A and Figure 7B Two combined DQS modules are shown.

[0055] Fig. 8A and Figure 8B A diagram showing an arrangement of an interface functional block including two data channels according to an embodiment. A data channel may represent a signal line for transmitting data between a transmitting / receiving device. In addition, the number of data channels may be determined based on the number of DQ modules included in the interface functional block.

[0056] refer to Fig. 8A , the interface function block 800-1 may include two DQ modules (e.g., a first DQ module and a second DQ module) DQ0 ​​and DQ1 sequentially arranged on the right side of the X-axis, a DQS module 120 arranged on the left side of the first DQ module DQ0, and a CLKGEN module 130 arranged on the right side of the second DQ module DQ1. Since the CLKGEN module 130 is arranged on the right side of the X-axis of the DQS module 120, Fig. 7A As shown, routing unit E and routing unit F can be combined with each other in DQS module 120. In DQ modules DQ0 and DQ1, because DQS module 120 is arranged on the left side of the X axis and CLKGEN module 130 is arranged on the right side of the X axis, Figure 6C As shown, routing units B and C may be combined with each other in each of DQ modules DQ0 and DQ1. The first clock CLKL and the second clock CLKH both generated by the CLKGEN module 130 may be transmitted to the DQS module 120 and the DQ modules DQ0 and DQ1 in the left direction of the X axis (not in the right direction of the X axis).

[0057] refer to Figure 8B , the interface function block 800-2 may include two DQ modules DQ0 and DQ1 sequentially arranged on the right side of the X axis, a CLKGEN module 130 arranged on the left side of the DQ modules DQ0 and DQ1, and a DQS module 120 arranged on the right side of the DQ modules DQ0 and DQ1. Since the CLKGEN module 130 is arranged on the left side of the DQS module 120, Figure 7B As shown in FIG. 1 , the flipped routing units E and F can be combined with each other in the flipped DQS module. In the DQ modules DQ0 and DQ1, since the DQS module 120 is arranged on the right side and the CLKGEN module 130 is arranged on the left side, as shown in FIG. Figure 6B As shown, routing units A and D may be combined with each other. The first clock CLKL and the second clock CLKH both generated by the CLKGEN module 130 may be transmitted to the DQS module 120 and the DQ modules DQ0 and DQ1 only in the right direction of the X-axis.

[0058] Fig.9A and Fig. 9B A diagram showing an arrangement of interface function blocks including four data channels according to an embodiment is shown.

[0059] refer to Fig.9A , the interface function block 900-1 can pass Fig. 8AThe interface function block 800-1 can be implemented by adding two DQ modules DQ2 and DQ3 to the left side of the DQS module 120. Both the DQS module 120 and the CLKGEN module 130 can be arranged on the right side of the X axis starting from the added DQ modules DQ2 and DQ3. Fig. 6A As shown, in each of the DQ module DQ2 and the DQ module DQ3 , the routing unit A and the routing unit C may be sequenced and combined.

[0060] refer to Fig. 9B , the interface function block 900-2 can pass Figure 8B The interface function block 800-2 can be implemented by adding two DQ modules DQ2 and DQ3 to the right side of the DQS module 120. Both the DQS module 120 and the CLKGEN module 130 can be arranged on the left side of the X axis starting from the added DQ modules DQ2 and DQ3. Fig.6D As shown, in each of the DQ module DQ2 and the DQ module DQ3 , the routing unit B and the routing unit D may be sequenced and combined.

[0061] Fig. 10A and Fig. 10B A diagram showing an arrangement of interface function blocks including eight data channels according to an embodiment is shown.

[0062] refer to Fig. 10A , the interface function block 1000-1 may also include adding Fig.9A The two DQ modules DQ4 and DQ5 on the left side of the DQ module DQ2 of the interface functional block 900-1, and the two DQ modules DQ6 and DQ7 added between the CLKGEN module 130 and the DQ module DQ1. In the two DQ modules DQ4 and DQ5 added to the left side of the DQ module DQ2, since the DQS module 120 and the CLKGEN module 130 are both arranged on the right side of the X axis, as shown in FIG. Fig. 6A As shown, routing unit A and routing unit C can be sequenced and combined with each other. In addition, in the two added DQ modules DQ6 and DQ7, because the DQS module 120 is arranged on the left side of the X axis and the CLKGEN module 130 is arranged on the right side of the X axis, as shown in FIG. Figure 6C As shown, routing unit B and routing unit C can be sequenced and combined with each other.

[0063] refer to Fig. 10B The interface function block 1000-2 may also include adding Fig. 9B The two DQ modules DQ4 and DQ5 between the DQ module DQ0 of the interface functional block 900-2 and the CLKGEN module 130, and the two DQ modules DQ6 and DQ7 added to the right side of the DQ module DQ3. Figure 6BAs shown, routing unit A and routing unit D may be combined with each other and may be arranged in two DQ modules DQ4 and DQ5 added between DQ module DQ0 and CLKGEN module 130. Fig.6D As shown, the routing unit B and the routing unit D may be combined with each other and may be arranged in two DQ modules DQ6 and DQ7 added to the right side of the DQ module DQ3.

[0064] 9A to 10B Each of the interface function blocks may include four or more even-numbered DQ modules arranged along the X-axis and a DQS module 120 disposed at the center of the DQ module. In addition, each interface function block may include a CLKGEN module 130 disposed at the leftmost or rightmost of the corresponding interface function block, and may transmit a clock only in one direction of the X-axis.

[0065] Fig.11 is a graph showing the delay of a signal with respect to the number of data lanes of an interface function block according to an embodiment.

[0066] refer to Fig.11 , the X-axis represents the number of data channels included in the interface function block (i.e., the number of DQ modules), and the Y-axis represents the delay of the signal. The dotted line represents the delay of the dedicated signal transmitted to the DQ module or the DQS module, and the solid line represents the delay of the first or second common signal. Even when the number of data channels of the interface function block increases, the delay of the dedicated signal remains unchanged, or as the number of data channels increases, the delay of the first or second common signal may increase.

[0067] Generally, after the interface functional block is manufactured, the layout information and the timing information can be extracted. Since the interface functional block using the routing unit according to the embodiment uses the routing unit designed in advance for routing between modules, the layout information can be extracted without the routing process for connection between signal lines. Fig.11 As shown, even without direct routing, the interface function block using the routing unit according to the embodiment can extract timing information about the signal of the interface function block including the intermediate data channel by performing interpolation of the minimum delay Lmin of the first or second common signal of the minimum data channel and the maximum delay Lmax of the first or second common signal of the maximum data channel. Accordingly, the interface function block can be implemented by using the compiled layout information and timing information based on the data channel configuration with the routing unit.

[0068] Fig.12 is a design flow chart of the interface function blocks according to the embodiment.

[0069] refer to Fig.12 and Figure 1In operation S121, the DQ module 110, the DQS module 120, and the CLKGEN module 130 may be prepared first. In operation S123, the signals between the DQ module 110, the DQS module 120, and the CLKGEN module 130 may be classified, and the DQ module 110 and the DQS module 120 may be prepared based on the classification result and the position where the DQ module 110 and the DQS module 120 can be arranged. Figure 5 The four routing units for DQ are shown, and the DQS module 120 and the CLKGEN module 130 can be prepared based on the classification result and the position where the DQS module 120 and the CLKGEN module 130 can be arranged. Figure 5 In operation S125, a combined DQ module and a combined DQS module may be prepared. In the combined DQ module, the DQ module 110 and the routing unit for DQ are as described above with reference to FIG. FIG. 6A to FIG. 6D The combined DQS module and the routing unit for DQS are as described above. Fig. 7A and Figure 7B The interface function block 100 is combined as described. In operation S127, the number of DQ modules may be determined based on the number of data channels of the interface function block 100, the position of the DQS module may be determined based on the DQ module, and the position of the CLKGEN module may be determined based on the DQS module. In operation S129, the combined DQ module and the combined DQS module may be arranged along the first axis based on the determined number of DQ modules 110. The CLKGEN module may be arranged at the far left or far right along the first axis, and therefore, the CLKGEN module may be arranged so that the clock generated by the CLKGEN module is transmitted toward the DQS module and the DQ module arranged at the first axis in the left direction or the right direction of the first axis, respectively (operation S131). After the combined DQ module, the combined DQS module, and the CLKGEN module are placed, in operation S133, a graphics design system (GDS) file including layout information may be generated. After the combined DQ module, the combined DQS module, and the CLKGEN module are placed, timing information may be checked by performing static timing analysis (STA) before generating a GDS file in operation S133.

[0070] The number of data channels (or the number of DQ modules) can be determined based on the data bandwidth to be transmitted as described above, and the pre-designed routing units can be selectively combined based on the arrangement positions of the DQS modules and the CLKGEN modules relative to the DQ modules, and therefore, the interface function blocks can be easily manufactured by using the prepared routing units even though the number of data channels is changed, thereby reducing the development time.

[0071] Fig.12 The design process can be performed by a computer system that executes an electronic design automation (EDA) program using a database, which includes DQ modules, DQS modules, CLKGEN modules, routing units for DQ, routing units for DQS, combined DQ modules, combined DQS modules, and other standard units.

[0072] Fig.13 is a block diagram of a semiconductor system 1300 including an interface functional block according to an embodiment.

[0073] refer to Fig.13 , the semiconductor system 1300 may be a communication system including a radio frequency (RF) chip 1310 and a modem chip (or a baseband (BB) chip) 1350. The RF chip 1310 may include an interface function block 1311, a logic block 1313, and an analog-to-digital converter (ADC) 1315. The RF chip 1310 may receive a high-frequency signal through an antenna, and may convert the high-frequency signal into a low-frequency signal, and may then generate digital data by using the ADC 1315. The logic block 1313 may configure the digital data generated by the ADC 1315 in units of frames, and may transmit the data included in the frame to the interface function block 1131. The interface function block 1131 may be the above-referenced Figures 1 to 10B One type of interface function block described serializes data transmitted in parallel from the logic block 1313 and transmits the serialized data to the modem chip 1350.

[0074] The modem chip 1350 may include an interface function block 1351 and a logic block 1353. The interface function block 1351 may be FIG. 8A to FIG. 10B The interface function block 1351 is a type of interface function block described, and can receive and deserialize the serialized digital data signal transmitted by the RF chip 1310. The logic block 1353 can receive the deserialized data from the interface function block 1351 and can process the data in units of frames.

[0075] Based on the number of data channels, the interface function blocks 1131 and 1351 respectively included in the RF chip 1310 and the modem chip 1350 may each be configured as a Figures 1 to 10BOne of the interface functional blocks. The number of data channels can be determined based on the data bandwidth required by the communication system 1300, and in the interface functional block according to the embodiment, when the arrangement of the modules included in the interface functional block is determined and the pre-designed routing units are combined and arranged accordingly, the routing of the signal can be completed, and accordingly, there is no need to redesign the routing, thereby shortening the manufacturing time while maintaining the optimized size. In addition, according to the embodiment, when implementing the layout of the semiconductor circuit, since it is not necessary to perform place & route (PnR) from the initial stage, routing units including various types of routing lines can be predefined, and IPs such as high-speed interface IPs can be manufactured by arranging only predefined routing units, thereby enhancing manufacturing efficiency.

[0076] In addition, in an embodiment, the combination of a DQ module or a DQS module with a routing unit may mean that at least one routing unit selected from a plurality of routing units defined as various types is combined with a DQ module or a DQS module by hard wiring. In addition, in an embodiment, a case where a routing unit according to an embodiment is applied to an RF chip and a modem chip is shown, but the embodiment may be applied to a physical layer of various types of semiconductor devices (e.g., semiconductor devices such as memory devices, memory controllers, application processors, and systems on chips) that transmit or receive at least one of data, a strobe signal, and a clock signal to or from an external component, or transmit at least one of data, a strobe signal, and a clock signal internally.

[0077] In addition, in a method for manufacturing an integrated circuit including a standard cell, a routing cell according to an embodiment may be included in a cell library used in the method for manufacturing an integrated circuit. For example, a cell library from resistor transistor logic (RTL) data written in a very high speed integrated circuit (VHSIC) hardware description language (VHDL) and a hardware description language (HDL) (such as Verilog) may be referenced to perform logic synthesis, and netlist data may be generated, or a cell library may be referenced to place standard cells used in the netlist, or a design such as connecting the placed standard cells to each other may be performed, and the cell library may include various types of routing cells described in the embodiments.

[0078] In the above, exemplary embodiments have been described in the drawings and the specification. The embodiments have been described by using the terms described herein, but this is only used to describe the embodiments, and is not used to limit the meaning or scope of the inventive concept defined in the following claims. Therefore, it can be understood by those of ordinary skill in the art that various modifications and other equivalent embodiments can be implemented according to the inventive concept. Accordingly, the spirit and scope of the inventive concept can be defined based on the following claims.

[0079] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An interface function block, comprising: A first data input / output I / O circuit and a second data I / O circuit are sequentially arranged along a first axis; a strobe signal I / O circuit, arranged on the left side of the first axis from the first data I / O circuit; a clock generator circuit arranged on the right side of the first axis from the second data I / O circuit; A first type routing unit and a second type routing unit are sequentially arranged at a first axis coordinate of the strobe signal I / O circuit along a second axis perpendicular to the first axis; a third type routing unit and a fourth type routing unit, sequentially arranged along the second axis at a first axis coordinate of the first data I / O circuit; and another third type routing unit and another fourth type routing unit are sequentially arranged along the second axis at the first axis coordinate of the second data I / O circuit, The clock generated by the clock generator circuit is transmitted in the left direction of the first axis toward the first data I / O circuit, the second data I / O circuit and the strobe signal I / O circuit.

2. The interface functional block according to claim 1, wherein: The clock comprises: a first clock having a data transfer frequency; and A second clock having a frequency lower than the data transfer frequency.

3. The interface functional block according to claim 2, wherein: The first type routing unit includes: a plurality of routing lines extending along the second axis, including a routing line for a strobe signal I / O dedicated signal, a routing line for a first common signal commonly applied to the first data I / O circuit and the second data I / O circuit, the strobe signal I / O circuit, and the clock generator circuit, and a routing line for a second common signal transmitted to the strobe signal I / O circuit and the clock generator circuit but not transmitted to the first data I / O circuit and the second data I / O circuit; and a routing line extending along the first axis, including a routing line for a third common signal transmitted from the clock generator circuit, and The second type routing unit includes: a plurality of routing lines corresponding to the plurality of routing lines extending along a second axis in the first type routing unit; and A routing line configured to transmit the first common signal along the first axis.

4. The interface functional block according to claim 3, wherein: The third type routing unit includes: a plurality of routing lines extending along the second axis, including routing lines for data I / O dedicated signals and routing lines for the first common signals; and a plurality of routing lines extending along the first axis, including a routing line configured to transmit the second common signal to the right side of the first axis and to transmit the third common signal to the left side of the first axis, and The fourth type routing unit includes: a plurality of routing lines extending along the second axis, corresponding to the routing lines for the first common signal and the routing lines for the data I / O dedicated signal in the third type routing unit; and A routing line configured to transmit the first common signal to a right side of the first axis.

5. The interface function block according to claim 4 further comprising: A third data I / O circuit and a fourth data I / O circuit are sequentially arranged on the left side of the strobe signal I / O circuit of the first axis; as well as The third type routing unit and the fifth type routing unit are sequentially arranged along the second axis starting from each of the third data I / O circuit and the fourth data I / O circuit.

6. The interface functional block according to claim 5, wherein: The fifth type of routing unit includes: a plurality of routing lines corresponding to the plurality of routing lines extending along the second axis in the third type routing unit; and A routing line configured to transmit the first common signal to a left side of the first axis.

7. The interface functional block according to claim 6, wherein: Each of the fourth type routing unit and the fifth type routing unit includes a buffer configured to transmit the first common signal, and a driving direction of the buffer of the fourth type routing unit is opposite to a driving direction of the buffer of the fifth type routing unit.

8. The interface function block according to claim 2, wherein: Each of the first data I / O circuit and the second data I / O circuit is configured to sort data input in parallel by using the second clock, and serialize and output the sorted data by using the first clock.

9. The interface function block according to claim 1, wherein: Each of the first data I / O circuit and the second data I / O circuit includes a test unit configured to generate a test pattern in a test mode.

10. An interface function block, comprising: A first data input / output I / O circuit and a second data I / O circuit are sequentially arranged along a first axis; a strobe signal I / O circuit, arranged on the right side of the first axis from the second data I / O circuit; a clock generator circuit arranged on the left side of the first axis from the first data I / O circuit; A first type routing unit and a second type routing unit are sequentially arranged at a first axis coordinate of the strobe signal I / O circuit along a second axis perpendicular to the first axis; a third type routing unit and a fourth type routing unit, sequentially arranged along the second axis at a first axis coordinate of the first data I / O circuit; and another third type routing unit and another fourth type routing unit are sequentially arranged along the second axis at the first axis coordinate of the second data I / O circuit, The clock generated by the clock generator circuit is transmitted in the right direction of the first axis toward the first data I / O circuit, the second data I / O circuit, and the strobe signal I / O circuit.

11. The interface functional block according to claim 10, wherein: The clock comprises: a first clock having a data transfer frequency; and a second clock having a frequency lower than the data transfer frequency, and Each of the first data I / O circuit and the second data I / O circuit is configured to sort data input in parallel by using the second clock, and serialize and output the sorted data by using the first clock.

12. The interface functional block according to claim 10, wherein: The first type routing unit includes: a plurality of routing lines extending along the second axis, including a routing line for a strobe signal I / O dedicated signal, a routing line for a first common signal commonly applied to the first data I / O circuit and the second data I / O circuit, the strobe signal I / O circuit, and the clock generator circuit, and a routing line for a second common signal transmitted only to the strobe signal I / O circuit and the clock generator circuit; and a routing line extending along the first axis, including a routing line for a third common signal transmitted from the clock generator circuit, and The second type routing unit includes: a plurality of routing lines corresponding to the plurality of routing lines extending along the second axis in the first type routing unit; and A routing line configured to transmit the first common signal along the first axis.

13. The interface functional block according to claim 12, wherein: The third type routing unit includes: a plurality of routing lines extending along the second axis, including routing lines for data I / O dedicated signals and routing lines for the first common signals; and a plurality of routing lines extending along the first axis, including a routing line for the second common signal and a routing line for the third common signal, and The fourth type routing unit includes: a plurality of routing lines extending along the second axis, corresponding to the routing lines for the first common signal and the routing lines for the data I / O dedicated signal in the third type routing unit; and A routing line configured to transmit the first common signal to a left side of the first axis.

14. The interface function block according to claim 13, further comprising: A third data I / O circuit and a fourth data I / O circuit are sequentially arranged on the right side of the first axis of the strobe signal I / O circuit; as well as The third type routing unit and the fifth type routing unit are sequentially arranged along the second axis from each of the third data I / O circuit and the fourth data I / O circuit.

15. The interface functional block according to claim 14, wherein: The fifth type of routing unit includes: a plurality of routing lines corresponding to the plurality of routing lines extending along the second axis in the third type routing unit; and A routing line configured to transmit the first common signal to a right side of the first axis.

16. The interface functional block according to claim 15, wherein: Each of the fourth type routing unit and the fifth type routing unit includes a buffer configured to transmit the first common signal, and a driving direction of the buffer of the fourth type routing unit is opposite to a driving direction of the buffer of the fifth type routing unit.

17. The interface function block according to claim 10, wherein: Each of the first data I / O circuit and the second data I / O circuit includes a test unit configured to generate a test pattern in a test mode.

18. A method for designing an interface function block, the method comprising: Based on the classification result of the signal lines between the data input / output I / O circuit, the strobe signal I / O circuit and the clock generator circuit, a routing unit for the data I / O circuit based on the arrangement positions of the data I / O circuit and the strobe signal I / O circuit and a routing unit for the strobe signal I / O circuit based on the arrangement positions of the strobe signal I / O circuit and the clock generator circuit are generated; generating a combined data I / O circuit in which the data I / O circuit is combined with a routing unit for the data I / O circuit and a combined strobe signal I / O circuit in which the strobe signal I / O circuit is combined with a routing unit for the strobe signal I / O circuit; placing two or more of the combined data I / O circuits and the combined strobe signal I / O circuits along a first axis; as well as The clock generator circuit is placed along the first axis so that a clock generated by the clock generator circuit is transmitted toward the combined data I / O circuit and the combined strobe signal I / O circuit in a left direction or a right direction of the first axis.

19. The design method according to claim 18, wherein: Each of the routing unit for the data I / O circuit and the routing unit for the strobe signal I / O circuit includes: routing lines for dedicated signals that are transmitted to the data I / O circuit and the strobe signal I / O circuit but not to the clock generator circuit; and A routing line for a first common signal commonly transmitted to the data I / O circuit, the strobe signal I / O circuit, and the clock generator circuit.

20. The design method according to claim 19, wherein: The clock comprises: a first clock having a data transfer frequency; and a second clock having a frequency lower than the data transfer frequency, and Each of the combined data I / O circuits is configured to sort data input in parallel through the routing line for the dedicated signal using the second clock, and serialize and output the sorted data using the first clock.

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