Micro-electro-mechanical system (MEMS) switch-based interface

Abstract

The invention relates to an interface based on a micro electro mechanical system (MEMS) switch. An interface, such as an input / output extender (IOE), includes a micro-electro-mechanical (MEMS) switch operable to connect or disconnect respective signal lines on the interface. The MEMS switches may be less susceptible to electrostatic discharge (ESD) damage, which eliminates the need for each MEMS switch for an ESD protection circuit. The interface can have improved performance due to the need to eliminate the ESD protection circuit that would otherwise introduce jitter in signal propagation.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memories and methods, and more particularly to apparatus, systems, and methods for microelectromechanical systems (MEMS) switch-based interfaces. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by maintaining stored data when not powered and can include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host when the computer or electronic system is operating. For example, the data, commands, and / or instructions may be transferred between the host and the memory device during operation of the computing or other electronic system. A controller may be used to manage the transfer of data, commands, and / or instructions between the host and the memory device. Summary of the invention

[0004] In one aspect, the present application provides a method for controlling an interface based on a microelectromechanical system (MEMS) switch, comprising: electrically connecting a first and second input / output (I / O) component to the second I / O component by placing a microelectromechanical system (MEMS) switch positioned on a corresponding signal line coupled between the first and second I / O components in a closed position to form a data path between the first and second I / O components; and electrically disconnecting the first and second I / O components by placing the MEMS switch in an open position.

[0005] On the other hand, the present application provides a device based on a microelectromechanical system (MEMS) switch interface, comprising: a first number of input / output (I / O) components; a second number of I / O components; and one or more microelectromechanical system (MEMS) switches, which are operable to selectively connect a first of the first number of I / O components to two or more of the second number of I / O components via corresponding signal lines coupled to the one or more MEMS switches.

[0006] On the other hand, the present application provides a device based on a microelectromechanical system (MEMS) switch interface, comprising: a first number of microelectromechanical system (MEMS) switches positioned on a first portion of the device, the first number of MEMS switches coupled to a first number of signal lines and operable to separately and selectively connect or disconnect the first number of signal lines; and a second number of MEMS switches positioned on a second end of the device, the second number of MEMS switches coupled to a second number of signal lines and operable to separately and selectively connect or disconnect the second number of signal lines.

[0007] On the other hand, the present application provides a system comprising: a first number of signal lines, the first number of signal lines turning to a second number of signal lines on a front end of an interface device and further turning to a third number of signal lines on a back end of the interface device; a first number of microelectromechanical system (MEMS) switches, each of the first number of MEMS switches being positioned on a corresponding signal line of the second number of signal lines, the first number of MEMS switches being operable to respectively connect or disconnect the corresponding signal lines of the second number of signal lines; and a second number of MEMS switches, each of the second number of MEMS switches being positioned on a corresponding signal line of the third number of signal lines, the second number of MEMS switches being operable to respectively connect or disconnect the corresponding signal lines of the third number of signal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an apparatus in the form of a computing system including a host, a memory device, and an interface coupled between the host and the memory device according to several embodiments of the present disclosure.

[0009] Figure 2 is a block diagram illustrating an example input / output expander (IOE) device including MEMS switches positioned on signal lines on the front and / or back end of an IOE, according to several embodiments of the present disclosure.

[0010] Figure 3is a block diagram illustrating another example IOE including MEMS switches positioned on signal lines on the front and / or back end of the IOE in accordance with several embodiments of the present disclosure.

[0011] Figure 4 is a block diagram illustrating another example IOE including MEMS switches positioned on signal lines on the front and / or back end of the IOE in accordance with several embodiments of the present disclosure.

[0012] Figure 5 is a block diagram illustrating another example IOE including MEMS switches positioned on signal lines on the front and / or back end of the IOE in accordance with several embodiments of the present disclosure.

[0013] Figure 6 is a block diagram illustrating another example IOE including MEMS switches positioned on signal lines on the front and / or back end of the IOE in accordance with several embodiments of the present disclosure.

[0014] Figure 7 is a flow chart of a method for controlling an electromechanical switch on an I / O component according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Systems, devices, and methods related to interfaces based on microelectromechanical systems (MEMS) switches are described. An input / output expander (IOE) is a device that can be used to increase / expand the number of input / output (IO) pins of a device such as a controller. An IOE can be used, for example, to increase the number of memory devices and / or memory channels that can be accessed via a specific IO input pin. Various existing IOEs utilize various analog circuit systems (e.g., analog receivers, drivers, multiplexing circuit systems, etc.) between IOE input and output pins. This analog circuit system can be implemented via CMOS logic (e.g., CMOS switches) and may be susceptible to noise (e.g., jitter) and electrostatic discharge (ESD) loading, which, for example, can reduce signal quality. As used herein, ESD refers to a sudden current between two charged objects (e.g., electrical components, circuits, etc.) caused by direct contact or close proximity. In order to prevent ESD damage, ESD protection circuits can be added to the IOE, such as to each CMOS switch. These circuits provide a low impedance path for the ESD current to flow to ground, thereby protecting the CMOS switch from damage.

[0016] The performance and / or capacity of the IOE may be degraded due to CMOS switch limitations. For example, parasitic capacitance on the CMOS switch and ESD protection circuitry may introduce jitter into the signal, which may further cause signal propagation delays, thereby reducing data transfer rates, etc. In addition, the number of extended memory channels that can be supported by the IOE may be limited because the volume is consumed by the ESD protection circuitry.

[0017] Aspects of the present disclosure address the above and other challenges associated with analog circuitry implemented, for example, via CMOS logic. Electromechanical switches, such as MEMS switches, may be implemented in place of CMOS switches and placed on those signal lines, further eliminating the need for analog circuitry (e.g., analog receivers, drivers, multiplexing circuitry, etc.) to have other circuits, components, etc. A MEMS switch may include a mechanical portion that may "physically" move in response to an electrical signal, allowing it to open or close the MEMS switch. Thus, a signal line that may be connected or disconnected via a MEMS switch may be "physically" connected or disconnected, which further "electrically" connects or disconnects the signal line, respectively.

[0018] To control the flow of electrical signals, MEMS switches rely on mechanical parts that are less likely to be affected by surges, rather than relying solely on electronic components like CMOS switches. Therefore, MEMS switches are less sensitive to ESD damage than CMOS switches, which eliminates the need for ESD protection circuits to be provided to CMOS switches. Since there is no parasitic capacitance mentioned above that would interfere with the operation of the IOE (which would be introduced by the CMOS switch and the ESD protection circuit), the MEMS switch can improve the performance of the IOE (such as signal propagation, data transfer rate, etc.), and in addition, this provides more flexibility in the structural design of the IOE by eliminating the ESD protection circuit that would otherwise consume a substantial portion of the volume.

[0019] As used herein, the singular forms "a", "an", and "the" include singular and plural referents unless the content clearly dictates otherwise. In addition, the word "may" is used throughout this application to mean permission (i.e., it is possible, can) rather than mandatory (i.e., must). The term "include" and its derivatives mean "including (but not limited to)". The term "coupled" means directly or indirectly connected.

[0020] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 208 may refer to Figure 2 Component "08" in , and similar components in Figure 3 It can be called 308 in China.

[0021] Similar elements within the figures may be referred to by a hyphen and an additional number or letter. See e.g. Figure 1112-1, ..., 112-N in. Such similar elements may be collectively referred to without hyphens and additional numbers or letters. For example, elements 112-1, ..., 112-N may be collectively referred to as 112. As used herein, the designators "N", "M", "X", "Y", and "Z" particularly with respect to the reference numbers in the drawings indicate that several specific features so designated may be included. It should be understood that the elements shown in the various embodiments herein may be added, exchanged, and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, it should be understood that the proportions and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be considered as intended to be limiting.

[0022] Figure 1 1 is a block diagram of an apparatus in the form of a computing system 100 including hosts 101-1, ..., 101-X (collectively referred to as "hosts 101"), memory devices 110-1, ..., 110-Y (collectively referred to as "memory devices 110"), and an interface 103 coupled between the hosts and the memory devices according to several embodiments of the present disclosure. As used herein, the hosts 101, the interfaces 103, and / or the memory devices 110 may also be individually considered as "apparatuses".

[0023] The host 101 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including a memory and a processing device. The host 101 may further or alternatively be a system controller for performing operations such as reading data, writing data, or erasing data and other such operations at the memory device 110. As a system controller, the host 101 may include a microcontroller, a dedicated logic circuit system (such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processing circuit system for performing the operations described herein.

[0024] The memory device 110 may include any combination of different types of nonvolatile memory devices and / or volatile memory devices. Some examples of volatile memory devices include, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM). Some examples of nonvolatile memory devices include, but are not limited to, non-AND (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices. Cross-point nonvolatile memory arrays may perform bit storage based on bulk resistance changes in conjunction with a stackable cross-grid data access array. Additionally, in contrast to many flash-based memories, cross-point nonvolatile memories may perform write-in-place operations, where nonvolatile memory cells may be programmed without pre-erasing the nonvolatile memory cells.

[0025] Each of the memory devices 110 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 110 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of the memory device 110 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. With respect to some types of memory, such as NAND, pages may be grouped to form blocks.

[0026] Although non-volatile memory components such as 3D crosspoints are described, the memory device 110 may be based on any other type of non-volatile memory or storage device, such as NAND, read-only memory (ROM), phase change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The host 101 may be coupled to the memory device 110 via an interface 103 (alternatively referred to as a "host interface"). In some embodiments, the interface 103 may be (e.g., integrated) part of one or more hosts 101. The interface 103 may be used to communicate data, addresses, commands, etc. between the host 101 and the memory device 110. Examples of the host interface include (but are not limited to) a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting a Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), etc. The host interface may be used to transfer data between the host 101 and the memory device 110. The host 101 may further utilize an NVM Express (NVMe) interface to access the memory device 110 through the PCIe interface. The host interface may provide an interface for transferring control, address, data, and other signals between the memory device 110 and the host 101. In some embodiments, the interface 103 may be or include an IOE device.

[0028] As used herein, the host side of the interface 103 (to which the host 101 may be coupled) may be referred to as the front end and the memory side of the interface 103 (to which the memory device 110 may be coupled) may be referred to as the back end. The interface 103 may include a number of ports 112-1-1, ..., 112-1-N (collectively referred to as "ports 112-1") on the front end and a number of ports 112-2-1, ..., 112-2-M (collectively referred to as "ports 112-2") on the back end. The host 101 may be coupled to those ports 112-1-1, ..., 112-1-N on the front end and the memory device 110 may be coupled to those ports 112-2-1, ..., 112-2-M on the back end to communicate commands (e.g., read, write, erase, program, etc.), addresses, data, etc. between the two devices.

[0029] One or more ports 112 may respectively include one or more I / O components (referred to as "I / O" for short), such as Figures 2 to 6 I / O 204, 304, 404, 504, 604 described in. Figures 2 to 6 To further illustrate, the front-end port 112-1 and the back-end port 112-2 of the IOE may not be symmetrical. For example, the port 112-2 on the back-end may include an I / O. The port 112-1 on the front-end may not include an I / O, but may be coupled to one or more (e.g., integrated) I / Os of the host 101. The I / O may include various circuit systems to facilitate the transmission of signals. For example, Figures 2 to 6 As further described in the specification, the I / O may include one or more signal lines, transceivers (such as transmitters, receivers, etc.), I / O pads, etc. that can receive external signals and / or output received signals.

[0030] The I / O of port 112 may be unidirectional I / O, bidirectional I / O, or a combination thereof. The I / O of port 112 may form a corresponding bus (e.g., a data bus, an address bus, a command bus, etc.) to receive and / or output various signals, such as those defined by an interface protocol (e.g., ONFI defined signals), signals indicating data (e.g., host data originally received from host 101), etc. In addition to port 112, the I / O may be placed in various locations of computing system 100 other than ports (e.g., port 112). For example, the I / O may be placed between peripheral devices (e.g., sensors, actuators, displays, etc.) and components of computing system 100 and / or implemented as part of a bus within host 101 and / or memory device 110, etc.

[0031] The port 112-1 on the front end and the port 112-2 on the back end may be coupled to each other via the intermediate connection component 107. Although the embodiment is not limited thereto, the intermediate connection component 107 may include a signal line (eg, Figures 2 to 6The signal lines 216, 316, 416, 516 and / or 616 described in the drawings, respectively), the electromechanical switches 108-1, ..., 108-Z ( Figure 1 ). The intermediate connection component 107 may include circuitry configured to functionally operate as a multiplexer and / or a demultiplexer to provide selective coupling between the port 112-1 and the port 112-2.

[0032] The interface 103 may include an interface controller 105 that is communicatively coupled to the host 101, the memory device 110, and the intermediate connection component 107. The interface controller 105 may be configured to control the flow of commands and / or data between one or more hosts 101 and the memory device 110, as directed by the host 101 and / or the memory device 110. For example, in response to receiving a command from the host 101 and / or the memory device 110, the interface controller 105 may dynamically configure the topology between the port 112-1 (e.g., on the front end) and the port 112-2 (e.g., on the back end) to selectively couple the port 112-1 to the port 112-2. The interface controller 105 may include various circuit systems to facilitate the operations described herein, such as controlling various portions of the intermediate connection component 107 (e.g., the electromechanical switch 108). For example, interface controller 105 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry or software and / or firmware that may allow interface controller 105 to control electromechanical switch 108 .

[0033] The interface controller 105 can configure / reconfigure the topology by enabling / disabling the electromechanical switches 108 on the intermediate connection components 107. As used herein, "disabling" an electromechanical switch refers to placing the electromechanical switch in an open position, while "enabling" an electromechanical switch refers to placing the switch in a "closed" position. Those switches in the "open" position disconnect the corresponding signal line (e.g., the signal line where the switch is located), while those switches in the "closed" position connect the corresponding signal line. Therefore, two components (e.g., the host 101 and the memory device 110) coupled to each other via a "connected" signal line are also "connected", while two components coupled to each other via a "disconnected" signal line are also "disconnected". As described herein, a MEMS switch may include a mechanical portion that can be "physically" moved between closed and open positions, which can provide both electrical and physical isolation when opened.

[0034] In some embodiments, a single host 101 may be coupled to multiple ports 112-1 to establish multiple "channels" between the host 101 and the memory devices 110. In this example, the multiple ports 112-1 coupled to the same host 101 may be respectively operated to transmit different types of signals (e.g., DQ signals, ONFI defined signals, etc.). In some embodiments, one port 112-1 may be used to transmit a differential clock signal to synchronize the operation of multiple memory devices 110, especially when coupled to the same host 101.

[0035] Figure 2 2 is a block diagram illustrating an example IOE 203 including MEMS switches 208-1, 208-2 (collectively referred to as MEMS switches 208) positioned on signal lines on the front and / or back end of the IOE 203 according to several embodiments of the present disclosure. The back end I / Os 204-2-1 and 204-2-2 may be collectively referred to as "I / O 204-2". The IOE 203 may be similar to Figure 1 In addition, I / O 204 may be similar to interface 103 described in and / or part thereof. Figure 1 I / O 104 described in .

[0036] Each I / O 204-2 may correspond to and / or represent a port (eg, Figure 1 As described herein, a front-end port (eg, a port coupled or coupleable to I / O 204-1) may be coupled to a host (eg, Figure 1 1), and those ports (such as the ports corresponding to I / O 204-2-1 and 204-2-2, respectively) can be coupled to memory devices (such as Figure 1 Memory device 110 described in FIG.

[0037] MEMS switches 208-1 and 208-2 may respectively and selectively connect or disconnect signal lines coupled to I / Os 204-2-1 and 204-2-2 to further selectively connect or disconnect I / O 204-1 to I / Os 204-2-1 and 204-2-2. For example, MEMS switch 208-1 may be placed in a closed position to connect I / O 204-1 to I / O 204-2-1 or in an open position to disconnect I / O 204-1 from I / O 204-2-1, and MEMS switch 208-2 may be placed in a closed position to connect I / O 204-1 to I / O 204-2-2 or in an open position to disconnect I / O 204-1 from I / O 204-2-2.

[0038] Compared to the IOE embodiments of the present disclosure, IOE approaches that utilize various CMOS logic (e.g., switches) in the form of logic gates and multiplexing / demultiplexing circuit systems may have disadvantages (e.g., relatively high parasitic capacitance and susceptibility to noise / jitter), as well as other disadvantages that may, for example, limit the data transfer bandwidth of the IOE and / or expand the available number of memory channels. In contrast, the IOE embodiments of the present disclosure having MEMS switches (e.g., MEMS switch 208) are substantially less susceptible to electrostatic discharge than CMOS switches, which eliminates the need for separate ESD protection circuits for the MEMS switches. For example, the parasitic capacitance associated with each MEMS switch 208 is below a threshold value, such that the MEMS switch 208 is configured to selectively connect / disconnect the corresponding signal line 216 in the absence of a separate ESD protection circuit coupled thereto. Thus, although the IOE 203 may include Figure 2 Although additional circuitry is not described in the drawings, IOE 203 may not include various ESD protection circuits that are typically required in previous IOE approaches that utilize various CMOS logic (eg, switches), such that IOE 203 does not impose significant bandwidth limitations that are typically introduced by previous IOE approaches.

[0039] Figure 3 304-2 is a block diagram illustrating another example IOE 303 device including MEMS switches 308-1, 308-2, 308-3, 308-4 (collectively referred to as MEMS switches 308) positioned on signal lines on the front and / or back end of the IOE 303 according to several embodiments of the present disclosure. Back end I / Os 304-2-1, ..., 304-2-4 on the back end may be collectively referred to as "I / O 304-2". The IOE 303 may be similar to Figure 1 In addition, I / O 304 may be similar to interface 103 described in and / or part thereof. Figure 1 I / O 104 described in .

[0040] Each I / O 304-2 may correspond to and / or represent a port (eg, Figure 1 As described herein, a front-end port (eg, a port coupled or coupleable to I / O 304-1) may be coupled to one or more hosts (eg, Figure 1 1), and those ports (eg, ports corresponding to I / O 304-2-1, ..., 304-2-4, respectively) may be coupled to memory devices (eg, Figure 1 Memory device 110 described in FIG.

[0041] IOE 303 includes a signal line 316, one end of which is coupled to I / O 304-1 (e.g., an I / O pad of I / O 304-1) and the other end of which is forwarded to four different signal lines respectively coupled to I / Os 304-2-1, ..., 304-2-4 (e.g., corresponding I / O pads of I / O 304-2-1, ..., 304-2-4). Figure 3 As further described in FIG. 3 , the MEMS switches 308 - 1 , . . . , 308 - 4 are respectively located on four signal lines.

[0042] MEMS switches 308-1, ..., 308-4 may respectively and selectively connect or disconnect signal lines coupled to I / Os 304-2-1, ..., 304-2-4 to further selectively connect (e.g., connect) I / O 304-1 to or disconnect I / O 304-1 from 304-2-1, ..., 304-2-4. For example, MEMS switch 308-1 may be placed in a closed position to connect I / O 304-1 to I / O 304-2-1 or in an open position to disconnect I / O 304-1 from I / O 304-2-1; MEMS switch 308-2 may be placed in a closed position to connect I / O 304-1 to I / O 304-2-2 or in an open position to disconnect I / O 304-1 from I / O 304-2-2; MEMS switch 308-3 may be placed in a closed position to connect I / O 304-1 to I / O 304-2-3 or in an open position to disconnect I / O 304-1 from I / O 304-2-3; and MEMS switch 308-4 may be placed in a closed position to connect I / O 304-1 to I / O 304-2-3. 304-1 is connected to I / O 304-2-4 or is placed in a disconnect position to disconnect I / O 304-1 from I / O 304-2-4.

[0043] Compared to the IOE embodiments of the present disclosure, IOE approaches that utilize various CMOS logic (e.g., switches) in the form of logic gates and multiplexing / demultiplexing circuit systems may have disadvantages (e.g., relatively high parasitic capacitance and susceptibility to noise / jitter), as well as other disadvantages that may, for example, limit the data transfer bandwidth of the IOE and / or expand the available number of memory channels. In contrast, the IOE embodiments of the present disclosure having MEMS switches (e.g., MEMS switch 308) are substantially less susceptible to electrostatic discharge than CMOS switches, which eliminates the need for separate ESD protection circuits for the MEMS switches. For example, the parasitic capacitance associated with each MEMS switch 308 is below a threshold value, such that the MEMS switch 308 is configured to selectively connect / disconnect the corresponding signal line 316 in the absence of a separate ESD protection circuit coupled thereto. Thus, although the IOE 303 may include Figure 3Although additional circuitry is not illustrated in the drawings, IOE 303 may not include various ESD protection circuits that are typically required in previous IOE approaches that utilize various CMOS logic (eg, switches), such that IOE 303 does not impose significant bandwidth limitations that are typically introduced by previous IOE approaches.

[0044] Figure 4 404-2-2. IOE 403 may be similar to IOE 403. Figure 1 In addition, I / O 404 may be similar to interface 103 described in and / or part thereof. Figure 1 I / O 104 described in .

[0045] Each I / O 404 may correspond to and / or represent a port (eg, Figure 1 As described herein, those ports (such as ports coupled or couplable to I / O 404-1-1 and 404-1-2, respectively) may be coupled to a host (such as Figure 1 1), and those ports (such as the ports corresponding to I / O 404-2-1 and 404-2-2, respectively) can be coupled to memory devices (such as Figure 1 Memory device 110 described in FIG.

[0046] IOE 403 includes signal lines 416-1 and 416-2. One end of each signal line 416 is coupled to two different signal lines of I / O 404-1-1 and 404-1-2 (e.g., corresponding I / O pads of I / O 404-1-1 and 404-1-2) and the other end is further coupled to two different signal lines of I / O 404-2-1 and 404-2-2 (e.g., corresponding I / O pads of I / O 404-2-1 and 404-2-2). Figure 4It is further illustrated in FIG. 1 that MEMS switches 408-1-1 and 408-1-2 are positioned on two turn signal lines of an I / O pad coupled to I / O 404-1-1; MEMS switches 408-1-3 and 408-1-4 are positioned on two turn signal lines of an I / O pad coupled to I / O 404-1-2; MEMS switches 408-2-1 and 408-2-2 are positioned on two turn signal lines of an I / O pad coupled to I / O 404-2-1; and MEMS switches 408-2-3 and 408-2-4 are positioned on two turn signal lines of an I / O pad coupled to I / O 404-2-2.

[0047] IOE 403 can allow for various / flexible topologies, where I / O 404-1 (e.g., I / O 404-1-1 and 404-1-2) can selectively connect to I / O 404-2 (e.g., I / O 404-2-1 and 404-2-2). In one example, I / O 404-1-1 can connect to both I / O 404-2-1 and 404-2-2. Vice versa, I / O 404-1-2 can connect to both I / O 404-2-1 and 404-2-2. In another example, I / O 404-1-1 may be connected to one I / O 404-2 (e.g., 404-2-1) via signal line 416-1, while I / O 404-1-2 may be connected to another I / O 404-2 (e.g., 404-2-2) via signal line 416-2 (e.g., without disconnecting a single one of I / O 404-1). In this example, MEMS switches 408-1-1, 408-1-4, 408-2-1, and 408-2-4 may be placed in a closed position, while MEMS switches 408-1-2, 408-1-3, 408-2-2, and 408-2-3 may be placed in an open position.

[0048] Compared to the IOE embodiments of the present disclosure, IOE approaches that utilize various CMOS logic (e.g., switches) in the form of logic gates and multiplexing / demultiplexing circuit systems may have disadvantages (e.g., relatively high parasitic capacitance and susceptibility to noise / jitter), as well as other disadvantages that may, for example, limit the data transfer bandwidth of the IOE and / or expand the available number of memory channels. In contrast, the IOE embodiments of the present disclosure having MEMS switches (e.g., MEMS switch 408) are substantially less susceptible to electrostatic discharge than CMOS switches, which eliminates the need for separate ESD protection circuits for the MEMS switches. For example, the parasitic capacitance associated with each MEMS switch 408 is below a threshold value, such that the MEMS switch 408 is configured to selectively connect / disconnect the corresponding signal line 416 in the absence of a separate ESD protection circuit coupled thereto. Thus, although the IOE 403 may include Figure 4Although additional circuitry is not described in the drawings, IOE 403 may not include various ESD protection circuits that are typically required in previous IOE approaches that utilize various CMOS logic (eg, switches), such that IOE 403 does not impose significant bandwidth limitations that are typically introduced by previous IOE approaches.

[0049] Figure 5 508-2-1, ..., 508-2-4 and 508-2-1, ..., 508-2-8 (collectively referred to as MEMS switches 508) positioned on signal lines on the front and / or back end of the IOE 503 according to several embodiments of the present disclosure. The front end I / Os 504-1-1 and 504-1-2 may be collectively referred to as "I / O 504-1", while the back end I / Os 504-2-1, ..., 504-2-4 may be collectively referred to as "I / O 504-2". The IOE 503 may be similar to Figure 1 In addition, I / O 504 may be similar to interface 103 described in and / or part thereof. Figure 1 I / O 104 described in .

[0050] Each I / O 504-2 may correspond to and / or represent a port (eg Figure 1 As described herein, those ports (such as ports coupled or couplable to I / O 504-1-1 and 504-1-2, respectively) may be coupled to a host (such as Figure 1 1), and those ports (such as ports corresponding to I / O 504-2-1, 504-2-2, 504-2-3, and 504-2-4, respectively) can be coupled to memory devices (such as Figure 1 Memory device 110 described in FIG.

[0051] IOE 503 includes signal lines 516-1 and 516-2. One end of each signal line 516 is turned to two different signal lines respectively coupled to I / O 504-1-1 and 504-1-2 (e.g., corresponding I / O pads of I / O 504-1-1 and 504-1-2) and the other end is further turned to two different signal lines respectively coupled to I / O 504-2-1, 504-2-2, 504-2-3, and 504-2-4 (e.g., corresponding I / O pads of I / O 504-2-1, 504-2-2, 504-2-3, and 504-2-4).

[0052] like Figure 5508-2-3 and 508-2-4 are positioned on the two turn signal lines of the I / O pad coupled to the I / O 504-2-2; MEMS switches 508-2-5 and 508-2-6 are positioned on the two turn signal lines of the I / O pad coupled to the I / O 504-2-3; and MEMS switches 508-2-7 and 508-2-8 are positioned on the two turn signal lines of the I / O pad coupled to the I / O 504-2-1. The 504-2-4 I / O pad has two turn signal lines.

[0053] IOE 503 can allow for various / flexible topologies, where I / O 504-1 (e.g., I / O 504-1-1 and 504-1-2) can be selectively connected to I / O 504-2 (e.g., I / O 504-2-1, ..., 504-2-4). In one example, I / O 504-1-1 can be connected to four I / Os 504-2-1, ..., 504-2-4. Vice versa, I / O 504-1-2 can be connected to four I / Os 504-2-1, ..., 504-2-4. In another example, I / O 504-1-1 may be connected to a first portion of I / O 504-2 (e.g., 504-2-1 and 504-2-2) via signal line 516-1, while I / O 504-1-2 may be connected to a second portion of I / O 504-2 (e.g., 504-2-3 and 504-2-4) via signal line 516-2 (e.g., without disconnecting a single one of I / O 504-1). In this example, MEMS switches 508-1-1, 508-1-4, 508-2-1, 508-2-3, 508-2-6, and 508-2-8 may be placed in a closed position, while MEMS switches 508-1-2, 508-1-3, 508-2-2, 508-2-4, 508-2-5, and 508-2-7 may be placed in an open position.

[0054] Compared to the IOE embodiments of the present disclosure, IOE approaches that utilize various CMOS logic (e.g., switches) in the form of logic gates and multiplexing / demultiplexing circuit systems may have disadvantages (e.g., relatively high parasitic capacitance and susceptibility to noise / jitter), as well as other disadvantages that may, for example, limit the data transfer bandwidth of the IOE and / or expand the available number of memory channels. In contrast, the IOE embodiments of the present disclosure having MEMS switches (e.g., MEMS switch 508) are substantially less susceptible to electrostatic discharge than CMOS switches, which eliminates the need for separate ESD protection circuits for the MEMS switches. For example, the parasitic capacitance associated with each MEMS switch 508 is below a threshold value, such that the MEMS switch 508 is configured to selectively connect / disconnect the corresponding signal line 516 in the absence of a separate ESD protection circuit coupled thereto. Thus, although the IOE 503 may include Figure 5 Although additional circuitry is not described in the drawings, IOE 503 may not include various ESD protection circuits that are typically required in previous IOE approaches that utilize various CMOS logic (eg, switches), such that IOE 503 does not impose significant bandwidth limitations that are typically introduced by previous IOE approaches.

[0055] Figure 6 608-1-1, ..., 608-1-16 and 608-2-1, ..., 608-2-16 (collectively referred to as MEMS switches 608) positioned on signal lines on the front and / or back end of the IOE 603 ​​according to several embodiments of the present disclosure. The front end I / O 604-1-1, ..., 604-1-4 may be collectively referred to as "I / O 604-1", and the back end I / O 604-2-1, ..., 604-2-4 may be collectively referred to as "I / O 604-2". The IOE 603 ​​may be similar to Figure 1 In addition, I / O 604 may be similar to interface 103 described in and / or part thereof. Figure 1 I / O 104 described in .

[0056] Each I / O 604-2 may correspond to and / or represent a port (eg Figure 1 As described herein, those ports (eg, ports coupled or couplable to I / O 604-1-1, ..., 604-1-4, respectively) may be coupled to a host (eg, Figure 1 1), and those ports (eg, ports corresponding to I / O 604-2-1, ..., 604-2-4, respectively) may be coupled to memory devices (eg, Figure 1 Memory device 110 described in FIG.

[0057] IOE 603 ​​includes signal lines 616-1, ..., 616-4. One end of each signal line 616 turns to four different signal lines respectively coupled to I / O 604-1-1 and 604-1-2 (e.g., corresponding I / O pads of I / O 604-1-1 and 604-1-2) and the other end further turns to four different signal lines respectively coupled to I / O 604-2-1, 604-2-2, 604-2-3, and 604-2-4 (e.g., corresponding I / O pads of I / O 604-2-1, 604-2-2, 604-2-3, and 604-2-4).

[0058] like Figure 6 608-1-1, ..., 608-1-4 are positioned on the two turn signal lines of the I / O pad coupled to the I / O 604-1-1; the MEMS switches 608-1-5, ..., 608-1-8 are positioned on the two turn signal lines of the I / O pad coupled to the I / O 604-1-2; the MEMS switches 608-1-9, ..., 608-1-12 are positioned on the two turn signal lines of the I / O pad coupled to the I / O 604-1-3; the MEMS switches 608-1-13, ..., 608-1-16 are positioned on the two turn signal lines of the I / O pad coupled to the I / O 604-1-4; the MEMS switches 608-2-1, ..., 608-2-4 are positioned on the two turn signal lines of the I / O pad coupled to the I / O MEMS switches 608-2-5, ..., 608-2-8 are positioned on the two turning signal lines of the I / O pad coupled to I / O 604-2-2; MEMS switches 608-2-9, ..., 608-2-12 are positioned on the two turning signal lines of the I / O pad coupled to I / O 604-2-3; and MEMS switches 608-2-13, ..., 608-2-16 are positioned on the two turning signal lines of the I / O pad coupled to I / O 604-2-4.

[0059] IOE 603 ​​can allow various / flexible topologies, where I / O 604-1 (e.g., I / O 604-1-1 and 604-1-2) can selectively connect to I / O 604-2 (e.g., I / O 604-2-1 and 604-2-2). In one example, one I / O 604-1 can connect to four I / Os 604-2-1, ..., 604-2-4.

[0060] By having a number of signal lines (coupled to each I / O 604) on the front or back end corresponding to the number of I / Os 604, each I / O 604-1 can be connected to different I / Os 604-2 at the same time without disconnecting a single one of the I / Os 604-1. For example, I / O 604-1-1 can be connected to I / O 604-2-1 via signal line 616-1; I / O 604-1-2 can be connected to I / O 604-2-2 via signal line 616-2; I / O 604-1-3 can be connected to I / O 604-2-3 via signal line 616-3; and I / O 604-1-4 can be connected to I / O 604-2-4 via signal line 616-4, but the embodiment is not limited thereto. In this example, MEMS switches 608-1-1, 608-1-6, 608-1-11, 608-1-16 and MEMS switches 608-2-1, 608-2-6, 608-2-11, 608-2-16 may be placed in a closed position while the other MEMS switches 608-1 and 608-2 are placed in an open position.

[0061] Compared to the IOE embodiments of the present disclosure, IOE approaches that utilize various CMOS logic (e.g., switches) in the form of logic gates and multiplexing / demultiplexing circuit systems may have disadvantages (e.g., relatively high parasitic capacitance and susceptibility to noise / jitter), as well as other disadvantages that may, for example, limit the data transfer bandwidth of the IOE and / or expand the available number of memory channels. In contrast, the IOE embodiments of the present disclosure having MEMS switches (e.g., MEMS switch 608) are substantially less susceptible to electrostatic discharge than CMOS switches, which eliminates the need for separate ESD protection circuits for the MEMS switches. For example, the parasitic capacitance associated with each MEMS switch 608 is below a threshold value, such that the MEMS switch 608 is configured to selectively connect / disconnect the corresponding signal line 616 in the absence of a separate ESD protection circuit coupled thereto. Thus, although the IOE 603 ​​may include Figure 6 Although additional circuitry is not described in the drawings, IOE 603 ​​may not include various ESD protection circuits that are typically required in previous IOE approaches that utilize various CMOS logic (eg, switches), such that IOE 603 ​​does not impose significant bandwidth limitations that are typically introduced by previous IOE approaches.

[0062] Figure 7730 is a flowchart of a method for controlling an electromechanical switch on an I / O component according to several embodiments of the present disclosure. The method illustrated by flowchart 730 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method is performed by Figure 1 105 described in the embodiment of the present invention. Although shown in a specific sequence or order, unless otherwise specified, the order of the process can be modified. Therefore, the illustrated embodiment should be understood as only an example, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0063] At 732, the first and second input / output I / O components may be coupled to a corresponding signal line (eg, Figures 2 to 6 MEMS switches (e.g., signal lines 216, 316, 416, 516, 616) on Figures 1 to 6 The MEMS switch 108, 208, 308, 408, 508, 608 described in the figure is placed in a closed position to electrically connect the first I / O component 204-1, 304-1, 404-1, 504-1, 604-1 to the second I / O component 204-2, 304-2, 404-2, 504-2, 604-2 to form a first I / O component (e.g., I / O component 204-1, 304-1, 404-1, 504-1, 604-1) and a second I / O component (e.g., Figures 2 to 6 At 734, the first I / O component 204-1, 304-1, 404-1, 504-1, 604-1 may be electrically disconnected from the second I / O component 204-2, 304-2, 404-2, 504-2, 604-2 by placing the MEMS switch 108, 208, 308, 408, 508, 608 in the disconnect position.

[0064] In some embodiments, the second I / O components 204-2, 304-2, 404-2, 504-2, 604-2 may be connected via a corresponding number of signal lines (eg, Figures 2 to 6 The signal lines 216, 316, 416, 516, 616 illustrated in FIG. 1 are coupled to a plurality of second I / O components (eg, Figures 2 to 6One of the I / O components 204-2, 304-2, 404-2, 504-2, 604-2) illustrated in FIG. In this example, a data path between a first I / O component 204-1, 304-1, 404-1, 504-1, 604-1 and a first portion of a plurality of second I / O components 204-2, 304-2, 404-2, 504-2, 604-2 may be selectively formed by placing one or more MEMS switches 108, 208, 308, 408, 508, 608 positioned on respective first signal lines 216, 316, 416, 516, 616 coupled between the first I / O component 204-1, 304-1, 404-1, 504-1, 604-1 and a first portion of a plurality of second I / O components 204-2, 304-2, 404-2, 504-2, 604-2 in a closed position. Furthermore, when a first I / O component 204-1, 304-1, 404-1, 504-1, 604-1 is (e.g., electrically and selectively) connected to a first portion of a second number of I / O components 204-2, 304-2, 404-2, 504-2, 604-2, one or more MEMS switches 108, 208, 308, 408, 508, 608 positioned on a respective second signal line 216, 316, 416, 516, 616 (coupled between the first I / O component 204-1, 304-1, 404-1, 504-1, 604-1 and second portions of the number of second I / O components 204-2, 304-2, 404-2, 504-2, 604-2) may be placed in an open position.

[0065] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be understood that the above description has been made in an illustrative and non-restrictive manner. A person of ordinary skill in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein after reviewing the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents authorized by such claims.

[0066] In the foregoing detailed description, some features are grouped together in a single embodiment in order to simplify the disclosure. The disclosed method should not be interpreted as reflecting the intention that the disclosed embodiments of the present disclosure must use more features than those explicitly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method for controlling an interface based on a micro-electromechanical system (MEMS) switch, comprising: By positioning the corresponding signal line (216; 316； 416-1, 416-2; 516-1, 516-2; 616-1, ..., 616-4) on a micro-electromechanical system MEMS switch (108-1, ..., 108-Z; 208-1, 208-2; 308-1, ..., 308-4; 408-1-1, ..., 408-1-4, 408-2-1, ..., 408-2-4; 508-1-1, ..., 508-1-4, 508-2-1, ..., 508-2-8; 608-1-1, ..., 608-1-16, 608-2-1, ..., 608-2-16) in a closed position to electrically connect the first I / O component to the second I / O component to form a data path between the first I / O component and the second I / O component; and The first I / O component is electrically disconnected from the second I / O component by placing the MEMS switch in an open position.

2. The method according to claim 1, wherein: The second I / O component is connected via a corresponding number of signal lines (216; 316; 416-1, 416-2; 516-1, 516-2; 616-1, ..., 616-4) coupled to one of a plurality of second I / O components of the first I / O component; and The method further includes placing one or more MEMS switches positioned on respective first signal lines in a closed position to selectively form a data path between the first I / O component and a first portion of the plurality of second I / O components, wherein the respective first signal lines are coupled between the first I / O component and the first portion of the plurality of second I / O components.

3. The method of claim 2 , further comprising placing one or more MEMS switches positioned on respective second signal lines in an open position when the first I / O component is connected to the first portion of the plurality of second I / O components, wherein the respective second signal lines are coupled between the first I / O component and the second portions of the plurality of second I / O components.

4. A device based on a micro-electromechanical system (MEMS) switch interface, comprising: a first number of input / output I / O components (204-1; 304-1； 404-1-1、404-1-2；504-1-1、504-1-2；604-1-1、…、604-1-4)； a second number of I / O components (204-2-1, 204-2-2; 304-2-1, ..., 304-2-4; 404-2-1, 404-2-2; 504-2-1, ..., 504-2-4; 604-2-1, ..., 604-2-4); and One or more micro-electromechanical system MEMS switches (108-1, ..., 108-Z; 208-1, 208-2; 308-1, ..., 308-4; 408-1-1, 408-1-2, 408-2-1, ..., 408-2-4; 508-1-1, 508-1-2, 508-2-1, ..., 508-2-8; 608-1-1, ..., 608-1-4 , 608-2-1, ..., 608-2-16), which can be operated to selectively connect a first of the first number of I / O components to two or more of the second number of I / O components via corresponding signal lines (216; 316; 416-1, 416-2; 516-1, 516-2; 616-1, ..., 616-4) coupled to the one or more MEMS switches.

5. The apparatus of claim 4, wherein a parasitic capacitance associated with the one or more MEMS switches is below a threshold value such that the one or more MEMS switches are configured to selectively connect the first of the first number of I / O components to the two or more of the second number of I / O components in the absence of a separate electrostatic discharge (ESD) protection circuit coupled thereto.

6. The apparatus of any of claims 4-5, further comprising one or more additional MEMS switches (108-1, ..., 108-Z; 408-1-3, 408-1-4, 408-2-1, ..., 408-2-4; 508-1-3, 508-1-4, 508-2-1, ..., 508-2-8; 608-1-5, ..., 608-1-16, 608-2-1, ..., 608-2-16), which is operable to selectively connect a second one of the first number of I / O components (404-1-2; 504-1-2; 604-1-2, ..., 604-1-4) to two or more of the second number of I / O components via corresponding signal lines coupled to the one or more additional MEMS switches.

7. The apparatus of claim 6, wherein the one or more MEMS switches include at least two MEMS switches, and wherein the one or more additional MEMS switches include at least two MEMS switches.

8. A device based on a micro-electromechanical system (MEMS) switch interface, comprising: A first number of micro-electromechanical system MEMS switches (108-1, ..., 108-Z; 408-1-1、…、408-1-4； 508-1-1、…、508-1-4； , 608-1-1, ..., 608-1-16), which are positioned on a first portion of the apparatus, the first number of MEMS switches coupled to a first number of signal lines (416-1, 416-2; 516-1, 516-2; 616-1, ..., 616-4) and operable to respectively and selectively connect or disconnect the first number of signal lines; and a second number of MEMS switches (108-1, ..., 108-Z; 408-2-1, ..., 408-2-4; 508-2-1, ..., 508-2-4; 608-2-1, ..., 608-2-16) positioned on a second end of the device, the second number of MEMS switches coupled to a second number of signal lines (416-1, 416-2; 516-1, 516-2; 616-1, ..., 616-4) and are operable to respectively and selectively connect or disconnect the second number of signal lines.

9. The apparatus of claim 8, wherein a capacitance of each MEMS switch of the first and second numbers of MEMS switches is below a threshold value such that each of the first and second MEMS switches does not include a separate electrostatic discharge (ESD) protection circuit.

10. The apparatus of any one of claims 8 to 9, further comprising: a first number of input / output I / O components (404-1-1, 404-1-2; 504-1-1, 504-1-2; 604-1-1, ..., 604-1-4) respectively coupled to the first number of MEMS switches; The first number of MEMS switches further comprises a plurality of groups of MEMS switches, each group of MEMS switches in the plurality of groups being coupled to a corresponding I / O component in the first number of I / O components.

11. The device according to any one of claims 8 to 9, wherein the device corresponds to an input / output I / O expander (203; 303; 403; 503; 603).

12. A system comprising: a first number of signal lines (416-1, 416-2; 516-1, 516-2; 616-1, ..., 616-4), the first number of signal lines being directed to a second number of signal lines on a front end of an interface device (203; 303; 403; 503; 603) and further to a third number of signal lines on a back end of the interface device; A first number of micro-electromechanical system MEMS switches (108-1, ..., 108-Z; 408-1-1, ..., 408-1-4; 508-1-1, ..., 508-1-4; 608-1-1, ..., 608-1-16), each MEMS switch of the first number of MEMS switches is positioned on a corresponding signal line of the second number of signal lines, and the first number of MEMS switches are operable to connect or disconnect the corresponding signal line of the second number of signal lines, respectively; and A second number of MEMS switches (108-1, ..., 108-Z; 408-2-1, ..., 408-2-4; 508-2-1, ..., 508-2-4; 608-2-1, ..., 608-2-16), each of the second number of MEMS switches being positioned on a corresponding signal line of the third number of signal lines, the second number of MEMS switches being operable to respectively connect or disconnect the corresponding signal lines of the third number of signal lines.

13. The system of claim 12, wherein: The interface device further includes a first number of input / output I / O components (204-2-1, 204-2-2; 304-2-1, ..., 304-2-4; 404-2-1, 404-2-2; 504-2-1, ..., 504-2-4; 604-2-1, ..., 604-2-4) respectively coupled to the third number of signal lines; and The system further comprises: a plurality of first ports (112-1-1, ..., 112-1-N) on the front end; and A plurality of second ports (112-1-1, ..., 112-1-M) on the back end, each port of the plurality of second ports comprising one or more I / O components of the first number of I / O components.

14. The system of claim 13, wherein: The first portion of the second number of MEMS switches corresponds to one port of the second number of ports; and A second portion of the second number of MEMS switches corresponds to different ports of the second number of ports.

15. The system of claim 13, wherein each port of the plurality of first ports is simultaneously connectable to a different port of the plurality of second ports without disconnecting a single port of the plurality of first ports or the plurality of second ports.

16. The system of claim 13, wherein each of the plurality of first ports on the front end is coupleable to an I / O component of one or more hosts (101-1, ..., 101-X).

17. The system of claim 12, further comprising an interface controller configured to: placing a MEMS switch of the first number of MEMS switches in an open position to disconnect a corresponding signal line of the second number of signal lines; and A MEMS switch of the first number of MEMS switches is placed in a closed position to connect a corresponding signal line of the second number of signal lines.

18. The system of claim 12, further comprising an interface controller configured to: placing a MEMS switch of the second number of MEMS switches in an open position to disconnect a corresponding signal line of the third number of signal lines; and A MEMS switch of the second number of MEMS switches is placed in a closed position to connect a corresponding signal line of the third number of signal lines.

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